[llvm] c7ddefd - [MC][RISCV] Make Zve32x a dependency of Zvabd (#223901)

[via llvm-commits]

Author: Zeyi Xu
Date: 2026-09-16T13:11:25+08:00
New Revision: c7ddefdcc81c32c2a05b636817fcb5d5e4cc0c40

URL: https://github.com/llvm/llvm-project/commit/c7ddefdcc81c32c2a05b636817fcb5d5e4cc0c40
DIFF: https://github.com/llvm/llvm-project/commit/c7ddefdcc81c32c2a05b636817fcb5d5e4cc0c40.diff

LOG: [MC][RISCV] Make Zve32x a dependency of Zvabd (#223901)

The Zvabd specification defines Zve32x as a dependency. This commit
fixes the dependency problem in MC's implementation.

See:
https://github.com/riscv/integer-vector-absolute-difference/blob/0092c8451bb24b957d8358f261c0535ece88defb/src/unpriv/zvabd.adoc#L26

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFeatures.td
    llvm/test/MC/RISCV/attribute-arch.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d2c24c3f22928..6c2a1f747abe8 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -702,7 +702,8 @@ def FeatureStdExtV
       RISCVExtensionBitmask<0, 21>;
 
 def FeatureStdExtZvabd
-    : RISCVExperimentalExtension<0, 9, "Vector Absolute Difference">;
+    : RISCVExperimentalExtension<0, 9, "Vector Absolute Difference",
+                                 [FeatureStdExtZve32x]>;
 def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">,
                      AssemblerPredicate<(all_of FeatureStdExtZvabd),
                                         "'Zvabd' (Vector Absolute Difference)">;

diff  --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 857f51e8dbe4f..1eb141a1bd00a 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -567,6 +567,9 @@
 .attribute arch, "rv64i_p0p21"
 # CHECK: attribute      5, "rv64i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0"
 
+.attribute arch, "rv32i_zvabd0p9"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvabd0p9_zve32x1p0_zvl32b1p0"
+
 .attribute arch, "rv32iv_zvqwbdota8i0p2"
 # CHECK: attribute      5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvqwbdota8i0p2"