[llvm] 8b66604 - [RISCV] Remap mop.rr.7 and mop.r.28 to sspush/sspopchk/ssrdp in the assembler. (#223894)

[via llvm-commits]

Author: Craig Topper
Date: 2026-09-15T22:00:50-07:00
New Revision: 8b66604bb8e699820c7f1fd06a43a3c6ed2cac76

URL: https://github.com/llvm/llvm-project/commit/8b66604bb8e699820c7f1fd06a43a3c6ed2cac76
DIFF: https://github.com/llvm/llvm-project/commit/8b66604bb8e699820c7f1fd06a43a3c6ed2cac76.diff

LOG: [RISCV] Remap mop.rr.7 and mop.r.28 to sspush/sspopchk/ssrdp in the assembler. (#223894)

This makes llvm-mc output match llvm-objdump. And is more consistent
with the InstAliases we use c.mop.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    llvm/test/MC/RISCV/zicfiss-valid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 4f1f3cbfb9b26..66902368a3234 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -4434,6 +4434,36 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
   switch (Inst.getOpcode()) {
   default:
     break;
+  case RISCV::MOP_RR_7: {
+    // Remap mop.rr.7 x0, x0, x1/x5 to sspush x1/x5.
+    if (Inst.getOperand(0).getReg() == RISCV::X0 &&
+        Inst.getOperand(1).getReg() == RISCV::X0 &&
+        (Inst.getOperand(2).getReg() == RISCV::X1 ||
+         Inst.getOperand(2).getReg() == RISCV::X5)) {
+      emitToStreamer(
+          Out, MCInstBuilder(RISCV::SSPUSH).addOperand(Inst.getOperand(2)));
+      return false;
+    }
+    break;
+  }
+  case RISCV::MOP_R_28: {
+    // Remap mop.r.28 x0, x1/x5 to sspopchk x1/x5.
+    if (Inst.getOperand(0).getReg() == RISCV::X0 &&
+        (Inst.getOperand(1).getReg() == RISCV::X1 ||
+         Inst.getOperand(1).getReg() == RISCV::X5)) {
+      emitToStreamer(
+          Out, MCInstBuilder(RISCV::SSPOPCHK).addOperand(Inst.getOperand(1)));
+      return false;
+    }
+    // Remap mop.r.28 rN, x0 to ssrdp rN.
+    if (Inst.getOperand(0).getReg() != RISCV::X0 &&
+        Inst.getOperand(1).getReg() == RISCV::X0) {
+      emitToStreamer(
+          Out, MCInstBuilder(RISCV::SSRDP).addOperand(Inst.getOperand(0)));
+      return false;
+    }
+    break;
+  }
   case RISCV::PseudoC_ADDI_NOP: {
     if (Inst.getOperand(2).getImm() == 0)
       emitToStreamer(Out, MCInstBuilder(RISCV::C_NOP));

diff  --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
index 7e7f29761e9a8..2cfea489ad72b 100644
--- a/llvm/test/MC/RISCV/zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -1,13 +1,13 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+zicfiss -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+zicfiss < %s \
-# RUN:     | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN:     | llvm-objdump --mattr=+a,+zicfiss -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc %s -triple=riscv64 -defsym=RV64=1 -mattr=+a,+zicfiss -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-RV64,CHECK-ASM,CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -defsym=RV64=1 -mattr=+a,+zicfiss < %s \
 # RUN:     | llvm-objdump --mattr=+a,+zicfiss -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s
 #
 # Zicfiss MOP-based instructions (sspopchk, ssrdp, sspush) only require Zimop,
 # not Zicfiss. SSAMOSWAP still requires Zicfiss.
@@ -71,38 +71,32 @@ ssrdp ra
 # assembly printer prints the mnemonic that was matched, while the
 # disassembler still prefers the more specific sspopchk/ssrdp/sspush).
 
-# CHECK-ASM: mop.r.28 zero, ra
-# CHECK-OBJ: sspopchk ra
+# CHECK-ASM-AND-OBJ: sspopchk ra
 # CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 mop.r.28 x0, x1
 
-# CHECK-ASM: mop.r.28 zero, t0
-# CHECK-OBJ: sspopchk t0
+# CHECK-ASM-AND-OBJ: sspopchk t0
 # CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 mop.r.28 x0, x5
 
-# CHECK-ASM: mop.r.28 ra, zero
-# CHECK-OBJ: ssrdp ra
+# CHECK-ASM-AND-OBJ: ssrdp ra
 # CHECK-ASM: encoding: [0xf3,0x40,0xc0,0xcd]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 mop.r.28 x1, x0
 
-# CHECK-ASM: mop.r.28 t0, zero
-# CHECK-OBJ: ssrdp t0
+# CHECK-ASM-AND-OBJ: ssrdp t0
 # CHECK-ASM: encoding: [0xf3,0x42,0xc0,0xcd]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 mop.r.28 x5, x0
 
-# CHECK-ASM: mop.rr.7 zero, zero, ra
-# CHECK-OBJ: sspush ra
+# CHECK-ASM-AND-OBJ: sspush ra
 # CHECK-ASM: encoding: [0x73,0x40,0x10,0xce]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 mop.rr.7 x0, x0, x1
 
-# CHECK-ASM: mop.rr.7 zero, zero, t0
-# CHECK-OBJ: sspush t0
+# CHECK-ASM-AND-OBJ: sspush t0
 # CHECK-ASM: encoding: [0x73,0x40,0x50,0xce]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 mop.rr.7 x0, x0, x5