[llvm] [SeparateConstOffsetFromGEP] Rebuild GEP indices at their definition point (PR #223546)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 15 10:56:39 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Kevin McAfee (kalxr)
<details>
<summary>Changes</summary>
When a constant offset is split out of a GEP index, the rebuilt index replaces the original one. Rebuilding the index immediately before the GEP amounts to sinking the index computation, increasing live ranges and register pressure. This change attempts to rebuild the index at the definition point of the original index instead. The same insertion point is used for the `idxprom` cast created by `canonicalizeArrayIndicesToIndexSize` too.
---
Patch is 67.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223546.diff
13 Files Affected:
- (modified) llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp (+11-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll (+39-39)
- (modified) llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll (+57-57)
- (modified) llvm/test/CodeGen/AMDGPU/memmove-var-size.ll (+72-72)
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/while-break.ll (+1-1)
- (modified) llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll (+15-15)
- (added) llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/index-insertion-point.ll (+151)
- (modified) llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll (+14-14)
- (added) llvm/test/Transforms/SeparateConstOffsetFromGEP/index-insertion-point-terminator-def.ll (+109)
- (modified) llvm/test/Transforms/SeparateConstOffsetFromGEP/pr45371-find-either-reset.ll (+1-1)
``````````diff
diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
index 4870b8c8882795..477ef6d502c8cc 100644
--- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
@@ -167,6 +167,7 @@
#include "llvm/Transforms/Utils/Local.h"
#include <cassert>
#include <cstdint>
+#include <optional>
#include <string>
using namespace llvm;
@@ -973,10 +974,18 @@ static bool allowsPreservingNUW(const User *U) {
return true;
}
+static BasicBlock::iterator getIndexInsertionPoint(Value *Idx,
+ GetElementPtrInst *GEP) {
+ if (auto *I = dyn_cast<Instruction>(Idx))
+ if (auto IP = I->getInsertionPointAfterDef())
+ return *IP;
+ return GEP->getIterator();
+}
+
Value *ConstantOffsetExtractor::Extract(Value *Idx, GetElementPtrInst *GEP,
User *&UserChainTail,
bool &PreservesNUW) {
- ConstantOffsetExtractor Extractor(GEP->getIterator());
+ ConstantOffsetExtractor Extractor(getIndexInsertionPoint(Idx, GEP));
// Find a non-zero constant offset first.
APInt ConstantOffset = Extractor.find(Idx, GEP, Idx, /* SignExtended */ false,
/* ZeroExtended */ false);
@@ -1010,7 +1019,7 @@ bool SeparateConstOffsetFromGEP::canonicalizeArrayIndicesToIndexSize(
if (GTI.isSequential()) {
if ((*I)->getType() != PtrIdxTy) {
*I = CastInst::CreateIntegerCast(*I, PtrIdxTy, true, "idxprom",
- GEP->getIterator());
+ getIndexInsertionPoint(*I, GEP));
Changed = true;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
index b6a79db5971438..1603d5211c686a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
@@ -210,12 +210,12 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: ; %bb.5: ; %loop.body
; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1
; GFX10-NEXT: global_load_dword v6, v[0:1], off
-; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, 4
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
-; GFX10-NEXT: s_add_i32 s0, s0, 1
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 4
-; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT: s_add_i32 s0, s0, 1
+; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, 4
+; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
+; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
; GFX10-NEXT: s_cselect_b32 s6, exec_lo, 0
; GFX10-NEXT: s_andn2_b32 s4, s4, exec_lo
; GFX10-NEXT: s_and_b32 s6, exec_lo, s6
@@ -312,14 +312,14 @@ define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: ; %bb.7: ; %loop.body
; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1
; GFX10-NEXT: global_load_dword v8, v[0:1], off
-; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v6, 4
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 4
+; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, 4
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
; GFX10-NEXT: s_add_i32 s0, s0, 1
-; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 4
+; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v6, 4
; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: s_cselect_b32 s8, exec_lo, 0
; GFX10-NEXT: s_andn2_b32 s6, s6, exec_lo
; GFX10-NEXT: s_and_b32 s8, exec_lo, s8
diff --git a/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll b/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
index d6089f85b8a4be..883bf28c8cbd86 100644
--- a/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
@@ -349,25 +349,25 @@ define amdgpu_kernel void @test_pipelined_loop_with_global(ptr addrspace(1) %foo
; SDAG-NEXT: s_add_co_i32 s12, s9, 8
; SDAG-NEXT: s_wait_loadcnt 0x0
; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v9, s12
-; SDAG-NEXT: v_mov_b32_e32 v8, v3
-; SDAG-NEXT: s_clause 0x1
+; SDAG-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v4, s12
+; SDAG-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, s9
; SDAG-NEXT: global_load_b32 v3, v0, s[4:5]
-; SDAG-NEXT: global_load_b32 v4, v0, s[0:1]
; SDAG-NEXT: v_dual_add_nc_u32 v10, v5, v6 :: v_dual_mov_b32 v6, v2
-; SDAG-NEXT: global_load_async_to_lds_b32 v9, v0, s[4:5] offset:4 nv
-; SDAG-NEXT: v_mov_b32_e32 v9, s9
+; SDAG-NEXT: s_clause 0x1
+; SDAG-NEXT: global_load_async_to_lds_b32 v4, v0, s[4:5] offset:4 nv
+; SDAG-NEXT: global_load_b32 v4, v0, s[0:1]
; SDAG-NEXT: ; asyncmark
; SDAG-NEXT: ; wait_asyncmark(2)
; SDAG-NEXT: s_wait_asynccnt 0x2
-; SDAG-NEXT: s_add_co_i32 s8, s8, 1
-; SDAG-NEXT: s_add_co_i32 s9, s9, 4
; SDAG-NEXT: ds_load_b32 v9, v9
; SDAG-NEXT: v_mov_b32_e32 v5, v1
+; SDAG-NEXT: s_add_co_i32 s8, s8, 1
+; SDAG-NEXT: s_add_co_i32 s9, s9, 4
; SDAG-NEXT: s_cmp_lt_i32 s8, s11
+; SDAG-NEXT: s_wait_xcnt 0x1
+; SDAG-NEXT: s_add_nc_u64 s[4:5], s[4:5], 4
; SDAG-NEXT: s_wait_xcnt 0x0
; SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 4
-; SDAG-NEXT: s_add_nc_u64 s[4:5], s[4:5], 4
; SDAG-NEXT: s_wait_dscnt 0x0
; SDAG-NEXT: v_add_nc_u32_e32 v9, v10, v9
; SDAG-NEXT: global_store_b32 v0, v9, s[6:7]
@@ -413,60 +413,60 @@ define amdgpu_kernel void @test_pipelined_loop_with_global(ptr addrspace(1) %foo
; GISEL-NEXT: s_mov_b32 s13, 2
; GISEL-NEXT: s_wait_kmcnt 0x0
; GISEL-NEXT: s_load_b32 s12, s[8:9], 0x0
-; GISEL-NEXT: s_load_b32 s17, s[0:1], 0x0
+; GISEL-NEXT: s_load_b32 s16, s[0:1], 0x0
; GISEL-NEXT: v_mov_b32_e32 v1, s10
; GISEL-NEXT: s_add_co_u32 s6, s10, 4
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-NEXT: v_dual_mov_b32 v3, 4 :: v_dual_mov_b32 v4, s6
-; GISEL-NEXT: s_mov_b32 s14, s10
+; GISEL-NEXT: s_add_co_u32 s6, s8, 8
; GISEL-NEXT: s_clause 0x2
; GISEL-NEXT: global_load_async_to_lds_b32 v1, v0, s[8:9] offset:4 nv
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: global_load_b32 v1, v0, s[8:9] offset:4
; GISEL-NEXT: global_load_b32 v2, v0, s[0:1] offset:4
; GISEL-NEXT: global_load_async_to_lds_b32 v4, v3, s[8:9] offset:4 nv
+; GISEL-NEXT: s_add_co_ci_u32 s7, s9, 0
; GISEL-NEXT: s_wait_xcnt 0x0
; GISEL-NEXT: s_add_co_u32 s0, s0, 8
-; GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
-; GISEL-NEXT: s_add_co_u32 s6, s8, 8
+; GISEL-NEXT: s_mov_b32 s14, s10
; GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
-; GISEL-NEXT: s_add_co_ci_u32 s7, s9, 0
+; GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: s_wait_loadcnt 0x1
-; GISEL-NEXT: v_readfirstlane_b32 s15, v1
+; GISEL-NEXT: v_readfirstlane_b32 s8, v1
; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: v_readfirstlane_b32 s16, v2
-; GISEL-NEXT: s_mov_b32 s8, s15
-; GISEL-NEXT: s_mov_b32 s19, s16
+; GISEL-NEXT: v_readfirstlane_b32 s15, v2
+; GISEL-NEXT: s_mov_b32 s9, s8
+; GISEL-NEXT: s_mov_b32 s19, s15
; GISEL-NEXT: .LBB2_1: ; %loop_body
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: s_add_co_u32 s9, s14, 8
-; GISEL-NEXT: s_clause 0x1
-; GISEL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GISEL-NEXT: global_load_b32 v2, v0, s[0:1]
-; GISEL-NEXT: v_mov_b32_e32 v3, s9
-; GISEL-NEXT: s_mov_b32 s18, s8
+; GISEL-NEXT: s_add_co_u32 s17, s14, 8
+; GISEL-NEXT: global_load_b32 v2, v0, s[6:7]
+; GISEL-NEXT: v_dual_mov_b32 v1, s17 :: v_dual_mov_b32 v3, s14
+; GISEL-NEXT: s_mov_b32 s18, s9
; GISEL-NEXT: s_wait_kmcnt 0x0
-; GISEL-NEXT: s_add_co_i32 s8, s12, s17
+; GISEL-NEXT: s_add_co_i32 s9, s12, s16
; GISEL-NEXT: s_add_co_i32 s13, s13, 1
-; GISEL-NEXT: s_mov_b32 s9, s19
-; GISEL-NEXT: global_load_async_to_lds_b32 v3, v0, s[6:7] offset:4 nv
-; GISEL-NEXT: v_mov_b32_e32 v3, s14
+; GISEL-NEXT: s_clause 0x1
+; GISEL-NEXT: global_load_async_to_lds_b32 v1, v0, s[6:7] offset:4 nv
+; GISEL-NEXT: global_load_b32 v1, v0, s[0:1]
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: ; wait_asyncmark(2)
; GISEL-NEXT: s_wait_asynccnt 0x2
-; GISEL-NEXT: s_mov_b32 s12, s15
; GISEL-NEXT: ds_load_b32 v3, v3
+; GISEL-NEXT: s_mov_b32 s17, s19
+; GISEL-NEXT: s_mov_b32 s12, s8
; GISEL-NEXT: s_wait_dscnt 0x0
-; GISEL-NEXT: v_readfirstlane_b32 s17, v3
-; GISEL-NEXT: s_add_co_i32 s8, s8, s17
+; GISEL-NEXT: v_readfirstlane_b32 s16, v3
+; GISEL-NEXT: s_add_co_i32 s9, s9, s16
+; GISEL-NEXT: s_wait_xcnt 0x1
+; GISEL-NEXT: s_add_co_u32 s6, s6, 4
+; GISEL-NEXT: v_mov_b32_e32 v3, s9
+; GISEL-NEXT: s_add_co_ci_u32 s7, s7, 0
; GISEL-NEXT: s_wait_xcnt 0x0
; GISEL-NEXT: s_add_co_u32 s0, s0, 4
-; GISEL-NEXT: v_mov_b32_e32 v3, s8
; GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
-; GISEL-NEXT: s_add_co_u32 s6, s6, 4
-; GISEL-NEXT: s_add_co_ci_u32 s7, s7, 0
-; GISEL-NEXT: s_mov_b32 s17, s16
+; GISEL-NEXT: s_mov_b32 s16, s15
; GISEL-NEXT: global_store_b32 v0, v3, s[4:5]
; GISEL-NEXT: s_wait_xcnt 0x0
; GISEL-NEXT: s_add_co_u32 s4, s4, 4
@@ -474,16 +474,16 @@ define amdgpu_kernel void @test_pipelined_loop_with_global(ptr addrspace(1) %foo
; GISEL-NEXT: s_add_co_u32 s14, s14, 4
; GISEL-NEXT: s_cmp_lt_i32 s13, s11
; GISEL-NEXT: s_wait_loadcnt 0x1
-; GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GISEL-NEXT: v_readfirstlane_b32 s9, v2
; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: v_readfirstlane_b32 s19, v2
+; GISEL-NEXT: v_readfirstlane_b32 s19, v1
; GISEL-NEXT: s_cbranch_scc1 .LBB2_1
; GISEL-NEXT: ; %bb.2: ; %epilog
; GISEL-NEXT: s_add_co_i32 s0, s11, -2
; GISEL-NEXT: ; wait_asyncmark(1)
; GISEL-NEXT: s_wait_asynccnt 0x1
; GISEL-NEXT: s_lshl_b32 s1, s0, 2
-; GISEL-NEXT: s_add_co_i32 s4, s18, s9
+; GISEL-NEXT: s_add_co_i32 s4, s18, s17
; GISEL-NEXT: s_add_co_u32 s1, s10, s1
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-NEXT: v_mov_b32_e32 v0, s1
@@ -494,7 +494,7 @@ define amdgpu_kernel void @test_pipelined_loop_with_global(ptr addrspace(1) %foo
; GISEL-NEXT: s_add_co_i32 s1, s4, s1
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-NEXT: v_mov_b32_e32 v2, s1
-; GISEL-NEXT: s_add_co_i32 s1, s8, s19
+; GISEL-NEXT: s_add_co_i32 s1, s9, s19
; GISEL-NEXT: global_store_b32 v1, v2, s[2:3] scale_offset
; GISEL-NEXT: ; wait_asyncmark(0)
; GISEL-NEXT: s_wait_asynccnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
index 4ef9df249c41cd..c345990cfc115e 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
@@ -418,8 +418,8 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
; GFX12-NEXT: v_mov_b32_e32 v2, s1
; GFX12-NEXT: v_mov_b32_e32 v4, s0
; GFX12-NEXT: s_add_co_i32 s2, s2, -1
-; GFX12-NEXT: s_add_co_i32 s0, s0, 16
; GFX12-NEXT: s_add_co_i32 s1, s1, 16
+; GFX12-NEXT: s_add_co_i32 s0, s0, 16
; GFX12-NEXT: ds_load_2addr_b32 v[0:1], v2 offset0:2 offset1:3
; GFX12-NEXT: ds_load_2addr_b32 v[2:3], v2 offset1:1
; GFX12-NEXT: s_cmp_lg_u32 s2, 0
@@ -443,8 +443,8 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
; GFX12-SPREFETCH-NEXT: v_mov_b32_e32 v2, s1
; GFX12-SPREFETCH-NEXT: v_mov_b32_e32 v4, s0
; GFX12-SPREFETCH-NEXT: s_add_co_i32 s2, s2, -1
-; GFX12-SPREFETCH-NEXT: s_add_co_i32 s0, s0, 16
; GFX12-SPREFETCH-NEXT: s_add_co_i32 s1, s1, 16
+; GFX12-SPREFETCH-NEXT: s_add_co_i32 s0, s0, 16
; GFX12-SPREFETCH-NEXT: ds_load_2addr_b32 v[0:1], v2 offset0:2 offset1:3
; GFX12-SPREFETCH-NEXT: ds_load_2addr_b32 v[2:3], v2 offset1:1
; GFX12-SPREFETCH-NEXT: s_cmp_lg_u32 s2, 0
@@ -469,8 +469,8 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
; GFX12ES2-SPREFETCH-NEXT: v_mov_b32_e32 v2, s1
; GFX12ES2-SPREFETCH-NEXT: v_mov_b32_e32 v4, s0
; GFX12ES2-SPREFETCH-NEXT: s_add_co_i32 s2, s2, -1
-; GFX12ES2-SPREFETCH-NEXT: s_add_co_i32 s0, s0, 16
; GFX12ES2-SPREFETCH-NEXT: s_add_co_i32 s1, s1, 16
+; GFX12ES2-SPREFETCH-NEXT: s_add_co_i32 s0, s0, 16
; GFX12ES2-SPREFETCH-NEXT: s_wait_alu depctr_va_vdst(1)
; GFX12ES2-SPREFETCH-NEXT: ds_load_2addr_b32 v[0:1], v2 offset0:2 offset1:3
; GFX12ES2-SPREFETCH-NEXT: s_wait_alu depctr_vm_vsrc(0)
@@ -499,8 +499,8 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v4, s0
; GFX1250-NEXT: s_add_co_i32 s2, s2, -1
-; GFX1250-NEXT: s_add_co_i32 s0, s0, 16
; GFX1250-NEXT: s_add_co_i32 s1, s1, 16
+; GFX1250-NEXT: s_add_co_i32 s0, s0, 16
; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset0:2 offset1:3
; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v2 offset1:1
; GFX1250-NEXT: s_cmp_lg_u32 s2, 0
diff --git a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
index c1765431d480da..3976ce2b5dc042 100644
--- a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+++ b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
@@ -3526,53 +3526,53 @@ define void @memcpy_p5_p5_sz2048(ptr addrspace(5) align 1 %dst, ptr addrspace(5)
; UNROLL3-LABEL: memcpy_p5_p5_sz2048:
; UNROLL3: ; %bb.0: ; %entry
; UNROLL3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; UNROLL3-NEXT: v_mov_b32_e32 v2, v1
-; UNROLL3-NEXT: v_mov_b32_e32 v3, v0
+; UNROLL3-NEXT: v_mov_b32_e32 v2, v0
+; UNROLL3-NEXT: v_mov_b32_e32 v3, v1
; UNROLL3-NEXT: s_mov_b64 s[4:5], 0
; UNROLL3-NEXT: .LBB3_1: ; %static-memcpy-expansion-main-body
; UNROLL3-NEXT: ; =>This Inner Loop Header: Depth=1
; UNROLL3-NEXT: s_clause 0xb
-; UNROLL3-NEXT: buffer_load_dword v4, v2, s[0:3], 0 offen offset:44
-; UNROLL3-NEXT: buffer_load_dword v5, v2, s[0:3], 0 offen offset:40
-; UNROLL3-NEXT: buffer_load_dword v6, v2, s[0:3], 0 offen offset:36
-; UNROLL3-NEXT: buffer_load_dword v7, v2, s[0:3], 0 offen offset:32
-; UNROLL3-NEXT: buffer_load_dword v8, v2, s[0:3], 0 offen offset:28
-; UNROLL3-NEXT: buffer_load_dword v9, v2, s[0:3], 0 offen offset:24
-; UNROLL3-NEXT: buffer_load_dword v10, v2, s[0:3], 0 offen offset:20
-; UNROLL3-NEXT: buffer_load_dword v11, v2, s[0:3], 0 offen offset:16
-; UNROLL3-NEXT: buffer_load_dword v12, v2, s[0:3], 0 offen offset:12
-; UNROLL3-NEXT: buffer_load_dword v13, v2, s[0:3], 0 offen offset:8
-; UNROLL3-NEXT: buffer_load_dword v14, v2, s[0:3], 0 offen offset:4
-; UNROLL3-NEXT: buffer_load_dword v15, v2, s[0:3], 0 offen
+; UNROLL3-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen offset:44
+; UNROLL3-NEXT: buffer_load_dword v5, v3, s[0:3], 0 offen offset:40
+; UNROLL3-NEXT: buffer_load_dword v6, v3, s[0:3], 0 offen offset:36
+; UNROLL3-NEXT: buffer_load_dword v7, v3, s[0:3], 0 offen offset:32
+; UNROLL3-NEXT: buffer_load_dword v8, v3, s[0:3], 0 offen offset:28
+; UNROLL3-NEXT: buffer_load_dword v9, v3, s[0:3], 0 offen offset:24
+; UNROLL3-NEXT: buffer_load_dword v10, v3, s[0:3], 0 offen offset:20
+; UNROLL3-NEXT: buffer_load_dword v11, v3, s[0:3], 0 offen offset:16
+; UNROLL3-NEXT: buffer_load_dword v12, v3, s[0:3], 0 offen offset:12
+; UNROLL3-NEXT: buffer_load_dword v13, v3, s[0:3], 0 offen offset:8
+; UNROLL3-NEXT: buffer_load_dword v14, v3, s[0:3], 0 offen offset:4
+; UNROLL3-NEXT: buffer_load_dword v15, v3, s[0:3], 0 offen
; UNROLL3-NEXT: s_add_u32 s4, s4, 48
; UNROLL3-NEXT: s_addc_u32 s5, s5, 0
-; UNROLL3-NEXT: v_add_nc_u32_e32 v2, 48, v2
+; UNROLL3-NEXT: v_add_nc_u32_e32 v3, 48, v3
; UNROLL3-NEXT: v_cmp_gt_u64_e64 s6, 0x7e0, s[4:5]
; UNROLL3-NEXT: s_waitcnt vmcnt(11)
-; UNROLL3-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen offset:44
+; UNROLL3-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen offset:44
; UNROLL3-NEXT: s_waitcnt vmcnt(10)
-; UNROLL3-NEXT: buffer_store_dword v5, v3, s[0:3], 0 offen offset:40
+; UNROLL3-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen offset:40
; UNROLL3-NEXT: s_waitcnt vmcnt(9)
-; UNROLL3-NEXT: buffer_store_dword v6, v3, s[0:3], 0 offen offset:36
+; UNROLL3-NEXT: buffer_store_dword v6, v2, s[0:3], 0 offen offset:36
; UNROLL3-NEXT: s_waitcnt vmcnt(8)
-; UNROLL3-NEXT: buffer_store_dword v7, v3, s[0:3], 0 offen offset:32
+; UNROLL3-NEXT: buffer_store_dword v7, v2, s[0:3], 0 offen offset:32
; UNROLL3-NEXT: s_waitcnt vmcnt(7)
-; UNROLL3-NEXT: buffer_store_dword v8, v3, s[0:3], 0 offen offset:28
+; UNROLL3-NEXT: buffer_store_dword v8, v2, s[0:3], 0 offen offset:28
; UNROLL3-NEXT: s_waitcnt vmcnt(6)
-; UNROLL3-NEXT: buffer_store_dword v9, v3, s[0:3], 0 offen offset:24
+; UNROLL3-NEXT: buffer_store_dword v9, v2, s[0:3], 0 offen offset:24
; UNROLL3-NEXT: s_waitcnt vmcnt(5)
-; UNROLL3-NEXT: buffer_store_dword v10, v3, s[0:3], 0 offen offset:20
+; UNROLL3-NEXT: buffer_store_dword v10, v2, s[0:3], 0 offen offset:20
; UNROLL3-NEXT: s_waitcnt vmcnt(4)
-; UNROLL3-NEXT: buffer_store_dword v11, v3, s[0:3], 0 offen offset:16
+; UNROLL3-NEXT: buffer_store_dword v11, v2, s[0:3], 0 offen offset:16
; UNROLL3-NEXT: s_waitcnt vmcnt(3)
-; UNROLL3-NEXT: buffer_store_dword v12, v3, s[0:3], 0 offen offset:12
+; UNROLL3-NEXT: buffer_store_dword v12, v2, s[0:3], 0 offen offset:12
; UNROLL3-NEXT: s_waitcnt vmcnt(2)
-; UNROLL3-NEXT: buffer_store_dword v13, v3, s[0:3], 0 offen offset:8
+; UNROLL3-NEXT: buffer_store_dword v13, v2, s[0:3], 0 offen offset:8
; UNROLL3-NEXT: s_waitcnt vmcnt(1)
-; UNROLL3-NEXT: buffer_store_dword v14, v3, s[0:3], 0 offen offset:4
+; UNROLL3-NEXT: buffer_store_dword v14, v2, s[0:3], 0 offen offset:4
; UNROLL3-NEXT: s_waitcnt vmcnt(0)
-; UNROLL3-NEXT: buffer_store_dword v15, v3, s[0:3], 0 offen
-; UNROLL3-NEXT: v_add_nc_u32_e32 v3, 48, v3
+; UNROLL3-NEXT: buffer_store_dword v15, v2, s[0:3], 0 offen
+; UNROLL3-NEXT: v_add_nc_u32_e32 v2, 48, v2
; UNROLL3-NEXT: s_and_b32 vcc_lo, exec_lo, s6
; UNROLL3-NEXT: s_cbranch_vccnz .LBB3_1
; UNROLL3-NEXT: ; %bb.2: ; %static-memcpy-post-expansion
@@ -12328,52 +12328,52 @@ define void @memmove_p5_p5_sz2048(ptr addrspace(5) align 1 %dst, ptr addrspace(5
; UNROLL3-NEXT: s_xor_b32 s6, exec_lo, s4
; UNROLL3-NEXT: s_cbranch_execz .LBB8_4
; UNROLL3-NEXT: ; %bb.1: ; %memmove_fwd_loop.preheader
-; UNROLL3-NEXT: v_mov_b32_e32 v2, v1
-; UNROLL3-NEXT: v_mov_b32_e32 v3, v0
+; UNROLL3-NEXT: v_mov_b32_e32 v2, v0
+; UNROLL3-NEXT: v_mov_b32_e32 v3, v1
; UNROLL3-NEXT: s_mov_b64 s[4:5], 0x7e0
; UNROLL3-NEXT: .LBB8_2: ; %memmove_fwd_loop
; UNROLL3-NEXT: ; =>This Inner Loop Header: Depth=1
; UNROLL3-NEXT: s_clause 0xb
-; UNROLL3-NEXT: buffer_load_dword v4, v2, s[0:3], 0 offen offset:44
-; UNROLL3-NEXT: buffer_load_dword v5, v2, s[0:3], 0 offen offset:40
-; UNROLL3-NEXT: buffer_load_dword v6, v2, s[0:3], 0 offen offset:36
-; UNROLL3-NEXT: buffer_load_dword v7, v2, s[0:3], 0 offen offset:32
-; UNROLL3-NEXT: buffer_load_dword v8, v2, s[0:3], 0 offen offset:28
-; UNROLL3-NEXT: buffer_load_dword v9, v2, s[0:3], 0 offen offset:24
-; UNROLL3-NEXT: buffer_load_dword v10, v2, s[0:3], 0 offen offset:20
-; UNROLL3-NEXT: buffer_load_dword v11, v2, s[0:3], 0 offen offset:16
-; UNROLL3-NEXT: buffer_load_dword v12, v2, s[0:3], 0 offen offset:12
-; UNROLL3-NEXT: buffer_load_dword v13, v2, s[0:3], 0 offen offset:8
-; UNROLL3-NEXT: buffer_load_dword v14, v2, s[0:3], 0 offen offset:4
-; UNROLL3-NEXT: buffer_load_dword v15, v2, s[0:3], 0 offen
-; UNROLL3-NEXT: v_add_nc_u32_e32 v2, 48, v2
+; UNROLL3-NEXT: buffer_load_dword v4, v3, s[0...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223546
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