[llvm] [CodeGen] Re-land reverted PR (#216510): "Use RegisterClassInfo for remaining allocation-order users" with additional PBQP fix. (PR #222450)

[Michael Halkenhäuser via llvm-commits]

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@@ -818,6 +816,12 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
 
   MF.getRegInfo().freezeReservedRegs();
 
+  RegisterClassInfo &RCI =
+      getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
+  // freezeReservedRegs() may add reservations the shared analysis has not seen.
+  // Refresh RCI so getOrder() excludes them.
+  RCI.updateReservedRegs(MF.getRegInfo().getReservedRegs());
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mhalk wrote:

> True... I could just split this into a separate PR migrating all 4 RAs to the shared analysis if that makes sense. Then we could merge this with just the AMDGPU and ARM patch.

Sounds great! This would simplify cleaning up my temporary fix significantly  -- I was exploring that route (switch RAs to shared analysis), too in the meantime.
That would allow me to remove the added (unnecessary & expensive) re-calculation I introduced.
Please ping me on any related PR or let me know if I can (try to) support.

https://github.com/llvm/llvm-project/pull/222450