[llvm] [AMDGPU] Add vector select cost model in getCmpSelInstrCost (PR #223625)
Carl Ritson via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 15 01:24:37 PDT 2026
https://github.com/perlfu created https://github.com/llvm/llvm-project/pull/223625
Implement basic version of getCmpSelInstrCost to correctly weigh cost of vector selects.
>From 1c7efc663cf51581cca6854c0ee27067c1261f4a Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Tue, 15 Sep 2026 14:15:43 +0900
Subject: [PATCH] [AMDGPU] Add vector select cost model in getCmpSelInstrCost
Implement basic version of getCmpSelInstrCost to correct weight
cost of vector selects.
---
.../AMDGPU/AMDGPUTargetTransformInfo.cpp | 42 +++
.../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 7 +
.../AMDGPU/vector-select-cost-model.ll | 276 ++++++++++++++++++
3 files changed, 325 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/vector-select-cost-model.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index a7556278b7e0d..1ed42a103e051 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -544,6 +544,48 @@ static bool canFuseFMulWithFAddSub(const SITargetLowering &TLI, Type *Ty,
return HasFMAD || (FAddSub->hasAllowContract() && FMul->hasAllowContract());
}
+InstructionCost GCNTTIImpl::getCmpSelInstrCost(
+ unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
+ TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info,
+ TTI::OperandValueInfo Op2Info, const Instruction *I) const {
+ int ISD = TLI->InstructionOpcodeToISD(Opcode);
+
+ if (ISD == ISD::SELECT) {
+ std::pair<InstructionCost, MVT> CondLT = getTypeLegalizationCost(CondTy);
+ std::pair<InstructionCost, MVT> ValLT = getTypeLegalizationCost(ValTy);
+ unsigned NElts =
+ ValLT.second.isVector() ? ValLT.second.getVectorNumElements() : 1;
+ MVT::SimpleValueType SLT = ValLT.second.getScalarType().SimpleTy;
+
+ switch (SLT) {
+ case MVT::i64:
+ case MVT::f64:
+ // > 32b must be split
+ NElts *= 2;
+ break;
+ case MVT::i8:
+ // < 32b can be packed assuming shared condition
+ if (!CondLT.second.isVector())
+ NElts = (NElts + 3) / 4;
+ break;
+ case MVT::i16:
+ case MVT::f16:
+ case MVT::bf16:
+ // < 32b can be packed assuming shared condition
+ if (!CondLT.second.isVector())
+ NElts = (NElts + 1) / 2;
+ break;
+ default:
+ break;
+ }
+
+ return NElts * ValLT.first * getFullRateInstrCost();
+ }
+
+ return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind,
+ Op1Info, Op2Info, I);
+}
+
InstructionCost GCNTTIImpl::getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 887802c950982..2ae6e9a1a756e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -165,6 +165,13 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
bool getTgtMemIntrinsic(IntrinsicInst *Inst,
MemIntrinsicInfo &Info) const override;
+ InstructionCost getCmpSelInstrCost(
+ unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
+ TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
+ TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
+ TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
+ const Instruction *I = nullptr) const override;
+
InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/test/CodeGen/AMDGPU/vector-select-cost-model.ll b/llvm/test/CodeGen/AMDGPU/vector-select-cost-model.ll
new file mode 100644
index 0000000000000..2715fa38e380e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/vector-select-cost-model.ll
@@ -0,0 +1,276 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mtriple=amdgpu11.00-- -S --passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -two-entry-phi-node-folding-threshold=4 < %s | FileCheck -check-prefix=THRESHOLD4
+; RUN: opt -mtriple=amdgpu11.00-- -S --passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -two-entry-phi-node-folding-threshold=5 < %s | FileCheck -check-prefixes=THRESHOLD5
+; RUN: opt -mtriple=amdgpu11.00-- -S --passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -two-entry-phi-node-folding-threshold=7 < %s | FileCheck -check-prefixes=THRESHOLD7
+; RUN: opt -mtriple=amdgpu11.00-- -S --passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -two-entry-phi-node-folding-threshold=13 < %s | FileCheck -check-prefixes=THRESHOLD13
+
+define amdgpu_cs void @folding_selects_16b(i32 %val.0) {
+; THRESHOLD4-LABEL: define amdgpu_cs void @folding_selects_16b(
+; THRESHOLD4-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD4-NEXT: [[DOTENTRY:.*]]:
+; THRESHOLD4-NEXT: [[A:%.*]] = insertelement <3 x half> zeroinitializer, half 0.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[B:%.*]] = insertelement <3 x half> zeroinitializer, half 1.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[C:%.*]] = insertelement <3 x half> zeroinitializer, half 2.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD4-NEXT: br i1 [[COND_0]], label %[[BLOCK_D:.*]], label %[[BLOCK_B:.*]]
+; THRESHOLD4: [[BLOCK_B]]:
+; THRESHOLD4-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD4-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x half> [[B]], <3 x half> [[C]]
+; THRESHOLD4-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x half> [[C]], <3 x half> [[B]]
+; THRESHOLD4-NEXT: br label %[[BLOCK_D]]
+; THRESHOLD4: [[BLOCK_D]]:
+; THRESHOLD4-NEXT: [[RES_PHI0:%.*]] = phi <3 x half> [ [[RES_0]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD4-NEXT: [[RES_PHI1:%.*]] = phi <3 x half> [ [[RES_1]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD4-NEXT: ret void
+;
+; THRESHOLD5-LABEL: define amdgpu_cs void @folding_selects_16b(
+; THRESHOLD5-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD5-NEXT: [[DOTENTRY:.*:]]
+; THRESHOLD5-NEXT: [[A:%.*]] = insertelement <3 x half> zeroinitializer, half 0.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[B:%.*]] = insertelement <3 x half> zeroinitializer, half 1.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[C:%.*]] = insertelement <3 x half> zeroinitializer, half 2.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD5-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD5-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x half> [[B]], <3 x half> [[C]]
+; THRESHOLD5-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x half> [[C]], <3 x half> [[B]]
+; THRESHOLD5-NEXT: [[RES_PHI0:%.*]] = select i1 [[COND_0]], <3 x half> [[A]], <3 x half> [[RES_0]]
+; THRESHOLD5-NEXT: [[RES_PHI1:%.*]] = select i1 [[COND_0]], <3 x half> [[A]], <3 x half> [[RES_1]]
+; THRESHOLD5-NEXT: ret void
+;
+; THRESHOLD7-LABEL: define amdgpu_cs void @folding_selects_16b(
+; THRESHOLD7-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD7-NEXT: [[DOTENTRY:.*:]]
+; THRESHOLD7-NEXT: [[A:%.*]] = insertelement <3 x half> zeroinitializer, half 0.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[B:%.*]] = insertelement <3 x half> zeroinitializer, half 1.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[C:%.*]] = insertelement <3 x half> zeroinitializer, half 2.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD7-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD7-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x half> [[B]], <3 x half> [[C]]
+; THRESHOLD7-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x half> [[C]], <3 x half> [[B]]
+; THRESHOLD7-NEXT: [[RES_PHI0:%.*]] = select i1 [[COND_0]], <3 x half> [[A]], <3 x half> [[RES_0]]
+; THRESHOLD7-NEXT: [[RES_PHI1:%.*]] = select i1 [[COND_0]], <3 x half> [[A]], <3 x half> [[RES_1]]
+; THRESHOLD7-NEXT: ret void
+;
+; THRESHOLD13-LABEL: define amdgpu_cs void @folding_selects_16b(
+; THRESHOLD13-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD13-NEXT: [[DOTENTRY:.*:]]
+; THRESHOLD13-NEXT: [[A:%.*]] = insertelement <3 x half> zeroinitializer, half 0.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[B:%.*]] = insertelement <3 x half> zeroinitializer, half 1.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[C:%.*]] = insertelement <3 x half> zeroinitializer, half 2.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD13-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD13-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x half> [[B]], <3 x half> [[C]]
+; THRESHOLD13-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x half> [[C]], <3 x half> [[B]]
+; THRESHOLD13-NEXT: [[RES_PHI0:%.*]] = select i1 [[COND_0]], <3 x half> [[A]], <3 x half> [[RES_0]]
+; THRESHOLD13-NEXT: [[RES_PHI1:%.*]] = select i1 [[COND_0]], <3 x half> [[A]], <3 x half> [[RES_1]]
+; THRESHOLD13-NEXT: ret void
+;
+.entry:
+ %a = insertelement <3 x half> zeroinitializer, half 0.000000e+00, i64 0
+ %b = insertelement <3 x half> zeroinitializer, half 1.000000e+00, i64 0
+ %c = insertelement <3 x half> zeroinitializer, half 2.000000e+00, i64 0
+ %cond.0 = icmp eq i32 %val.0, 0
+ br i1 %cond.0, label %block.a, label %block.b
+
+block.a: ; preds = %.entry
+ br label %block.c
+
+block.b: ; preds = %.entry
+ %cond.1 = icmp eq i32 %val.0, 1
+ %res.0 = select i1 %cond.1, <3 x half> %b, <3 x half> %c
+ %res.1 = select i1 %cond.1, <3 x half> %c, <3 x half> %b
+ br label %block.c
+
+block.c: ; preds = %block.b, %block.a
+ %res.phi0 = phi <3 x half> [ %a, %block.a ], [ %res.0, %block.b ]
+ %res.phi1 = phi <3 x half> [ %a, %block.a ], [ %res.1, %block.b ]
+ br label %block.d
+
+block.d: ; preds = %block.c
+ ret void
+}
+
+
+define amdgpu_cs void @folding_selects_32b(i32 %val.0) {
+; THRESHOLD4-LABEL: define amdgpu_cs void @folding_selects_32b(
+; THRESHOLD4-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD4-NEXT: [[DOTENTRY:.*]]:
+; THRESHOLD4-NEXT: [[A:%.*]] = insertelement <3 x float> zeroinitializer, float 0.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[B:%.*]] = insertelement <3 x float> zeroinitializer, float 1.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[C:%.*]] = insertelement <3 x float> zeroinitializer, float 2.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD4-NEXT: br i1 [[COND_0]], label %[[BLOCK_D:.*]], label %[[BLOCK_B:.*]]
+; THRESHOLD4: [[BLOCK_B]]:
+; THRESHOLD4-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD4-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x float> [[B]], <3 x float> [[C]]
+; THRESHOLD4-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x float> [[C]], <3 x float> [[B]]
+; THRESHOLD4-NEXT: br label %[[BLOCK_D]]
+; THRESHOLD4: [[BLOCK_D]]:
+; THRESHOLD4-NEXT: [[RES_PHI0:%.*]] = phi <3 x float> [ [[RES_0]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD4-NEXT: [[RES_PHI1:%.*]] = phi <3 x float> [ [[RES_1]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD4-NEXT: ret void
+;
+; THRESHOLD5-LABEL: define amdgpu_cs void @folding_selects_32b(
+; THRESHOLD5-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD5-NEXT: [[DOTENTRY:.*]]:
+; THRESHOLD5-NEXT: [[A:%.*]] = insertelement <3 x float> zeroinitializer, float 0.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[B:%.*]] = insertelement <3 x float> zeroinitializer, float 1.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[C:%.*]] = insertelement <3 x float> zeroinitializer, float 2.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD5-NEXT: br i1 [[COND_0]], label %[[BLOCK_D:.*]], label %[[BLOCK_B:.*]]
+; THRESHOLD5: [[BLOCK_B]]:
+; THRESHOLD5-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD5-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x float> [[B]], <3 x float> [[C]]
+; THRESHOLD5-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x float> [[C]], <3 x float> [[B]]
+; THRESHOLD5-NEXT: br label %[[BLOCK_D]]
+; THRESHOLD5: [[BLOCK_D]]:
+; THRESHOLD5-NEXT: [[RES_PHI0:%.*]] = phi <3 x float> [ [[RES_0]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD5-NEXT: [[RES_PHI1:%.*]] = phi <3 x float> [ [[RES_1]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD5-NEXT: ret void
+;
+; THRESHOLD7-LABEL: define amdgpu_cs void @folding_selects_32b(
+; THRESHOLD7-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD7-NEXT: [[DOTENTRY:.*:]]
+; THRESHOLD7-NEXT: [[A:%.*]] = insertelement <3 x float> zeroinitializer, float 0.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[B:%.*]] = insertelement <3 x float> zeroinitializer, float 1.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[C:%.*]] = insertelement <3 x float> zeroinitializer, float 2.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD7-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD7-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x float> [[B]], <3 x float> [[C]]
+; THRESHOLD7-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x float> [[C]], <3 x float> [[B]]
+; THRESHOLD7-NEXT: [[RES_PHI0:%.*]] = select i1 [[COND_0]], <3 x float> [[A]], <3 x float> [[RES_0]]
+; THRESHOLD7-NEXT: [[RES_PHI1:%.*]] = select i1 [[COND_0]], <3 x float> [[A]], <3 x float> [[RES_1]]
+; THRESHOLD7-NEXT: ret void
+;
+; THRESHOLD13-LABEL: define amdgpu_cs void @folding_selects_32b(
+; THRESHOLD13-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD13-NEXT: [[DOTENTRY:.*:]]
+; THRESHOLD13-NEXT: [[A:%.*]] = insertelement <3 x float> zeroinitializer, float 0.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[B:%.*]] = insertelement <3 x float> zeroinitializer, float 1.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[C:%.*]] = insertelement <3 x float> zeroinitializer, float 2.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD13-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD13-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x float> [[B]], <3 x float> [[C]]
+; THRESHOLD13-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x float> [[C]], <3 x float> [[B]]
+; THRESHOLD13-NEXT: [[RES_PHI0:%.*]] = select i1 [[COND_0]], <3 x float> [[A]], <3 x float> [[RES_0]]
+; THRESHOLD13-NEXT: [[RES_PHI1:%.*]] = select i1 [[COND_0]], <3 x float> [[A]], <3 x float> [[RES_1]]
+; THRESHOLD13-NEXT: ret void
+;
+.entry:
+ %a = insertelement <3 x float> zeroinitializer, float 0.000000e+00, i64 0
+ %b = insertelement <3 x float> zeroinitializer, float 1.000000e+00, i64 0
+ %c = insertelement <3 x float> zeroinitializer, float 2.000000e+00, i64 0
+ %cond.0 = icmp eq i32 %val.0, 0
+ br i1 %cond.0, label %block.a, label %block.b
+
+block.a: ; preds = %.entry
+ br label %block.c
+
+block.b: ; preds = %.entry
+ %cond.1 = icmp eq i32 %val.0, 1
+ %res.0 = select i1 %cond.1, <3 x float> %b, <3 x float> %c
+ %res.1 = select i1 %cond.1, <3 x float> %c, <3 x float> %b
+ br label %block.c
+
+block.c: ; preds = %block.b, %block.a
+ %res.phi0 = phi <3 x float> [ %a, %block.a ], [ %res.0, %block.b ]
+ %res.phi1 = phi <3 x float> [ %a, %block.a ], [ %res.1, %block.b ]
+ br label %block.d
+
+block.d: ; preds = %block.c
+ ret void
+}
+
+define amdgpu_cs void @folding_selects_64b(i32 %val.0) {
+; THRESHOLD4-LABEL: define amdgpu_cs void @folding_selects_64b(
+; THRESHOLD4-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD4-NEXT: [[DOTENTRY:.*]]:
+; THRESHOLD4-NEXT: [[A:%.*]] = insertelement <3 x double> zeroinitializer, double 0.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[B:%.*]] = insertelement <3 x double> zeroinitializer, double 1.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[C:%.*]] = insertelement <3 x double> zeroinitializer, double 2.000000e+00, i64 0
+; THRESHOLD4-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD4-NEXT: br i1 [[COND_0]], label %[[BLOCK_D:.*]], label %[[BLOCK_B:.*]]
+; THRESHOLD4: [[BLOCK_B]]:
+; THRESHOLD4-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD4-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x double> [[B]], <3 x double> [[C]]
+; THRESHOLD4-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x double> [[C]], <3 x double> [[B]]
+; THRESHOLD4-NEXT: br label %[[BLOCK_D]]
+; THRESHOLD4: [[BLOCK_D]]:
+; THRESHOLD4-NEXT: [[RES_PHI0:%.*]] = phi <3 x double> [ [[RES_0]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD4-NEXT: [[RES_PHI1:%.*]] = phi <3 x double> [ [[RES_1]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD4-NEXT: ret void
+;
+; THRESHOLD5-LABEL: define amdgpu_cs void @folding_selects_64b(
+; THRESHOLD5-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD5-NEXT: [[DOTENTRY:.*]]:
+; THRESHOLD5-NEXT: [[A:%.*]] = insertelement <3 x double> zeroinitializer, double 0.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[B:%.*]] = insertelement <3 x double> zeroinitializer, double 1.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[C:%.*]] = insertelement <3 x double> zeroinitializer, double 2.000000e+00, i64 0
+; THRESHOLD5-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD5-NEXT: br i1 [[COND_0]], label %[[BLOCK_D:.*]], label %[[BLOCK_B:.*]]
+; THRESHOLD5: [[BLOCK_B]]:
+; THRESHOLD5-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD5-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x double> [[B]], <3 x double> [[C]]
+; THRESHOLD5-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x double> [[C]], <3 x double> [[B]]
+; THRESHOLD5-NEXT: br label %[[BLOCK_D]]
+; THRESHOLD5: [[BLOCK_D]]:
+; THRESHOLD5-NEXT: [[RES_PHI0:%.*]] = phi <3 x double> [ [[RES_0]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD5-NEXT: [[RES_PHI1:%.*]] = phi <3 x double> [ [[RES_1]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD5-NEXT: ret void
+;
+; THRESHOLD7-LABEL: define amdgpu_cs void @folding_selects_64b(
+; THRESHOLD7-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD7-NEXT: [[DOTENTRY:.*]]:
+; THRESHOLD7-NEXT: [[A:%.*]] = insertelement <3 x double> zeroinitializer, double 0.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[B:%.*]] = insertelement <3 x double> zeroinitializer, double 1.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[C:%.*]] = insertelement <3 x double> zeroinitializer, double 2.000000e+00, i64 0
+; THRESHOLD7-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD7-NEXT: br i1 [[COND_0]], label %[[BLOCK_D:.*]], label %[[BLOCK_B:.*]]
+; THRESHOLD7: [[BLOCK_B]]:
+; THRESHOLD7-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD7-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x double> [[B]], <3 x double> [[C]]
+; THRESHOLD7-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x double> [[C]], <3 x double> [[B]]
+; THRESHOLD7-NEXT: br label %[[BLOCK_D]]
+; THRESHOLD7: [[BLOCK_D]]:
+; THRESHOLD7-NEXT: [[RES_PHI0:%.*]] = phi <3 x double> [ [[RES_0]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD7-NEXT: [[RES_PHI1:%.*]] = phi <3 x double> [ [[RES_1]], %[[BLOCK_B]] ], [ [[A]], %[[DOTENTRY]] ]
+; THRESHOLD7-NEXT: ret void
+;
+; THRESHOLD13-LABEL: define amdgpu_cs void @folding_selects_64b(
+; THRESHOLD13-SAME: i32 [[VAL_0:%.*]]) {
+; THRESHOLD13-NEXT: [[DOTENTRY:.*:]]
+; THRESHOLD13-NEXT: [[A:%.*]] = insertelement <3 x double> zeroinitializer, double 0.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[B:%.*]] = insertelement <3 x double> zeroinitializer, double 1.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[C:%.*]] = insertelement <3 x double> zeroinitializer, double 2.000000e+00, i64 0
+; THRESHOLD13-NEXT: [[COND_0:%.*]] = icmp eq i32 [[VAL_0]], 0
+; THRESHOLD13-NEXT: [[COND_1:%.*]] = icmp eq i32 [[VAL_0]], 1
+; THRESHOLD13-NEXT: [[RES_0:%.*]] = select i1 [[COND_1]], <3 x double> [[B]], <3 x double> [[C]]
+; THRESHOLD13-NEXT: [[RES_1:%.*]] = select i1 [[COND_1]], <3 x double> [[C]], <3 x double> [[B]]
+; THRESHOLD13-NEXT: [[RES_PHI0:%.*]] = select i1 [[COND_0]], <3 x double> [[A]], <3 x double> [[RES_0]]
+; THRESHOLD13-NEXT: [[RES_PHI1:%.*]] = select i1 [[COND_0]], <3 x double> [[A]], <3 x double> [[RES_1]]
+; THRESHOLD13-NEXT: ret void
+;
+.entry:
+ %a = insertelement <3 x double> zeroinitializer, double 0.000000e+00, i64 0
+ %b = insertelement <3 x double> zeroinitializer, double 1.000000e+00, i64 0
+ %c = insertelement <3 x double> zeroinitializer, double 2.000000e+00, i64 0
+ %cond.0 = icmp eq i32 %val.0, 0
+ br i1 %cond.0, label %block.a, label %block.b
+
+block.a: ; preds = %.entry
+ br label %block.c
+
+block.b: ; preds = %.entry
+ %cond.1 = icmp eq i32 %val.0, 1
+ %res.0 = select i1 %cond.1, <3 x double> %b, <3 x double> %c
+ %res.1 = select i1 %cond.1, <3 x double> %c, <3 x double> %b
+ br label %block.c
+
+block.c: ; preds = %block.b, %block.a
+ %res.phi0 = phi <3 x double> [ %a, %block.a ], [ %res.0, %block.b ]
+ %res.phi1 = phi <3 x double> [ %a, %block.a ], [ %res.1, %block.b ]
+ br label %block.d
+
+block.d: ; preds = %block.c
+ ret void
+}
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