[llvm] [RISCV][MC] Require H for HINVAL instructions (PR #223588)

[Zeyi Xu via llvm-commits]

https://github.com/zeyi2 updated https://github.com/llvm/llvm-project/pull/223588

>From 4249dbd4505b1cd73db376ae6f17eabe766507b0 Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Tue, 15 Sep 2026 11:15:09 +0800
Subject: [PATCH 1/2] [RISCV][MC] Require H for HINVAL instructions

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td |  5 ++++-
 llvm/test/MC/RISCV/hinval-invalid.s     | 16 ++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/RISCV/hinval-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index a9dafff24862c..6518011d115f8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1048,9 +1048,12 @@ def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>, Sched<[]> {
   let rs2 = 0b00001;
 }
 def SINVAL_VMA  : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>;
+} // Predicates = [HasStdExtSvinval]
+
+let Predicates = [HasStdExtH, HasStdExtSvinval] in {
 def HINVAL_VVMA : Priv_rr<"hinval.vvma", 0b0010011>, Sched<[]>;
 def HINVAL_GVMA : Priv_rr<"hinval.gvma", 0b0110011>, Sched<[]>;
-} // Predicates = [HasStdExtSvinval]
+} // Predicates = [HasStdExtH, HasStdExtSvinval]
 
 def SFENCE_VMA  : Priv_rr<"sfence.vma", 0b0001001>, Sched<[]>;
 
diff --git a/llvm/test/MC/RISCV/hinval-invalid.s b/llvm/test/MC/RISCV/hinval-invalid.s
new file mode 100644
index 0000000000000..d52c04a57f83d
--- /dev/null
+++ b/llvm/test/MC/RISCV/hinval-invalid.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+svinval < %s 2>&1 \
+# RUN:     | FileCheck %s --check-prefix=NO-H
+# RUN: not llvm-mc -triple=riscv64 -mattr=+svinval < %s 2>&1 \
+# RUN:     | FileCheck %s --check-prefix=NO-H
+# RUN: not llvm-mc -triple=riscv32 -mattr=+h < %s 2>&1 \
+# RUN:     | FileCheck %s --check-prefix=NO-SVINVAL
+# RUN: not llvm-mc -triple=riscv64 -mattr=+h < %s 2>&1 \
+# RUN:     | FileCheck %s --check-prefix=NO-SVINVAL
+
+hinval.vvma a0, a1
+# NO-H: :[[@LINE-1]]:1: error: instruction requires the following: 'H' (Hypervisor)
+# NO-SVINVAL: :[[@LINE-2]]:1: error: instruction requires the following: 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
+
+hinval.gvma a0, a1
+# NO-H: :[[@LINE-1]]:1: error: instruction requires the following: 'H' (Hypervisor)
+# NO-SVINVAL: :[[@LINE-2]]:1: error: instruction requires the following: 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)

>From b633074c4fc97832218f3d8c0a95ef4b1abff15c Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Tue, 15 Sep 2026 14:50:38 +0800
Subject: [PATCH 2/2] address feedback, thanks lenary

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 6518011d115f8..3a7ed150ea063 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1048,12 +1048,12 @@ def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>, Sched<[]> {
   let rs2 = 0b00001;
 }
 def SINVAL_VMA  : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>;
-} // Predicates = [HasStdExtSvinval]
 
-let Predicates = [HasStdExtH, HasStdExtSvinval] in {
+let append Predicates = [HasStdExtH] in {
 def HINVAL_VVMA : Priv_rr<"hinval.vvma", 0b0010011>, Sched<[]>;
 def HINVAL_GVMA : Priv_rr<"hinval.gvma", 0b0110011>, Sched<[]>;
-} // Predicates = [HasStdExtH, HasStdExtSvinval]
+} // append Predicates = [HasStdExtH]
+} // Predicates = [HasStdExtSvinval]
 
 def SFENCE_VMA  : Priv_rr<"sfence.vma", 0b0001001>, Sched<[]>;