[llvm] 8e38a37 - [RISCV] Improve the earlyclobber constraint for vector index load. (#223565)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 22:48:02 PDT 2026
Author: Craig Topper
Date: 2026-09-14T22:47:56-07:00
New Revision: 8e38a37adaf935561d6fe8d7e2323a4042cee556
URL: https://github.com/llvm/llvm-project/commit/8e38a37adaf935561d6fe8d7e2323a4042cee556
DIFF: https://github.com/llvm/llvm-project/commit/8e38a37adaf935561d6fe8d7e2323a4042cee556.diff
LOG: [RISCV] Improve the earlyclobber constraint for vector index load. (#223565)
When the data EEW is smaller than the index EEW, the destination may
overlap the index operand as long as the overlap is in the
lowest-numbered part of the index register group. If the index EMUL is
no larger than 1 then both operands are a single register, so any
overlap is necessarily the lowest-numbered part and no constraint is
needed.
Assisted-by: Claude
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vloxei.ll
llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vluxei.ll
llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 86ea79581e7a6..c6241f582de67 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1898,15 +1898,23 @@ multiclass VPseudoILoad<bit Ordered> {
defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
defvar Vreg = dataEMUL.vrclass;
defvar IdxVreg = idxEMUL.vrclass;
- defvar HasConstraint = !ne(dataEEW, idxEEW);
- defvar TypeConstraints =
+ // When the data EEW is smaller than the index EEW, the destination
+ // may overlap the index operand as long as the overlap is in the
+ // lowest-numbered part of the index register group. If the index
+ // EMUL is no larger than 1 then both operands are a single register,
+ // so any overlap is necessarily the lowest-numbered part and no
+ // constraint is needed.
+ defvar EarlyClobber = !if(!lt(dataEEW, idxEEW),
+ !gt(idxEMULOctuple, 8),
+ !ne(dataEEW, idxEEW));
+ defvar TypeConstraints =
!if(!eq(dataEEW, idxEEW), 1, !if(!gt(dataEEW, idxEEW), !if(!ge(idxEMULOctuple, 8), 3, 1), 2));
let VLMul = dataEMUL.value in {
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
- VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
+ VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, EarlyClobber, TypeConstraints>,
VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
- VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
+ VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, EarlyClobber, TypeConstraints>,
RISCVMaskedPseudo<MaskIdx=3>,
VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
index 48b162078ea86..a2746c365ca2f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
@@ -144,8 +143,7 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
@@ -280,8 +278,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
@@ -548,8 +545,7 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(ptr %0, <
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
@@ -684,8 +680,7 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(ptr %0,
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
index 6b676890bcb65..d0ac41e64aa87 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
@@ -42,8 +41,7 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
@@ -178,8 +176,7 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
@@ -212,8 +209,7 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
@@ -652,8 +648,7 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, <
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
@@ -686,8 +681,7 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, <
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
@@ -1126,8 +1120,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vloxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
@@ -1160,8 +1153,7 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vloxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
@@ -1194,8 +1186,7 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vloxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
index 0c4afaf0a7397..593ba37140e05 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
@@ -144,8 +143,7 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
@@ -280,8 +278,7 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
@@ -548,8 +545,7 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(ptr %0, <
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
@@ -684,8 +680,7 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(ptr %0,
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
index ce6ba6c3209d8..c44d34b112e6b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
@@ -42,8 +41,7 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
@@ -178,8 +176,7 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
@@ -212,8 +209,7 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
@@ -652,8 +648,7 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, <
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
@@ -686,8 +681,7 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, <
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
@@ -1126,8 +1120,7 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vluxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
@@ -1160,8 +1153,7 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vluxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
@@ -1194,8 +1186,7 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vluxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index e8a117ac53377..5f99971612eb5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -516,8 +516,7 @@ define <4 x i8> @mgather_truemask_v4i8(<4 x ptr> %ptrs, <4 x i8> %passthru) {
; RV32-LABEL: mgather_truemask_v4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_truemask_v4i8:
@@ -1197,8 +1196,7 @@ define <4 x i16> @mgather_truemask_v4i16(<4 x ptr> %ptrs, <4 x i16> %passthru) {
; RV32-LABEL: mgather_truemask_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_truemask_v4i16:
@@ -6945,8 +6943,7 @@ define <4 x bfloat> @mgather_truemask_v4bf16(<4 x ptr> %ptrs, <4 x bfloat> %pass
; RV32-LABEL: mgather_truemask_v4bf16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_truemask_v4bf16:
@@ -7901,8 +7898,7 @@ define <4 x half> @mgather_truemask_v4f16(<4 x ptr> %ptrs, <4 x half> %passthru)
; RV32-LABEL: mgather_truemask_v4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_truemask_v4f16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
index db2dae784b213..f719bd674cc8c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
@@ -12,15 +12,13 @@ define <2 x i8> @vpgather_v2i8(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -156,8 +154,7 @@ define <3 x i8> @vpgather_v3i8(<3 x ptr> %ptrs, <3 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_v3i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v3i8:
@@ -174,8 +171,7 @@ define <3 x i8> @vpgather_truemask_v3i8(<3 x ptr> %ptrs, i32 zeroext %evl) {
; RV32-LABEL: vpgather_truemask_v3i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v3i8:
@@ -192,8 +188,7 @@ define <4 x i8> @vpgather_v4i8(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_v4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4i8:
@@ -210,8 +205,7 @@ define <4 x i8> @vpgather_truemask_v4i8(<4 x ptr> %ptrs, i32 zeroext %evl) {
; RV32-LABEL: vpgather_truemask_v4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4i8:
@@ -310,15 +304,13 @@ define <2 x i16> @vpgather_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl)
; RV32-LABEL: vpgather_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -412,8 +404,7 @@ define <4 x i16> @vpgather_v4i16(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl)
; RV32-LABEL: vpgather_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4i16:
@@ -430,8 +421,7 @@ define <4 x i16> @vpgather_truemask_v4i16(<4 x ptr> %ptrs, i32 zeroext %evl) {
; RV32-LABEL: vpgather_truemask_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4i16:
@@ -563,8 +553,7 @@ define <2 x i32> @vpgather_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl)
; RV64-LABEL: vpgather_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -1134,15 +1123,13 @@ define <2 x bfloat> @vpgather_v2bf16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %
; RV32-LABEL: vpgather_v2bf16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2bf16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <2 x bfloat> @llvm.vp.gather.v2bf16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x bfloat> %v
@@ -1152,8 +1139,7 @@ define <4 x bfloat> @vpgather_v4bf16(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %
; RV32-LABEL: vpgather_v4bf16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4bf16:
@@ -1170,8 +1156,7 @@ define <4 x bfloat> @vpgather_truemask_v4bf16(<4 x ptr> %ptrs, i32 zeroext %evl)
; RV32-LABEL: vpgather_truemask_v4bf16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4bf16:
@@ -1297,15 +1282,13 @@ define <2 x half> @vpgather_v2f16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <2 x half> @llvm.vp.gather.v2f16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x half> %v
@@ -1315,8 +1298,7 @@ define <4 x half> @vpgather_v4f16(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4f16:
@@ -1333,8 +1315,7 @@ define <4 x half> @vpgather_truemask_v4f16(<4 x ptr> %ptrs, i32 zeroext %evl) {
; RV32-LABEL: vpgather_truemask_v4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4f16:
@@ -1466,8 +1447,7 @@ define <2 x float> @vpgather_v2f32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %ev
; RV64-LABEL: vpgather_v2f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <2 x float> @llvm.vp.gather.v2f32.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x float> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll b/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
index 2daba2d57367f..fbdfcea6cc511 100644
--- a/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
@@ -338,32 +338,28 @@ define <vscale x 1 x i8> @test_nontemporal_vp_gather_nxv1i8_P1(<vscale x 1 x ptr
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64V-NEXT: ntl.p1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i8_P1:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32V-NEXT: ntl.p1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i8_P1:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i8_P1:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.p1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !1
ret <vscale x 1 x i8> %x
@@ -375,32 +371,28 @@ define <vscale x 1 x i8> @test_nontemporal_vp_gather_nxv1i8_PALL(<vscale x 1 x p
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64V-NEXT: ntl.pall
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i8_PALL:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32V-NEXT: ntl.pall
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i8_PALL:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i8_PALL:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.pall
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !2
ret <vscale x 1 x i8> %x
@@ -412,32 +404,28 @@ define <vscale x 1 x i8> @test_nontemporal_vp_gather_nxv1i8_S1(<vscale x 1 x ptr
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64V-NEXT: ntl.s1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i8_S1:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32V-NEXT: ntl.s1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i8_S1:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i8_S1:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.s1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !3
ret <vscale x 1 x i8> %x
@@ -449,32 +437,28 @@ define <vscale x 1 x i8> @test_nontemporal_vp_gather_nxv1i8_ALL(<vscale x 1 x pt
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i8_ALL:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i8_ALL:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i8_ALL:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !4
ret <vscale x 1 x i8> %x
@@ -485,32 +469,28 @@ define <vscale x 1 x i8> @test_nontemporal_vp_gather_nxv1i8_DEFAULT(<vscale x 1
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i8_DEFAULT:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i8_DEFAULT:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i8_DEFAULT:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0
ret <vscale x 1 x i8> %x
@@ -1342,32 +1322,28 @@ define <vscale x 1 x i16> @test_nontemporal_vp_gather_nxv1i16_P1(<vscale x 1 x p
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64V-NEXT: ntl.p1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i16_P1:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.p1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i16_P1:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i16_P1:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.p1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !1
ret <vscale x 1 x i16> %x
@@ -1379,32 +1355,28 @@ define <vscale x 1 x i16> @test_nontemporal_vp_gather_nxv1i16_PALL(<vscale x 1 x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64V-NEXT: ntl.pall
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i16_PALL:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.pall
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i16_PALL:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i16_PALL:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.pall
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !2
ret <vscale x 1 x i16> %x
@@ -1416,32 +1388,28 @@ define <vscale x 1 x i16> @test_nontemporal_vp_gather_nxv1i16_S1(<vscale x 1 x p
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64V-NEXT: ntl.s1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i16_S1:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.s1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i16_S1:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i16_S1:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.s1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !3
ret <vscale x 1 x i16> %x
@@ -1453,32 +1421,28 @@ define <vscale x 1 x i16> @test_nontemporal_vp_gather_nxv1i16_ALL(<vscale x 1 x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i16_ALL:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i16_ALL:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i16_ALL:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !4
ret <vscale x 1 x i16> %x
@@ -1489,32 +1453,28 @@ define <vscale x 1 x i16> @test_nontemporal_vp_gather_nxv1i16_DEFAULT(<vscale x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i16_DEFAULT:
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv1i16_DEFAULT:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i16_DEFAULT:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> splat(i1 true), i32 %vl), !nontemporal !0
ret <vscale x 1 x i16> %x
@@ -2346,8 +2306,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_P1(<vscale x 1 x p
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.p1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i32_P1:
@@ -2361,8 +2320,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_P1(<vscale x 1 x p
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i32_P1:
@@ -2381,8 +2339,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_PALL(<vscale x 1 x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.pall
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i32_PALL:
@@ -2396,8 +2353,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_PALL(<vscale x 1 x
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i32_PALL:
@@ -2416,8 +2372,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_S1(<vscale x 1 x p
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.s1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i32_S1:
@@ -2431,8 +2386,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_S1(<vscale x 1 x p
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i32_S1:
@@ -2451,8 +2405,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_ALL(<vscale x 1 x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i32_ALL:
@@ -2466,8 +2419,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_ALL(<vscale x 1 x
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i32_ALL:
@@ -2485,8 +2437,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_DEFAULT(<vscale x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1i32_DEFAULT:
@@ -2500,8 +2451,7 @@ define <vscale x 1 x i32> @test_nontemporal_vp_gather_nxv1i32_DEFAULT(<vscale x
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1i32_DEFAULT:
@@ -4334,8 +4284,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_P1(<vscale x 1 x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.p1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1f32_P1:
@@ -4349,8 +4298,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_P1(<vscale x 1 x
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1f32_P1:
@@ -4369,8 +4317,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_PALL(<vscale x 1
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.pall
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1f32_PALL:
@@ -4384,8 +4331,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_PALL(<vscale x 1
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1f32_PALL:
@@ -4404,8 +4350,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_S1(<vscale x 1 x
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.s1
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1f32_S1:
@@ -4419,8 +4364,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_S1(<vscale x 1 x
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1f32_S1:
@@ -4439,8 +4383,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_ALL(<vscale x 1
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1f32_ALL:
@@ -4454,8 +4397,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_ALL(<vscale x 1
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1f32_ALL:
@@ -4473,8 +4415,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_DEFAULT(<vscale
; CHECK-RV64V: # %bb.0:
; CHECK-RV64V-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64V-NEXT: ntl.all
-; CHECK-RV64V-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64V-NEXT: vmv1r.v v8, v9
+; CHECK-RV64V-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64V-NEXT: ret
;
; CHECK-RV32V-LABEL: test_nontemporal_vp_gather_nxv1f32_DEFAULT:
@@ -4488,8 +4429,7 @@ define <vscale x 1 x float> @test_nontemporal_vp_gather_nxv1f32_DEFAULT(<vscale
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
-; CHECK-RV64VC-NEXT: vluxei64.v v9, (zero), v8
-; CHECK-RV64VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV64VC-NEXT: vluxei64.v v8, (zero), v8
; CHECK-RV64VC-NEXT: ret
;
; CHECK-RV32VC-LABEL: test_nontemporal_vp_gather_nxv1f32_DEFAULT:
@@ -6330,8 +6270,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_P1(<vscale x 2 x ptr
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.p1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i8_P1:
@@ -6346,8 +6285,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_P1(<vscale x 2 x ptr
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.p1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !1
ret <vscale x 2 x i8> %x
@@ -6367,8 +6305,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_PALL(<vscale x 2 x p
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.pall
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i8_PALL:
@@ -6383,8 +6320,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_PALL(<vscale x 2 x p
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.pall
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !2
ret <vscale x 2 x i8> %x
@@ -6404,8 +6340,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_S1(<vscale x 2 x ptr
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.s1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i8_S1:
@@ -6420,8 +6355,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_S1(<vscale x 2 x ptr
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.s1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !3
ret <vscale x 2 x i8> %x
@@ -6441,8 +6375,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_ALL(<vscale x 2 x pt
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i8_ALL:
@@ -6457,8 +6390,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_ALL(<vscale x 2 x pt
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !4
ret <vscale x 2 x i8> %x
@@ -6477,8 +6409,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_DEFAULT(<vscale x 2
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i8_DEFAULT:
@@ -6493,8 +6424,7 @@ define <vscale x 2 x i8> @test_nontemporal_vp_gather_nxv2i8_DEFAULT(<vscale x 2
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0
ret <vscale x 2 x i8> %x
@@ -7334,8 +7264,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_P1(<vscale x 2 x p
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32V-NEXT: ntl.p1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i16_P1:
@@ -7350,8 +7279,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_P1(<vscale x 2 x p
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.p1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !1
ret <vscale x 2 x i16> %x
@@ -7371,8 +7299,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_PALL(<vscale x 2 x
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32V-NEXT: ntl.pall
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i16_PALL:
@@ -7387,8 +7314,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_PALL(<vscale x 2 x
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.pall
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !2
ret <vscale x 2 x i16> %x
@@ -7408,8 +7334,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_S1(<vscale x 2 x p
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32V-NEXT: ntl.s1
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i16_S1:
@@ -7424,8 +7349,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_S1(<vscale x 2 x p
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.s1
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !3
ret <vscale x 2 x i16> %x
@@ -7445,8 +7369,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_ALL(<vscale x 2 x
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i16_ALL:
@@ -7461,8 +7384,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_ALL(<vscale x 2 x
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0, !riscv-nontemporal-domain !4
ret <vscale x 2 x i16> %x
@@ -7481,8 +7403,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_DEFAULT(<vscale x
; CHECK-RV32V: # %bb.0:
; CHECK-RV32V-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32V-NEXT: ntl.all
-; CHECK-RV32V-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32V-NEXT: vmv1r.v v8, v9
+; CHECK-RV32V-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32V-NEXT: ret
;
; CHECK-RV64VC-LABEL: test_nontemporal_vp_gather_nxv2i16_DEFAULT:
@@ -7497,8 +7418,7 @@ define <vscale x 2 x i16> @test_nontemporal_vp_gather_nxv2i16_DEFAULT(<vscale x
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
-; CHECK-RV32VC-NEXT: vluxei32.v v9, (zero), v8
-; CHECK-RV32VC-NEXT: vmv1r.v v8, v9
+; CHECK-RV32VC-NEXT: vluxei32.v v8, (zero), v8
; CHECK-RV32VC-NEXT: ret
%x = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> splat(i1 true), i32 %vl), !nontemporal !0
ret <vscale x 2 x i16> %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
index d2fba96381bf2..a5d9fab3ba908 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
@@ -144,8 +143,7 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
@@ -280,8 +278,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
@@ -548,8 +545,7 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(ptr %0, <
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
@@ -684,8 +680,7 @@ define <vscale x 1 x bfloat> @intrinsic_vloxei_v_nxv1bf16_nxv1bf16_nxv1i64(ptr %
; CHECK-LABEL: intrinsic_vloxei_v_nxv1bf16_nxv1bf16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.nxv1i64(
@@ -820,8 +815,7 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(ptr %0,
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vloxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei.ll
index d76db678ced7f..acb88f5e54624 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vloxei.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vloxei.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
@@ -42,8 +41,7 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
@@ -178,8 +176,7 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
@@ -212,8 +209,7 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
@@ -649,8 +645,7 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, <
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
@@ -683,8 +678,7 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, <
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
@@ -1120,8 +1114,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vloxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
@@ -1154,8 +1147,7 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vloxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
@@ -1188,8 +1180,7 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vloxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
@@ -3277,8 +3268,7 @@ define <vscale x 1 x bfloat> @intrinsic_vloxei_v_nxv1bf16_nxv1bf16_nxv1i32(ptr %
; CHECK-LABEL: intrinsic_vloxei_v_nxv1bf16_nxv1bf16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.nxv1i32(
@@ -3311,8 +3301,7 @@ define <vscale x 2 x bfloat> @intrinsic_vloxei_v_nxv2bf16_nxv2bf16_nxv2i32(ptr %
; CHECK-LABEL: intrinsic_vloxei_v_nxv2bf16_nxv2bf16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vloxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.nxv2i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
index 720e9759e52ac..1d4800281cc95 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
@@ -144,8 +143,7 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
@@ -280,8 +278,7 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
@@ -548,8 +545,7 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(ptr %0, <
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
@@ -684,8 +680,7 @@ define <vscale x 1 x bfloat> @intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i64(ptr %
; CHECK-LABEL: intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.nxv1i64(
@@ -820,8 +815,7 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(ptr %0,
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vluxei64.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei.ll
index 2360cc1f9dd4c..afb8e52099466 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vluxei.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vluxei.ll
@@ -8,8 +8,7 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
@@ -42,8 +41,7 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
@@ -178,8 +176,7 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
@@ -212,8 +209,7 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <v
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
@@ -649,8 +645,7 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, <
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
@@ -683,8 +678,7 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, <
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
@@ -819,8 +813,7 @@ define <vscale x 1 x bfloat> @intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i32(ptr %
; CHECK-LABEL: intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.nxv1i32(
@@ -853,8 +846,7 @@ define <vscale x 2 x bfloat> @intrinsic_vluxei_v_nxv2bf16_nxv2bf16_nxv2i32(ptr %
; CHECK-LABEL: intrinsic_vluxei_v_nxv2bf16_nxv2bf16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vluxei32.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.nxv2i32(
@@ -1290,8 +1282,7 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vluxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
@@ -1324,8 +1315,7 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vluxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
@@ -1358,8 +1348,7 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vluxei16.v v9, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index 7da35085dc8a6..d4b22091a65c0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -16,15 +16,13 @@ define <vscale x 1 x i8> @vpgather_nxv1i8(<vscale x 1 x ptr> %ptrs, <vscale x 1
; RV32-LABEL: vpgather_nxv1i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -34,8 +32,7 @@ define <vscale x 2 x i8> @vpgather_nxv2i8(<vscale x 2 x ptr> %ptrs, <vscale x 2
; RV32-LABEL: vpgather_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8:
@@ -342,15 +339,13 @@ define <vscale x 1 x i16> @vpgather_nxv1i16(<vscale x 1 x ptr> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv1i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -360,8 +355,7 @@ define <vscale x 2 x i16> @vpgather_nxv2i16(<vscale x 2 x ptr> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i16:
@@ -628,8 +622,7 @@ define <vscale x 1 x i32> @vpgather_nxv1i32(<vscale x 1 x ptr> %ptrs, <vscale x
; RV64-LABEL: vpgather_nxv1i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.gather.nxv1i32.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1297,15 +1290,13 @@ define <vscale x 1 x bfloat> @vpgather_nxv1bf16(<vscale x 1 x ptr> %ptrs, <vscal
; RV32-LABEL: vpgather_nxv1bf16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1bf16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.gather.nxv1bf16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x bfloat> %v
@@ -1315,8 +1306,7 @@ define <vscale x 2 x bfloat> @vpgather_nxv2bf16(<vscale x 2 x ptr> %ptrs, <vscal
; RV32-LABEL: vpgather_nxv2bf16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2bf16:
@@ -1493,15 +1483,13 @@ define <vscale x 1 x half> @vpgather_nxv1f16(<vscale x 1 x ptr> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv1f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.gather.nxv1f16.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -1511,8 +1499,7 @@ define <vscale x 2 x half> @vpgather_nxv2f16(<vscale x 2 x ptr> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v9
+; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2f16:
@@ -1695,8 +1682,7 @@ define <vscale x 1 x float> @vpgather_nxv1f32(<vscale x 1 x ptr> %ptrs, <vscale
; RV64-LABEL: vpgather_nxv1f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v9
+; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret
%v = call <vscale x 1 x float> @llvm.vp.gather.nxv1f32.nxv1p0(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x float> %v
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