[llvm] [AMDGPU] Fix for GFX11 VOPD interlock hazard (PR #220348)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 21:59:18 PDT 2026
https://github.com/hidekisaito updated https://github.com/llvm/llvm-project/pull/220348
>From b41b19cd7792af84208464a38a8e119746c98b42 Mon Sep 17 00:00:00 2001
From: Hideki Saito <hidekido at amd.com>
Date: Tue, 1 Sep 2026 14:21:36 -0500
Subject: [PATCH] [AMDGPU] Fix for GFX11 VOPD interlock hazard
---
llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp | 7 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 8 +-
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 3 +-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll | 20 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 313 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 47 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 59 +-
.../AMDGPU/GlobalISel/insertelement.i16.ll | 46 +-
.../AMDGPU/GlobalISel/insertelement.i8.ll | 25 +-
.../llvm.amdgcn.image.atomic.dim.a16.ll | 6 +-
.../llvm.amdgcn.image.load.3d.a16.ll | 14 +-
.../CodeGen/AMDGPU/GlobalISel/llvm.powi.ll | 15 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 8 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 5 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll | 51 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 6 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 7966 +++++++++--------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 1338 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 2413 ++---
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 32 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll | 188 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 4647 +++++-----
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 581 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 782 +-
.../test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll | 14 +-
.../AMDGPU/amdgpu-cs-chain-preserve-cc.ll | 14 +-
.../AMDGPU/arbitrary-fp-to-float-fp8-hw.ll | 24 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 5026 +++++------
.../buffer-fat-pointer-atomicrmw-fadd.ll | 50 +-
.../buffer-fat-pointer-atomicrmw-fmax.ll | 20 +-
.../buffer-fat-pointer-atomicrmw-fmin.ll | 20 +-
.../CodeGen/AMDGPU/combine_andor_with_cmps.ll | 25 +-
.../AMDGPU/combine_andor_with_cmps_nnan.ll | 12 +-
.../CodeGen/AMDGPU/dagcombine-fma-fmad.ll | 39 +-
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 54 +-
.../AMDGPU/dual-source-blend-export.ll | 6 +-
llvm/test/CodeGen/AMDGPU/fabs.bf16.ll | 34 +-
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 81 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 199 +-
llvm/test/CodeGen/AMDGPU/fdiv.ll | 6 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fadd.ll | 252 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmax.ll | 158 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmin.ll | 158 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fsub.ll | 158 +-
llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll | 72 +-
llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll | 5 +-
llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll | 18 +-
llvm/test/CodeGen/AMDGPU/fmed3.ll | 20 +-
llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll | 72 +-
llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll | 5 +-
.../CodeGen/AMDGPU/fneg-modifier-casting.ll | 48 +-
llvm/test/CodeGen/AMDGPU/fneg.bf16.ll | 24 +-
llvm/test/CodeGen/AMDGPU/fp_to_uint.ll | 5 +-
llvm/test/CodeGen/AMDGPU/fpow.ll | 180 +-
llvm/test/CodeGen/AMDGPU/freeze-binary.ll | 98 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 10 +-
.../AMDGPU/gfx-callable-argument-types.ll | 16 +-
.../AMDGPU/gfx-callable-return-types.ll | 31 +-
.../CodeGen/AMDGPU/global-atomicrmw-fadd.ll | 329 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmax.ll | 188 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmin.ll | 188 +-
.../CodeGen/AMDGPU/global-atomicrmw-fsub.ll | 188 +-
llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll | 136 +-
.../AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll | 17 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll | 12 +-
.../test/CodeGen/AMDGPU/llvm.fptrunc.round.ll | 28 +-
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 66 +-
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 66 +-
llvm/test/CodeGen/AMDGPU/llvm.log2.ll | 8 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll | 15 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll | 26 +-
llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll | 15 +-
llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll | 26 +-
llvm/test/CodeGen/AMDGPU/llvm.mulo.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.powi.ll | 5 +-
llvm/test/CodeGen/AMDGPU/llvm.round.ll | 21 +-
.../CodeGen/AMDGPU/local-atomicrmw-fadd.ll | 24 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmax.ll | 24 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmin.ll | 24 +-
.../CodeGen/AMDGPU/local-atomicrmw-fsub.ll | 24 +-
llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll | 803 +-
llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll | 803 +-
llvm/test/CodeGen/AMDGPU/repeated-divisor.ll | 12 +-
llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 42 +-
llvm/test/CodeGen/AMDGPU/select.f16.ll | 30 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmax.ll | 54 +-
.../CodeGen/AMDGPU/vector-reduce-fmaximum.ll | 58 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmin.ll | 54 +-
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 58 +-
llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll | 6 +-
.../CodeGen/AMDGPU/vector_shuffle.packed.ll | 151 +-
llvm/test/CodeGen/AMDGPU/vopd-combine.mir | 261 +-
93 files changed, 14964 insertions(+), 14350 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 3def256f07f787..c2627db4766164 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -223,9 +223,14 @@ bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII,
MIX.getOpcode() == AMDGPU::V_MOV_B32_e32 &&
MIY.getOpcode() == AMDGPU::V_MOV_B32_e32;
+ // GFX11 destination-buffer forwarding can lose the interlock when the X/Y
+ // operands of SRC0 or SRC1 are distinct VGPRs with the same parity. Require
+ // opposite parity instead of merely different banks when forming the pair.
+ bool HasGFX11InterlockHazard = ST.hasGFX11Insts() && !ST.hasGFX12Insts();
+
// Check VGPR bank constraints for operand registers across both instructions.
if (InstInfo.hasInvalidOperand(GetVRegIdx, *TRI, SkipSrc, AllowSameVGPR,
- IsVOPD3))
+ IsVOPD3, HasGFX11InterlockHazard))
return false;
LLVM_DEBUG(dbgs() << "VOPD Reg Constraints Passed\n\tX: " << MIX
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 58ca7e69cecf80..3bc50b5017ecfd 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -976,8 +976,8 @@ unsigned ComponentInfo::getIndexInParsedOperands(unsigned CompOprIdx) const {
std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
- const MCRegisterInfo &MRI, bool SkipSrc, bool AllowSameVGPR,
- bool VOPD3) const {
+ const MCRegisterInfo &MRI, bool SkipSrc, bool AllowSameVGPR, bool VOPD3,
+ bool HasGFX11InterlockHazard) const {
auto OpXRegs = getRegIndices(ComponentIndex::X, GetRegIdx,
CompInfo[ComponentIndex::X].isVOP3());
@@ -1009,7 +1009,9 @@ std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
unsigned CompOprIdx;
for (CompOprIdx = 0; CompOprIdx < Component::MAX_OPR_NUM; ++CompOprIdx) {
unsigned BanksMasks = VOPD3 ? VOPD3_VGPR_BANK_MASKS[CompOprIdx]
- : VOPD_VGPR_BANK_MASKS[CompOprIdx];
+ : HasGFX11InterlockHazard
+ ? VOPD_GFX11_VGPR_BANK_MASKS[CompOprIdx]
+ : VOPD_VGPR_BANK_MASKS[CompOprIdx];
if (!OpXRegs[CompOprIdx] || !OpYRegs[CompOprIdx])
continue;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 22968c499e019b..309e5e0284b8c3 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -631,6 +631,10 @@ enum Component : unsigned {
// 4 banks result in a mask 3, setting 2 lower bits.
constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
constexpr unsigned VOPD3_VGPR_BANK_MASKS[] = {1, 3, 3, 3};
+// GFX11 VOPD interlock hazard requires SRC0/SRC1 to have
+// different parities, not just on different banks. Else,
+// non-deterministic forwarding error may occur.
+constexpr unsigned VOPD_GFX11_VGPR_BANK_MASKS[] = {1, 1, 1, 1};
enum ComponentIndex : unsigned { X = 0, Y = 1 };
constexpr unsigned COMPONENTS[] = {ComponentIndex::X, ComponentIndex::Y};
@@ -876,12 +880,15 @@ class InstInfo {
// even though it violates requirement to be from different banks.
// If \p VOPD3 is set to true both dst registers allowed to be either odd
// or even and instruction may have real src2 as opposed to tied accumulator.
+ // If \p HasGFX11InterlockHazard is set then X/Y SRC0 and SRC1 VGPRs
+ // must have different register-number parity.
bool
hasInvalidOperand(std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
const MCRegisterInfo &MRI, bool SkipSrc = false,
- bool AllowSameVGPR = false, bool VOPD3 = false) const {
+ bool AllowSameVGPR = false, bool VOPD3 = false,
+ bool HasGFX11InterlockHazard = false) const {
return getInvalidCompOperandIndex(GetRegIdx, MRI, SkipSrc, AllowSameVGPR,
- VOPD3)
+ VOPD3, HasGFX11InterlockHazard)
.has_value();
}
@@ -893,10 +900,13 @@ class InstInfo {
// even though it violates requirement to be from different banks.
// If \p VOPD3 is set to true both dst registers allowed to be either odd
// or even and instruction may have real src2 as opposed to tied accumulator.
+ // If \p HasGFX11InterlockHazard is set then X/Y SRC0 and SRC1 VGPRs
+ // must have different register-number parity.
std::optional<unsigned> getInvalidCompOperandIndex(
std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
const MCRegisterInfo &MRI, bool SkipSrc = false,
- bool AllowSameVGPR = false, bool VOPD3 = false) const;
+ bool AllowSameVGPR = false, bool VOPD3 = false,
+ bool HasGFX11InterlockHazard = false) const;
private:
RegIndices
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 8a4d6c1d67b4d8..2b6e3b5b692dbf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -1850,7 +1850,8 @@ define i65 @v_ashr_i65(i65 %value, i65 %amount) {
; GFX11-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5]
; GFX11-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5]
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v5
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, v1, s0
; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 32c30f76484e95..a42e915a4b4799 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -1741,8 +1741,8 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX11-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_add_f32 v3, v3, v6
; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
@@ -2034,8 +2034,8 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX11-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_add_f32 v3, v3, v6
; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
@@ -3112,8 +3112,8 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX11-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_add_f32 v3, v3, v6
; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
@@ -5687,8 +5687,8 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v6, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_add_f32 v3, v3, v6
; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
@@ -5992,8 +5992,8 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v6, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v3
; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_add_f32 v3, v3, v6
; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index 384868d0e706f1..c6bab22bf26412 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -177,8 +177,9 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v6, v3
@@ -467,14 +468,15 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_cmp_class_f32_e64 s4, v0, 24
; GFX11-NEXT: v_trunc_f32_e32 v8, v2
-; GFX11-NEXT: v_dual_mul_f32 v9, 0.5, v3 :: v_dual_and_b32 v10, 0x80000000, v1
+; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v1
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
; GFX11-NEXT: v_cmp_class_f32_e64 s5, v1, 24
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v9, 0.5, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v5, |v1|, v5
; GFX11-NEXT: v_log_f32_e32 v5, v5
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -1114,48 +1116,50 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v1
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v7
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v9
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0x80000000, v2
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v2, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v7
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v2, v5
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v7
; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v8, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_2)
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v2, v5
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, s1, exec_lo
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v3, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v13
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v1
-; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v9
; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v14
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, s1, exec_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
@@ -1587,55 +1591,60 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3
; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v9
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v1
+; GFX11-TRUE16-NEXT: s_xor_b32 s6, s1, exec_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v8
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v5
-; GFX11-TRUE16-NEXT: s_xor_b32 s6, s1, exec_lo
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v4, v5, v4 :: v_dual_cndmask_b32 v1, v2, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v9
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v5
; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v7
; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v7
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -2050,10 +2059,10 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v5.l
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
@@ -2071,30 +2080,31 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0x80000000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v8, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v5
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v13, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v12, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v13, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, vcc_lo
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v10, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v3, v1
; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -2125,15 +2135,17 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v7
; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -2151,38 +2163,39 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v5
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v7
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v6
; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v6
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v1
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v1
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, s0
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v12, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, 0x7fffffff, v3, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v10
; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
@@ -2528,10 +2541,10 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0x80000000, v2
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24
; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4
@@ -2549,45 +2562,47 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v8, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0
; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x80000000, v0
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v8
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x80000000, v0
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v8
; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v10, v5
+; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v13
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, v3, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -2599,86 +2614,87 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2|
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0x80000000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42000000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v8 :: v_dual_lshlrev_b32 v3, 5, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v3, v7, v3 :: v_dual_mul_dx9_zero_f32 v4, v6, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v7
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5
-; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v5
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v6
-; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v8, v1
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v1
+; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v6
; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v8, v1
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
+; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_or_b32 v10, 0x7fffffff, v3, v12
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v7
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v6
-; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v10, s0
; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0
-; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v9
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fneg = fneg <2 x half> %x
@@ -3328,8 +3344,9 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v0
; GFX11-NEXT: v_exp_f32_e32 v1, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v5, v2
@@ -4013,8 +4030,9 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v7, v3
@@ -4895,8 +4913,9 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v6, v3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index bf5d5cb5462fe5..7e4e9c6aeefe17 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -8543,8 +8543,7 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX11-NEXT: v_or_b32_e32 v0, v22, v24
; GFX11-NEXT: v_lshrrev_b64 v[16:17], v23, v[10:11]
; GFX11-NEXT: v_or_b32_e32 v22, v26, v28
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v23, v1, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v29
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v19, s1
@@ -8552,52 +8551,60 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX11-NEXT: v_cndmask_b32_e64 v10, v17, v22, s1
; GFX11-NEXT: v_cndmask_b32_e64 v22, v23, v3, s0
; GFX11-NEXT: v_and_b32_e32 v23, 0x7f, v20
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v8, vcc_lo
; GFX11-NEXT: v_bfi_b32 v20, v20, 0, 0x7f
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v3, v10, v9, vcc_lo
-; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
-; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v23
; GFX11-NEXT: v_cndmask_b32_e64 v24, 0, v0, s1
+; GFX11-NEXT: v_sub_nc_u32_e32 v10, 64, v23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_add_nc_u32_e32 v26, 0xffffffc0, v20
+; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v8, vcc_lo
+; GFX11-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
+; GFX11-NEXT: v_lshlrev_b64 v[12:13], v23, v[4:5]
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
; GFX11-NEXT: v_cndmask_b32_e64 v25, 0, v1, s1
; GFX11-NEXT: v_or_b32_e32 v0, v30, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v23
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
; GFX11-NEXT: v_lshl_or_b32 v9, v14, 31, v9
-; GFX11-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
-; GFX11-NEXT: v_add_nc_u32_e32 v26, 0xffffffc0, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v1, v18, v3
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v10, v[4:5]
; GFX11-NEXT: v_lshlrev_b64 v[10:11], v23, v[6:7]
+; GFX11-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX11-NEXT: v_lshlrev_b64 v[12:13], v23, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[8:9]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v23
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
; GFX11-NEXT: v_or_b32_e32 v10, v2, v10
+; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v23
; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
; GFX11-NEXT: v_or_b32_e32 v2, v21, v24
; GFX11-NEXT: v_or_b32_e32 v11, v3, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_dual_cndmask_b32 v12, 0, v12 :: v_dual_cndmask_b32 v21, v4, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v4, v10, vcc_lo
; GFX11-NEXT: v_lshrrev_b64 v[3:4], v26, v[14:15]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v10, v16, v18
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v23
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v10, s1
; GFX11-NEXT: v_lshrrev_b64 v[10:11], v20, v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; GFX11-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v8, s2
+; GFX11-NEXT: v_or_b32_e32 v3, v22, v25
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v8, v4, v9, s2
; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, v10, s1
; GFX11-NEXT: v_cndmask_b32_e64 v10, 0, v11, s1
-; GFX11-NEXT: v_or_b32_e32 v3, v22, v25
; GFX11-NEXT: v_or_b32_e32 v4, v12, v5
; GFX11-NEXT: v_or_b32_e32 v5, v13, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v6, v6, v9
; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 42c153ff5023af..6ae2b9f9e8e1b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -6651,8 +6651,8 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX11-NEXT: v_and_b32_e32 v12, 0x7f, v0
; GFX11-NEXT: v_lshlrev_b64 v[3:4], v11, s[8:9]
; GFX11-NEXT: v_lshrrev_b64 v[1:2], v1, s[0:1]
-; GFX11-NEXT: v_dual_cndmask_b32 v5, 0, v5 :: v_dual_add_nc_u32 v0, 0xffffffc0, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 0xffffffc0, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
; GFX11-NEXT: v_sub_nc_u32_e32 v9, 64, v12
; GFX11-NEXT: v_lshrrev_b64 v[7:8], v12, s[4:5]
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v12
@@ -8239,69 +8239,68 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX11-NEXT: v_add_nc_u32_e32 v19, 0xffffffc0, v25
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v25
; GFX11-NEXT: v_dual_cndmask_b32 v23, 0, v23 :: v_dual_cndmask_b32 v24, 0, v24
-; GFX11-NEXT: v_bfi_b32 v25, v20, 0, 0x7f
+; GFX11-NEXT: v_add_nc_u32_e32 v27, 0xffffffc0, v26
; GFX11-NEXT: v_or_b32_e32 v22, v18, v22
; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v26
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v21
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v19, v[0:1]
+; GFX11-NEXT: v_or_b32_e32 v21, v17, v21
; GFX11-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
-; GFX11-NEXT: v_and_b32_e32 v20, 0x7f, v20
+; GFX11-NEXT: v_bfi_b32 v25, v20, 0, 0x7f
; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_cndmask_b32 v21, v0, v21 :: v_dual_cndmask_b32 v22, v1, v22
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v26
; GFX11-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX11-NEXT: v_add_nc_u32_e32 v27, 0xffffffc0, v26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v21, v21, v2, s0
; GFX11-NEXT: v_or_b32_e32 v17, v17, v19
; GFX11-NEXT: v_cndmask_b32_e64 v22, v22, v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v26
-; GFX11-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 31, v5
; GFX11-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v20
-; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_cndmask_b32 v1, v1, v17
-; GFX11-NEXT: v_cndmask_b32_e32 v26, 0, v2, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v10
-; GFX11-NEXT: v_cndmask_b32_e32 v27, 0, v3, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v8, s0
; GFX11-NEXT: v_sub_nc_u32_e32 v8, 64, v25
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v10
+; GFX11-NEXT: v_dual_cndmask_b32 v26, 0, v2 :: v_dual_cndmask_b32 v27, 0, v3
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshrrev_b64 v[2:3], v8, v[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[8:9], v25, v[6:7]
; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
; GFX11-NEXT: v_lshlrev_b64 v[10:11], v25, v[4:5]
; GFX11-NEXT: v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT: v_lshrrev_b64 v[2:3], v8, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[8:9], v25, v[6:7]
-; GFX11-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v20
-; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v25
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
+; GFX11-NEXT: v_or_b32_e32 v1, v24, v1
; GFX11-NEXT: v_or_b32_e32 v8, v2, v8
; GFX11-NEXT: v_add_nc_u32_e32 v16, 0xffffffc0, v25
-; GFX11-NEXT: v_or_b32_e32 v2, v21, v26
; GFX11-NEXT: v_or_b32_e32 v9, v3, v9
-; GFX11-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
-; GFX11-NEXT: v_or_b32_e32 v1, v24, v1
+; GFX11-NEXT: v_or_b32_e32 v2, v21, v26
+; GFX11-NEXT: v_dual_cndmask_b32 v10, 0, v10 :: v_dual_cndmask_b32 v11, 0, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_and_b32 v20, 0x7f, v20
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v18, 64, v20
+; GFX11-NEXT: v_add_nc_u32_e32 v23, 0xffffffc0, v20
; GFX11-NEXT: v_lshrrev_b64 v[16:17], v20, v[12:13]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v21, v4, v8, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v20
+; GFX11-NEXT: v_lshlrev_b64 v[18:19], v18, v[14:15]
; GFX11-NEXT: v_lshrrev_b64 v[3:4], v23, v[14:15]
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v20
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
; GFX11-NEXT: v_or_b32_e32 v8, v16, v18
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v16, v17, v19
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v21, v6, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v8, s1
; GFX11-NEXT: v_lshrrev_b64 v[8:9], v20, v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v5, v7, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v5, v3, v12, s2
; GFX11-NEXT: v_or_b32_e32 v3, v22, v27
; GFX11-NEXT: v_cndmask_b32_e64 v12, v4, v13, s2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
index 0f963ba85b73e6..b74665f781b56c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
@@ -1585,21 +1585,20 @@ define amdgpu_ps void @insertelement_v_v4i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v4, 1, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_not_b32_e32 v3, v5
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v4, v4, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
@@ -2682,26 +2681,26 @@ define amdgpu_ps void @insertelement_v_v8i16_v_v(ptr addrspace(1) %ptr, i16 %val
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v3
-; GFX11-NEXT: v_mov_b32_e32 v9, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_and_b32 v0, 1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v4, v5 :: v_dual_lshlrev_b32 v0, 4, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-NEXT: v_lshlrev_b32_e64 v8, v0, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e32 v0, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v6, s0
; GFX11-NEXT: v_not_b32_e32 v2, v8
; GFX11-NEXT: v_mov_b32_e32 v8, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
; GFX11-NEXT: v_and_or_b32 v3, v3, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v3, s2
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
@@ -3365,9 +3364,10 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v13, 1, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: s_and_b32 s5, s4, 0xffff
-; GFX11-NEXT: v_dual_mov_b32 v11, 16 :: v_dual_and_b32 v0, 1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v11, 16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v13
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v13
@@ -3627,10 +3627,10 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[0:7], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT: v_mov_b32_e32 v13, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mov_b32 v13, 0 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX11-NEXT: v_mov_b32_e32 v12, 16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -3664,8 +3664,8 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX11-NEXT: v_and_or_b32 v15, v10, v1, v0
; GFX11-NEXT: v_mov_b32_e32 v10, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v12, 16 :: v_dual_cndmask_b32 v1, v3, v15
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v15, s6
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v15, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v15, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, v15, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, v6, v15, s2
@@ -3876,19 +3876,19 @@ define amdgpu_ps void @insertelement_v_v16i16_s_v(ptr addrspace(1) %ptr, i16 inr
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v2
-; GFX11-NEXT: s_and_b32 s5, s2, 0xffff
-; GFX11-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 16
; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: s_and_b32 s5, s2, 0xffff
+; GFX11-NEXT: v_dual_mov_b32 v13, 16 :: v_dual_mov_b32 v12, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 6, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e64 v11, v2, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, s5
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
index 620cba152f5a2a..9e412537526699 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
@@ -2604,21 +2604,20 @@ define amdgpu_ps void @insertelement_v_v8i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_and_b32_e32 v4, 3, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e64 v5, v4, 0xff
; GFX11-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_not_b32_e32 v3, v5
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v4, v4, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
@@ -3701,26 +3700,26 @@ define amdgpu_ps void @insertelement_v_v16i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v3
-; GFX11-NEXT: v_mov_b32_e32 v9, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_and_b32 v0, 3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 3, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v1
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v4, v5 :: v_dual_lshlrev_b32 v0, 3, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-NEXT: v_lshlrev_b32_e64 v8, v0, 0xff
; GFX11-NEXT: v_lshlrev_b32_e32 v0, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v6, s0
; GFX11-NEXT: v_not_b32_e32 v2, v8
; GFX11-NEXT: v_mov_b32_e32 v8, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
; GFX11-NEXT: v_and_or_b32 v3, v3, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v3, s2
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
index 394d145f6064d3..dd5bcfdf47bba7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
@@ -1951,7 +1951,8 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d
;
; GFX11-TRUE16-LABEL: atomic_add_i32_2darraymsaa:
; GFX11-TRUE16: ; %bb.0: ; %main_body
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v6, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
@@ -4066,7 +4067,8 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc,
;
; GFX11-TRUE16-LABEL: atomic_add_i64_2darraymsaa:
; GFX11-TRUE16: ; %bb.0: ; %main_body
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, v4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
index cd1b7227e427a1..1bd95c656c6e89 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
@@ -174,16 +174,15 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr
;
; GFX11-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v1.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, v7
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v7
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v7
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6
@@ -342,16 +341,15 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc,
;
; GFX11-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v1.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, v7
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v7
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v7
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index 40678dbc7ff8d9..c15f6a0f37b4bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -113,8 +113,9 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
@@ -159,8 +160,9 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v3
@@ -290,8 +292,9 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
index 7d9c1e95094a38..8b5e9d45a08bcb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -946,8 +946,8 @@ define i64 @v_mul_i64(i64 %num, i64 %den) {
; GFX11-LABEL: v_mul_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v2
-; GFX11-NEXT: v_mov_b32_e32 v6, v1
+; GFX11-NEXT: v_mov_b32_e32 v4, v0
+; GFX11-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v5, 0
; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v4, v3, v[1:2]
; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v6, v5, v[7:8]
@@ -1642,8 +1642,8 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v9, v1
-; GFX11-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v4
-; GFX11-NEXT: v_mov_b32_e32 v12, v3
+; GFX11-NEXT: v_mov_b32_e32 v10, v2
+; GFX11-NEXT: v_dual_mov_b32 v11, v4 :: v_dual_mov_b32 v12, v3
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v8, v6, 0
; GFX11-NEXT: v_mul_lo_u32 v4, v9, v6
; GFX11-NEXT: v_mul_lo_u32 v6, v8, v7
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index dc11e84be1abb2..3850141f089a77 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -5799,9 +5799,10 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX11-FAKE16-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, 0, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_add_nc_u32 v3, 0x80000000, v2
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX11-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v4, v2 :: v_dual_cndmask_b32 v3, v7, v3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
index efb8fc0ed4c4c5..7730d2e14032c0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
@@ -1719,40 +1719,23 @@ define i65 @v_shl_i65(i65 %value, i65 %amount) {
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_shl_i65:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, 64, v3
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]
-; GFX10-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v3
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
-; GFX10-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
-; GFX10-NEXT: v_or_b32_e32 v1, v5, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_shl_i65:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 64, v3
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v3
-; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
-; GFX11-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v4
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v1 :: v_dual_cndmask_b32 v1, 0, v7
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_shl_i65:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_sub_nc_u32_e32 v6, 64, v3
+; GFX10PLUS-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]
+; GFX10PLUS-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v3
+; GFX10PLUS-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
+; GFX10PLUS-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1]
+; GFX10PLUS-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]
+; GFX10PLUS-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
+; GFX10PLUS-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v8, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = shl i65 %value, %amount
ret i65 %result
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index d797b0fe33673a..fb824fa0ee11bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -5603,8 +5603,9 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v2, 31, v5
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_add_nc_u32 v3, 0x80000000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
@@ -5771,8 +5772,9 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v2, 31, v5
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_add_nc_u32 v3, 0x80000000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 9a885b02a4a580..47468f3c7c4cf4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -17033,8 +17033,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v83, v4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -25498,274 +25498,282 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v47, v36, v37, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v35, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v45, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v43, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v41, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v5, 16, v31
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -25780,13 +25788,12 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v29
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -25799,70 +25806,73 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v61, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v28
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -25918,46 +25928,48 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v2, v7 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
@@ -25968,53 +25980,58 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
@@ -26075,136 +26092,140 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v32, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v39, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v37, v34, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v34, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
@@ -26213,325 +26234,346 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v31
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v31
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v31, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v28, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v24, 0x40c00000, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v23
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v21, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v36, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v33, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v32, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v38, v33, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v36, 16, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v34, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
@@ -26539,9 +26581,8 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v34, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v33, 0x7fff
@@ -26550,7 +26591,6 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v19, 0x7fff
@@ -26558,15 +26598,17 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v16
@@ -28920,8 +28962,8 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -28934,8 +28976,8 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
@@ -28953,119 +28995,115 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, s47, 0xffff0000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s47, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s46, 16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s45, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s44, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v2, v7 :: v_dual_add_nc_u32 v1, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s43, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -29073,56 +29111,58 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s42, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v17, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s41, 16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v18, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s40, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -29130,11 +29170,11 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s39, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s39, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v16, v18
@@ -29244,11 +29284,11 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s65, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s65, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v20, v24
@@ -29301,56 +29341,57 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s62, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s62, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v25, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v21, v25
; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s61, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: s_and_b32 s0, s60, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v16.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v19, v22
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_add_nc_u32 v17, v19, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s60, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
; GFX11-TRUE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
@@ -29358,11 +29399,11 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s59, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s59, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
@@ -29406,64 +29447,67 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v16, v33 :: v_dual_add_nc_u32 v19, v19, v20
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v18.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s55, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_and_b32 s0, s54, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v18.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s54, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v33, v16
@@ -29636,31 +29680,30 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB19_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s51, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s50, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s50, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s49, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s49, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s48, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -29691,8 +29734,8 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -29701,104 +29744,116 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s46, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s44, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -29823,14 +29878,15 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s41, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
@@ -30234,7 +30290,8 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v33, v34 :: v_dual_add_nc_u32 v33, v35, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s53, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
@@ -53092,8 +53149,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v83, v4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -61696,274 +61753,282 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v47, v36, v37, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v35, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v45, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v43, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v41, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v5, 16, v31
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -61978,13 +62043,12 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v29
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -61997,70 +62061,73 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v61, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v28
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -62116,46 +62183,48 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v2, v7 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
@@ -62166,53 +62235,58 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
@@ -62273,136 +62347,140 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v32, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v39, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v37, v34, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v34, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
@@ -62411,325 +62489,346 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v31
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v31
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v31, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v28, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v24, 0x40c00000, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v23
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v21, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v36, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v33, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v32, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v38, v33, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v36, 16, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v34, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
@@ -62737,9 +62836,8 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v34, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v33, 0x7fff
@@ -62748,7 +62846,6 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v19, 0x7fff
@@ -62756,15 +62853,17 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v16
@@ -65118,8 +65217,8 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -65132,8 +65231,8 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
@@ -65151,119 +65250,115 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, s47, 0xffff0000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s47, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s46, 16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s45, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s44, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v2, v7 :: v_dual_add_nc_u32 v1, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s43, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -65271,56 +65366,58 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s42, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v17, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s41, 16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v18, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s40, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -65328,11 +65425,11 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s39, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s39, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v16, v18
@@ -65442,11 +65539,11 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s65, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s65, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v20, v24
@@ -65499,56 +65596,57 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s62, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s62, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v25, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v21, v25
; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s61, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: s_and_b32 s0, s60, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v16.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v19, v22
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_add_nc_u32 v17, v19, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s60, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
; GFX11-TRUE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
@@ -65556,11 +65654,11 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s59, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s59, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
@@ -65604,64 +65702,67 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v16, v33 :: v_dual_add_nc_u32 v19, v19, v20
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v18.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s55, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_and_b32 s0, s54, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v18.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s54, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v33, v16
@@ -65834,31 +65935,30 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB43_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s51, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s50, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s50, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s49, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s49, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s48, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -65889,8 +65989,8 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -65899,104 +65999,116 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s46, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s44, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -66021,14 +66133,15 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s41, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
@@ -66432,7 +66545,8 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v33, v34 :: v_dual_add_nc_u32 v33, v35, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s53, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
@@ -87370,8 +87484,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v83, v4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -95843,274 +95957,282 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB62_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v47, v36, v37, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v35, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v45, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v43, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v41, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v5, 16, v31
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -96125,13 +96247,12 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v29
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -96144,70 +96265,73 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v61, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v28
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -96263,46 +96387,48 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v2, v7 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
@@ -96313,53 +96439,58 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
@@ -96420,136 +96551,140 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB62_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v32, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v39, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v37, v34, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v34, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
@@ -96558,325 +96693,346 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v31
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v31
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v31, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v28, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v24, 0x40c00000, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v23
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v21, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v36, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v33, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v32, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v38, v33, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v36, 16, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v34, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
@@ -96884,9 +97040,8 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v34, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v33, 0x7fff
@@ -96895,7 +97050,6 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v19, 0x7fff
@@ -96903,15 +97057,17 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v16
@@ -99265,8 +99421,8 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -99279,8 +99435,8 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
@@ -99298,119 +99454,115 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, s47, 0xffff0000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s47, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s46, 16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s45, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s44, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v2, v7 :: v_dual_add_nc_u32 v1, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s43, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -99418,56 +99570,58 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s42, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v17, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s41, 16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v18, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s40, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -99475,11 +99629,11 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s39, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s39, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v16, v18
@@ -99589,11 +99743,11 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s65, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s65, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v20, v24
@@ -99646,56 +99800,57 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s62, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s62, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v25, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v21, v25
; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s61, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: s_and_b32 s0, s60, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v16.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v19, v22
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_add_nc_u32 v17, v19, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s60, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
; GFX11-TRUE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
@@ -99703,11 +99858,11 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s59, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s59, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
@@ -99751,64 +99906,67 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v16, v33 :: v_dual_add_nc_u32 v19, v19, v20
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v18.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s55, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_and_b32 s0, s54, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v18.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s54, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v33, v16
@@ -99981,31 +100139,30 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB63_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s51, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s50, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s50, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s49, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s49, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s48, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -100036,8 +100193,8 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -100046,104 +100203,116 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s46, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s44, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -100168,14 +100337,15 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s41, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
@@ -100579,7 +100749,8 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v33, v34 :: v_dual_add_nc_u32 v33, v35, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s53, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
@@ -120548,8 +120719,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v81, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v83, v4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -129021,274 +129192,282 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB78_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v47, v36, v37, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v35, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v45, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v43, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v41, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v5, 16, v31
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -129303,13 +129482,12 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v29
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -129322,70 +129500,73 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v61, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v28
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -129441,46 +129622,48 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v2, v7 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
@@ -129491,53 +129674,58 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
@@ -129598,136 +129786,140 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB78_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v32, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v39, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v37, v34, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v34, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
@@ -129736,325 +129928,346 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v3
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v31
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v31
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v31, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v28, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v24, 0x40c00000, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v25
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v34, v38 :: v_dual_lshlrev_b32 v37, 16, v23
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v34, 16, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v21, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v35, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v35
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v36, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v33, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v32, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v38, v33, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v36
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v36, 16, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v34, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
@@ -130062,9 +130275,8 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v34, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v36
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v33, 0x7fff
@@ -130073,7 +130285,6 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v37, v19, 0x7fff
@@ -130081,15 +130292,17 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v18, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v16
@@ -132443,8 +132656,8 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -132457,8 +132670,8 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
@@ -132476,119 +132689,115 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v4, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, s47, 0xffff0000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v7, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s47, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s46, 16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s45, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s44, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v2, v7 :: v_dual_add_nc_u32 v1, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s43, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -132596,56 +132805,58 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s42, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v17, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s41, 16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v16, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v18, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s40, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -132653,11 +132864,11 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s39, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v17 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s39, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v16, v18
@@ -132767,11 +132978,11 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s65, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s65, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v20, v24
@@ -132824,56 +133035,57 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s62, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s62, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v25, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s61, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v21, v25
; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v23, v19
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s61, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: s_and_b32 s0, s60, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v16.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v24, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v19, v22
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_add_nc_u32 v17, v19, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s60, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
; GFX11-TRUE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
@@ -132881,11 +133093,11 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v16.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s59, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v23 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s59, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v24
@@ -132929,64 +133141,67 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v16, v33 :: v_dual_add_nc_u32 v19, v19, v20
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s56, 0xffff0000
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v18.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s56, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v33, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s55, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s55, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_and_b32 s0, s54, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v35, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v18.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s54, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v16
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s52, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v33, v16
@@ -133159,31 +133374,30 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB79_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s51, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s51, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s50, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s50, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s49, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s49, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s48, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s48, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -133214,8 +133428,8 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s47, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -133224,104 +133438,116 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s46, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s45, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s45, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s44, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s44, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s43, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s43, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
@@ -133346,14 +133572,15 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s41, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
@@ -133757,7 +133984,8 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v33, v34 :: v_dual_add_nc_u32 v33, v35, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s53, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
@@ -145569,8 +145797,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v12 :: v_dual_mov_b32 v33, v7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v11 :: v_dual_mov_b32 v55, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v35, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v37, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:384
@@ -145674,8 +145902,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v86, v28
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v80, v27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v80, v27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v86, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v81, v25
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(62)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v127, 8, v0
@@ -156343,148 +156571,136 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB90_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v18
; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v32 :: v_dual_add_f32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v31 :: v_dual_lshlrev_b32 v20, 16, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v32
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v31, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v31, v38, v34, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v32, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v39, v32, v37 :: v_dual_and_b32 v18, 0xffff0000, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v17, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v17
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v33
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v31, v38, v34, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v17, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v39.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 24, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v39.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v119, v37, v49, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v19
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v31, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v31, v31, v33 :: v_dual_add_f32 v36, 0x40c00000, v34
; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v20, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v18
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v119.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 24, v32
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v36, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v150, v33, v35, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v36, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v17, v34, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v19
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v19, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v151, v17, v33 :: v_dual_and_b32 v18, 0xffff0000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_cndmask_b32 v33, v20, v35
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_lshlrev_b32 v21, 16, v21
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.l, v150.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v33.l, v151.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 24, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 8, v34
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v33.l, v151.h
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v160, v19, v35, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v24
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v17, v36, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.l, v160.h
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 24, v36
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v161, v17, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_add_f32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.l, v160.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v19, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.l, v161.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.l, v161.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v36
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v162, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v17, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 24, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v36
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v163, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
@@ -156506,7 +156722,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v49, v17, v24
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v17, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
@@ -156529,15 +156746,15 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v38.l, v162.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v165.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v166, v19, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v51, v17, v24
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v17, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
@@ -156545,9 +156762,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[37:38]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 24, v38
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v38
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v167, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
@@ -156569,7 +156784,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v83
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v53, v17, v24
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v17, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
@@ -156578,7 +156794,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v82
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.l, v150.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v177, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
@@ -156592,9 +156809,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.l, v164.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v52.l, v177.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 24, v34
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 8, v34
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v178, v19, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
@@ -156608,10 +156825,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v49
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v179, v17, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
@@ -156641,9 +156856,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[48:49]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v18, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v181, v17, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
@@ -156660,24 +156873,24 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v51.l, v166.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v64.l, v181.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v182, v2, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v17, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v67, v1, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v1, v20, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v17, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[50:51]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v53.l, v176.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 24, v51
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v50
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v183, v1, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
@@ -156693,27 +156906,26 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 8, v53
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v51
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v69, v1, v18
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v69, v1, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v50
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v64
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[84:85], 24, v[52:53]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v52
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v1, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v5, v6, 0x7fff
@@ -156729,17 +156941,18 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v71, v1, v18
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v71, v1, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v7
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v67.l, v182.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v5.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v48
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v70, v1, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
@@ -156750,7 +156963,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
@@ -156767,17 +156981,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v1.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v6.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v55.l, v178.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v38.l, v162.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 24, v71
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v98, v3, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v17, v8, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[70:71]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[80:81], 24, v[54:55]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[132:133], 24, v[31:32]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[37:38]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v99
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 8, v99
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v12, v10, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v17, v9, 0x7fff
@@ -156785,7 +156999,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v9
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.h, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.l, v164.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v17, 16, 1
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_lshlrev_b32 v8, 16, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -156797,9 +157011,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v118, v12, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v65.l, v180.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v2.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v51.l, v166.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v117, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v10, 0x40c00000, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
@@ -156810,26 +157024,27 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v10, 16, 1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[98:99]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[129:130], 24, v[33:34]
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v12 :: v_dual_add_f32 v11, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v7.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v17, v9, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v10, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v53.l, v176.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v135, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v13
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v19, v11, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v17, v18 :: v_dual_and_b32 v14, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v67.l, v182.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v55.l, v178.h
; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v14 :: v_dual_lshlrev_b32 v14, 16, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v134, v12, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
@@ -156856,28 +157071,39 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v13, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v20, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v9.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v10.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v17, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v8.h
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[144:145], 24, v[68:69]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[115:116], 24, v[117:118]
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.h, v5.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[134:135]
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v149, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v65.l, v180.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v149.l, v12.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[134:135]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[145:146], 24, v[66:67]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[146:147], 24, v[64:65]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[98:99]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[70:71]
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v148, v13, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v148.l, v14.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[145:146], 24, v[66:67]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[115:116], 24, v[117:118]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[146:147], 24, v[64:65]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[80:81], 24, v[54:55]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[148:149]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[84:85], 24, v[52:53]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[50:51]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[48:49]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[113:114], 24, v[35:36]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[129:130], 24, v[33:34]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[132:133], 24, v[31:32]
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.h, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.h, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.h, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.h, v4.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.h, v2.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[148:149]
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.h, v7.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.h, v3.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v9.h
@@ -156894,10 +157120,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 24, v118
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v118
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 8, v117
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v99
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 8, v99
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v98
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 24, v71
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v71
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v70
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 24, v69
@@ -156908,11 +157131,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 8, v66
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 24, v65
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v65
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v64
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v55
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v55
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v54
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v53
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 8, v53
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 24, v51
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v51
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v48
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 24, v38
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v38
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v32
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v31
; GFX11-TRUE16-NEXT: .LBB90_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -157390,105 +157621,108 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB90_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v33
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v33, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v33
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v35, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v33, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v36, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v38, v38, v34, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v36 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: v_add3_u32 v36, v48, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v18, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v18
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v37, v39, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v37, v39 :: v_dual_lshlrev_b32 v37, 16, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v67, v18, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v46, 16, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v35, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v38, v33, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v46, 16, v18
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v73, 24, v67
+; GFX11-FAKE16-NEXT: v_add3_u32 v36, v48, v35, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v74, 8, v67
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v33
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v40, v36, v39, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v20, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v66, v40, v33, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v34
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v39, 0x40c00000, v19
+; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v20, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_perm_b32 v66, v40, v33, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v73, 24, v67
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v36, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v39, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v75, 8, v66
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v74, 8, v67
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v49, v36, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v38, v34, v39, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v39
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v40, 16, v40
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v20, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v20, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v39, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v49, v36, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v39
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v37, v48, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT: v_add3_u32 v38, v34, v39, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v22
; GFX11-FAKE16-NEXT: v_perm_b32 v71, v20, v19, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v48
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v43, 16, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v48
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v36, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v36
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v63, 24, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v38, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v36, 0x7fff
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v36, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v36
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v38 :: v_dual_add_f32 v49, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v36, 0x7fff
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v44, 16, v35
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v37, v48 :: v_dual_add_f32 v22, 0x40c00000, v22
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v38, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v49, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v37, v48, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v37, v51, v38, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v48, v36, v49, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v49
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v22, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v22
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: v_add3_u32 v37, v51, v38, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v48, v36, v49, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v39, v22, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v49
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v39, v50, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38
@@ -157517,8 +157751,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v48, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v51, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v70, v35, v34, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v62, 24, v81
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v49, v52, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v26
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v53, v48, 0x7fff
@@ -157543,13 +157777,13 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v51, v51, v26, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v50 :: v_dual_add_f32 v53, 0x40c00000, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v80, v37, v36, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v83, v24, v23, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v49, v52, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v50, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v53, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v180, 16, v24
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v51, v54, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v28
; GFX11-FAKE16-NEXT: v_add3_u32 v49, v55, v50, 0x7fff
@@ -157574,13 +157808,13 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v52, 0x40c00000, v52 :: v_dual_add_f32 v55, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v83, v24, v23, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v85, v26, v25, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v51, v54, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-FAKE16-NEXT: v_bfe_u32 v65, v52, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v55, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v177, 16, v49
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v180, 16, v24
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v176, 16, v26
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v64, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v30
; GFX11-FAKE16-NEXT: v_add3_u32 v51, v65, v52, 0x7fff
@@ -157605,13 +157839,13 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v55, v55, v30, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v54, 0x40c00000, v54 :: v_dual_add_f32 v65, 0x40c00000, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v85, v26, v25, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v87, v28, v27, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v53, v64, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v54, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v65, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v176, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v177, 16, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v162, 16, v28
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v55, v68, vcc_lo
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v32
@@ -157629,21 +157863,22 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v54
; GFX11-FAKE16-NEXT: v_bfe_u32 v65, v32, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v32
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v64, v69, vcc_lo
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v64, v69 :: v_dual_lshlrev_b32 v64, 16, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v31
; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; GFX11-FAKE16-NEXT: v_add3_u32 v55, v55, v54, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX11-FAKE16-NEXT: v_add3_u32 v65, v65, v32, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v64, 0x40c00000, v64 :: v_dual_add_f32 v69, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v82, v39, v38, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v97, v30, v29, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v55, v68, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v64, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v54, v69, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v151, 16, v53
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v65, v98, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v55, v99, v64, 0x7fff
@@ -157660,20 +157895,21 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v64
; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v55, v68, v99 :: v_dual_lshlrev_b32 v68, 16, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v99, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v65, v65, v64, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
; GFX11-FAKE16-NEXT: v_add3_u32 v69, v69, v2, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v68, 0x40c00000, v68 :: v_dual_add_f32 v101, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v84, v49, v48, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v99, v32, v31, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v65, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_bfe_u32 v103, v68, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v101, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v48
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v38
+; GFX11-FAKE16-NEXT: v_perm_b32 v98, v55, v54, 0x7060302
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v165, 16, v51
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v69, v102, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v65, v103, v68, 0x7fff
@@ -157713,7 +157949,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_f32_e32 v112, 0x40c00000, v112
; GFX11-FAKE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v69, v69, v103
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v113
-; GFX11-FAKE16-NEXT: v_perm_b32 v87, v28, v27, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v101, v2, v1, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v113, v112, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v115, v6, 16, 1
@@ -157796,18 +158032,18 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add3_u32 v116, v116, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v129, 0x400000, v9
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v102, v68, v69, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v100, v65, v64, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v132, v117, v119 :: v_dual_add_f32 v117, 0x40c00000, v128
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v119, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v113, v6, v135, 0x7060302
-; GFX11-FAKE16-NEXT: v_perm_b32 v112, v5, v144, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v103, v4, v3, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v102, v68, v69, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v118, v117, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v116, v129 :: v_dual_lshlrev_b32 v116, 16, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v116, v129, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v117
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v118, v118, v117, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117
; GFX11-FAKE16-NEXT: v_add_f32_e32 v116, 0x40c00000, v116
@@ -157819,12 +158055,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v116
; GFX11-FAKE16-NEXT: v_bfe_u32 v128, v11, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v42, v10, v131, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v113, v6, v135, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v117, v130, v116, 0x7fff
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v119, v129 :: v_dual_lshlrev_b32 v119, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v116, v116
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v41, v9, v132, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v112, v5, v144, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v182, v12, v145, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v116, 0x40c00000, v119
@@ -157836,7 +158072,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_bfe_u32 v128, v116, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: v_perm_b32 v97, v30, v29, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v42, v10, v131, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v117, v118, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v117, 0x40c00000, v119
; GFX11-FAKE16-NEXT: v_add3_u32 v118, v128, v116, 0x7fff
@@ -157855,7 +158091,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_bfe_u32 v147, v13, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; GFX11-FAKE16-NEXT: v_perm_b32 v181, v11, v130, 0x7060302
-; GFX11-FAKE16-NEXT: v_perm_b32 v96, v53, v52, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v41, v9, v132, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v116, v118, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v116, 0x40c00000, v129
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117
@@ -157868,8 +158104,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v179, v14, v119, 0x7060302
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v4, v3, 0x7060302
-; GFX11-FAKE16-NEXT: v_perm_b32 v101, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v150, 16, v65
+; GFX11-FAKE16-NEXT: v_perm_b32 v80, v37, v36, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v117, v118, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v117, 0x40c00000, v146
; GFX11-FAKE16-NEXT: v_add3_u32 v118, v129, v116, 0x7fff
@@ -157887,7 +158123,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_bfe_u32 v116, v15, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v147, v147, v117, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v149, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v100, v65, v64, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v84, v49, v48, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v129, v146, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117
; GFX11-FAKE16-NEXT: v_add3_u32 v116, v116, v15, 0x7fff
@@ -157896,24 +158132,34 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v164, v16, v118, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v129, v147, v148, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v86, v51, v50, 0x7060302
-; GFX11-FAKE16-NEXT: v_perm_b32 v99, v32, v31, 0x7060302
-; GFX11-FAKE16-NEXT: v_perm_b32 v98, v55, v54, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[112:113]
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v148, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[100:101]
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v116, v149, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[66:67]
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v67, v76
+; GFX11-FAKE16-NEXT: v_perm_b32 v96, v53, v52, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v70, v35, v34, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v163, v15, v129, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v82, v39, v38, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v86, v51, v50, 0x7060302
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v36
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[163:164]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[178:179]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[181:182]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v149, 16, v30
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v52
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[41:42]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[112:113]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[102:103]
-; GFX11-FAKE16-NEXT: v_perm_b32 v163, v15, v129, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v118
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v129
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[163:164]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[178:179]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[181:182]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[41:42]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v119
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v13
@@ -157938,30 +158184,22 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v68
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v69
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v148, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v150, 16, v65
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v64
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v32
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v31
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v54
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v162, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v38
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[114:115]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[100:101]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[96:97]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[84:85]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[80:81]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v55
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v165, 16, v51
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v183, 16, v39
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[98:99]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[86:87]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[82:83]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v72, 8, v70
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[70:71]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[66:67]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v160, 24, v164
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v161, 8, v164
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v163, 8, v163
@@ -158001,12 +158239,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v61, 24, v83
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 8, v83
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v82
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v62, 24, v81
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 8, v81
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 8, v80
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v71
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v71, v77
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v67, v76
; GFX11-FAKE16-NEXT: .LBB90_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v102, 0xc0c0004
@@ -164170,19 +164406,18 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s29, s41, 0xffff0000
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s29
+; GFX11-TRUE16-NEXT: s_and_b32 s29, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s41, s41, 16
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s29
; GFX11-TRUE16-NEXT: s_and_b32 s28, s40, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s29, s40, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v11, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -164203,7 +164438,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v51.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v9 :: v_dual_add_nc_u32 v4, v5, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v5, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v6, v8
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s28
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s29
@@ -164270,20 +164506,20 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v67.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v65.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v8, v10
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v8, v11, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v11, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s13
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-TRUE16-NEXT: s_and_b32 s12, s11, 0xffff0000
@@ -164307,31 +164543,31 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v12, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v70.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v12
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_add_nc_u32 v10, v13, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v13, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s11
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-TRUE16-NEXT: s_and_b32 s10, s9, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v15, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s9, s9, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v13, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v14, v15
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s9
@@ -164344,20 +164580,20 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v15
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v71.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v14, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v52.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 16, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v12, v14
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v17 :: v_dual_add_nc_u32 v12, v15, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v15, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
; GFX11-TRUE16-NEXT: s_and_b32 s8, s7, 0xffff0000
@@ -164382,19 +164618,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v97.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v13, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v16, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v81.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v14, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v11, v19 :: v_dual_add_nc_u32 v14, v17, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v17, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s7
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
; GFX11-TRUE16-NEXT: s_and_b32 s6, s5, 0xffff0000
@@ -164427,10 +164663,10 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v16, v18
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v13, v21 :: v_dual_add_nc_u32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v13, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
@@ -164443,7 +164679,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v21 :: v_dual_add_nc_u32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v20, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
@@ -164453,8 +164690,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v99.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
@@ -164463,67 +164700,67 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s3, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v22, v23
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v22, v23
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v112.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v23
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v112.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v102.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v113.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v87.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v23, v22
; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v19
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v19
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v23, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v87.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v98.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v103.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v22, v23
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v23
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v66.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v23, v22
; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
@@ -164542,7 +164779,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v22, v23
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
@@ -164561,7 +164799,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v23, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
@@ -164572,19 +164811,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s26, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v81.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v114.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v117.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v97.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v115.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v23 :: v_dual_add_nc_u32 v16, v17, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v86.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v29.h, v128.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v19, v24
@@ -164598,7 +164837,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v16
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v22 :: v_dual_add_nc_u32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -164621,7 +164861,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v16, v24 :: v_dual_add_nc_u32 v15, v17, v23
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.l, v131.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v18
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
@@ -164634,7 +164874,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v19 :: v_dual_add_nc_u32 v16, v17, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v22, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
@@ -164667,77 +164908,81 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, v25, v24
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v17, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x7fff, v25
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v16 :: v_dual_add_nc_u32 v16, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v19
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, v25, v24
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v18, v22
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x7fff, v25
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 16, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v17, v23
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v23
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v15
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v16
; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v13
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v18 :: v_dual_add_nc_u32 v18, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 16, v17
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s27, 16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v9
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v43.l, v134.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v43.h, v149.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v22, v15
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 16, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s27, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v18
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v23, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v43.h, v149.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 16, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
@@ -164745,32 +164990,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v23
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v24
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v44.l, v150.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v44.l, v150.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v44.h, v163.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v42.l, v146.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v25, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v42.l, v146.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v42.h, v151.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.h, v145.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v98.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v103.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 16, v19
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.l, v131.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.h, v145.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v40.l, v135.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.l, v162.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v18
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v176.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v165.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v18
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v40.h, v148.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v100.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v114.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v117.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v82.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v177.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v115.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v29.h, v128.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v100.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v119.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.h, v133.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v130.l
@@ -164780,8 +165026,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v166.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v167.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v67.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v68.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v69.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v80.l
@@ -165603,22 +165847,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s42
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s28
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s29, s41, 0xffff0000
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT: s_and_b32 s29, s41, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s41, s41, 16
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s29
; GFX11-FAKE16-NEXT: s_and_b32 s28, s40, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s29, s40, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v6
@@ -165661,20 +165904,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v8, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s28
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v10, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s15, s14, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s14, s14, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v48
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v4, v11 :: v_dual_add_nc_u32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v10
@@ -165686,15 +165928,15 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v50
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v11, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s14, s13, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s13, s13, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v49, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v7, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v10, v11
@@ -165710,18 +165952,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v10, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v51, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v12
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v55
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v49, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v6, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
@@ -165730,53 +165973,50 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v12
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v65, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_add_nc_u32 v8, v9, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v9, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s12
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s11
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: s_and_b32 s11, s10, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s10, s10, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
+; GFX11-FAKE16-NEXT: s_and_b32 s11, s10, 0xffff0000
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
+; GFX11-FAKE16-NEXT: s_lshl_b32 s10, s10, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v12, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v10, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v8, v15 :: v_dual_add_nc_u32 v10, v13, v14
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v8, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: s_and_b32 s10, s9, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v52
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v15, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
+; GFX11-FAKE16-NEXT: s_and_b32 s10, s9, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s9, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v14, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo
@@ -165784,40 +166024,34 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
-; GFX11-FAKE16-NEXT: s_and_b32 s9, s8, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
+; GFX11-FAKE16-NEXT: s_and_b32 s9, s8, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v70
+; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s8, 16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v15, v16
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v10, v17 :: v_dual_add_nc_u32 v12, v15, v16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v10, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s7, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s7, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v17, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v82, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v13 :: v_dual_and_b32 v9, 0xffff, v83
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s7, 0xffff0000
+; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s7, 16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v15, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v86, 16, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v13, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v16, v17
@@ -165834,27 +166068,26 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v16, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v53, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v14, v16
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v12, v19 :: v_dual_add_nc_u32 v14, v17, v18
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
; GFX11-FAKE16-NEXT: s_and_b32 s6, s5, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v17, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v71
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v15, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v19
@@ -165870,10 +166103,11 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v16, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v54
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v15
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v21 :: v_dual_add_nc_u32 v15, v16, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v16, v18
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s4
@@ -165892,7 +166126,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v20, v21
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v15
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v22 :: v_dual_add_nc_u32 v15, v16, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v16, v19
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000
@@ -165902,13 +166137,13 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v85
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v87, 16, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v64, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v50
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v66
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v20
@@ -165924,12 +166159,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v21, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s3, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v51, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v68
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v99, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
@@ -165942,88 +166177,103 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v96
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v69, 16, v7
; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s2, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v52
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v101, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v80
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v21, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v97
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v102, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v100
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v21, 16, 1
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v103, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v112
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v70
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v19
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v22, v21
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v115, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v113
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v85
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v99, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v96
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v118, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v114
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v101, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v97
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v87, 16, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v102, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v100
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v39, v119, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v15
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v21, v22
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v103, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v112
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v115, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v113
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v118, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v114
; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v116
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v23, v19
-; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v24, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v39, v119, 16, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v21, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v38, v130, 16, v14
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v82, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v83
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v81, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v67, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v61, 24, v39
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v23, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v86, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v13
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v20, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v19
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v19
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
@@ -166031,33 +166281,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v84
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v20, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v53, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v22, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v21 :: v_dual_add_nc_u32 v15, v15, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v18
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v117
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v14 :: v_dual_and_b32 v22, 0xffff, v129
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v54
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v129
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v98, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v131, 16, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v40, v134, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v15, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v40, v134, 16, v22
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v58, 8, v40
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v14
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
@@ -166089,12 +166339,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v64, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v47, 24, v43
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v28, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v133
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v47, 24, v43
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v46, 8, v43
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v132
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v23, vcc_lo
@@ -166126,32 +166376,33 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v27, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v55
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v20, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v65, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v151, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v146
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v23 :: v_dual_add_nc_u32 v15, v15, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v151, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v44, v151, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v144
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v150, 16, v14
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v146
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v42, v147, 16, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v150, 16, v18
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v14, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v42, v147, 16, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v73, 24, v45
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v21, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
@@ -166172,47 +166423,46 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v66
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v20, v21 :: v_dual_add_nc_u32 v15, v15, v27
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v27
; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v27
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s27, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v24, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v148, 16, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v21, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v164, 16, v14
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v21, v24
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s26, 16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v165, 16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v21, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
+; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v23, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v23, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, v27, v21
; GFX11-FAKE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v29, v23
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v21
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v29, v23
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v22
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v28, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v23
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v30, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
@@ -166235,29 +166485,31 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v160
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v181, v164, 16, v20
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v182, v162, 16, v21
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v44, v151, 16, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[42:43]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v167, 16, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v163
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v177, v166, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[42:43]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v46, 8, v43
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v74, 8, v44
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v43, 24, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v176, v167, 16, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v180, v165, 16, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v43, 24, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v68
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[40:41]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[38:39]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[9:10]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[180:181]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[28:29], 24, v[182:183]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[44:45]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[31:32]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v58, 8, v40
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v61, 24, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[25:26]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v60, 8, v39
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 8, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v40, 8, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[176:177]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[16:17]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[5:6]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 24, v177
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v177
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v179, 24, v181
@@ -166265,7 +166517,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v178, 8, v180
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v181, 24, v183
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v180, 8, v183
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v73, 24, v45
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v183, 8, v45
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v45, 8, v42
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v57, 24, v41
@@ -166274,20 +166525,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v41, 8, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2]
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, v43
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v69, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v80
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v98, 16, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v67, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v74, 8, v44
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[25:26]
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v81, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[9:10]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[16:17]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v176, 8, v176
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[5:6]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v182, 8, v182
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v59, 8, v38
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v62, 24, v32
@@ -166311,6 +166549,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 24, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, v43
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v44, v73 :: v_dual_mov_b32 v43, v74
; GFX11-FAKE16-NEXT: s_branch .LBB91_6
; GFX11-FAKE16-NEXT: .LBB91_5:
@@ -172173,8 +172412,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v12 :: v_dual_mov_b32 v33, v7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v11 :: v_dual_mov_b32 v55, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v35, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v37, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:384
@@ -172278,8 +172517,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v86, v28
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v80, v27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v80, v27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v86, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v81, v25
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(62)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v127, 8, v0
@@ -192902,8 +193141,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, v12 :: v_dual_mov_b32 v33, v7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v11 :: v_dual_mov_b32 v55, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v6 :: v_dual_mov_b32 v36, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v37, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v35, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v4 :: v_dual_mov_b32 v35, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v3 :: v_dual_mov_b32 v37, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:384
@@ -193007,8 +193246,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v86, v28
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v80, v27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, v30 :: v_dual_mov_b32 v80, v27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v29 :: v_dual_mov_b32 v86, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v26 :: v_dual_mov_b32 v81, v25
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(62)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v127, 8, v0
@@ -210302,76 +210541,57 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB100_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v49
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v48
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v49
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v49
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v50
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_add_f32 v17, 0x40c00000, v17
; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v54
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v56
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v58
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v60
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v62
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v48
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v49
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v27, 16, v53
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v56
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v29, 16, v55
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v18, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v57
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v59
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v21, v22 :: v_dual_lshlrev_b32 v35, 16, v61
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v21, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v19, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v51
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v63
-; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v58
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v23, v25, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v19, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v20 :: v_dual_lshlrev_b32 v25, 16, v51
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v50
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v19, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v24, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_lshlrev_b32 v27, 16, v53
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v52
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v48.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v24, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v52
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v60
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v22, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v21, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v22, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v49.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v62
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v55
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
@@ -210379,119 +210599,141 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v25
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v24, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v19, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v26 :: v_dual_lshlrev_b32 v22, 16, v52
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v52
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v23, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v19, v23, v25
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v20, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v51, v20, v25 :: v_dual_lshlrev_b32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v26, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v53
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v51.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v20, v20, v24 :: v_dual_add_f32 v23, 0x40c00000, v23
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v25, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v23, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v51.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v49.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v21, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v25, v26, v23, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 0x40c00000, v28 :: v_dual_lshlrev_b32 v24, 16, v54
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v54
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v48.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v26, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v25, v27, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v55
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v25, 0x40c00000, v25
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v50.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v55
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v26, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v31, 16, v57
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v52.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v22, v27, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v28, v23, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v28
; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v59
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v61
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v53.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v23, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v23
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v63
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v28, v23, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v25, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v23, v27, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v27, v28, v25, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_add3_u32 v27, v28, v25, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v29
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v25
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v28, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v23, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v30 :: v_dual_lshlrev_b32 v26, 16, v56
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v56
; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v52.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v54.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v27, v29, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v57
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v57
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_cndmask_b32 v55, v24, v29
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v30
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v24, v29, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v24, v30, v25, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v26, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v50.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v55.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v25
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v24, v30, v25, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v55.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v25, v29, v26, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v29, v30, v27, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v31
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v27
+; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v30, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v25, v28, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 0x40c00000, v32 :: v_dual_lshlrev_b32 v28, 16, v58
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v54.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v29, v31, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v59
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v58
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v26, v26, v30, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v64.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v29, v31, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v27, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_f32 v29, 0x40c00000, v29
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v59
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_cndmask_b32 v65, v26, v31
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v28, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v65.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v27, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v26, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-TRUE16-NEXT: v_add3_u32 v26, v32, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v28, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v65.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v27, v31, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v31, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v26, v30, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v28
+; GFX11-TRUE16-NEXT: v_add3_u32 v31, v32, v29, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v29
@@ -210499,57 +210741,64 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v32, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v27, v30, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v29, 0x40c00000, v34 :: v_dual_lshlrev_b32 v30, 16, v60
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v60
; GFX11-TRUE16-NEXT: v_add3_u32 v28, v28, v32, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v64.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v66.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v31, v33, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v61
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v61
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_cndmask_b32 v67, v28, v33
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v28, v33, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v28, v34, v29, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v30, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v67.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v29, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v29
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v28, v34, v29, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v67.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v29, v33, v30, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v28, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v31, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v31
+; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v34, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v29, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v36 :: v_dual_lshlrev_b32 v32, 16, v62
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v66.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v33, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v63
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v62
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v30, v30, v34, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v68.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v33, v35, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v31, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_add_f32 v33, 0x40c00000, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v63
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_cndmask_b32 v69, v30, v35
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v36
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v69.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v31, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v69, v30, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
; GFX11-TRUE16-NEXT: v_add3_u32 v30, v36, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v69.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v31, v35, v32, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v36, v33, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v30, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v36, v33, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v37
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v33
@@ -210567,7 +210816,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v38, 16, 1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v68.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v32, v35, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v37, v33, 0x7fff
@@ -210618,14 +210867,15 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v80
; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v35, v38, v39 :: v_dual_and_b32 v38, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v38, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v36, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v38 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v38 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v37, v80, v36, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v36
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v4, 16, 1
@@ -210639,20 +210889,23 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v80, v81, v38, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v38
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v37, v39, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
; GFX11-TRUE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v82
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v39, v39, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v37, v80, v81 :: v_dual_and_b32 v80, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v80, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v82, v38, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v39, v81, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v39, v82, v38, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v38
; GFX11-TRUE16-NEXT: v_bfe_u32 v82, v6, 16, 1
@@ -210666,13 +210919,14 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v82, v83, v80, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v80
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v39, v81, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80
; GFX11-TRUE16-NEXT: v_bfe_u32 v81, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v84 :: v_dual_cndmask_b32 v39, v82, v83
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v80, 0x40c00000, v84
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v82, v83, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v81, v81, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v80, 16, 1
@@ -210695,7 +210949,6 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v80, v81, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
@@ -210740,7 +210993,6 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v80, v83, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v80, v84, v81, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v81
@@ -210760,37 +211012,38 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v80, v81, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v13, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v81, 0x40c00000, v85 :: v_dual_lshlrev_b32 v82, 16, v15
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v81, 0x40c00000, v85
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v15
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v80, v80, v13, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v45, v83, v84, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v81, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v82, 0x40c00000, v82
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v81
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v80, v83, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v14, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v83, v84, v81, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v82, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_add3_u32 v80, v80, v14, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v82
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v80, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11-TRUE16-NEXT: v_add3_u32 v84, v84, v82, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v81
-; GFX11-TRUE16-NEXT: v_bfe_u32 v87, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v80, v86, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v15
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v80, v87, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v14, v80, v86 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v87, v15, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v84, v96, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v87, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v83, v85, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
@@ -210842,62 +211095,69 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_lshlrev_b32 v70, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v71, 0x40c00000, v71
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v8
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v32, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v87
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v81, 0x40c00000, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v10
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v32, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_cndmask_b32 v16, v16, v38
; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v11
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v17, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v33
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v34, v36, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v36
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v12, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v37, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v87
+; GFX11-FAKE16-NEXT: v_bfe_u32 v98, v12, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v37, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v38, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v97, 0x400000, v87
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v33, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v34, v36, vcc_lo
@@ -210909,58 +211169,64 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v37, 16, 1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v36, v39, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v39
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v48, 0x40c00000, v19 :: v_dual_add_f32 v39, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v38, v37, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v37
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v48, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v49, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v38, v48, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v39, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v49, 0x40c00000, v20 :: v_dual_add_f32 v48, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v70, 0x40c00000, v70
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v36, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v38, v39, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v39
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v49, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v48, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v50, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v35, v19, 0x7060302
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v49, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v49
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v49, 0x40c00000, v22 :: v_dual_lshlrev_b32 v22, 16, v23
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v21 :: v_dual_add_f32 v49, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v37, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v39, v48, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v48
+; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v50, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v49, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v51, 0x40c00000, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v35, v19, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v50, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v37, v21, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v38, v39, v50, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v50
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
; GFX11-FAKE16-NEXT: v_add_f32_e32 v50, 0x40c00000, v23
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v80, 0x40c00000, v80
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v38, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v38, v48, v49, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v49
@@ -210969,6 +211235,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v50, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v48, v51, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v51
@@ -210979,19 +211246,20 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v49, v50, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v50
+; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v52, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v51, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v53, 0x40c00000, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v37, v21, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v52, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v39, v23, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v48, v49, v52, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v52
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
; GFX11-FAKE16-NEXT: v_add_f32_e32 v52, 0x40c00000, v25
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v82, 0x40c00000, v82
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v9
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v48, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v48, v50, v51, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v51
@@ -211000,6 +211268,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v52, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v49, v50, v53, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v53
@@ -211010,19 +211279,20 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v49, v50, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v49, v51, v52, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v52
+; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v54, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v53, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v55, 0x40c00000, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v48, v24, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v39, v23, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v54, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v49, v25, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v50, v51, v54, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v54
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX11-FAKE16-NEXT: v_add_f32_e32 v54, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v11
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v50, v51, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v50, v52, v53, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v53
@@ -211031,6 +211301,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v54, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v51, v52, v55, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v55
@@ -211041,19 +211312,19 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v51, v52, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v51, v53, v54, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v54
+; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v64, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX11-FAKE16-NEXT: v_bfe_u32 v54, v55, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v65, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v50, v26, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v49, v25, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v64, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v51, v27, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v52, v53, v64, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v64
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
; GFX11-FAKE16-NEXT: v_add_f32_e32 v64, 0x40c00000, v29
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v86, 0x40c00000, v86
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v52, v53, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v52, v54, v55, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v55
@@ -211062,6 +211333,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v64, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v51, v27, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v53, v54, v65, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v65
@@ -211073,19 +211345,17 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v53, v54, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v53, v55, v64, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v64
+; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v66, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v65, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v30
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v52, v28, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v66, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v53, v29, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v54, v55, v66, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v66
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
; GFX11-FAKE16-NEXT: v_add_f32_e32 v66, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v54, v55, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v54, v64, v65, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v65
@@ -211094,248 +211364,216 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v65, v66, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v53, v29, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v55, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v55, v64, v67, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v67
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v68, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v68, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v67, 16, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v54, v30, 0x7060302
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v55, v65, v66, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v66
; GFX11-FAKE16-NEXT: v_bfe_u32 v65, v68, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v67
; GFX11-FAKE16-NEXT: v_bfe_u32 v66, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v67
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v54, v30, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v64, v65, v68, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v65, 0x400000, v68
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v67, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v55, v31, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v64, v65, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v65, v66, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v65, v66 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v55, v31, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v65, v66, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v65, v68, v67, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v67
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v64, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v64, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v65, v66, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v66, v68, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v69, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v66, v67, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v66, v68, v69, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v69
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69
+; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v70, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v65, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v66, v67, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v67, v68, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v67, v68 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v70, 0x40c00000, v70 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v66, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v70, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v67, v68, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v67, v69, v70, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v70
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-FAKE16-NEXT: v_add3_u32 v67, v69, v70, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v3, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v70, v71, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v66, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v68, v69, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v69, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v68, v69 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v71, 0x40c00000, v71 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v67, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v70, v71, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v69, 0x400000, v71
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v68, v69, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v68, v70, v71, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v69, 0x400000, v71
; GFX11-FAKE16-NEXT: v_bfe_u32 v70, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-FAKE16-NEXT: v_bfe_u32 v71, v80, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v67, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v68, v69, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v69, v70, v4, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v69, v70 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v68, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v71, v80, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v69, v70, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v69, v71, v80, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v80
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80
-; GFX11-FAKE16-NEXT: v_add3_u32 v69, v71, v80, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v71, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v80, v81, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v68, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v69, v70, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v70, v71, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v70, v71 :: v_dual_and_b32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v81, 0x40c00000, v81 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v69, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v80, v81, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v81
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v70, v71, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v70, v80, v81, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v81
; GFX11-FAKE16-NEXT: v_bfe_u32 v80, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-FAKE16-NEXT: v_bfe_u32 v81, v82, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v69, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v70, v71, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v71, v80, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v71, v80 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v70, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v81, v82, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v71, v80, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v71, v81, v82, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v82
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
-; GFX11-FAKE16-NEXT: v_add3_u32 v71, v81, v82, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v81, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v82, v83, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v70, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v71, v71, v80, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v80, v81, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v81, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v80, v81 :: v_dual_and_b32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v71, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v82, v83, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v81, 0x400000, v83
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v80, v81, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v80, v82, v83, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v81, 0x400000, v83
; GFX11-FAKE16-NEXT: v_bfe_u32 v82, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-FAKE16-NEXT: v_bfe_u32 v83, v84, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v71, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v80, v81, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v81, v82, v8, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v81, v82 :: v_dual_and_b32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v84, 0x40c00000, v84 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v80, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v83, v84, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v81, v83, v84, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v84
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-FAKE16-NEXT: v_add3_u32 v81, v83, v84, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v83, v9, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v84, v85, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v80, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v81, v82, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v82, v83, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v83, 0x400000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v82, v83 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v81, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v84, v85, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v83, 0x400000, v85
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v82, v83, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v82, v84, v85, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v83, 0x400000, v85
; GFX11-FAKE16-NEXT: v_bfe_u32 v84, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v86, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v81, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v82, v83, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v83, v84, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v83, v84 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_add_f32 v11, 0x40c00000, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v82, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v86, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v83, v84, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v83, v85, v86, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v86
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_add3_u32 v83, v85, v86, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v11, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
; GFX11-FAKE16-NEXT: v_bfe_u32 v86, v87, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v97, 0x400000, v87
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v82, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-FAKE16-NEXT: v_add3_u32 v86, v86, v87, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v87, v87
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_bfe_u32 v98, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v84, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v85, v85, v11, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v87, v98, v12, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v86, v97, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v97, 0x400000, v12
-; GFX11-FAKE16-NEXT: v_add3_u32 v87, v98, v12, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v98, v99, v84, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v84, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v84
-; GFX11-FAKE16-NEXT: v_bfe_u32 v101, v13, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v87, v97 :: v_dual_add_f32 v87, 0x40c00000, v99
+; GFX11-FAKE16-NEXT: v_add3_u32 v85, v85, v11, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v11
+; GFX11-FAKE16-NEXT: v_add3_u32 v98, v99, v84, 0x7fff
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v87, v97 :: v_dual_lshlrev_b32 v99, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v97, v101, v13, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v99
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v86, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v87, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v98, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v101, 0x400000, v87
-; GFX11-FAKE16-NEXT: v_bfe_u32 v102, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v87, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v98, 0x40c00000, v98
+; GFX11-FAKE16-NEXT: v_bfe_u32 v101, v13, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v99, v99, v87, 0x7fff
+; GFX11-FAKE16-NEXT: v_bfe_u32 v102, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_add3_u32 v97, v101, v13, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v101, 0x400000, v87
+; GFX11-FAKE16-NEXT: v_bfe_u32 v103, v98, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v98
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v113, 0x400000, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v98, 0x40c00000, v98 :: v_dual_cndmask_b32 v87, v99, v101
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v87, v99, v101, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v101, v102, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_bfe_u32 v103, v98, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v98
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v101, v102 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v15, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v103, v103, v98, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v101, v102, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v99, v99, v15, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v87, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v15, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v113, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v98, v103, v112, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v99, v99, v15, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v99, v113, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
@@ -214514,11 +214752,11 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: s_and_b32 s2, s38, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -214526,104 +214764,107 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s38, 16
; GFX11-TRUE16-NEXT: s_and_b32 s1, s25, 0xffff0000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v85, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v85, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v85
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v6, v2 :: v_dual_add_nc_u32 v2, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s39, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v2, v3 :: v_dual_add_nc_u32 v3, v4, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s27, 0xffff0000
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v4, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s39, 16
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v85
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s39, 16
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v97, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v3 :: v_dual_add_nc_u32 v3, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v2, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v98, v97, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v2, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s40, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v98, v98, v97
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v97, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s41, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s41, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s42, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v98, 0x7fff, v98
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s42, 0xffff0000
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v35.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v98, v97, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s42, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v98, v98, v97
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v35.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v98, 0x7fff, v98
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
@@ -214638,23 +214879,22 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
@@ -214686,9 +214926,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
@@ -214865,8 +215105,8 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v5 :: v_dual_add_nc_u32 v4, v6, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v6, v2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
@@ -215045,7 +215285,8 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v83.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v12, v12, v14 :: v_dual_add_nc_u32 v13, v15, v84
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v15, v84
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v82, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v85, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
@@ -215207,11 +215448,11 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: s_and_b32 s2, s38, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -215238,76 +215479,77 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s39, 0xffff0000
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v3 :: v_dual_add_nc_u32 v3, v4, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v4, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s39, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s39, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v3 :: v_dual_add_nc_u32 v3, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v2, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s40, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v2, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s40, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v5, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v5, v1
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s41, 16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s41, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s42, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v1, 16, 1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s42, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s42, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -215326,22 +215568,22 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s44, 0xffff0000
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s44, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
@@ -215372,9 +215614,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: s_and_b32 s0, s46, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
@@ -215492,19 +215734,19 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s12, 0xffff0000
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_add_nc_u32 v3, 0x7fff, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_add_nc_u32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
@@ -215517,8 +215759,8 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff, v54
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
@@ -215532,22 +215774,20 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: s_and_b32 s0, s14, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v6
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_add_nc_u32 v4, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s15, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v8, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v9, 16, 1
@@ -215556,9 +215796,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v9
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s15, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v6
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v8 :: v_dual_add_nc_u32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
@@ -215566,10 +215806,10 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v8 :: v_dual_add_nc_u32 v8, 0x7fff, v10
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
@@ -215598,37 +215838,39 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v7, v8 :: v_dual_and_b32 v67, 0xffff, v67
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v67, 0xffff, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_add_nc_u32 v8, 0x7fff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v8, v9 :: v_dual_add_nc_u32 v8, v10, v11
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v11
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
@@ -215637,26 +215879,20 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v11, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v12, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v68, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v12 :: v_dual_and_b32 v68, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v65, 16, v67
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
@@ -215678,8 +215914,8 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v10
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v28
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
@@ -215706,9 +215942,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v11
; GFX11-FAKE16-NEXT: v_bfe_u32 v82, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v12, v15 :: v_dual_and_b32 v80, 0xffff, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
@@ -215717,7 +215953,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v83, v12, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v68
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v68, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v82
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
@@ -215746,15 +215982,15 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v86, v82, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v83, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v85 :: v_dual_add_nc_u32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v85, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v85, 0x400000, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v86, v86, v82
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v83, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v83
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v15, v85, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v86
; GFX11-FAKE16-NEXT: v_add_f32_e64 v86, 0x40c00000, s0
@@ -215780,12 +216016,12 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v101, v98, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v96
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v99, 0x7fff, v99
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v82, v97, v103 :: v_dual_add_nc_u32 v85, 0x7fff, v85
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v85, 0x7fff, v85
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v97, v103, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v101, v101, v98
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v14, v83
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v14, v83
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v82
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v99, v112, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
@@ -215796,17 +216032,22 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v85, v85, v102, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v97, v101, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v85
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 16, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v68, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v86
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff, v96
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v65, 16, v67
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v80, 0xffff, v80
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v83, 16, v82
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v85, 16, v86
; GFX11-FAKE16-NEXT: v_and_b32_e32 v83, 0xffff, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff, v11
@@ -215848,6 +216089,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v71, 16, v80
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v83
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v68
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v70
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v26, 16, v66
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v21, 16, v53
@@ -221032,15 +221274,14 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v52, 16, v24
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v82, 16, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v33, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v32
@@ -221049,9 +221290,9 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v38, v38, v33, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v24
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc_lo
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v34, 16, v18
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
@@ -221061,36 +221302,37 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v17, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v82, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v54, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v28
; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v16, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v37, v39, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v17
; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v36, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v38, v48
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v38, v48, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v20
@@ -221120,38 +221362,38 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v35, v38, v39 :: v_dual_lshlrev_b32 v38, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v38, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v21
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v36, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v34.h
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v33.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v37, v39, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v36, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v36
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v20, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_bfe_u32 v49, v38, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v32.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v37, v39, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v48, v49, v38, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v38
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v37, v39, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
; GFX11-TRUE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v50
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v36.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v39, v39, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v37, v48, v49 :: v_dual_lshlrev_b32 v48, 16, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v48, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v23
; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v21
; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v38, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
@@ -221177,14 +221419,14 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
; GFX11-TRUE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v52
; GFX11-TRUE16-NEXT: v_add3_u32 v49, v49, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v39, v50, v51 :: v_dual_lshlrev_b32 v50, 16, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v50, v51, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v25
; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v23
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v48, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v50 :: v_dual_cndmask_b32 v23, v49, v51
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v49, v52, v48, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v48
; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v24, 16, 1
@@ -221204,15 +221446,14 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
; GFX11-TRUE16-NEXT: v_add_f32_e32 v50, 0x40c00000, v54
; GFX11-TRUE16-NEXT: v_add3_u32 v51, v51, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v49, v52, v53 :: v_dual_lshlrev_b32 v52, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v52, v53, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v25
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v50, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v52, 0x40c00000, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v38.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v51, v53, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v52, 0x40c00000, v52 :: v_dual_cndmask_b32 v25, v51, v53
; GFX11-TRUE16-NEXT: v_add3_u32 v51, v54, v50, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v50
; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v26, 16, 1
@@ -221226,21 +221467,21 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX11-TRUE16-NEXT: v_add3_u32 v54, v55, v52, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v52
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v51, v53, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v53, v27, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
; GFX11-TRUE16-NEXT: v_add_f32_e32 v52, 0x40c00000, v64
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v50.h
; GFX11-TRUE16-NEXT: v_add3_u32 v53, v53, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v51, v54, v55 :: v_dual_lshlrev_b32 v54, 16, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v54, v55, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29
; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v27
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v52, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v48.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v53, v55, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v54, 0x40c00000, v54 :: v_dual_cndmask_b32 v27, v53, v55
; GFX11-TRUE16-NEXT: v_add3_u32 v53, v64, v52, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v52
; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v28, 16, 1
@@ -221254,14 +221495,16 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-TRUE16-NEXT: v_add3_u32 v64, v65, v54, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v54
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v55, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v29, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX11-TRUE16-NEXT: v_add_f32_e32 v54, 0x40c00000, v66
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v52.h
; GFX11-TRUE16-NEXT: v_add3_u32 v55, v55, v29, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v64, v65, vcc_lo
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v64, v65 :: v_dual_lshlrev_b32 v64, 16, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v31
; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v29
; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v54, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
@@ -221281,20 +221524,21 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11-TRUE16-NEXT: v_add3_u32 v66, v67, v64, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v55, v65, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v31, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
; GFX11-TRUE16-NEXT: v_add_f32_e32 v64, 0x40c00000, v68
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v54.h
; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v55, v66, v67 :: v_dual_lshlrev_b32 v66, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v66, v67, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v31
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v68, v64, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v66, 0x40c00000, v66 :: v_dual_cndmask_b32 v31, v65, v67
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v65, v68, v64, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64
; GFX11-TRUE16-NEXT: v_bfe_u32 v68, v0, 16, 1
@@ -221308,11 +221552,12 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v68, v69, v66, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v66
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v65, v67, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
; GFX11-TRUE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v70
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v64.h
; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v68, v69, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v3
@@ -221320,28 +221565,28 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v70, v67, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v68, 0x40c00000, v68
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v50.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v65, v69, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v68, 0x40c00000, v68 :: v_dual_cndmask_b32 v1, v65, v69
; GFX11-TRUE16-NEXT: v_add3_u32 v65, v70, v67, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v67
; GFX11-TRUE16-NEXT: v_bfe_u32 v70, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
; GFX11-TRUE16-NEXT: v_bfe_u32 v71, v68, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v66.h
; GFX11-TRUE16-NEXT: v_add3_u32 v67, v70, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v65, v69, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v70, v71, v68, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v68
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v67, v69, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68
; GFX11-TRUE16-NEXT: v_add_f32_e32 v69, 0x40c00000, v80
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v65.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v34.h
; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v70, v71, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v5
@@ -221349,9 +221594,8 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v69, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v70, 0x40c00000, v70
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v52.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v67, v71, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v70, 0x40c00000, v70 :: v_dual_cndmask_b32 v3, v67, v71
; GFX11-TRUE16-NEXT: v_add3_u32 v67, v80, v69, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v69
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v4, 16, 1
@@ -221421,12 +221665,13 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v84, v85, v82, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v82
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v83, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v81, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
; GFX11-TRUE16-NEXT: v_add_f32_e32 v83, 0x40c00000, v86
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v71.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v36.h
; GFX11-TRUE16-NEXT: v_add3_u32 v81, v81, v9, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v84, v85, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v11
@@ -221434,9 +221679,8 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v83, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v54.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v81, v85, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v84, 0x40c00000, v84 :: v_dual_cndmask_b32 v9, v81, v85
; GFX11-TRUE16-NEXT: v_add3_u32 v81, v86, v83, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v83
; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v10, 16, 1
@@ -221463,7 +221707,6 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v96, v85, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v64.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v83, v86, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v83, 0x40c00000, v87
; GFX11-TRUE16-NEXT: v_add3_u32 v86, v96, v85, 0x7fff
@@ -221495,7 +221738,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v97, v86, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v66.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v38.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v87, v96, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v98
; GFX11-TRUE16-NEXT: v_add3_u32 v96, v97, v86, 0x7fff
@@ -221505,6 +221748,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v99, v87, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v83.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v48.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v86, v96, v97, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v97, v98, v14, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v98, v99, v87, 0x7fff
@@ -221543,62 +221787,69 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_lshlrev_b32 v70, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v71, 0x40c00000, v71
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v8
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v32, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v87
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v81, 0x40c00000, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v10
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v32, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v9
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v38, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_cndmask_b32 v16, v16, v38
; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v34, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v11
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v34, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v17, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v33
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v34, v36, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v36
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v12, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v37, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v35, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v87
+; GFX11-FAKE16-NEXT: v_bfe_u32 v98, v12, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v37, v35, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v38, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v97, 0x400000, v87
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v33, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v34, v36, vcc_lo
@@ -221610,58 +221861,64 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v37, 16, 1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v36, v39, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v39
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v48, 0x40c00000, v19 :: v_dual_add_f32 v39, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v38, v37, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v37
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v48, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v49, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v38, v48, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v39, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v49, 0x40c00000, v20 :: v_dual_add_f32 v48, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v70, 0x40c00000, v70
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v36, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v36, v38, v39, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v39
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v49, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v48, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v50, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v35, v19, 0x7060302
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v49, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v49
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v49, 0x40c00000, v22 :: v_dual_lshlrev_b32 v22, 16, v23
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v21 :: v_dual_add_f32 v49, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v37, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v39, v48, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v48
+; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v50, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v49, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v51, 0x40c00000, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v20, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v35, v19, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v50, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v37, v21, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v38, v39, v50, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v50
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
; GFX11-FAKE16-NEXT: v_add_f32_e32 v50, 0x40c00000, v23
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v80, 0x40c00000, v80
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v38, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v38, v48, v49, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v49
@@ -221670,6 +221927,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v50, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v48, v51, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v51
@@ -221680,19 +221938,20 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v49, v50, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v50
+; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v52, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v51, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v53, 0x40c00000, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v22, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v37, v21, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v52, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v39, v23, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v48, v49, v52, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v52
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
; GFX11-FAKE16-NEXT: v_add_f32_e32 v52, 0x40c00000, v25
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v82, 0x40c00000, v82
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v9
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v48, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v48, v50, v51, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v51
@@ -221701,6 +221960,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v52, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v49, v50, v53, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v53
@@ -221711,19 +221971,20 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v49, v50, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v49, v51, v52, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v52
+; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v54, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v53, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v55, 0x40c00000, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v48, v24, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v39, v23, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v54, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v49, v25, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v50, v51, v54, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v54
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX11-FAKE16-NEXT: v_add_f32_e32 v54, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v11
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v50, v51, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v50, v52, v53, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v53
@@ -221732,6 +221993,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v54, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v51, v52, v55, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v55
@@ -221742,19 +222004,19 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v51, v52, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v51, v53, v54, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v54
+; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v64, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX11-FAKE16-NEXT: v_bfe_u32 v54, v55, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v65, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v50, v26, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v49, v25, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v53, v64, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v51, v27, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v52, v53, v64, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v64
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
; GFX11-FAKE16-NEXT: v_add_f32_e32 v64, 0x40c00000, v29
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v86, 0x40c00000, v86
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v52, v53, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v52, v54, v55, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v55
@@ -221763,6 +222025,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v64, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v51, v27, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v53, v54, v65, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v65
@@ -221774,19 +222037,17 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v53, v54, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v53, v55, v64, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v64
+; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v66, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
; GFX11-FAKE16-NEXT: v_bfe_u32 v64, v65, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v30
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v52, v28, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v55, v66, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v53, v29, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v54, v55, v66, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v66
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
; GFX11-FAKE16-NEXT: v_add_f32_e32 v66, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v54, v55, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v54, v64, v65, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v65
@@ -221795,248 +222056,216 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v65, v66, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v53, v29, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v55, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v55, v64, v67, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v67
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v68, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v68, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v67, 16, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v54, v30, 0x7060302
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v55, v65, v66, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v66
; GFX11-FAKE16-NEXT: v_bfe_u32 v65, v68, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v67
; GFX11-FAKE16-NEXT: v_bfe_u32 v66, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v67
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v54, v30, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v64, v65, v68, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v65, 0x400000, v68
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v67, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v55, v31, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v64, v65, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v65, v66, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v65, v66 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v55, v31, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v65, v66, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v65, v68, v67, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v67
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v64, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v64, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v65, v66, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v66, v68, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v69, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v66, v67, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v66, v68, v69, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v67, 0x400000, v69
; GFX11-FAKE16-NEXT: v_bfe_u32 v68, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69
+; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v70, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v65, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v66, v66, v67, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v67, v68, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v67, v68 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v70, 0x40c00000, v70 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v66, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v70, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v67, v68, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v67, v69, v70, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v70
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-FAKE16-NEXT: v_add3_u32 v67, v69, v70, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v69, v3, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v70, v71, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v66, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v68, v69, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v69, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v68, v69 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v71, 0x40c00000, v71 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v67, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v70, v71, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v69, 0x400000, v71
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v68, v69, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v68, v70, v71, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v69, 0x400000, v71
; GFX11-FAKE16-NEXT: v_bfe_u32 v70, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-FAKE16-NEXT: v_bfe_u32 v71, v80, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v67, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v68, v69, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v69, v70, v4, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v69, v70 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v68, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v71, v80, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v69, v70, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v69, v71, v80, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v80
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80
-; GFX11-FAKE16-NEXT: v_add3_u32 v69, v71, v80, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v71, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v80, v81, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v68, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v69, v69, v70, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v70, v71, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v70, v71 :: v_dual_and_b32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v81, 0x40c00000, v81 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v69, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v80, v81, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v81
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v70, v71, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v70, v80, v81, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v71, 0x400000, v81
; GFX11-FAKE16-NEXT: v_bfe_u32 v80, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-FAKE16-NEXT: v_bfe_u32 v81, v82, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v69, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v70, v71, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v71, v80, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v71, v80 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v70, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v81, v82, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v71, v80, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v71, v81, v82, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v82
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
-; GFX11-FAKE16-NEXT: v_add3_u32 v71, v81, v82, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v81, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v82, v83, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v70, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v71, v71, v80, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v80, v81, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v81, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v80, v81 :: v_dual_and_b32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v71, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v82, v83, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v81, 0x400000, v83
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v80, v81, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v80, v82, v83, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v81, 0x400000, v83
; GFX11-FAKE16-NEXT: v_bfe_u32 v82, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-FAKE16-NEXT: v_bfe_u32 v83, v84, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v71, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v80, v81, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v81, v82, v8, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v81, v82 :: v_dual_and_b32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v84, 0x40c00000, v84 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v80, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v83, v84, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v81, v83, v84, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v84
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-FAKE16-NEXT: v_add3_u32 v81, v83, v84, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v83, v9, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v84, v85, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v80, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v81, v82, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v82, v83, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v83, 0x400000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v82, v83 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v81, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v84, v85, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v83, 0x400000, v85
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v82, v83, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v82, v84, v85, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v83, 0x400000, v85
; GFX11-FAKE16-NEXT: v_bfe_u32 v84, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v86, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v81, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v82, v83, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v83, v84, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v83, v84 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_add_f32 v11, 0x40c00000, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v82, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v86, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v83, v84, vcc_lo
+; GFX11-FAKE16-NEXT: v_add3_u32 v83, v85, v86, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v86
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_add3_u32 v83, v85, v86, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v11, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
; GFX11-FAKE16-NEXT: v_bfe_u32 v86, v87, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v97, 0x400000, v87
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v82, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-FAKE16-NEXT: v_add3_u32 v86, v86, v87, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v87, v87
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_bfe_u32 v98, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v84, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v85, v85, v11, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v87, v98, v12, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT: v_bfe_u32 v85, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v86, v97, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v97, 0x400000, v12
-; GFX11-FAKE16-NEXT: v_add3_u32 v87, v98, v12, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v98, v99, v84, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v84, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v84
-; GFX11-FAKE16-NEXT: v_bfe_u32 v101, v13, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v87, v97 :: v_dual_add_f32 v87, 0x40c00000, v99
+; GFX11-FAKE16-NEXT: v_add3_u32 v85, v85, v11, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v11
+; GFX11-FAKE16-NEXT: v_add3_u32 v98, v99, v84, 0x7fff
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v87, v97 :: v_dual_lshlrev_b32 v99, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v97, v101, v13, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v99
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v86, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v87, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v98, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v101, 0x400000, v87
-; GFX11-FAKE16-NEXT: v_bfe_u32 v102, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v87, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v98, 0x40c00000, v98
+; GFX11-FAKE16-NEXT: v_bfe_u32 v101, v13, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v99, v99, v87, 0x7fff
+; GFX11-FAKE16-NEXT: v_bfe_u32 v102, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_add3_u32 v97, v101, v13, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v101, 0x400000, v87
+; GFX11-FAKE16-NEXT: v_bfe_u32 v103, v98, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v98
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v113, 0x400000, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v98, 0x40c00000, v98 :: v_dual_cndmask_b32 v87, v99, v101
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v87, v99, v101, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v101, v102, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_bfe_u32 v103, v98, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v98
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v101, v102 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v15, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v103, v103, v98, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v101, v102, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v99, v99, v15, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v87, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v99, v15, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v113, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v98, v103, v112, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v99, v99, v15, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v99, v113, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
@@ -224720,326 +224949,328 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: s_and_b32 s0, s37, 0xffff0000
; GFX11-TRUE16-NEXT: s_and_b32 s1, s25, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s37, 16
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s37, 16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s38, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v10, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s38, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v3, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v10, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s38, 16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s39, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v32.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v6, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s39, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v6
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s40, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v1, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v7, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v7
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s40, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s41, 0xffff0000
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v34.h
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s41, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s42, 0xffff0000
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v1, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s42, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s43, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s43, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s44, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v1, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s44, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s45, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s45, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s46, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v1, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s46, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s47, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s47, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s48, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v1, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s48, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s49, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s49, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s50, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v1, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s50, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s51, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s51, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s12, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v1, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s12, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v0, v3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v5 :: v_dual_add_nc_u32 v1, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v9, 16, 1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v55.h
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v54.h
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v64.h
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v8 :: v_dual_add_nc_u32 v2, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s15, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v2, v5
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v2, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v3, v7 :: v_dual_add_nc_u32 v3, 0x7fff, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s16, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v11, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v65.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v66.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v4, v9 :: v_dual_add_nc_u32 v4, 0x7fff, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
@@ -225072,7 +225303,8 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v67.h
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v68.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v6, v11 :: v_dual_add_nc_u32 v6, 0x7fff, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
@@ -225104,7 +225336,8 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v69.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v70.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v8, v13 :: v_dual_add_nc_u32 v8, 0x7fff, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v11
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
@@ -225137,7 +225370,8 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v71.h
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v81
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v82.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v10, v15 :: v_dual_add_nc_u32 v10, 0x7fff, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v10, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v13
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
@@ -225231,17 +225465,15 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v87.h
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v96, 0x7fff, v96
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v80.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v55.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v53.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v81, v100, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v99, v99
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v83.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v54.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v53.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v52.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v96, v101, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v97.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v51.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v50.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v96, v101, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v97.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v49.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v48.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v39.h
@@ -225249,8 +225481,8 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v37.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v36.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v34.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v32.h
; GFX11-TRUE16-NEXT: s_branch .LBB105_5
; GFX11-TRUE16-NEXT: .LBB105_4:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
@@ -225331,34 +225563,33 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB105_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s36, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s36, 0xffff0000
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s36, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s37, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s37, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s2, s38, 0xffff0000
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v3
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s38, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v2, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v10, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v4, v9, vcc_lo
@@ -225404,35 +225635,36 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s41, 0xffff0000
-; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v2, v3 :: v_dual_add_nc_u32 v1, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s41, 16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v2, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s41, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v5, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v5, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s42, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s42, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v36, v2, v3 :: v_dual_add_nc_u32 v3, v5, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s42, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v2, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v5, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v0, v2 :: v_dual_add_nc_u32 v2, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
@@ -225447,6 +225679,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s43, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v5, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s44, 0xffff0000
@@ -225592,14 +225825,15 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v2, v3 :: v_dual_add_nc_u32 v3, v5, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v2, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v5, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v0, v2 :: v_dual_add_nc_u32 v0, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
@@ -225801,14 +226035,16 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v86, v82, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s25, 0xffff0000
; GFX11-FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v82
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v83, v12, v83 :: v_dual_add_nc_u32 v12, 0x7fff, v13
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v12, v83, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v84
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v85, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v85, v86, v82
; GFX11-FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v13 :: v_dual_add_nc_u32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v85, 0x7fff, v85
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 9e2c1f062baec4..c9af784cf88bc4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -2943,73 +2943,75 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v8 :: v_dual_lshlrev_b32 v8, 16, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
; GFX11-TRUE16-NEXT: .LBB22_4: ; %end
@@ -3030,66 +3032,70 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB22_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v9, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v10, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x7060302
@@ -3406,27 +3412,26 @@ define inreg <4 x i32> @bitcast_v8bf16_to_v4i32_scalar(<8 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s3
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
@@ -3451,8 +3456,8 @@ define inreg <4 x i32> @bitcast_v8bf16_to_v4i32_scalar(<8 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v9, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v5
@@ -3501,27 +3506,28 @@ define inreg <4 x i32> @bitcast_v8bf16_to_v4i32_scalar(<8 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s3, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s4, 0, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -3556,8 +3562,8 @@ define inreg <4 x i32> @bitcast_v8bf16_to_v4i32_scalar(<8 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -7697,73 +7703,75 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v8 :: v_dual_lshlrev_b32 v8, 16, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
; GFX11-TRUE16-NEXT: .LBB46_4: ; %end
@@ -7784,66 +7792,70 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v9, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v10, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x7060302
@@ -8160,27 +8172,26 @@ define inreg <4 x float> @bitcast_v8bf16_to_v4f32_scalar(<8 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s3
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
@@ -8205,8 +8216,8 @@ define inreg <4 x float> @bitcast_v8bf16_to_v4f32_scalar(<8 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v9, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v5
@@ -8255,27 +8266,28 @@ define inreg <4 x float> @bitcast_v8bf16_to_v4f32_scalar(<8 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s3, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s4, 0, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -8310,8 +8322,8 @@ define inreg <4 x float> @bitcast_v8bf16_to_v4f32_scalar(<8 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -12044,73 +12056,75 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v8 :: v_dual_lshlrev_b32 v8, 16, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
; GFX11-TRUE16-NEXT: .LBB66_4: ; %end
@@ -12131,66 +12145,70 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB66_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v9, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v10, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x7060302
@@ -12507,27 +12525,26 @@ define inreg <2 x i64> @bitcast_v8bf16_to_v2i64_scalar(<8 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s3
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
@@ -12552,8 +12569,8 @@ define inreg <2 x i64> @bitcast_v8bf16_to_v2i64_scalar(<8 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v9, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v5
@@ -12602,27 +12619,28 @@ define inreg <2 x i64> @bitcast_v8bf16_to_v2i64_scalar(<8 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s3, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s4, 0, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -12657,8 +12675,8 @@ define inreg <2 x i64> @bitcast_v8bf16_to_v2i64_scalar(<8 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -15950,73 +15968,75 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v8 :: v_dual_lshlrev_b32 v8, 16, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
; GFX11-TRUE16-NEXT: .LBB82_4: ; %end
@@ -16037,66 +16057,70 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB82_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v9, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v10, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v6, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x7060302
@@ -16413,27 +16437,26 @@ define inreg <2 x double> @bitcast_v8bf16_to_v2f64_scalar(<8 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s3
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
@@ -16458,8 +16481,8 @@ define inreg <2 x double> @bitcast_v8bf16_to_v2f64_scalar(<8 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v9, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v5
@@ -16508,27 +16531,28 @@ define inreg <2 x double> @bitcast_v8bf16_to_v2f64_scalar(<8 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s3, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s4, 0, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
@@ -16563,8 +16587,8 @@ define inreg <2 x double> @bitcast_v8bf16_to_v2f64_scalar(<8 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -19499,44 +19523,46 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v9, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.h
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v10, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, v8, v9 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v9, v12 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
@@ -19554,68 +19580,69 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB94_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_and_b32 v12, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v1, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v7, v8 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v11, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v1, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v12, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v13, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v3, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x7060302
; GFX11-FAKE16-NEXT: .LBB94_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -19950,29 +19977,29 @@ define inreg <8 x i16> @bitcast_v8bf16_to_v8i16_scalar(<8 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, 0x7fff, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v3, v10, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s2, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v8 :: v_dual_add_nc_u32 v6, 0x7fff, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v5.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc_lo
@@ -20039,78 +20066,74 @@ define inreg <8 x i16> @bitcast_v8bf16_to_v8i16_scalar(<8 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s4
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, v5, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v3, v10, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s2, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v5, 16, 1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s3, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v10, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v12, v9
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v11, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v12, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v5, v4
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v3, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v3, v7
; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v6, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffff0000, v0, v9
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB95_4:
@@ -22499,73 +22522,69 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v4, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v13, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v8, v9 :: v_dual_and_b32 v6, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v8, v12 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v10, v10, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v13, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v10.h
; GFX11-TRUE16-NEXT: .LBB102_4: ; %end
@@ -22586,68 +22605,69 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB102_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v11, v12 :: v_dual_and_b32 v12, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v13, v1, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v7, v8 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v11, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v1, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v12, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v13, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v3, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x7060302
; GFX11-FAKE16-NEXT: .LBB102_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -22986,25 +23006,24 @@ define inreg <8 x half> @bitcast_v8bf16_to_v8f16_scalar(<8 x bfloat> inreg %a, i
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s1, 0, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s1, 0, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, v5, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s2, 16
@@ -23017,38 +23036,37 @@ define inreg <8 x half> @bitcast_v8bf16_to_v8f16_scalar(<8 x bfloat> inreg %a, i
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v7, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v7, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s3, 16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v5, v11 :: v_dual_add_nc_u32 v10, v10, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v5, v11 :: v_dual_add_nc_u32 v10, 0x7fff, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v12, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v10, v11 :: v_dual_add_nc_u32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
@@ -23087,70 +23105,68 @@ define inreg <8 x half> @bitcast_v8bf16_to_v8f16_scalar(<8 x bfloat> inreg %a, i
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s4
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, v5, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v3, v10, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s2, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s3, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s3, 16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v8 :: v_dual_add_nc_u32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v11, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v10, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v12, v9
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v11, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v12, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
@@ -25339,69 +25355,69 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v6 :: v_dual_lshlrev_b32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v13, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v11, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v6.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v0, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v11, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v6.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v7, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v3, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.h
@@ -25469,87 +25485,83 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v2, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v18
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v2, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v7, v8 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v7, v8 :: v_dual_lshlrev_b32 v7, 16, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v9, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_add3_u32 v1, v11, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add3_u32 v1, v11, v3, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v1, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v7 :: v_dual_lshlrev_b32 v1, 16, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v3
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v9, v4, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v8, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v6, v4, 0x7060302
-; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 24, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v12, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v0, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v3, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 24, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v9, v11, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[7:8]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 8, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
@@ -26035,28 +26047,27 @@ define inreg <16 x i8> @bitcast_v8bf16_to_v16i8_scalar(<8 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s1, 0, s1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s4, 0, s3
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s1, 0, s0
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s4, 0, s3
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s3, 16
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
@@ -26064,70 +26075,65 @@ define inreg <16 x i8> @bitcast_v8bf16_to_v16i8_scalar(<8 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v17.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v9, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v8, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v2 :: v_dual_add_nc_u32 v1, v8, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v6.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v17.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_add_nc_u32 v10, 0x7fff, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v6.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v14.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v14.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v16.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v21
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v21
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v8.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[20:21]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v20
; GFX11-TRUE16-NEXT: s_branch .LBB109_6
@@ -26196,23 +26202,22 @@ define inreg <16 x i8> @bitcast_v8bf16_to_v16i8_scalar(<8 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s3, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s1, 0, s3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v8 :: v_dual_add_nc_u32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0
@@ -26220,29 +26225,30 @@ define inreg <16 x i8> @bitcast_v8bf16_to_v16i8_scalar(<8 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v2, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s2, 16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v10, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v17
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v12, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v6, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index edd6ffe1d0c164..65ce4e7da8a237 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -4046,126 +4046,124 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v12, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v4, v5 :: v_dual_add_f32 v5, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -4196,74 +4194,81 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB22_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v12 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
@@ -4271,59 +4276,56 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v14, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-FAKE16-NEXT: .LBB22_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -4851,52 +4853,52 @@ define inreg <8 x i32> @bitcast_v16bf16_to_v8i32_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: s_and_b32 s6, s5, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s6
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v6, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v3.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
@@ -4930,8 +4932,9 @@ define inreg <8 x i32> @bitcast_v16bf16_to_v8i32_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v8 :: v_dual_add_nc_u32 v3, v9, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -5031,30 +5034,28 @@ define inreg <8 x i32> @bitcast_v16bf16_to_v8i32_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s8
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
; GFX11-FAKE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
@@ -5064,72 +5065,74 @@ define inreg <8 x i32> @bitcast_v16bf16_to_v8i32_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v8, v4 :: v_dual_add_nc_u32 v4, v9, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_add_nc_u32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v9, v10
-; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v3, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_and_b32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s2
; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v10
@@ -5142,35 +5145,37 @@ define inreg <8 x i32> @bitcast_v16bf16_to_v8i32_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v10 :: v_dual_add_nc_u32 v9, v11, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -11520,126 +11525,124 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v12, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v4, v5 :: v_dual_add_f32 v5, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -11670,74 +11673,81 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v12 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
@@ -11745,59 +11755,56 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v14, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -12325,52 +12332,52 @@ define inreg <8 x float> @bitcast_v16bf16_to_v8f32_scalar(<16 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: s_and_b32 s6, s5, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s6
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v6, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v3.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
@@ -12404,8 +12411,9 @@ define inreg <8 x float> @bitcast_v16bf16_to_v8f32_scalar(<16 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v8 :: v_dual_add_nc_u32 v3, v9, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -12505,30 +12513,28 @@ define inreg <8 x float> @bitcast_v16bf16_to_v8f32_scalar(<16 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s8
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
; GFX11-FAKE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
@@ -12538,72 +12544,74 @@ define inreg <8 x float> @bitcast_v16bf16_to_v8f32_scalar(<16 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v8, v4 :: v_dual_add_nc_u32 v4, v9, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_add_nc_u32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v9, v10
-; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v3, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_and_b32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s2
; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v10
@@ -12616,35 +12624,37 @@ define inreg <8 x float> @bitcast_v16bf16_to_v8f32_scalar(<16 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v10 :: v_dual_add_nc_u32 v9, v11, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -18493,126 +18503,124 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v12, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v4, v5 :: v_dual_add_f32 v5, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -18643,74 +18651,81 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB66_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v12 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
@@ -18718,59 +18733,56 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v14, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-FAKE16-NEXT: .LBB66_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -19298,52 +19310,52 @@ define inreg <4 x i64> @bitcast_v16bf16_to_v4i64_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: s_and_b32 s6, s5, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s6
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v6, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v3.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
@@ -19377,8 +19389,9 @@ define inreg <4 x i64> @bitcast_v16bf16_to_v4i64_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v8 :: v_dual_add_nc_u32 v3, v9, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -19478,30 +19491,28 @@ define inreg <4 x i64> @bitcast_v16bf16_to_v4i64_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s8
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
; GFX11-FAKE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
@@ -19511,72 +19522,74 @@ define inreg <4 x i64> @bitcast_v16bf16_to_v4i64_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v8, v4 :: v_dual_add_nc_u32 v4, v9, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_add_nc_u32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v9, v10
-; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v3, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_and_b32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s2
; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v10
@@ -19589,35 +19602,37 @@ define inreg <4 x i64> @bitcast_v16bf16_to_v4i64_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v10 :: v_dual_add_nc_u32 v9, v11, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -24903,126 +24918,124 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v12, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v4, v5 :: v_dual_add_f32 v5, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -25053,74 +25066,81 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB82_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v15, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v9, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v12, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v12 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v9, 0x7fff
@@ -25128,59 +25148,56 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v12, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v14, v15, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v14, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v16, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v12, 0x7060302
; GFX11-FAKE16-NEXT: .LBB82_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -25708,52 +25725,52 @@ define inreg <4 x double> @bitcast_v16bf16_to_v4f64_scalar(<16 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: s_and_b32 s6, s5, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s6
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v6, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v3.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
@@ -25787,8 +25804,9 @@ define inreg <4 x double> @bitcast_v16bf16_to_v4f64_scalar(<16 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v8 :: v_dual_add_nc_u32 v3, v9, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -25888,30 +25906,28 @@ define inreg <4 x double> @bitcast_v16bf16_to_v4f64_scalar(<16 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s8
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s7, s5, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7
; GFX11-FAKE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
@@ -25921,72 +25937,74 @@ define inreg <4 x double> @bitcast_v16bf16_to_v4f64_scalar(<16 x bfloat> inreg %
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v8, v4 :: v_dual_add_nc_u32 v4, v9, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v11, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_add_nc_u32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v1, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v9, v10
-; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s3
; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v6, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v3, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v9, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_and_b32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s2
; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v10
@@ -25999,35 +26017,37 @@ define inreg <4 x double> @bitcast_v16bf16_to_v4f64_scalar(<16 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v10 :: v_dual_add_nc_u32 v9, v11, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -30904,50 +30924,52 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v14, v16, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v11, v13 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v14, v10, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v14, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v14, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v15, v12, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v11, v13 :: v_dual_add_f32 v13, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
@@ -30956,68 +30978,61 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v11, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v13, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v17, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v14, v15 :: v_dual_lshlrev_b32 v17, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v14, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v19, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v13.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v16, v18 :: v_dual_lshlrev_b32 v18, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v19, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v14, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v15, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v17, v14, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v11.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v18, v19, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v17, v20, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v16, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
@@ -31046,50 +31061,47 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v11, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v13, v11 :: v_dual_and_b32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v12, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v9, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v9, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
@@ -31111,43 +31123,41 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v12, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v19, v12, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v14, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v19 :: v_dual_cndmask_b32 v12, v18, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v21, v5, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v23, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
@@ -31158,11 +31168,10 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v19, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v14, 0x7060302
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v12, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v13, v16, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -31734,27 +31743,26 @@ define inreg <16 x i16> @bitcast_v16bf16_to_v16i16_scalar(<16 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, 0x7fff, v5
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s5, 0xffff0000
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v3, v10, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s2, 16
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s5, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
@@ -31775,7 +31783,8 @@ define inreg <16 x i16> @bitcast_v16bf16_to_v16i16_scalar(<16 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v12, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v10.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v3, v4 :: v_dual_add_nc_u32 v3, v5, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
@@ -31891,28 +31900,27 @@ define inreg <16 x i16> @bitcast_v16bf16_to_v16i16_scalar(<16 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s8
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s2, 0xffff0000
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s2, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s2, 16
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s5, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v8 :: v_dual_add_nc_u32 v5, 0x7fff, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s5, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -31921,105 +31929,110 @@ define inreg <16 x i16> @bitcast_v16bf16_to_v16i16_scalar(<16 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v5, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v4, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s3, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s3, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v10, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s4, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v12, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s4, 16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v12, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s5, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v11, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v5, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s5, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v13, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v5, v12 :: v_dual_add_nc_u32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v15, v11
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, 0xffff0000
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s6, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v13
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s7, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v14, v18 :: v_dual_add_nc_u32 v14, 0x7fff, v16
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v7
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s7, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v15, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v13
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v14, v18 :: v_dual_add_nc_u32 v14, v20, v17
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s7, 0xffff0000
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v14, v18, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v14, v18, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v20, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v22, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v21, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v24, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v22, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v24, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, 0xffff0000, v11, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v3, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v19
-; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v3, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v6, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0xffff0000, v16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
@@ -36324,11 +36337,11 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_2
; GFX11-TRUE16-NEXT: .LBB102_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -36345,33 +36358,32 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v9, v7, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v4 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v10.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
@@ -36387,14 +36399,15 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v17.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v14
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v10.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v4, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v12, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
@@ -36476,50 +36489,47 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v12, v12, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v11, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v13, v11 :: v_dual_and_b32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v12, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v9, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v9, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
@@ -36541,43 +36551,41 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v12, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v15, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v19, v12, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v14, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v19 :: v_dual_cndmask_b32 v12, v18, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v21, v5, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v23, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
@@ -36588,11 +36596,10 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v19, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v14, 0x7060302
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v12, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v13, v16, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -37175,8 +37182,8 @@ define inreg <16 x half> @bitcast_v16bf16_to_v16f16_scalar(<16 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -37188,9 +37195,9 @@ define inreg <16 x half> @bitcast_v16bf16_to_v16f16_scalar(<16 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s8
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -37352,17 +37359,17 @@ define inreg <16 x half> @bitcast_v16bf16_to_v16f16_scalar(<16 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s2, 16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: s_and_b32 s8, s2, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_and_b32 s8, s2, 0xffff0000
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s2, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s4, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -37371,57 +37378,52 @@ define inreg <16 x half> @bitcast_v16bf16_to_v16f16_scalar(<16 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, 0xffff0000
-; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_add_nc_u32 v4, v6, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s3, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s4, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v9 :: v_dual_add_nc_u32 v5, 0x7fff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, 0xffff0000
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s5, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v12, 16, 1
@@ -37436,75 +37438,79 @@ define inreg <16 x half> @bitcast_v16bf16_to_v16f16_scalar(<16 x bfloat> inreg %
; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v15, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s6, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v6
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v10 :: v_dual_add_nc_u32 v10, v14, v15
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s7, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s0, s7, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v13, v16, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v20, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v16 :: v_dual_add_nc_u32 v15, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v12
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v15, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v20, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v11, 16, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v13, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v15, v16, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v17, 16, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v17, 16, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v9, 16, v12
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v11, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v8, 16, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v14
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB103_4:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -41503,20 +41509,21 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v10 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
@@ -41524,7 +41531,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v17, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v3
@@ -41534,108 +41541,107 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v11, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v0, v9, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v12, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v11.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v12, v0, v3 :: v_dual_and_b32 v3, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v14
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v27
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v0, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v9, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v8, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v12.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[26:27]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v1, v2 :: v_dual_add_f32 v1, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v11.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v26
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v13, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v9 :: v_dual_add_f32 v1, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v14, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v14, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v9, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v14, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v20.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v3, v5 :: v_dual_add_f32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v16.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v1, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v20.h
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v13, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v16.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v6, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v35
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v34
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v32
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v6, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 24, v27
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 24, v27
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v1, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v24.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v51
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v51
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[50:51]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[34:35]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[32:33]
@@ -41733,148 +41739,148 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB108_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v39
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v38
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v38
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v36
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v34
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v34
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v39
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_and_b32 v3, 0xffff0000, v38
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v6, v8 :: v_dual_and_b32 v8, 0xffff0000, v37
; GFX11-FAKE16-NEXT: v_add3_u32 v1, v9, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v7, v0 :: v_dual_lshlrev_b32 v6, 16, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v6 :: v_dual_lshlrev_b32 v7, 16, v36
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v36
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v1, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v4, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v3, v11, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v13, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v3, v11, 0x7060302
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v12, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v6, v2, 0x7060302
+; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v10, v12, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v35
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v13, v14, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v7, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v13, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v15
; GFX11-FAKE16-NEXT: v_add3_u32 v14, v16, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v10, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v16, v10, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v15 :: v_dual_add_f32 v15, 0x40c00000, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v10, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v18, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v16, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v16, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v20, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v17, v19 :: v_dual_lshlrev_b32 v20, 16, v32
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v33
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v16, v17 :: v_dual_add_f32 v16, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v32
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v19 :: v_dual_add_f32 v19, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v7, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v16, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v21, v16, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v32
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v15, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v10, v14, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v21 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v15, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v20
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v15, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v22, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v10
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v15, 0x7fff
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v17, v13, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v7, v24, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v9, v12, 0x7060302
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v20, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 8, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v21, v19, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[15:16]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[7:8]
@@ -41885,7 +41891,9 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 24, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 8, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 8, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 24, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 8, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
@@ -42770,30 +42778,28 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-TRUE16-NEXT: s_and_b32 s4, s0, 0xffff0000
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s3
+; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x400000, v3
@@ -42802,34 +42808,33 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s18, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s18, 16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v35.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v12, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v9, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v13, v12
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s2, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v7
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s2, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.h, v6.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.h, v6.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v12, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
@@ -42844,7 +42849,7 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s17, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v13, v12
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4
@@ -42861,27 +42866,26 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v4, v4, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s16, 16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_add_nc_u32 v7, v11, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v11, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.h, v14.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v34.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v9, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
@@ -42901,7 +42905,7 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.h, v14.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -42909,36 +42913,38 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v8.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v22.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.h, v10.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[36:37]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.h, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v32.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[38:39]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v51
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.h, v10.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[36:37]
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v24.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v16.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[38:39]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v51
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v51
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v49
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.h, v26.l
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[48:49]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v49
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v48
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v39
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v39
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[50:51]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v50
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v39
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v39
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v38
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v37
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v37
@@ -43044,85 +43050,94 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, 0xffff0000
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v4, v10, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v10, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v6, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v6, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_and_b32 v1, 0xffff, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v35
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, 0x400000, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v11, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v37, v6, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v10, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v11, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s2, 16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v36, v2, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v34
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v37
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v4
; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v37
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v34
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v39, v14, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v4, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v10, v9
@@ -43134,9 +43149,8 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v12
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
@@ -43158,65 +43172,64 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v13, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v17, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v16, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v16
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v15, v20 :: v_dual_and_b32 v5, 0xffff, v33
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v15, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v33
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v49, v22, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 24, v49
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 8, v49
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v11, v13 :: v_dual_and_b32 v3, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 24, v39
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v39
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v37
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v49, v22, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v38, v10, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v51, v30, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 24, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[38:39]
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v51
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v50, v26, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v48, v18, 16, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v32
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v38, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[36:37]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v50
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 8, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 8, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[50:51]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[48:49]
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v51, v30, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[38:39]
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v50
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 8, v48
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 24, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v39
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 8, v38
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v37
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v36
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[50:51]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v51
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 8, v51
; GFX11-FAKE16-NEXT: s_branch .LBB109_6
; GFX11-FAKE16-NEXT: .LBB109_5:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, s18 :: v_dual_mov_b32 v33, s17
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index a0bc1b4c244c07..f14faa1f45d57b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -18565,8 +18565,8 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v35, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v35, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v33, v3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v1 :: v_dual_mov_b32 v37, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:32
@@ -18579,11 +18579,11 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v53, v9
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v51, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v53, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v31, v8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v39, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v39, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(9)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v66, 8, v0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
@@ -24984,8 +24984,8 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v35, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v35, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v33, v3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v1 :: v_dual_mov_b32 v37, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:32
@@ -24998,11 +24998,11 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v51, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v53, v9
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v15 :: v_dual_mov_b32 v49, v10
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v51, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v12 :: v_dual_mov_b32 v53, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v11 :: v_dual_mov_b32 v31, v8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v7 :: v_dual_mov_b32 v39, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v39, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(9)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v66, 8, v0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
@@ -29461,8 +29461,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v32, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v34, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v34, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v32, v13
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
@@ -33307,8 +33307,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v32, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v34, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v34, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v32, v13
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
index 4e307f1d8aca20..8f8cd9205e24bd 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
@@ -170,14 +170,14 @@ define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x7fc0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX11-TRUE16-NEXT: .LBB0_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -195,32 +195,31 @@ define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB0_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, 0x7fc0, v1, 16
; GFX11-FAKE16-NEXT: .LBB0_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -409,39 +408,39 @@ define inreg <3 x half> @bitcast_v3bf16_to_v3f16_scalar(<3 x bfloat> inreg %a, i
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB1_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0x7fc0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -465,41 +464,43 @@ define inreg <3 x half> @bitcast_v3bf16_to_v3f16_scalar(<3 x bfloat> inreg %a, i
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB1_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s0, 16
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v8 :: v_dual_and_b32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, 0x7fc0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB1_4:
@@ -928,16 +929,14 @@ define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v3, v7 :: v_dual_mov_b32 v3, 0x7fc0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fc0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: .LBB4_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -954,32 +953,31 @@ define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB4_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, 0x7fc0, v1, 16
; GFX11-FAKE16-NEXT: .LBB4_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1182,20 +1180,20 @@ define inreg <3 x i16> @bitcast_v3bf16_to_v3i16_scalar(<3 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v4, v4, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0x7fc0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB5_4:
@@ -1218,38 +1216,38 @@ define inreg <3 x i16> @bitcast_v3bf16_to_v3i16_scalar(<3 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB5_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s0, 16
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, 0x7fc0, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffff0000, v2, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB5_4:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 6912544b7271ae..59725b5b5dea6c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -6482,219 +6482,230 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v20, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v19, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
@@ -6703,35 +6714,34 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -6766,136 +6776,140 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB22_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -6904,143 +6918,138 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v18, v22 :: v_dual_lshlrev_b32 v21, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v21 :: v_dual_lshlrev_b32 v18, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v20, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
; GFX11-FAKE16-NEXT: .LBB22_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -8046,58 +8055,60 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
@@ -8118,136 +8129,141 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
@@ -8376,31 +8392,30 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB23_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -8431,8 +8446,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -8441,93 +8456,104 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -8553,18 +8579,18 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v5 :: v_dual_and_b32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
@@ -8572,7 +8598,6 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
@@ -8628,38 +8653,46 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
@@ -8668,40 +8701,39 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB23_4:
@@ -21407,219 +21439,230 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v20, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v19, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
@@ -21628,35 +21671,34 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -21691,136 +21733,140 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -21829,143 +21875,138 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v18, v22 :: v_dual_lshlrev_b32 v21, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v21 :: v_dual_lshlrev_b32 v18, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v20, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -22971,58 +23012,60 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
@@ -23043,136 +23086,141 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
@@ -23301,31 +23349,30 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB47_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -23356,8 +23403,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -23366,93 +23413,104 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -23478,18 +23536,18 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v5 :: v_dual_and_b32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
@@ -23497,7 +23555,6 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
@@ -23553,38 +23610,46 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
@@ -23593,40 +23658,39 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB47_4:
@@ -35688,219 +35752,230 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v20, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v19, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
@@ -35909,35 +35984,34 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -35972,136 +36046,140 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB66_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -36110,143 +36188,138 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v18, v22 :: v_dual_lshlrev_b32 v21, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v21 :: v_dual_lshlrev_b32 v18, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v20, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
; GFX11-FAKE16-NEXT: .LBB66_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -37252,58 +37325,60 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
@@ -37324,136 +37399,141 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
@@ -37582,31 +37662,30 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB67_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -37637,8 +37716,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -37647,93 +37726,104 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -37759,18 +37849,18 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v5 :: v_dual_and_b32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
@@ -37778,7 +37868,6 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
@@ -37834,38 +37923,46 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
@@ -37874,40 +37971,39 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB67_4:
@@ -49030,219 +49126,230 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v20, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v19, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
@@ -49251,35 +49358,34 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
@@ -49314,136 +49420,140 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB82_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v12
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v9
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -49452,143 +49562,138 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v18, v22 :: v_dual_lshlrev_b32 v21, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v21 :: v_dual_lshlrev_b32 v18, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v20
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v20, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
; GFX11-FAKE16-NEXT: .LBB82_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -50594,58 +50699,60 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
@@ -50666,136 +50773,141 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
@@ -50924,31 +51036,30 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB83_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
@@ -50979,8 +51090,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
@@ -50989,93 +51100,104 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -51101,18 +51223,18 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v5 :: v_dual_and_b32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
@@ -51120,7 +51242,6 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
@@ -51176,38 +51297,46 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v19, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
@@ -51216,40 +51345,39 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB83_4:
@@ -62027,13 +62155,12 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v30, 16, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
@@ -62042,70 +62169,69 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v17, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v20, vcc_lo
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v18, 16, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v21, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v20, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v22, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v19, v21 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v18, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v2, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v23, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v19, v21 :: v_dual_add_f32 v21, 0x40c00000, v24
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v20, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v22, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v3, v19, v23
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v24, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
@@ -62113,19 +62239,20 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v22, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v20.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v24, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v19, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v24, v25, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v21, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v26
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v24, v25, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v7
@@ -62182,7 +62309,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v30
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v23.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v20.h
; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v9, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v28, v29, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v11
@@ -62198,20 +62325,19 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v28, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v26.h
; GFX11-TRUE16-NEXT: v_add3_u32 v27, v30, v10, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v25, v29, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v30, v31, v28, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v27, v29, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v11, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v25.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v24.h
; GFX11-TRUE16-NEXT: v_add3_u32 v27, v27, v11, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v30, v31, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v11
@@ -62228,6 +62354,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v27, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v28.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v30, v32, v12, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v12
@@ -62249,7 +62376,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v30, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v22.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v31, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v34
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v33, v30, 0x7fff
@@ -62259,6 +62386,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v31, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v24.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v14, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v34, v35, v31, 0x7fff
@@ -62276,7 +62404,6 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v32, v37, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v31.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v28.h
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -62294,110 +62421,109 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_lshlrev_b32 v27, 16, v8
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v19, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_add_f32 v25, 0x40c00000, v25
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_lshlrev_b32 v29, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v20, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
-; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v12
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v22, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v23, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v21, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v22, v23, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v4, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v19, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v4, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v23, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
@@ -62417,6 +62543,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v26, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v21, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v24, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v6
@@ -62476,68 +62603,70 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v31, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v26, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v34, v12, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_add3_u32 v29, v29, v11, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v33, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v28
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v31, v33, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v35, v28, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v13, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v26, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v30, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v13 :: v_dual_add_f32 v14, 0x40c00000, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v37, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v13, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v37, v13, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v35, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v15, 16, 1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v39, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v37, v38 :: v_dual_add_f32 v15, 0x40c00000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v15, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v31, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v15, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v15, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v35, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v34, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v30, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v29, v32, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v27, 0x7060302
; GFX11-FAKE16-NEXT: .LBB94_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -63664,23 +63793,23 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: s_and_b32 s1, s25, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v3, v10, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
@@ -63717,7 +63846,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v3, v7 :: v_dual_add_nc_u32 v5, v5, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s16, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v10
@@ -63756,7 +63886,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v12
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v6, v11 :: v_dual_add_nc_u32 v6, 0x7fff, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
@@ -63789,7 +63920,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v15
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v8, v13 :: v_dual_add_nc_u32 v8, 0x7fff, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v11
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
@@ -63821,7 +63953,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v24
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v26.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v10, v15 :: v_dual_add_nc_u32 v10, 0x7fff, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v10, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v13
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
@@ -63962,18 +64095,18 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s13, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s14, 0xffff0000
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s14, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s27, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc_lo
@@ -63981,58 +64114,58 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v2, v6, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v5
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v3
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v7
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s15, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v5, v6, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v4
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v6, v8 :: v_dual_add_nc_u32 v7, v9, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v6, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
@@ -64163,11 +64296,11 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v27
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v28, 16, 1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v29 :: v_dual_add_nc_u32 v15, v30, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v30, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v29, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v14
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v13, v31, vcc_lo
@@ -74466,29 +74599,31 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v7, v9 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v8, v10 :: v_dual_and_b32 v10, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v17, v5, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v20
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
@@ -74511,6 +74646,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
@@ -74520,120 +74656,116 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v10, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v10, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v12 :: v_dual_lshlrev_b32 v8, 16, v23
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v10, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v24
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v12, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v12, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v12, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v12, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v12, 16, 1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v14 :: v_dual_lshlrev_b32 v10, 16, v25
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v12, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v8, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v13, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v9, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v27
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v24 :: v_dual_lshlrev_b32 v12, 16, v27
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v24
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v13, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v14, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_add_f32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v26, v10, v15 :: v_dual_add_f32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v25.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v10, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v24, v11, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v29
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v26.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v24, v13, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v24, v13, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v27
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v25.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v24, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v11, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v28 :: v_dual_lshlrev_b32 v14, 16, v29
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v24, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v33.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v15, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v30
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24
; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v13, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v30, 16, v30
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v27, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v28, v13, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v13
; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v14, 16, 1
@@ -74706,110 +74838,109 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_lshlrev_b32 v27, 16, v8
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v19, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2
; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_add_f32 v25, 0x40c00000, v25
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_lshlrev_b32 v29, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v20, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
-; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v18, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v12
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v22, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v23, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v21, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v22, v23, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v4, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v19, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v17, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v4, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v23, v24, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
@@ -74829,6 +74960,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v26, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v21, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v24, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v6
@@ -74888,68 +75020,70 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v31, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v26, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v34, v12, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_add3_u32 v29, v29, v11, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v33, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v28
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v31, v33, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v35, v28, 0x7fff
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v13, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v26, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v30, 0x7060302
; GFX11-FAKE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v13 :: v_dual_add_f32 v14, 0x40c00000, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-FAKE16-NEXT: v_add3_u32 v33, v37, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v13, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v14, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_add3_u32 v33, v37, v13, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v35, v37, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v14, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v15, 16, 1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v39, v34, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v37, v38 :: v_dual_add_f32 v15, 0x40c00000, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v15, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v31, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v15, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v15, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v35, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v34, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v30, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v29, v32, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v27, 0x7060302
; GFX11-FAKE16-NEXT: .LBB102_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -76186,8 +76320,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -76199,25 +76333,24 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s27, 0xffff0000
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v6, v2 :: v_dual_add_nc_u32 v2, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v4, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
@@ -76228,48 +76361,43 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v29
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v6, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s16, 16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v33
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v18.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v7 :: v_dual_add_nc_u32 v4, 0x7fff, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s16, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v4, v6 :: v_dual_add_nc_u32 v4, v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v29
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v4, v6 :: v_dual_add_nc_u32 v4, v7, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v33, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
@@ -76295,7 +76423,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v33
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v6, v8 :: v_dual_add_nc_u32 v6, v9, v11
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
@@ -76305,7 +76433,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
@@ -76331,7 +76459,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v22.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v8, v10 :: v_dual_add_nc_u32 v8, v11, v13
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
@@ -76341,7 +76469,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
@@ -76367,7 +76495,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v24.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v10, v12 :: v_dual_add_nc_u32 v10, v13, v15
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v15
@@ -76377,7 +76505,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v14
; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
@@ -76402,12 +76530,13 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v27.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v12, v12, v14 :: v_dual_add_nc_u32 v13, v15, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v15, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v26, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v29, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v27.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v28
@@ -76460,20 +76589,24 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v25.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v33
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v36, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v22.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v28, v37, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v19.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v28
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v31.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB103_4:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
@@ -76518,8 +76651,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
@@ -76548,7 +76681,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s15, 16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v33
+; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v33, 16, 1
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v3, v4 :: v_dual_add_nc_u32 v3, v6, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v8, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
@@ -76558,7 +76691,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v33, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v33
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
@@ -76567,9 +76700,9 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v3, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
@@ -76593,58 +76726,56 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_add_nc_u32 v8, 0x7fff, v10
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v11, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
@@ -76746,8 +76877,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v26, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v27, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v29 :: v_dual_add_nc_u32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v29, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, v30, v26
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
@@ -87047,115 +87178,117 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v20, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v24, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v52, v18, v23 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v18, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v19
; GFX11-TRUE16-NEXT: v_add3_u32 v23, v25, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v21, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v52.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v23, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v53.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v20 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v53.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[17:18]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v19, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v1, v20, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v1, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v54.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v55.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v55.h
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v19
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v64, v3, v21 :: v_dual_and_b32 v3, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v3, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v64.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v5, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v54.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v1, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v2, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
@@ -87180,84 +87313,89 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v20
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v3, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v66.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v68, v1, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v1, 16, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v67.h
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v66.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v23
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v67.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v68.h
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v23
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v68.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v82.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v81, v1, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v26
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v82.h
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v25
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v81.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v25
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v27, v2, v3 :: v_dual_add_f32 v2, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v28
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v98, v4, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
@@ -87277,48 +87415,49 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v98.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v9 :: v_dual_lshlrev_b32 v3, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v99.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[27:28]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[27:28]
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[25:26]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v115, v4, v6 :: v_dual_add_f32 v6, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v115, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v115.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v117, v2, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v115.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v33
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v33
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v118, v7, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v33
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v27
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v4, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v117.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v27
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v118.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v49
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v49
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[48:49]
@@ -87523,286 +87662,279 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB108_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v17, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v19, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v1, v1, v17, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v18, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v20 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v19, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v21, v23, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v21, v23 :: v_dual_lshlrev_b32 v21, 16, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v19, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v22, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
+; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v19, 0x7fff
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v18
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v3 :: v_dual_add_f32 v21, 0x40c00000, v21
-; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v20, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v21, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v21, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v21, v28, v20, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v18, v17, 0x7060302
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v23, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v24, 16, 1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
-; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v24, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v18, v17, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v17
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v24, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v21, v28, v20, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v4, v3, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v21, v22 :: v_dual_add_f32 v21, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v21, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v25, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v19, v25 :: v_dual_add_f32 v6, 0x40c00000, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v21
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v21, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v19, v20, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v22, v25 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v19, v20, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v6, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v24, v30 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v30, 16, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v24, v30, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v23, 16, 1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v5, 16, 1
; GFX11-FAKE16-NEXT: v_perm_b32 v97, v6, v21, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v31, v23, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v5, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v6
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v30
; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 8, v97
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v24, v25 :: v_dual_add_f32 v24, 0x40c00000, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v8, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v22, v31, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v24, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v8, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v24
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v24, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v8, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v31, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v30, v32, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_lshlrev_b32 v32, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v96, v5, v23, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v31, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v96
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v30, v32 :: v_dual_add_f32 v25, 0x40c00000, v25
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v32, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v25
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v96
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v33, v25, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v25, v30, v31 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v32
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v10
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v25, v30, v31 :: v_dual_add_f32 v30, 0x40c00000, v32
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v10, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v10, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v31, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v7, 0x7fff
-; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v10, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v24, v33, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v30, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v10, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v10
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v30, 0x7fff
-; GFX11-FAKE16-NEXT: v_perm_b32 v85, v8, v22, 0x7060302
-; GFX11-FAKE16-NEXT: v_perm_b32 v84, v7, v25, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v33, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v32, v34 :: v_dual_and_b32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v32, v34, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v12
-; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v84, v7, v25, 0x7060302
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_add_f32 v31, 0x40c00000, v31
; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v35, v31, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v34 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v9, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v34
+; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v32, v33, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v31, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v9, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v31
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v12, 16, 1
-; GFX11-FAKE16-NEXT: v_perm_b32 v83, v10, v24, 0x7060302
-; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v30, v35, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v31, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v12, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v32, v34, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v82, v9, v38, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 8, v83
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v30, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v33, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v30
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v33, v35 :: v_dual_lshlrev_b32 v33, 16, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v11, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v36, v30, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v69, v12, v37, 0x7060302
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 8, v82
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v31, v32, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v33
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v13
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v36, v31, v32 :: v_dual_and_b32 v13, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v34, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v31, v32, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v30, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v4, v3, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v31, v32, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v68, v11, v36, 0x7060302
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v34, v30, 0x7fff
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v32, v33 :: v_dual_and_b32 v14, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v30, v34, v14, 0x7fff
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v32, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v31
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v65, v14, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v30, v34, v14, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v32, v33, vcc_lo
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v14
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v35, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v65
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v34, v34, v39 :: v_dual_add_f32 v13, 0x40c00000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v68, v11, v36, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v83, v10, v24, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v85, v8, v22, 0x7060302
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v32, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v13, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: v_add3_u32 v31, v48, v13, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v13
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-FAKE16-NEXT: v_add3_u32 v31, v48, v13, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v15
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v65, v14, v33, 0x7060302
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v31, v32, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v39
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v35, v30, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v30
+; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v16, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v15, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v31, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v31
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v15, 0x7fff
-; GFX11-FAKE16-NEXT: v_add3_u32 v48, v48, v31, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; GFX11-FAKE16-NEXT: v_perm_b32 v64, v13, v34, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v64
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v16, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v39, v16, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v15, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v48, v48, v31, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v82, v9, v38, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v35, v39, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v15, 0x7fff
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v65
+; GFX11-FAKE16-NEXT: v_perm_b32 v51, v16, v32, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v48, v49, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v25
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 24, v51
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v51
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v30, v50, vcc_lo
-; GFX11-FAKE16-NEXT: v_perm_b32 v51, v16, v32, 0x7060302
+; GFX11-FAKE16-NEXT: v_perm_b32 v69, v12, v37, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v32
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
@@ -87830,14 +87962,15 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v24
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[28:29]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[26:27]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 24, v51
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v51
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 8, v50
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 24, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v64
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 24, v69
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 8, v69
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 8, v68
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 24, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 8, v83
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 8, v82
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 24, v85
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 8, v85
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v84
@@ -90179,19 +90312,18 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, 0xffff0000
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v11, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -90212,7 +90344,8 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v17.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v9 :: v_dual_add_nc_u32 v4, v5, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v5, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v6, v8
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
@@ -90280,7 +90413,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -90301,7 +90434,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v11, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v12 :: v_dual_add_nc_u32 v7, v9, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
@@ -90341,48 +90474,47 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v11, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v15, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_add_nc_u32 v7, v9, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v10
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v14, 16, 1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v12 :: v_dual_add_nc_u32 v8, v9, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
@@ -90395,7 +90527,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_add_nc_u32 v8, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v10, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v12
@@ -90403,38 +90535,31 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v34.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v48.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.h, v33.l
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.h, v29.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v10 :: v_dual_add_nc_u32 v10, 0x7fff, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v7
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v10 :: v_dual_add_nc_u32 v10, 0x7fff, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v39.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v31.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v37.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.h, v32.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v12, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
@@ -90444,68 +90569,77 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v12, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v13, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v13, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v7
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v49.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v11, v51 :: v_dual_add_nc_u32 v10, v10, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v11, v51 :: v_dual_add_nc_u32 v8, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v55.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v38.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v15, v51, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v35.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v52, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v19.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 24, v67
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.h, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v31.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.h, v32.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v54.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v81
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v80
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v84
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v22.l
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[66:67]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[68:69]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v19.l
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[9:10], 24, v[80:81]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[83:84]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[85:86]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 24, v67
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 8, v67
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v66
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v69
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v69
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 8, v68
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v81
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v81
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v80
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v84
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v84
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v83
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v86
@@ -90514,6 +90648,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
@@ -90781,22 +90916,21 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, 0xffff0000
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s2, 16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v6
@@ -90839,13 +90973,13 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v8, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v17, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
@@ -90858,96 +90992,96 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v19, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v9, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v12, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v22, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v12, v8
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v10, v13
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v9
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v12, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v97, v23, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v25
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 24, v97
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v96, v27, 16, v12
+; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 24, v97
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 8, v96
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v15, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 8, v96
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v6
-; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v24
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v84, v26, 16, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v13, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v28, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v29, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v30, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
@@ -90975,41 +91109,44 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v11, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v12, v12, v10
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v31, v11
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v33 :: v_dual_add_nc_u32 v8, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v33, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v11
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v7
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v30
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v13 :: v_dual_add_nc_u32 v7, v7, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v34
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v81, v35, 16, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v83, v32, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v70, v33, 16, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v81, v35, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 24, v70
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
@@ -91086,7 +91223,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v39, 16, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v83, v32, 16, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v82
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v53, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
@@ -91096,14 +91233,14 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v53
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v65, v51, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 24, v70
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v82
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v81
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v64, v52, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v66, v48, 16, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 24, v65
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v81
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[5:6], 24, v[64:65]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[66:67]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[69:70]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[81:82]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index e63aa18c6cfc60..009da205edba14 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -2408,34 +2408,34 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
@@ -2458,37 +2458,37 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB22_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
; GFX11-FAKE16-NEXT: .LBB22_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -2712,23 +2712,23 @@ define inreg i64 @bitcast_v4bf16_to_i64_scalar(<4 x bfloat> inreg %a, i32 inreg
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v9.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2758,42 +2758,42 @@ define inreg i64 @bitcast_v4bf16_to_i64_scalar(<4 x bfloat> inreg %a, i32 inreg
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s1, 0, s1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB23_4:
@@ -5833,34 +5833,34 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
@@ -5883,37 +5883,37 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -6137,23 +6137,23 @@ define inreg double @bitcast_v4bf16_to_f64_scalar(<4 x bfloat> inreg %a, i32 inr
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v9.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6183,42 +6183,42 @@ define inreg double @bitcast_v4bf16_to_f64_scalar(<4 x bfloat> inreg %a, i32 inr
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s1, 0, s1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB47_4:
@@ -8911,34 +8911,34 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
@@ -8961,37 +8961,37 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB66_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
; GFX11-FAKE16-NEXT: .LBB66_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -9215,23 +9215,23 @@ define inreg <2 x i32> @bitcast_v4bf16_to_v2i32_scalar(<4 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v9.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -9261,42 +9261,42 @@ define inreg <2 x i32> @bitcast_v4bf16_to_v2i32_scalar(<4 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s1, 0, s1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB67_4:
@@ -11631,34 +11631,34 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
@@ -11681,37 +11681,37 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB82_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
; GFX11-FAKE16-NEXT: .LBB82_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -11935,23 +11935,23 @@ define inreg <2 x float> @bitcast_v4bf16_to_v2f32_scalar(<4 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v5 :: v_dual_add_nc_u32 v9, v9, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v9.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -11981,42 +11981,42 @@ define inreg <2 x float> @bitcast_v4bf16_to_v2f32_scalar(<4 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s1, 0, s1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB83_4:
@@ -14270,27 +14270,30 @@ define inreg <4 x i16> @bitcast_v4bf16_to_v4i16_scalar(<4 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s0, 16
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v7, vcc_lo
@@ -14325,31 +14328,32 @@ define inreg <4 x i16> @bitcast_v4bf16_to_v4i16_scalar(<4 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v4, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v3, v1
@@ -15895,30 +15899,30 @@ define <4 x half> @bitcast_v4bf16_to_v4f16(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_and_b32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -16195,31 +16199,31 @@ define inreg <4 x half> @bitcast_v4bf16_to_v4f16_scalar(<4 x bfloat> inreg %a, i
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s1
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s2
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, v5, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -16261,41 +16265,42 @@ define inreg <4 x half> @bitcast_v4bf16_to_v4f16_scalar(<4 x bfloat> inreg %a, i
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v4, v8 :: v_dual_and_b32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB103_4:
@@ -17728,40 +17733,42 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v8
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v7 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v1, v6, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v1, v0, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v2, v3, 0x7060302
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
@@ -18146,28 +18153,28 @@ define inreg <8 x i8> @bitcast_v4bf16_to_v8i8_scalar(<4 x bfloat> inreg %a, i32
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s1, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s1, 0, s1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v6, v6, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v4, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_add_nc_u32 v3, v3, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index 969385f9b0fe2b..c20a4ae3cc6043 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -554,8 +554,8 @@ define <12 x i8> @bitcast_v3i32_to_v12i8(<3 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v3i32_to_v12i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v1 :: v_dual_mov_b32 v11, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
@@ -602,8 +602,8 @@ define <12 x i8> @bitcast_v3i32_to_v12i8(<3 x i32> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v3i32_to_v12i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
@@ -1250,8 +1250,8 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v12i8_to_v3i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v15, v2 :: v_dual_mov_b32 v14, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v14, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v12
@@ -2121,48 +2121,48 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v5 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v8, v11 :: v_dual_and_b32 v2, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v8, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v2, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v11, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc_lo
@@ -2216,24 +2216,24 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -2497,57 +2497,57 @@ define inreg <3 x i32> @bitcast_v6bf16_to_v3i32_scalar(<6 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s3
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v7, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v1, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
@@ -2579,52 +2579,54 @@ define inreg <3 x i32> @bitcast_v6bf16_to_v3i32_scalar(<6 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s3
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v11 :: v_dual_and_b32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc_lo
@@ -3869,8 +3871,8 @@ define <12 x i8> @bitcast_v3f32_to_v12i8(<3 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v3f32_to_v12i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v1 :: v_dual_mov_b32 v11, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
@@ -3916,8 +3918,8 @@ define <12 x i8> @bitcast_v3f32_to_v12i8(<3 x float> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v3f32_to_v12i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
@@ -4583,8 +4585,8 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v12i8_to_v3f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v15, v2 :: v_dual_mov_b32 v14, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v14, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v12
@@ -5465,48 +5467,48 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v5 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v8, v11 :: v_dual_and_b32 v2, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v8, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v2, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v11, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc_lo
@@ -5560,24 +5562,24 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v3, v2, 0x7060302
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -5841,57 +5843,57 @@ define inreg <3 x float> @bitcast_v6bf16_to_v3f32_scalar(<6 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s3
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v7, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v1, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
@@ -5923,52 +5925,54 @@ define inreg <3 x float> @bitcast_v6bf16_to_v3f32_scalar(<6 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s2, 0, s0
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s3
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v11 :: v_dual_and_b32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc_lo
@@ -8171,63 +8175,61 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB38_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, 0x7fc07fc0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, 0x7fc07fc0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v4 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v4, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v8, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v8, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v10, v9, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[10:11]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v10
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v0, v1, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[16:17]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
; GFX11-TRUE16-NEXT: .LBB38_4: ; %end
@@ -8246,8 +8248,8 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v12i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
@@ -8276,31 +8278,31 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB38_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, 0x7fc07fc0 :: v_dual_lshlrev_b32 v1, 16, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, 0x7fc07fc0 :: v_dual_lshlrev_b32 v3, 16, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v2, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v8
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v2, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v4
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v1, v10, v2, 0x7fff
@@ -8732,12 +8734,12 @@ define inreg <12 x i8> @bitcast_v6bf16_to_v12i8_scalar(<6 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, 0x7fc07fc0
@@ -8870,53 +8872,53 @@ define inreg <12 x i8> @bitcast_v6bf16_to_v12i8_scalar(<6 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v8, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v2, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v0, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
+; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v7, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v0, v11, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v9 :: v_dual_add_nc_u32 v3, v3, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v3, v5 :: v_dual_and_b32 v4, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v2, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v6, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v10, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[14:15]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v2, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[14:15]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[11:12]
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v14
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v13
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB39_5:
@@ -11365,8 +11367,8 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v6i16_to_v12i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
@@ -11960,50 +11962,49 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v0, v9, v10
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v11, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
@@ -12025,38 +12026,37 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v9, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
@@ -12350,32 +12350,31 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s3, 0, s1
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s3
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v6, 16, 1
@@ -12386,17 +12385,17 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v7
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
@@ -12438,20 +12437,20 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s4, 0, s2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v3
@@ -12460,40 +12459,41 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v4, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v9 :: v_dual_add_nc_u32 v1, v1, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB49_4:
@@ -13062,58 +13062,54 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v6, v7 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v9, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v9 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.h
; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
@@ -13132,38 +13128,37 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v0, 16, 1
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v9, v1, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
@@ -13460,43 +13455,44 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s3
-; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v4, v9 :: v_dual_add_nc_u32 v9, v10, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v2, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v8, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v1, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo
@@ -13534,41 +13530,43 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s3
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_pack_lh_b32_b16 s0, 0, s2
+; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v8 :: v_dual_add_nc_u32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v9 :: v_dual_add_nc_u32 v4, 0x7fff, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v11 :: v_dual_add_nc_u32 v7, v7, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v10, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v9, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v10, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
index 283c03d8df5bc0..520ee0be981cd2 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
@@ -417,14 +417,15 @@ define amdgpu_cs_chain void @alloca_and_call() #0 {
define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) #0 {
; GISEL-GFX11-LABEL: cs_to_chain:
; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v10, v2
+; GISEL-GFX11-NEXT: v_mov_b32_e32 v3, v0
; GISEL-GFX11-NEXT: s_mov_b32 s3, s0
; GISEL-GFX11-NEXT: ;;#ASMSTART
; GISEL-GFX11-NEXT: s_nop
; GISEL-GFX11-NEXT: ;;#ASMEND
+; GISEL-GFX11-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v10, v2
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX11-NEXT: v_mov_b32_e32 v8, v3
; GISEL-GFX11-NEXT: s_mov_b32 s4, chain_callee at abs32@lo
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v1
; GISEL-GFX11-NEXT: s_mov_b32 s5, chain_callee at abs32@hi
; GISEL-GFX11-NEXT: s_mov_b32 s0, s3
; GISEL-GFX11-NEXT: s_mov_b32 s32, 0
@@ -459,14 +460,15 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) #0 {
;
; DAGISEL-GFX11-LABEL: cs_to_chain:
; DAGISEL-GFX11: ; %bb.0:
-; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v10, v2
+; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v3, v0
; DAGISEL-GFX11-NEXT: s_mov_b32 s3, s0
; DAGISEL-GFX11-NEXT: ;;#ASMSTART
; DAGISEL-GFX11-NEXT: s_nop
; DAGISEL-GFX11-NEXT: ;;#ASMEND
+; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v10, v2
+; DAGISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v8, v3
; DAGISEL-GFX11-NEXT: s_mov_b32 s5, chain_callee at abs32@hi
-; DAGISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v1
; DAGISEL-GFX11-NEXT: s_mov_b32 s4, chain_callee at abs32@lo
; DAGISEL-GFX11-NEXT: s_mov_b32 s0, s3
; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
index 181ffe3ce6aed5..9be79553c40257 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
@@ -30,14 +30,15 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_no_stack({ptr, i3
define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %a, <3 x i32> %b) #0 {
; GISEL-GFX11-LABEL: cs_to_chain_preserve:
; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v10, v2
+; GISEL-GFX11-NEXT: v_mov_b32_e32 v3, v0
; GISEL-GFX11-NEXT: s_mov_b32 s3, s0
; GISEL-GFX11-NEXT: ;;#ASMSTART
; GISEL-GFX11-NEXT: s_nop
; GISEL-GFX11-NEXT: ;;#ASMEND
+; GISEL-GFX11-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v10, v2
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX11-NEXT: v_mov_b32_e32 v8, v3
; GISEL-GFX11-NEXT: s_mov_b32 s4, chain_preserve_callee at abs32@lo
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v1
; GISEL-GFX11-NEXT: s_mov_b32 s5, chain_preserve_callee at abs32@hi
; GISEL-GFX11-NEXT: s_mov_b32 s0, s3
; GISEL-GFX11-NEXT: s_mov_b32 s32, 0
@@ -72,14 +73,15 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %a, <3 x i32> %b) #0
;
; DAGISEL-GFX11-LABEL: cs_to_chain_preserve:
; DAGISEL-GFX11: ; %bb.0:
-; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v10, v2
+; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v3, v0
; DAGISEL-GFX11-NEXT: s_mov_b32 s3, s0
; DAGISEL-GFX11-NEXT: ;;#ASMSTART
; DAGISEL-GFX11-NEXT: s_nop
; DAGISEL-GFX11-NEXT: ;;#ASMEND
+; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v10, v2
+; DAGISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v8, v3
; DAGISEL-GFX11-NEXT: s_mov_b32 s5, chain_preserve_callee at abs32@hi
-; DAGISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v1
; DAGISEL-GFX11-NEXT: s_mov_b32 s4, chain_preserve_callee at abs32@lo
; DAGISEL-GFX11-NEXT: s_mov_b32 s0, s3
; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0
diff --git a/llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll b/llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
index e289b558aecdf0..b8930146c00cf8 100644
--- a/llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
@@ -297,9 +297,8 @@ define float @from_e5m3fnu_f32(i8 %x) {
; GFX1170-NEXT: v_and_b32_e32 v1, 7, v0
; GFX1170-NEXT: v_bfe_u32 v0, v0, 3, 5
; GFX1170-NEXT: v_clz_i32_u32_e32 v2, v1
-; GFX1170-NEXT: v_lshlrev_b32_e32 v5, 20, v1
; GFX1170-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1170-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
; GFX1170-NEXT: v_sub_nc_u32_e32 v3, 31, v2
; GFX1170-NEXT: v_add_nc_u32_e32 v4, -8, v2
@@ -310,18 +309,20 @@ define float @from_e5m3fnu_f32(i8 %x) {
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-NEXT: v_xor_b32_e32 v3, v1, v3
; GFX1170-NEXT: v_lshlrev_b32_e32 v3, v4, v3
-; GFX1170-NEXT: v_lshl_or_b32 v4, v0, 23, v5
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1170-NEXT: v_lshl_or_b32 v2, v2, 23, v3
+; GFX1170-NEXT: v_lshlrev_b32_e32 v5, 20, v1
+; GFX1170-NEXT: v_lshl_or_b32 v4, v0, 23, v5
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_add_nc_u32_e32 v3, 0x38000000, v4
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1170-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1170-NEXT: v_or_b32_e32 v4, v0, v1
-; GFX1170-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
+; GFX1170-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_cmp_ne_u32_e64 s1, 0, v4
-; GFX1170-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1170-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
; GFX1170-NEXT: v_cndmask_b32_e64 v0, 0, v2, s1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1170-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
@@ -651,9 +652,10 @@ define <4 x float> @v4_from_e5m3fnu(<4 x i8> %x) {
; GFX1170-NEXT: v_lshl_or_b32 v9, v12, 23, v9
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-NEXT: v_cmp_eq_u32_e64 s4, 0, v3
-; GFX1170-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_add_nc_u32 v9, -8, v15
+; GFX1170-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
+; GFX1170-NEXT: v_add_nc_u32_e32 v9, -8, v15
; GFX1170-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-NEXT: v_lshlrev_b32_e32 v4, v9, v4
; GFX1170-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
; GFX1170-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v5
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 38bf0c95bd77e3..a15d21d8e6a99d 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -9590,33 +9590,32 @@ define <3 x bfloat> @v_fadd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fadd_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_add_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
@@ -9867,11 +9866,12 @@ define <4 x bfloat> @v_fadd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_dual_add_f32 v3, v7, v6 :: v_dual_add_f32 v4, v5, v4
+; GFX11TRUE16-NEXT: v_add_f32_e32 v3, v7, v6
+; GFX11TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -9907,11 +9907,12 @@ define <4 x bfloat> @v_fadd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_add_f32 v3, v7, v6 :: v_dual_add_f32 v4, v5, v4
+; GFX11FAKE16-NEXT: v_add_f32_e32 v3, v7, v6
+; GFX11FAKE16-NEXT: v_add_f32_e32 v4, v5, v4
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
@@ -10293,28 +10294,22 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fadd_v8bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_add_f32_e32 v7, v3, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_dual_add_f32 v7, v3, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add_f32_e32 v9, v10, v9
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
@@ -10325,35 +10320,38 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v7, v2, v8 :: v_dual_and_b32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
; GFX11TRUE16-NEXT: v_add_f32_e32 v5, v12, v11
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX11TRUE16-NEXT: v_add_f32_e32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
@@ -10371,83 +10369,81 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_fadd_v8bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v8, v9, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_add_f32_e32 v3, v3, v7
; GFX11FAKE16-NEXT: v_add_f32_e32 v7, v10, v9
; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_add_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_add_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11FAKE16-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_add_f32 v1, v1, v5
; GFX11FAKE16-NEXT: v_add_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -11137,51 +11133,51 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_add_f32 v12, v4, v12 :: v_dual_add_f32 v13, v5, v13
; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v19, v18 :: v_dual_add_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
@@ -11229,39 +11225,43 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v9, v20, v19
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v22, v21
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_add_f32 v17, v22, v21 :: v_dual_add_f32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v9, v20, v19 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v8
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -11269,8 +11269,8 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_fadd_v16bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -11286,34 +11286,37 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add_f32_e32 v7, v7, v15
; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc_lo
; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v17, v20, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add_f32_e32 v4, v4, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
@@ -11325,81 +11328,79 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11FAKE16-NEXT: v_add_f32_e32 v12, v18, v12
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_add_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v18, v19, v18
+; GFX11FAKE16-NEXT: v_dual_add_f32 v18, v19, v18 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_add_f32_e32 v3, v3, v11
; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v3, v19, v20 :: v_dual_lshlrev_b32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_dual_add_f32 v1, v1, v9 :: v_dual_add_f32 v2, v2, v10
+; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
; GFX11FAKE16-NEXT: v_add_f32_e32 v19, v22, v20
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_add_f32 v0, v0, v8 :: v_dual_add_f32 v1, v1, v9
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_add_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v8
+; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
@@ -12724,109 +12725,128 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_add_f32 v23, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_dual_add_f32 v20, v4, v20 :: v_dual_and_b32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_dual_add_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_add_f32_e32 v22, v6, v22
-; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v16 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v21, v5, v21 :: v_dual_and_b32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_dual_add_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v2, v18 :: v_dual_add_f32 v1, v1, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_add_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_dual_add_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_dual_add_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_add_f32 v17, v86, v85 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_dual_add_f32 v26, v10, v26 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11TRUE16-NEXT: v_dual_add_f32 v22, v6, v22 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_add_f32_e32 v19, v3, v19
+; GFX11TRUE16-NEXT: v_dual_add_f32 v24, v8, v24 :: v_dual_lshlrev_b32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v28
+; GFX11TRUE16-NEXT: v_dual_add_f32 v27, v11, v27 :: v_dual_and_b32 v38, 0xffff0000, v12
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_dual_add_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_dual_add_f32 v29, v13, v29 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_add_f32_e32 v33, v34, v33
; GFX11TRUE16-NEXT: v_add_f32_e32 v34, v36, v35
; GFX11TRUE16-NEXT: v_add_f32_e32 v36, v48, v39
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_add_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_add_f32_e32 v35, v38, v37
-; GFX11TRUE16-NEXT: v_dual_add_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_dual_add_f32 v35, v38, v37 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_add_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v30, v14, v30
+; GFX11TRUE16-NEXT: v_add_f32_e32 v48, v64, v55
+; GFX11TRUE16-NEXT: v_dual_add_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_add_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_add_f32_e32 v52, v80, v71
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_add_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_add_f32_e32 v54, v84, v83
+; GFX11TRUE16-NEXT: v_add_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_add_f32_e32 v49, v66, v65
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_dual_add_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_dual_add_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11TRUE16-NEXT: v_add_f32_e32 v25, v9, v25
@@ -12839,130 +12859,113 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_add_f32_e32 v37, v50, v49
-; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add_f32_e32 v49, v66, v65
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
-; GFX11TRUE16-NEXT: v_add_f32_e32 v38, v52, v51
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
; GFX11TRUE16-NEXT: v_add_f32_e32 v51, v70, v69
; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
-; GFX11TRUE16-NEXT: v_add_f32_e32 v52, v80, v71
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v50, v68, v67
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v53, v82, v81
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -12998,238 +13001,236 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_add_f32 v7, v7, v23 :: v_dual_and_b32 v26, 0xffff0000, v26
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_add_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_add_f32_e32 v17, v86, v85
+; GFX11FAKE16-NEXT: v_dual_add_f32 v6, v6, v22 :: v_dual_and_b32 v13, 0xffff0000, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11FAKE16-NEXT: v_add_f32_e32 v22, v68, v67
+; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_add_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_add_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_add_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_add_f32 v23, v66, v65 :: v_dual_add_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_add_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_add_f32 v4, v4, v20 :: v_dual_and_b32 v19, 0xffff0000, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11FAKE16-NEXT: v_dual_add_f32 v2, v2, v18 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11FAKE16-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_add_f32_e32 v4, v4, v20
; GFX11FAKE16-NEXT: v_add_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11FAKE16-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11FAKE16-NEXT: v_add_f32_e32 v3, v3, v19
+; GFX11FAKE16-NEXT: v_add_f32_e32 v18, v84, v83
+; GFX11FAKE16-NEXT: v_dual_add_f32 v19, v82, v81 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11FAKE16-NEXT: v_add_f32_e32 v23, v66, v65
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_add_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_add_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_add_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX11FAKE16-NEXT: v_add_f32_e32 v10, v10, v26
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v30
; GFX11FAKE16-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v16
+; GFX11FAKE16-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11FAKE16-NEXT: v_add_f32_e32 v24, v64, v55
+; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_add_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_add_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_dual_add_f32 v14, v14, v30 :: v_dual_lshlrev_b32 v31, 16, v15
+; GFX11FAKE16-NEXT: v_add_f32_e32 v30, v36, v35
+; GFX11FAKE16-NEXT: v_add_f32_e32 v33, v34, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11FAKE16-NEXT: v_add_f32_e32 v26, v52, v51
+; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11FAKE16-NEXT: v_dual_add_f32 v9, v9, v25 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_add_f32 v25, v54, v53 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11FAKE16-NEXT: v_add_f32_e32 v27, v50, v49
+; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11FAKE16-NEXT: v_add_f32_e32 v12, v12, v28
+; GFX11FAKE16-NEXT: v_add_f32_e32 v28, v48, v39
+; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -13958,33 +13959,32 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fsub_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
@@ -14235,11 +14235,12 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_dual_sub_f32 v3, v7, v6 :: v_dual_sub_f32 v4, v5, v4
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v3, v7, v6
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -14275,11 +14276,12 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_sub_f32 v3, v7, v6 :: v_dual_sub_f32 v4, v5, v4
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v3, v7, v6
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v4, v5, v4
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
@@ -14758,33 +14760,32 @@ define <3 x bfloat> @v_fmul_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fmul_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
@@ -15035,11 +15036,12 @@ define <4 x bfloat> @v_fmul_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v3, v7, v6 :: v_dual_mul_f32 v4, v5, v4
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v7, v6
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -15075,11 +15077,12 @@ define <4 x bfloat> @v_fmul_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v3, v7, v6 :: v_dual_mul_f32 v4, v5, v4
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v7, v6
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v4, v5, v4
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
@@ -15461,28 +15464,22 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fmul_v8bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v7, v3, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v7, v3, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v9, v10, v9
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
@@ -15493,35 +15490,38 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v7, v2, v8 :: v_dual_and_b32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v5
; GFX11TRUE16-NEXT: v_mul_f32_e32 v5, v12, v11
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
@@ -15539,83 +15539,81 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_fmul_v8bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v8, v9, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v2, v2, v6
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v3, v7
; GFX11FAKE16-NEXT: v_mul_f32_e32 v7, v10, v9
; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_mul_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_mul_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_mul_f32 v1, v1, v5
; GFX11FAKE16-NEXT: v_mul_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16305,51 +16303,51 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_mul_f32 v12, v4, v12 :: v_dual_mul_f32 v13, v5, v13
; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v19, v18 :: v_dual_mul_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
@@ -16397,39 +16395,43 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v9, v20, v19
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v22, v21
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v17, v22, v21 :: v_dual_mul_f32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v9, v20, v19 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v8
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -16437,8 +16439,8 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_fmul_v16bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -16454,34 +16456,37 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_mul_f32_e32 v7, v7, v15
; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc_lo
; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v17, v20, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_mul_f32_e32 v4, v4, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
@@ -16493,81 +16498,79 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v12, v18, v12
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v18, v19, v18
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v18, v19, v18 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v3, v11
; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v3, v19, v20 :: v_dual_lshlrev_b32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v1, v1, v9 :: v_dual_mul_f32 v2, v2, v10
+; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
; GFX11FAKE16-NEXT: v_mul_f32_e32 v19, v22, v20
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v0, v0, v8 :: v_dual_mul_f32 v1, v1, v9
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_mul_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v8
+; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
@@ -17892,109 +17895,128 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v23, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v20, v4, v20 :: v_dual_and_b32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v22, v6, v22
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v16 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v21, v5, v21 :: v_dual_and_b32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v2, v18 :: v_dual_mul_f32 v1, v1, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v17, v86, v85 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v26, v10, v26 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v22, v6, v22 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v19, v3, v19
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v24, v8, v24 :: v_dual_lshlrev_b32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v28
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v27, v11, v27 :: v_dual_and_b32 v38, 0xffff0000, v12
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v29, v13, v29 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v33, v34, v33
; GFX11TRUE16-NEXT: v_mul_f32_e32 v34, v36, v35
; GFX11TRUE16-NEXT: v_mul_f32_e32 v36, v48, v39
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v35, v38, v37
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v35, v38, v37 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v30, v14, v30
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v48, v64, v55
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v52, v80, v71
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v54, v84, v83
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v49, v66, v65
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11TRUE16-NEXT: v_mul_f32_e32 v25, v9, v25
@@ -18007,130 +18029,113 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v37, v50, v49
-; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v49, v66, v65
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v38, v52, v51
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
; GFX11TRUE16-NEXT: v_mul_f32_e32 v51, v70, v69
; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v52, v80, v71
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v50, v68, v67
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v53, v82, v81
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -18166,238 +18171,236 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v7, v7, v23 :: v_dual_and_b32 v26, 0xffff0000, v26
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v17, v86, v85
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v6, v6, v22 :: v_dual_and_b32 v13, 0xffff0000, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v22, v68, v67
+; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v23, v66, v65 :: v_dual_mul_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v4, v4, v20 :: v_dual_and_b32 v19, 0xffff0000, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v2, v2, v18 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v4, v4, v20
; GFX11FAKE16-NEXT: v_mul_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v3, v19
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v18, v84, v83
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v19, v82, v81 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v23, v66, v65
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v10, v10, v26
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v30
; GFX11FAKE16-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v16
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v24, v64, v55
+; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_mul_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v14, v14, v30 :: v_dual_lshlrev_b32 v31, 16, v15
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v30, v36, v35
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v33, v34, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v26, v52, v51
+; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v9, v9, v25 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_mul_f32 v25, v54, v53 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v27, v50, v49
+; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v12, v12, v28
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v28, v48, v39
+; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -19511,33 +19514,32 @@ define <3 x bfloat> @v_minnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_minnum_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
@@ -19804,11 +19806,12 @@ define <4 x bfloat> @v_minnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_dual_min_f32 v3, v7, v6 :: v_dual_min_f32 v4, v5, v4
+; GFX11TRUE16-NEXT: v_min_f32_e32 v3, v7, v6
+; GFX11TRUE16-NEXT: v_min_f32_e32 v4, v5, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -19844,11 +19847,12 @@ define <4 x bfloat> @v_minnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_min_f32 v3, v7, v6 :: v_dual_min_f32 v4, v5, v4
+; GFX11FAKE16-NEXT: v_min_f32_e32 v3, v7, v6
+; GFX11FAKE16-NEXT: v_min_f32_e32 v4, v5, v4
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
@@ -20262,28 +20266,22 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_minnum_v8bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_min_f32_e32 v7, v3, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_dual_min_f32 v7, v3, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_min_f32_e32 v9, v10, v9
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
@@ -20294,35 +20292,38 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v7, v2, v8 :: v_dual_and_b32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v5
; GFX11TRUE16-NEXT: v_min_f32_e32 v5, v12, v11
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v4
+; GFX11TRUE16-NEXT: v_min_f32_e32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v4 :: v_dual_min_f32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
@@ -20340,83 +20341,81 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_minnum_v8bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_min_f32_e32 v8, v9, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_min_f32_e32 v2, v2, v6
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_min_f32_e32 v3, v3, v7
; GFX11FAKE16-NEXT: v_min_f32_e32 v7, v10, v9
; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_min_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_min_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11FAKE16-NEXT: v_dual_min_f32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_min_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_min_f32 v1, v1, v5
; GFX11FAKE16-NEXT: v_min_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -21170,51 +21169,51 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_min_f32 v12, v4, v12 :: v_dual_min_f32 v13, v5, v13
; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v19, v18 :: v_dual_min_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
@@ -21262,39 +21261,43 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v9, v20, v19
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v22, v21
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_min_f32 v17, v22, v21 :: v_dual_min_f32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v9, v20, v19 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v8
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -21302,8 +21305,8 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_minnum_v16bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -21319,34 +21322,37 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_min_f32_e32 v7, v7, v15
; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc_lo
; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_min_f32_e32 v17, v20, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_min_f32_e32 v4, v4, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
@@ -21358,81 +21364,79 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11FAKE16-NEXT: v_min_f32_e32 v12, v18, v12
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_min_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v18, v19, v18
+; GFX11FAKE16-NEXT: v_dual_min_f32 v18, v19, v18 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_min_f32_e32 v3, v3, v11
; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v3, v19, v20 :: v_dual_lshlrev_b32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_dual_min_f32 v1, v1, v9 :: v_dual_min_f32 v2, v2, v10
+; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
; GFX11FAKE16-NEXT: v_min_f32_e32 v19, v22, v20
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_min_f32 v0, v0, v8 :: v_dual_min_f32 v1, v1, v9
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_min_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v8
+; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
@@ -22885,109 +22889,128 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_min_f32 v23, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_dual_min_f32 v20, v4, v20 :: v_dual_and_b32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_dual_min_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_min_f32_e32 v22, v6, v22
-; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v16 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v21, v5, v21 :: v_dual_and_b32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_dual_min_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v2, v18 :: v_dual_min_f32 v1, v1, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_min_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_dual_min_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_dual_min_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_min_f32 v17, v86, v85 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_dual_min_f32 v26, v10, v26 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11TRUE16-NEXT: v_dual_min_f32 v22, v6, v22 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_min_f32_e32 v19, v3, v19
+; GFX11TRUE16-NEXT: v_dual_min_f32 v24, v8, v24 :: v_dual_lshlrev_b32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v28
+; GFX11TRUE16-NEXT: v_dual_min_f32 v27, v11, v27 :: v_dual_and_b32 v38, 0xffff0000, v12
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_dual_min_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_dual_min_f32 v29, v13, v29 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_min_f32_e32 v33, v34, v33
; GFX11TRUE16-NEXT: v_min_f32_e32 v34, v36, v35
; GFX11TRUE16-NEXT: v_min_f32_e32 v36, v48, v39
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_min_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_min_f32_e32 v35, v38, v37
-; GFX11TRUE16-NEXT: v_dual_min_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_dual_min_f32 v35, v38, v37 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_min_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v30, v14, v30
+; GFX11TRUE16-NEXT: v_min_f32_e32 v48, v64, v55
+; GFX11TRUE16-NEXT: v_dual_min_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_min_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_min_f32_e32 v52, v80, v71
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_min_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_min_f32_e32 v54, v84, v83
+; GFX11TRUE16-NEXT: v_min_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_min_f32_e32 v49, v66, v65
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_dual_min_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_dual_min_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11TRUE16-NEXT: v_min_f32_e32 v25, v9, v25
@@ -23000,130 +23023,113 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_min_f32_e32 v37, v50, v49
-; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_min_f32_e32 v49, v66, v65
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
-; GFX11TRUE16-NEXT: v_min_f32_e32 v38, v52, v51
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
; GFX11TRUE16-NEXT: v_min_f32_e32 v51, v70, v69
; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
-; GFX11TRUE16-NEXT: v_min_f32_e32 v52, v80, v71
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v50, v68, v67
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v53, v82, v81
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -23159,238 +23165,236 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_min_f32 v7, v7, v23 :: v_dual_and_b32 v26, 0xffff0000, v26
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_min_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_min_f32_e32 v17, v86, v85
+; GFX11FAKE16-NEXT: v_dual_min_f32 v6, v6, v22 :: v_dual_and_b32 v13, 0xffff0000, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11FAKE16-NEXT: v_min_f32_e32 v22, v68, v67
+; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_min_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_min_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_min_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_min_f32 v23, v66, v65 :: v_dual_min_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_min_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_min_f32 v4, v4, v20 :: v_dual_and_b32 v19, 0xffff0000, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11FAKE16-NEXT: v_dual_min_f32 v2, v2, v18 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11FAKE16-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_min_f32_e32 v4, v4, v20
; GFX11FAKE16-NEXT: v_min_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11FAKE16-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11FAKE16-NEXT: v_min_f32_e32 v3, v3, v19
+; GFX11FAKE16-NEXT: v_min_f32_e32 v18, v84, v83
+; GFX11FAKE16-NEXT: v_dual_min_f32 v19, v82, v81 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11FAKE16-NEXT: v_min_f32_e32 v23, v66, v65
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_min_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_min_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_min_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX11FAKE16-NEXT: v_min_f32_e32 v10, v10, v26
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v30
; GFX11FAKE16-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v16
+; GFX11FAKE16-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11FAKE16-NEXT: v_min_f32_e32 v24, v64, v55
+; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_min_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_min_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_dual_min_f32 v14, v14, v30 :: v_dual_lshlrev_b32 v31, 16, v15
+; GFX11FAKE16-NEXT: v_min_f32_e32 v30, v36, v35
+; GFX11FAKE16-NEXT: v_min_f32_e32 v33, v34, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11FAKE16-NEXT: v_min_f32_e32 v26, v52, v51
+; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11FAKE16-NEXT: v_dual_min_f32 v9, v9, v25 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_min_f32 v25, v54, v53 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11FAKE16-NEXT: v_min_f32_e32 v27, v50, v49
+; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11FAKE16-NEXT: v_min_f32_e32 v12, v12, v28
+; GFX11FAKE16-NEXT: v_min_f32_e32 v28, v48, v39
+; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -23936,33 +23940,32 @@ define <3 x bfloat> @v_maxnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_maxnum_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_max_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
@@ -24229,11 +24232,12 @@ define <4 x bfloat> @v_maxnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_dual_max_f32 v3, v7, v6 :: v_dual_max_f32 v4, v5, v4
+; GFX11TRUE16-NEXT: v_max_f32_e32 v3, v7, v6
+; GFX11TRUE16-NEXT: v_max_f32_e32 v4, v5, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -24269,11 +24273,12 @@ define <4 x bfloat> @v_maxnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_max_f32 v3, v7, v6 :: v_dual_max_f32 v4, v5, v4
+; GFX11FAKE16-NEXT: v_max_f32_e32 v3, v7, v6
+; GFX11FAKE16-NEXT: v_max_f32_e32 v4, v5, v4
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
@@ -24687,28 +24692,22 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_maxnum_v8bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_max_f32_e32 v7, v3, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_dual_max_f32 v7, v3, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_max_f32_e32 v9, v10, v9
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
@@ -24719,35 +24718,38 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v7, v2, v8 :: v_dual_and_b32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v5
; GFX11TRUE16-NEXT: v_max_f32_e32 v5, v12, v11
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v4
+; GFX11TRUE16-NEXT: v_max_f32_e32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v4 :: v_dual_max_f32 v9, v14, v13
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
@@ -24765,83 +24767,81 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_maxnum_v8bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_max_f32_e32 v8, v9, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_max_f32_e32 v2, v2, v6
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_max_f32_e32 v3, v3, v7
; GFX11FAKE16-NEXT: v_max_f32_e32 v7, v10, v9
; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_max_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_max_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11FAKE16-NEXT: v_dual_max_f32 v0, v0, v4 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_max_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_max_f32 v1, v1, v5
; GFX11FAKE16-NEXT: v_max_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -25595,51 +25595,51 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_max_f32 v12, v4, v12 :: v_dual_max_f32 v13, v5, v13
; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v19, v18 :: v_dual_max_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
@@ -25687,39 +25687,43 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v9, v20, v19
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v22, v21
; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
-; GFX11TRUE16-NEXT: v_dual_max_f32 v17, v22, v21 :: v_dual_max_f32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v9, v20, v19 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v8
; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -25727,8 +25731,8 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-LABEL: v_maxnum_v16bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -25744,34 +25748,37 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_max_f32_e32 v7, v7, v15
; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc_lo
; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_max_f32_e32 v17, v20, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_max_f32_e32 v4, v4, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
@@ -25783,81 +25790,79 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11FAKE16-NEXT: v_max_f32_e32 v12, v18, v12
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_max_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v18, v19, v18
+; GFX11FAKE16-NEXT: v_dual_max_f32 v18, v19, v18 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_max_f32_e32 v3, v3, v11
; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v3, v19, v20 :: v_dual_lshlrev_b32 v20, 16, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_dual_max_f32 v1, v1, v9 :: v_dual_max_f32 v2, v2, v10
+; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
; GFX11FAKE16-NEXT: v_max_f32_e32 v19, v22, v20
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_max_f32 v0, v0, v8 :: v_dual_max_f32 v1, v1, v9
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11FAKE16-NEXT: v_max_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v8
+; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
@@ -27310,109 +27315,128 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_max_f32 v23, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_dual_max_f32 v20, v4, v20 :: v_dual_and_b32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_dual_max_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_max_f32_e32 v22, v6, v22
-; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v16 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v21, v5, v21 :: v_dual_and_b32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_dual_max_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v2, v18 :: v_dual_max_f32 v1, v1, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_max_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_dual_max_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_dual_max_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_max_f32 v17, v86, v85 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_dual_max_f32 v26, v10, v26 :: v_dual_and_b32 v35, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11TRUE16-NEXT: v_dual_max_f32 v22, v6, v22 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_max_f32_e32 v19, v3, v19
+; GFX11TRUE16-NEXT: v_dual_max_f32 v24, v8, v24 :: v_dual_lshlrev_b32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v28
+; GFX11TRUE16-NEXT: v_dual_max_f32 v27, v11, v27 :: v_dual_and_b32 v38, 0xffff0000, v12
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_dual_max_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_dual_max_f32 v29, v13, v29 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_max_f32_e32 v33, v34, v33
; GFX11TRUE16-NEXT: v_max_f32_e32 v34, v36, v35
; GFX11TRUE16-NEXT: v_max_f32_e32 v36, v48, v39
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_max_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_max_f32_e32 v35, v38, v37
-; GFX11TRUE16-NEXT: v_dual_max_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_dual_max_f32 v35, v38, v37 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_max_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v30, v14, v30
+; GFX11TRUE16-NEXT: v_max_f32_e32 v48, v64, v55
+; GFX11TRUE16-NEXT: v_dual_max_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_max_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_max_f32_e32 v52, v80, v71
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11TRUE16-NEXT: v_max_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_max_f32_e32 v54, v84, v83
+; GFX11TRUE16-NEXT: v_max_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_max_f32_e32 v49, v66, v65
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_dual_max_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_dual_max_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11TRUE16-NEXT: v_max_f32_e32 v25, v9, v25
@@ -27425,130 +27449,113 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_max_f32_e32 v37, v50, v49
-; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_max_f32_e32 v49, v66, v65
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
-; GFX11TRUE16-NEXT: v_max_f32_e32 v38, v52, v51
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
; GFX11TRUE16-NEXT: v_max_f32_e32 v51, v70, v69
; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
-; GFX11TRUE16-NEXT: v_max_f32_e32 v52, v80, v71
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v50, v68, v67
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v53, v82, v81
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -27584,238 +27591,236 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_max_f32 v7, v7, v23 :: v_dual_and_b32 v26, 0xffff0000, v26
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_max_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_max_f32_e32 v17, v86, v85
+; GFX11FAKE16-NEXT: v_dual_max_f32 v6, v6, v22 :: v_dual_and_b32 v13, 0xffff0000, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11FAKE16-NEXT: v_max_f32_e32 v22, v68, v67
+; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_max_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_max_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_max_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_max_f32 v23, v66, v65 :: v_dual_max_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_max_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_max_f32 v4, v4, v20 :: v_dual_and_b32 v19, 0xffff0000, v19
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11FAKE16-NEXT: v_dual_max_f32 v2, v2, v18 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11FAKE16-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_max_f32_e32 v4, v4, v20
; GFX11FAKE16-NEXT: v_max_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11FAKE16-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11FAKE16-NEXT: v_max_f32_e32 v3, v3, v19
+; GFX11FAKE16-NEXT: v_max_f32_e32 v18, v84, v83
+; GFX11FAKE16-NEXT: v_dual_max_f32 v19, v82, v81 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11FAKE16-NEXT: v_max_f32_e32 v23, v66, v65
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_max_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_max_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_max_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX11FAKE16-NEXT: v_max_f32_e32 v10, v10, v26
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v30
; GFX11FAKE16-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v16
+; GFX11FAKE16-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11FAKE16-NEXT: v_max_f32_e32 v24, v64, v55
+; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_max_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_max_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_dual_max_f32 v14, v14, v30 :: v_dual_lshlrev_b32 v31, 16, v15
+; GFX11FAKE16-NEXT: v_max_f32_e32 v30, v36, v35
+; GFX11FAKE16-NEXT: v_max_f32_e32 v33, v34, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11FAKE16-NEXT: v_max_f32_e32 v26, v52, v51
+; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11FAKE16-NEXT: v_dual_max_f32 v9, v9, v25 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_dual_max_f32 v25, v54, v53 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11FAKE16-NEXT: v_max_f32_e32 v27, v50, v49
+; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11FAKE16-NEXT: v_max_f32_e32 v12, v12, v28
+; GFX11FAKE16-NEXT: v_max_f32_e32 v28, v48, v39
+; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
@@ -30066,9 +30071,9 @@ define bfloat @v_exp_bf16(bfloat %a) #0 {
; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX11TRUE16-NEXT: v_fmamk_f32 v3, v0, 0x32a5705f, v3
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
; GFX11TRUE16-NEXT: v_exp_f32_e32 v1, v1
; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
@@ -30098,9 +30103,9 @@ define bfloat @v_exp_bf16(bfloat %a) #0 {
; GFX11FAKE16-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX11FAKE16-NEXT: v_fmamk_f32 v3, v0, 0x32a5705f, v3
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
; GFX11FAKE16-NEXT: v_exp_f32_e32 v1, v1
; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
@@ -30534,9 +30539,9 @@ define bfloat @v_exp10_bf16(bfloat %a) #0 {
; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX11TRUE16-NEXT: v_fmamk_f32 v3, v0, 0x33979a37, v3
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0
; GFX11TRUE16-NEXT: v_exp_f32_e32 v1, v1
; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
@@ -30566,9 +30571,9 @@ define bfloat @v_exp10_bf16(bfloat %a) #0 {
; GFX11FAKE16-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX11FAKE16-NEXT: v_fmamk_f32 v3, v0, 0x33979a37, v3
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0
; GFX11FAKE16-NEXT: v_exp_f32_e32 v1, v1
; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
@@ -35339,18 +35344,19 @@ define <4 x bfloat> @v_sitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
@@ -35362,39 +35368,38 @@ define <4 x bfloat> @v_sitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX11FAKE16-NEXT: v_bfe_i32 v3, v0, 0, 16
; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v3, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
; GFX11FAKE16-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -35784,21 +35789,21 @@ define <3 x bfloat> @v_sitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -37084,24 +37089,24 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) #0 {
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v1, 16
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -37622,73 +37627,62 @@ define <4 x bfloat> @v_sitofp_v4i64_to_v4bf16(<4 x i64> %x) #0 {
; GFX11TRUE16-NEXT: v_xor_b32_e32 v13, v2, v3
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v9
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v11
; GFX11TRUE16-NEXT: v_xor_b32_e32 v15, v0, v1
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v11
; GFX11TRUE16-NEXT: v_cls_i32_e32 v14, v1
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8
; GFX11TRUE16-NEXT: v_cls_i32_e32 v12, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v11, 32, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v14, -1, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_min_u32_e32 v8, v9, v8
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v10
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v10, 31, v13
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v13, 31, v15
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v12
; GFX11TRUE16-NEXT: v_lshlrev_b64 v[6:7], v8, v[6:7]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_min_u32_e32 v9, v9, v11
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, 32, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v13, 32, v13
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v9, v[4:5]
+; GFX11TRUE16-NEXT: v_min_u32_e32 v10, v12, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v11, v14, v13
; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 1, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v11, v[0:1]
; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
; GFX11TRUE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v7, 32, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v9
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v4
-; GFX11TRUE16-NEXT: v_ldexp_f32 v4, v4, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v14, -1, v14
-; GFX11TRUE16-NEXT: v_min_u32_e32 v11, v14, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v11, v[0:1]
-; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v4
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v11
; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v6, v7
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v10
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v10, v12, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v2, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -38277,20 +38271,13 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX11FAKE16-LABEL: v_uitofp_v3i16_to_v3bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -38300,11 +38287,17 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v0, v5, v8 :: v_dual_and_b32 v1, 0xffff, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v1, 16
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -38496,33 +38489,34 @@ define <4 x bfloat> @v_uitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v4i16_to_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
@@ -38960,21 +38954,21 @@ define <3 x bfloat> @v_uitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -40570,27 +40564,26 @@ define <4 x bfloat> @v_uitofp_v4i64_to_v4bf16(<4 x i64> %x) #0 {
; GFX11FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11FAKE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX11FAKE16-NEXT: v_ldexp_f32 v4, v4, v9
+; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
; GFX11FAKE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -42867,18 +42860,19 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo
; GFX11FAKE16-LABEL: v_vselect_v4bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v6
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v5 :: v_dual_and_b32 v3, 1, v3
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v0, v6, v4 :: v_dual_and_b32 v1, 1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
@@ -43205,31 +43199,32 @@ define <8 x bfloat> @v_vselect_v8bf16(<8 x i1> %cond, <8 x bfloat> %a, <8 x bflo
; GFX11FAKE16-LABEL: v_vselect_v8bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v10
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v14
; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 1, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v10
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v6, v15, v11 :: v_dual_and_b32 v1, 1, v1
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v4, v14, v10 :: v_dual_and_b32 v3, 1, v3
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v2, v13, v9 :: v_dual_and_b32 v7, 1, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc_lo
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc_lo
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v0, v12, v8 :: v_dual_and_b32 v3, 1, v3
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v14, v10, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
@@ -43856,37 +43851,36 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v34, v33, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v24
; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 1, v8
; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v20
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v20
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v28
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v25
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v36, v35, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v25
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v8, v28, v20 :: v_dual_and_b32 v15, 1, v15
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v38, v37, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v4, v26, v18 :: v_dual_and_b32 v7, 1, v7
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v4, v26, v18 :: v_dual_and_b32 v5, 1, v5
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v52, v51, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v0, v24, v16 :: v_dual_and_b32 v7, 1, v7
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v54, v53, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
@@ -43897,19 +43891,17 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX11FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX11FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v48, v39, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11FAKE16-NEXT: v_perm_b32 v4, v9, v8, 0x5040100
; GFX11FAKE16-NEXT: v_perm_b32 v5, v11, v10, 0x5040100
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v31
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v31, v23, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v3, v32, vcc_lo
; GFX11FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
; GFX11FAKE16-NEXT: v_perm_b32 v6, v13, v12, 0x5040100
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_perm_b32 v7, v15, v14, 0x5040100
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -45502,63 +45494,64 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 1, v20
; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 1, v18
; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(30)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v33, v32, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28
; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(28)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v35, v34, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 1, v5
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(26)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v37, v36, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24
; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 1, v7
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v37
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(24)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v39, v38, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22
; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 1, v9
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v38
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v39
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(22)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v49, v48, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 1, v11
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v48
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v49
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 1, v10
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(20)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v51, v50, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 1, v13
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v50
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v51
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 1, v8
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(18)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v18, v53, v52, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 1, v15
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v52
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v53
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v16, v55, v54 :: v_dual_and_b32 v15, 1, v15
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v55, v54, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 1, v17
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v54
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v55
-; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v14, v65, v64 :: v_dual_and_b32 v17, 1, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v65, v64, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 1, v19
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v64
@@ -46478,14 +46471,15 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX11TRUE16-LABEL: v_fma_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v6, v8, v7
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v0, v2
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
@@ -46493,7 +46487,7 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
@@ -46517,31 +46511,30 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX11FAKE16-LABEL: v_fma_v3bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v4, v0, v2 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v6, v8, v7
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v1, v6, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11FAKE16-NEXT: v_bfe_u32 v0, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -46781,31 +46774,31 @@ define <4 x bfloat> @v_fma_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat>
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_lshlrev_b32 v8, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v4, v9, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v0, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v7, v10, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v0, v7, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
@@ -46827,47 +46820,47 @@ define <4 x bfloat> @v_fma_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat>
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_lshlrev_b32 v8, 16, v2
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v7, v9, v8
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v3, v7, 16, 1
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v0, v2
; GFX11FAKE16-NEXT: v_add3_u32 v0, v10, v6, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v7, v9, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v0, v2, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v7, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v2, v3, v7, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v7
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_add3_u32 v6, v8, v4, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v3, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v9, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v3, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -47275,16 +47268,16 @@ define <8 x bfloat> @v_fma_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat>
; GFX11TRUE16-LABEL: v_fma_v8bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v11, v3, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v10
@@ -47295,58 +47288,59 @@ define <8 x bfloat> @v_fma_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat>
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v12, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v13, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v10
; GFX11TRUE16-NEXT: v_bfe_u32 v10, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v13, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v13, v17, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v14, v16, v15
; GFX11TRUE16-NEXT: v_add3_u32 v2, v10, v11, 0x7fff
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11TRUE16-NEXT: v_bfe_u32 v15, v14, 16, 1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v7, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v2, v6, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v10, v15, v14, 0x7fff
; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v9
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v9, v1, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v8
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.h
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v9, v1, v5
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v12, vcc_lo
; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v7, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v11 :: v_dual_and_b32 v5, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v11 :: v_dual_lshlrev_b32 v13, 16, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v9, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v15, v17, v16
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v15, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v13, v16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v0, v1
; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v15, 0x7fff
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v15, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v0, v13, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v13
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
@@ -47368,85 +47362,85 @@ define <8 x bfloat> @v_fma_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat>
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v0
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v3
; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v12, v14, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v12, v14, v13
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v11, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v2
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; GFX11FAKE16-NEXT: v_bfe_u32 v13, v12, 16, 1
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v11, v3, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; GFX11FAKE16-NEXT: v_bfe_u32 v16, v11, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v11
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11FAKE16-NEXT: v_add3_u32 v12, v16, v11, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v3, v14, v7
; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v10, v13, v15 :: v_dual_and_b32 v7, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v12, v16, v11, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_bfe_u32 v13, v3, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v3
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff
; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v3, v13, v15 :: v_dual_and_b32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v7, v2, v6 :: v_dual_lshlrev_b32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v7, v2, v6 :: v_dual_lshlrev_b32 v2, 16, v9
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11FAKE16-NEXT: v_bfe_u32 v16, v7, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v2, v14, v6 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v2, v14, v6
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v9, v1, v5
; GFX11FAKE16-NEXT: v_add3_u32 v6, v16, v7, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v9, v1, v5 :: v_dual_and_b32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_bfe_u32 v14, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; GFX11FAKE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v8, v0, v4
; GFX11FAKE16-NEXT: v_add3_u32 v0, v14, v2, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v4, v9, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v15, v18, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add3_u32 v0, v4, v9, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v5, v15, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v15
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v2, v5, v15, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v5, v7, v8, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v0, v13, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v4, v2, 0x7060302
; GFX11FAKE16-NEXT: v_perm_b32 v2, v6, v3, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v5, v1, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v12, v17, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v3, v7, v10, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -48219,9 +48213,10 @@ define <16 x bfloat> @v_fma_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b, <16 x bf
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v24, v26, v25 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v26, v25
; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v22
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
@@ -48230,26 +48225,23 @@ define <16 x bfloat> @v_fma_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b, <16 x bf
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v22, v6, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v21
; GFX11TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11TRUE16-NEXT: v_add3_u32 v25, v25, v24, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v24
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_bfe_u32 v24, v26, 16, 1
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v23, v7, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v25, v29, vcc_lo
-; GFX11TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v15, v23, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v24, v26, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v14, v29, v28 :: v_dual_cndmask_b32 v15, v15, v25
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v25, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v4
@@ -48260,108 +48252,110 @@ define <16 x bfloat> @v_fma_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b, <16 x bf
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX11TRUE16-NEXT: v_add3_u32 v23, v23, v22, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v22
-; GFX11TRUE16-NEXT: v_bfe_u32 v28, v14, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v26, v25
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v20, v4, v12
; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v19
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v26, v25
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
+; GFX11TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v24
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v14, v29, v28 :: v_dual_lshlrev_b32 v19, 16, v19
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v21, v5, v13
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v23, v27, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v28, v14, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v28, v14, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v23, v21, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v27, v20, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v24
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v28, v14, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
+; GFX11TRUE16-NEXT: v_add3_u32 v14, v23, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v23, v25, v24, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v22, vcc_lo
; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
-; GFX11TRUE16-NEXT: v_add3_u32 v14, v23, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_add3_u32 v23, v25, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_add3_u32 v21, v27, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v12, v25, v4
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v14, v22, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v20
-; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v14.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v12, v25, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v23, v26, vcc_lo
; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v19, v3, v11
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v23, v26, vcc_lo
; GFX11TRUE16-NEXT: v_bfe_u32 v23, v12, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v18
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v26, v25
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v20, v21, v22 :: v_dual_and_b32 v25, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v26, v25
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc_lo
; GFX11TRUE16-NEXT: v_add3_u32 v21, v23, v12, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v23, v24, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v23, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v19, v3, v11
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v3, v21, v22 :: v_dual_and_b32 v22, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v22, v25, v23 :: v_dual_fmac_f32 v11, v2, v10
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11TRUE16-NEXT: v_bfe_u32 v23, v24, 16, 1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v11, v2, v10
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v19
; GFX11TRUE16-NEXT: v_add3_u32 v2, v18, v19, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v21, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v23, v24, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v24
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v8
; GFX11TRUE16-NEXT: v_bfe_u32 v21, v11, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v17, v1, v9 :: v_dual_cndmask_b32 v10, v2, v10
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v17
+; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v10, v2, v10 :: v_dual_and_b32 v25, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v22, v25, v23 :: v_dual_lshlrev_b32 v23, 16, v8
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v12, v18, vcc_lo
; GFX11TRUE16-NEXT: v_add3_u32 v12, v21, v11, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v11
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v17, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v17, v1, v9
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v21, v24, v23
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v9, v0, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v17, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v12, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v19, v22, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v16
; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v17, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v21, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v19, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v9, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v21, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v22
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v16, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v22
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v18, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v18, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v21, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v10.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v18, v9, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v0, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v10.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v14.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v11.h
@@ -48375,110 +48369,110 @@ define <16 x bfloat> @v_fma_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b, <16 x bf
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v23
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v15
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v24, v26, v25 :: v_dual_and_b32 v23, 0xffff0000, v23
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v24, v26, v25
; GFX11FAKE16-NEXT: v_dual_fmac_f32 v23, v7, v15 :: v_dual_lshlrev_b32 v26, 16, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v22
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v25, v24, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11FAKE16-NEXT: v_bfe_u32 v28, v23, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11FAKE16-NEXT: v_add3_u32 v25, v25, v24, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v22
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v24, v28, v23, 0x7fff
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v7, v26, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v27 :: v_dual_and_b32 v15, 0xffff0000, v22
; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11FAKE16-NEXT: v_bfe_u32 v26, v7, 16, 1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v15, v6, v14 :: v_dual_lshlrev_b32 v6, 16, v21
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v13
; GFX11FAKE16-NEXT: v_add3_u32 v24, v26, v7, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v7
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v24, v25 :: v_dual_and_b32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v15, v6, v14 :: v_dual_lshlrev_b32 v14, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v15
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v21
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v26, v15, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v6, v27, v14
; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v21
+; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11FAKE16-NEXT: v_add3_u32 v21, v26, v15, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v24, v25 :: v_dual_lshlrev_b32 v26, 16, v4
+; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v15
; GFX11FAKE16-NEXT: v_bfe_u32 v25, v6, 16, 1
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v14, v5, v13 :: v_dual_lshlrev_b32 v5, 16, v20
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v14, v5, v13 :: v_dual_lshlrev_b32 v13, 16, v12
+; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v21, v24, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_add3_u32 v21, v25, v6, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v6
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11FAKE16-NEXT: v_bfe_u32 v25, v14, 16, 1
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v5, v26, v13 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v21, v24, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v14
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v20
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v5, v26, v13
; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_add3_u32 v20, v25, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v6, v21, v24 :: v_dual_lshlrev_b32 v25, 16, v3
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v14
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11FAKE16-NEXT: v_bfe_u32 v24, v5, 16, 1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v2
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v20, v21, vcc_lo
+; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11FAKE16-NEXT: v_add3_u32 v20, v24, v5, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v5, v20, v21 :: v_dual_and_b32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_dual_fmac_f32 v13, v4, v12 :: v_dual_lshlrev_b32 v4, 16, v19
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v25, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v20, v21, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v24, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v24, v13, 16, 1
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v25, v12
; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v12, v3, v11 :: v_dual_cndmask_b32 v5, v20, v21
; GFX11FAKE16-NEXT: v_add3_u32 v21, v24, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v13
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v24, v12, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v19, v26, v25
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v12, v3, v11
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v19, v26, v25 :: v_dual_and_b32 v18, 0xffff0000, v18
+; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v4
+; GFX11FAKE16-NEXT: v_bfe_u32 v24, v12, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v25, v19, 16, 1
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v18, v2, v10
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; GFX11FAKE16-NEXT: v_bfe_u32 v25, v19, 16, 1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX11FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v19
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v11, v20, vcc_lo
; GFX11FAKE16-NEXT: v_add3_u32 v11, v24, v12, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
; GFX11FAKE16-NEXT: v_add3_u32 v24, v25, v19, 0x7fff
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v19
; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v2, v25, v10 :: v_dual_and_b32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v2, v25, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v20, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v13
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v8
; GFX11FAKE16-NEXT: v_bfe_u32 v20, v2, 16, 1
; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
@@ -50258,305 +50252,310 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11TRUE16-NEXT: scratch_load_b32 v53, off, s32 offset:12
; GFX11TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:8
; GFX11TRUE16-NEXT: scratch_load_b32 v55, off, s32 offset:4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v99, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v100, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v115, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v116, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v99, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v103, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_and_b32_e32 v112, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(16)
; GFX11TRUE16-NEXT: v_and_b32_e32 v119, 0xffff0000, v31
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(15)
; GFX11TRUE16-NEXT: v_and_b32_e32 v128, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v33
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v33
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v13
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(13)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v34
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v28
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(12)
; GFX11TRUE16-NEXT: v_and_b32_e32 v131, 0xffff0000, v35
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(10)
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(11)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v36
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
+; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(8)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v135, 0xffff0000, v39
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v37
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(9)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v38
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
+; GFX11TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11TRUE16-NEXT: v_and_b32_e32 v144, 0xffff0000, v48
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v48
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v50
-; GFX11TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v49
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(4)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v147, 0xffff0000, v51
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v16
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v148, 0xffff0000, v55
-; GFX11TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v146, v100, v99 :: v_dual_lshlrev_b32 v25, 16, v25
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55
-; GFX11TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v48, v7, v23
-; GFX11TRUE16-NEXT: v_and_b32_e32 v135, 0xffff0000, v39
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v49, v6, v22
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v134, v84, v83 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v146, 16, 1
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v51, v4, v20 :: v_dual_fmac_f32 v148, v118, v117
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v144, v96, v87 :: v_dual_and_b32 v81, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v55, v0, v16 :: v_dual_lshlrev_b32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v145, v98, v97
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v146
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v146, 0x7fff
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v135, v86, v85 :: v_dual_and_b32 v66, 0xffff0000, v14
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v131, v70, v69 :: v_dual_lshlrev_b32 v32, 16, v32
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v55, v0, v16 :: v_dual_and_b32 v64, 0xffff0000, v15
+; GFX11TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v131
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v147, v102, v101 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v38
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v38
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v28
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v37, v10, v26 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v39, v8, v24
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v133, v82, v81 :: v_dual_and_b32 v70, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v51, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v23, v37, 16, 1
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v135, v86, v85 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v35
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v36
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v133
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v37
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v51
-; GFX11TRUE16-NEXT: v_add3_u32 v23, v23, v37, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v51, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v34
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v35, v12, v28 :: v_dual_lshlrev_b32 v34, 16, v34
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v36, v11, v27
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v50, v5, v21
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v132, v80, v71 :: v_dual_and_b32 v67, 0xffff0000, v29
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v130, v68, v67 :: v_dual_and_b32 v65, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v36
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v34, v13, v29 :: v_dual_fmac_f32 v31, v15, v32
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v119, v64, v128 :: v_dual_and_b32 v66, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v52
-; GFX11TRUE16-NEXT: v_and_b32_e32 v128, 0xffff0000, v53
+; GFX11TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v31, v15, v32 :: v_dual_and_b32 v68, 0xffff0000, v13
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v119, v64, v128 :: v_dual_and_b32 v128, 0xffff0000, v53
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v147, 0xffff0000, v51
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v129, v66, v65 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v53, v2, v18 :: v_dual_and_b32 v116, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v54
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v64, v112, v103
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v38, v9, v25
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v131, v70, v69 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v53, v2, v18
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v128, v114, v113
; GFX11TRUE16-NEXT: v_bfe_u32 v0, v119, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v31, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v33, v14, v30 :: v_dual_fmac_f32 v52, v3, v19
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v54, v1, v17
+; GFX11TRUE16-NEXT: v_bfe_u32 v113, v53, 16, 1
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v147, v102, v101 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v54, v1, v17 :: v_dual_and_b32 v81, 0xffff0000, v26
; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v119
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v31
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v129, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v53
; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v119, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v119, v119
+; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v10
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v53, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v23
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v39
+; GFX11TRUE16-NEXT: v_and_b32_e32 v100, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v50
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v144, v96, v87
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v147, 16, 1
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v15, v0, v1 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v133, v82, v81
+; GFX11TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v49
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v50, v5, v21
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v147
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v133, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v147, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v112, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v33
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v39, v8, v24
+; GFX11TRUE16-NEXT: v_add3_u32 v21, v21, v133, 0x7fff
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v49, v6, v22
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v133
+; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v30
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v52
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v130, v68, v67
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v129, v66, v65 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v39, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v31, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v39
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v33, v14, v30
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v51, v4, v20 :: v_dual_fmac_f32 v52, v3, v19
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v31
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v132, v80, v71
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v129, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v31, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e64 s0, v31, v31
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v145, v98, v97 :: v_dual_lshlrev_b32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v64, v112, v103
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v129
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v33, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v14, v132, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v97, v51, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v128, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v149, v2, v3, s0
; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v129, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v35
+; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v48, v7, v23
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v33
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v130, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v51
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v128
; GFX11TRUE16-NEXT: v_add3_u32 v3, v6, v33, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v132, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v51, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v128, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v130
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v34, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v13, v35, 16, 1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11TRUE16-NEXT: v_add3_u32 v4, v8, v130, 0x7fff
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v38, v9, v25
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v130
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v33, v3, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v34
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v135
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v35, v12, v28
+; GFX11TRUE16-NEXT: v_bfe_u32 v71, v145, 16, 1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v37, v10, v26
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v49, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v145
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v49
+; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v145, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v23, v37, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v37
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_add3_u32 v23, v23, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v131, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v35
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v36, v11, v27
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v132
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v34, v13, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v35, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v131, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v36, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v36
+; GFX11TRUE16-NEXT: v_bfe_u32 v10, v34, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v34
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v134, v84, v83
+; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v36, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v27, v38, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v6, v10, v34, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v35, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v4, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v131
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v131, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v35
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v132
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v131, v131
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v36, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v21, v133, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v25, v134, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v134
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v8, v16, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v36, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v21, v21, v133, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v27, v38, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v25, v25, v134, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v10, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v132, v132
; GFX11TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v38
; GFX11TRUE16-NEXT: v_bfe_u32 v29, v135, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v131, v131
+; GFX11TRUE16-NEXT: v_add3_u32 v25, v25, v134, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v27, v27, v38, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v135
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v150, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v39, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v29, v29, v135, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v39
; GFX11TRUE16-NEXT: v_bfe_u32 v67, v144, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v8, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v144
; GFX11TRUE16-NEXT: v_bfe_u32 v69, v48, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v144, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v21, v22, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v48
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v145, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v10, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v132, v132
; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v48, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v145
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v52, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v52
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v55, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v150, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v146, v100, v99
+; GFX11TRUE16-NEXT: v_bfe_u32 v85, v50, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v50
+; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133
+; GFX11TRUE16-NEXT: v_bfe_u32 v83, v146, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v146
+; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v50, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v55
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v21, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v146, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v55, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v17.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v33.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v23, v24, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v49, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v145, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v49
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v50, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e64 v15.l, v149.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v25, v26, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v49, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v50
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v147, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v50, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v27, v28, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v135, v135
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v147
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v147, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v99, v64, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v64
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v27, v28, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v135, v135
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v64, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v19.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v29, v30, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v52, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v64, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v52
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v54, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v65, v66, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v144, v144
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v52, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v54
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v55, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v54, 0x7fff
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v32, v116, v115
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v20.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v67, v68, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v55
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v55, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v148, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v148
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v148, v118, v117
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v54, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v54
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v32, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v69, v70, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v20.h
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v148, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v19.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v21.h
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v54, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v32
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v148, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v32, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v71, v80, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v17.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v34.h
+; GFX11TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v148
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v148, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v21.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v81, v82, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v33.h
-; GFX11TRUE16-NEXT: v_mov_b16_e64 v15.l, v149.h
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v83, v84, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v85, v86, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v147, v147
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v34.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v23.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v87, v96, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v128, v114, v113
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v53, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v53
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v97, v98, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v128, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v128
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v53, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v24.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v99, v100, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v128, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v128, v128
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v32, v116, v115
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v25.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v103, v112, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v32, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v32
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v32, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v26.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v0, v1, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v25.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v115, v116, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v148, v148
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v27.h
@@ -50585,174 +50584,201 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: scratch_load_b32 v53, off, s32 offset:12
; GFX11FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:8
; GFX11FAKE16-NEXT: scratch_load_b32 v55, off, s32 offset:4
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v27
+; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v8
+; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v21
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v22
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v20
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v118, 16, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v17
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v6
; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v18
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v19
+; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v118, 16, v0
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(16)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v31
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(15)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v32
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v33
-; GFX11FAKE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v13
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v35
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v37
+; GFX11FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v15
+; GFX11FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(11)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v36
+; GFX11FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v36
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v24
+; GFX11FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(9)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v38
-; GFX11FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v37
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v48
-; GFX11FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v48
+; GFX11FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v38
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v20
+; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(8)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v39
+; GFX11FAKE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v39
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v100, 16, v5
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v50
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v49
-; GFX11FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v9
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(4)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v51
; GFX11FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v51
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v25
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v146, v100, v99 :: v_dual_and_b32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v39
-; GFX11FAKE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v39
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v48, v7, v23 :: v_dual_fmac_f32 v49, v6, v22
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v134, v84, v83 :: v_dual_and_b32 v13, 0xffff0000, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v26
+; GFX11FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v37
+; GFX11FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v37
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v31, v15, v32
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v39, v8, v24
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v146, v100, v99 :: v_dual_lshlrev_b32 v15, 16, v54
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v51, v4, v20
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v144, v96, v87 :: v_dual_lshlrev_b32 v81, 16, v26
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v145, v98, v97 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v146
-; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v10
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v147, v102, v101 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v38
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v28
+; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v96, 16, v7
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v119, v64, v128 :: v_dual_lshlrev_b32 v68, 16, v13
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v135, v86, v85 :: v_dual_lshlrev_b32 v70, 16, v12
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v37, v10, v26 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v39, v8, v24
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v133, v82, v81 :: v_dual_lshlrev_b32 v70, 16, v12
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v135, v86, v85 :: v_dual_and_b32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v35
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v37, v10, v26
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v33
+; GFX11FAKE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v33
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v34
+; GFX11FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v34
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v35
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v15, v116, v115
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v133, v82, v81
+; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v37
+; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v28
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v11
; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v36
-; GFX11FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v36
-; GFX11FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v133
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v37
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v27
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v130, 16, v34
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v35, v12, v28 :: v_dual_and_b32 v34, 0xffff0000, v34
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v22
+; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v49
+; GFX11FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v49
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v36, v11, v27
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v50, v5, v21
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v132, v80, v71 :: v_dual_lshlrev_b32 v67, 16, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v51
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v31
-; GFX11FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v15
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v34, v13, v29 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v130, v68, v67 :: v_dual_lshlrev_b32 v65, 16, v30
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v37, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v31, v15, v32 :: v_dual_lshlrev_b32 v66, 16, v14
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v119, v64, v128
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v52
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v3
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v48
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v18
+; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v36
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v29
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v30
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v53
; GFX11FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v53
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v54
-; GFX11FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v54
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
-; GFX11FAKE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v55
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v131, v70, v69
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v130, v68, v67
; GFX11FAKE16-NEXT: v_dual_fmac_f32 v129, v66, v65 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v49, v6, v22
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v145, v98, v97 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v147, v102, v101 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v35
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v9
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v52
; GFX11FAKE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v52
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v64, v112, v103
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v38, v9, v25
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v131, v70, v69 :: v_dual_and_b32 v14, 0xffff0000, v14
+; GFX11FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v54
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v33, v14, v30
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v132, v80, v71
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v53, v2, v18
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v55, v0, v16
-; GFX11FAKE16-NEXT: v_bfe_u32 v0, v119, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v31, 16, 1
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v33, v14, v30 :: v_dual_fmac_f32 v52, v3, v19
+; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v49
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v25
+; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v50
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v35, v12, v28 :: v_dual_fmac_f32 v52, v3, v19
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v134, v84, v83
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v128, v114, v113
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v32, v1, v17
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v119
; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v31
; GFX11FAKE16-NEXT: v_bfe_u32 v4, v129, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v119, 0x7fff
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v119, v119
+; GFX11FAKE16-NEXT: v_bfe_u32 v8, v130, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v12, v131, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v17, v132, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v31, 0x7fff
; GFX11FAKE16-NEXT: v_cmp_u_f32_e64 s0, v31, v31
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v128, v114, v113
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v54, v118, v117
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v129
+; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v132
+; GFX11FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v134
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v64, v112, v103
+; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v128
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v23
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v149, v2, v3, s0
+; GFX11FAKE16-NEXT: v_add3_u32 v2, v4, v129, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v4, v8, v130, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v8, v12, v131, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v12, v17, v132, 0x7fff
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v50, v5, v21
+; GFX11FAKE16-NEXT: v_bfe_u32 v21, v133, 16, 1
+; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v48
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v144, v96, v87
+; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v133
+; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v147
+; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v51
+; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; GFX11FAKE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v55
+; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v52
+; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v133, 0x7fff
+; GFX11FAKE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v48, v7, v23 :: v_dual_fmac_f32 v55, v0, v16
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v38, v9, v25
+; GFX11FAKE16-NEXT: v_bfe_u32 v0, v119, 16, 1
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v34, v13, v29
+; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v119
; GFX11FAKE16-NEXT: v_bfe_u32 v6, v33, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v10, v34, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v14, v35, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v19, v36, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v10, v34, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v23, v37, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v25, v134, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v27, v38, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v29, v135, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v65, v39, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v67, v144, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v69, v48, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v119, 0x7fff
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v119, v119
+; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v129
+; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v144
+; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v48
; GFX11FAKE16-NEXT: v_bfe_u32 v81, v49, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v85, v50, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v97, v51, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v101, v52, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v113, v53, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v32, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v148, v0, v1, vcc_lo
-; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v149, v2, v3, s0
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v4, v129, 0x7fff
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v15, v116, v115
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v130, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v3, v6, v33, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v6, v10, v34, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v10, v14, v35, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v14, v19, v36, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v19, v23, v37, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v21, v25, v134, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v23, v27, v38, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v25, v29, v135, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v27, v65, v39, 0x7fff
+; GFX11FAKE16-NEXT: v_add3_u32 v29, v67, v144, 0x7fff
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v54, v118, v117
+; GFX11FAKE16-NEXT: v_bfe_u32 v117, v32, 16, 1
; GFX11FAKE16-NEXT: v_add3_u32 v65, v69, v48, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v148, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
+; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v33
; GFX11FAKE16-NEXT: v_add3_u32 v69, v81, v49, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v81, v85, v50, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v85, v97, v51, 0x7fff
@@ -50762,12 +50788,6 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v117, v2, v5, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v130
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v131, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v17, v132, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v133, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v25, v134, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v29, v135, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v144, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v71, v145, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v83, v146, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v87, v147, 16, 1
@@ -50775,16 +50795,9 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_bfe_u32 v103, v128, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v115, v15, 16, 1
; GFX11FAKE16-NEXT: v_bfe_u32 v119, v54, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v8, v130, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v33, v3, v7, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v34
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v12, v131, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v12, v17, v132, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v133, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v21, v25, v134, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v25, v29, v135, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v29, v67, v144, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v67, v71, v145, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v71, v83, v146, 0x7fff
; GFX11FAKE16-NEXT: v_add3_u32 v83, v87, v147, 0x7fff
@@ -50795,50 +50808,41 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v119, v4, v9, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v131
+; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v146
; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v35
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v132
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v36
+; GFX11FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v38
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v34, v6, v11, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v131, v131
-; GFX11FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v134
-; GFX11FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v38
; GFX11FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v135
; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v39
+; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v145
+; GFX11FAKE16-NEXT: v_bfe_u32 v0, v55, 16, 1
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v8, v13, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v144
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v48
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v145
-; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v49
+; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v55
+; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v15
+; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v55, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v32
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v10, v16, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v132, v132
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v50
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v147
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v64
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v52
+; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v53
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v18, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v128
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v15
-; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v32
-; GFX11FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v54
+; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v50
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v20, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133
-; GFX11FAKE16-NEXT: v_bfe_u32 v0, v55, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v55
-; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v53
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v11, v12, v11, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v17, v22, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v55, 0x7fff
; GFX11FAKE16-NEXT: v_perm_b32 v12, v16, v13, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v34, v119, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v19, v24, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v10, v14, v10, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v21, v26, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v64
; GFX11FAKE16-NEXT: v_perm_b32 v14, v33, v117, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v28, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v135, v135
@@ -50851,6 +50855,7 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_perm_b32 v8, v18, v8, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v29, v68, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v54
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v65, v70, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
@@ -50862,10 +50867,9 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_perm_b32 v6, v20, v6, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v71, v84, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11FAKE16-NEXT: v_perm_b32 v13, v34, v119, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v81, v86, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v147, v147
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v21, v5, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v83, v96, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v87, v100, vcc_lo
@@ -50885,14 +50889,14 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
; GFX11FAKE16-NEXT: v_perm_b32 v1, v23, v15, 0x7060302
+; GFX11FAKE16-NEXT: v_perm_b32 v5, v21, v5, 0x7060302
; GFX11FAKE16-NEXT: v_perm_b32 v15, v149, v148, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v24, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v101, v114, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v2, v25, v2, 0x7060302
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v85, v98, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v4, v26, v4, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -51466,14 +51470,15 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX11TRUE16-LABEL: v_fmuladd_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v6, v8, v7
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v0, v2
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
@@ -51481,7 +51486,7 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
@@ -51505,31 +51510,30 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX11FAKE16-LABEL: v_fmuladd_v3bf16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v4, v0, v2 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v6, v8, v7
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11FAKE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v1, v6, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11FAKE16-NEXT: v_bfe_u32 v0, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -51785,31 +51789,31 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_lshlrev_b32 v8, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add3_u32 v4, v9, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v0, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v7, v10, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v0, v7, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
@@ -51831,47 +51835,47 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_lshlrev_b32 v8, 16, v2
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v7, v9, v8
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v3, v7, 16, 1
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v0, v2
; GFX11FAKE16-NEXT: v_add3_u32 v0, v10, v6, 0x7fff
; GFX11FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v7, v9, v8
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_add3_u32 v0, v2, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v7, 16, 1
+; GFX11FAKE16-NEXT: v_add3_u32 v2, v3, v7, 0x7fff
+; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v7
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11FAKE16-NEXT: v_add3_u32 v6, v8, v4, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v3, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v9, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v3, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index 73a078eb41f3cb..fea0ec953e345d 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -9503,20 +9503,20 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_add_f32 v5, v5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10099,21 +10099,21 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX11-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX11-FAKE16-NEXT: ; Child Loop BB28_6 Depth 2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
; GFX11-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v5, v5, v8
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v8 :: v_dual_add_f32 v6, v6, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
@@ -11319,20 +11319,20 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset(ptr addrspace
; GFX11-FAKE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_add_f32 v5, v5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -12255,20 +12255,20 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_re
; GFX11-FAKE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_add_f32 v5, v5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -12716,20 +12716,20 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-FAKE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_add_f32 v5, v5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index fe0cc95dc0a51b..6859d7fbbb95d9 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -8094,20 +8094,20 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-FAKE16-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-FAKE16-NEXT: v_dual_max_f32 v5, v5, v3 :: v_dual_max_f32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_max_f32 v5, v5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -8870,21 +8870,21 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX11-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX11-FAKE16-NEXT: ; Child Loop BB21_6 Depth 2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
; GFX11-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX11-FAKE16-NEXT: v_dual_max_f32 v6, v6, v9 :: v_dual_max_f32 v5, v5, v8
+; GFX11-FAKE16-NEXT: v_dual_max_f32 v5, v5, v8 :: v_dual_max_f32 v6, v6, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index 6ba9f61ba7faf5..bd86786c1df676 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -8094,20 +8094,20 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-FAKE16-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-FAKE16-NEXT: v_dual_min_f32 v5, v5, v3 :: v_dual_min_f32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v5, v5, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -8870,21 +8870,21 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX11-FAKE16-NEXT: ; =>This Loop Header: Depth=1
; GFX11-FAKE16-NEXT: ; Child Loop BB21_6 Depth 2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
; GFX11-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX11-FAKE16-NEXT: v_dual_min_f32 v6, v6, v9 :: v_dual_min_f32 v5, v5, v8
+; GFX11-FAKE16-NEXT: v_dual_min_f32 v5, v5, v8 :: v_dual_min_f32 v6, v6, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
index 2ce5ae6a93bb9d..374234a43b1a50 100644
--- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
@@ -2069,7 +2069,8 @@ define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
; GCN-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
-; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GCN-NEXT: v_min_f32_e32 v0, v0, v1
+; GCN-NEXT: v_max_f32_e32 v1, v2, v3
; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v4
; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
@@ -2091,7 +2092,8 @@ define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GCN-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
+; GCN-NEXT: v_max_f32_e32 v0, v0, v1
+; GCN-NEXT: v_min_f32_e32 v1, v2, v3
; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v8
; GCN-NEXT: s_and_b32 s0, vcc_lo, s0
@@ -2144,8 +2146,8 @@ define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_min3_f32 v0, v0, v1, v2
-; GCN-NEXT: v_dual_max_f32 v1, v3, v3 :: v_dual_max_f32 v2, v5, v5
-; GCN-NEXT: v_max_f32_e32 v3, v6, v6
+; GCN-NEXT: v_max_f32_e32 v1, v3, v3
+; GCN-NEXT: v_dual_max_f32 v2, v5, v5 :: v_dual_max_f32 v3, v6, v6
; GCN-NEXT: v_cmp_nge_f32_e32 vcc_lo, v4, v8
; GCN-NEXT: v_min3_f32 v0, v0, v1, v2
; GCN-NEXT: v_min_f32_e32 v0, v0, v3
@@ -2215,7 +2217,8 @@ define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1
; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v3
-; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GCN-NEXT: v_min_f32_e32 v0, v0, v1
+; GCN-NEXT: v_max_f32_e32 v1, v2, v3
; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
; GCN-NEXT: v_cmp_nge_f32_e64 s0, v1, v4
; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
@@ -2243,8 +2246,10 @@ define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
; GCN-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v7, v7, v7
; GCN-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v9, v9, v9
; GCN-NEXT: v_min3_f32 v0, v0, v1, v8
-; GCN-NEXT: v_dual_max_f32 v1, v2, v3 :: v_dual_min_f32 v2, v4, v5
-; GCN-NEXT: v_dual_max_f32 v3, v6, v7 :: v_dual_min_f32 v0, v0, v9
+; GCN-NEXT: v_max_f32_e32 v1, v2, v3
+; GCN-NEXT: v_min_f32_e32 v2, v4, v5
+; GCN-NEXT: v_max_f32_e32 v3, v6, v7
+; GCN-NEXT: v_min_f32_e32 v0, v0, v9
; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v10
; GCN-NEXT: v_cmp_lt_f32_e64 s0, v2, v10
; GCN-NEXT: v_cmp_gt_f32_e64 s1, v3, v10
@@ -2282,11 +2287,13 @@ define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
; GCN-NEXT: v_max_f32_e32 v2, v2, v2
-; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v3, v3
+; GCN-NEXT: v_min_f32_e32 v0, v0, v1
+; GCN-NEXT: v_max_f32_e32 v1, v3, v3
; GCN-NEXT: v_min3_f32 v3, v4, v5, v6
; GCN-NEXT: v_max_f32_e32 v4, v7, v7
; GCN-NEXT: v_min3_f32 v5, v8, v9, v10
-; GCN-NEXT: v_dual_max_f32 v6, v11, v11 :: v_dual_min_f32 v1, v2, v1
+; GCN-NEXT: v_max_f32_e32 v6, v11, v11
+; GCN-NEXT: v_min_f32_e32 v1, v2, v1
; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12
; GCN-NEXT: v_min_f32_e32 v2, v3, v4
; GCN-NEXT: v_min_f32_e32 v0, v5, v6
diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
index 550cfec413d79a..87fff9b9b0e018 100644
--- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
@@ -759,7 +759,8 @@ define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
; GCN-LABEL: test109:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GCN-NEXT: v_min_f32_e32 v0, v0, v1
+; GCN-NEXT: v_max_f32_e32 v1, v2, v3
; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v4
; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
@@ -781,7 +782,8 @@ define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GCN-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
+; GCN-NEXT: v_max_f32_e32 v0, v0, v1
+; GCN-NEXT: v_min_f32_e32 v1, v2, v3
; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v8
; GCN-NEXT: s_and_b32 s0, vcc_lo, s0
@@ -917,8 +919,10 @@ define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_min3_f32 v0, v0, v1, v8
-; GCN-NEXT: v_dual_max_f32 v1, v2, v3 :: v_dual_min_f32 v2, v4, v5
-; GCN-NEXT: v_dual_max_f32 v3, v6, v7 :: v_dual_min_f32 v0, v0, v9
+; GCN-NEXT: v_max_f32_e32 v1, v2, v3
+; GCN-NEXT: v_min_f32_e32 v2, v4, v5
+; GCN-NEXT: v_max_f32_e32 v3, v6, v7
+; GCN-NEXT: v_min_f32_e32 v0, v0, v9
; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v10
; GCN-NEXT: v_cmp_lt_f32_e64 s0, v2, v10
; GCN-NEXT: v_cmp_gt_f32_e64 s1, v3, v10
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
index 433e19f1128efa..8482eb35361544 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
@@ -96,46 +96,47 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
; GFX11-NEXT: s_buffer_load_b32 s0, s[0:3], 0x2c
; GFX11-NEXT: v_sub_f32_e64 v5, s24, s28
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: s_clause 0x4
; GFX11-NEXT: s_buffer_load_b128 s[8:11], s[0:3], 0x60
; GFX11-NEXT: s_buffer_load_b128 s[12:15], s[0:3], 0x20
; GFX11-NEXT: s_buffer_load_b128 s[16:19], s[0:3], 0x0
; GFX11-NEXT: s_buffer_load_b128 s[20:23], s[0:3], 0x70
-; GFX11-NEXT: v_fma_f32 v1, v1, v5, s28
; GFX11-NEXT: s_buffer_load_b128 s[24:27], s[0:3], 0x10
+; GFX11-NEXT: v_fma_f32 v1, v1, v5, s28
; GFX11-NEXT: v_max_f32_e64 v6, s0, s0 clamp
; GFX11-NEXT: v_add_f32_e64 v5, s29, -1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_sub_f32_e32 v8, s0, v1
; GFX11-NEXT: s_mov_b32 s0, 0x3c23d70a
-; GFX11-NEXT: v_fma_f32 v7, -s2, v6, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f32 v5, v6, v5, 1.0
+; GFX11-NEXT: v_fma_f32 v7, -s2, v6, s6
; GFX11-NEXT: v_fma_f32 v10, s2, v6, v2
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_fmac_f32 v10, v7, v6 :: v_dual_mul_f32 v9, s10, v0
+; GFX11-NEXT: v_mul_f32_e32 v9, s10, v0
; GFX11-NEXT: v_fma_f32 v0, -v0, s10, s14
-; GFX11-NEXT: v_dual_fmac_f32 v1, v6, v8 :: v_dual_mul_f32 v8, s18, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, s22, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_fmac_f32_e32 v1, v6, v8
+; GFX11-NEXT: v_dual_mul_f32 v8, s18, v2 :: v_dual_mul_f32 v3, s22, v3
+; GFX11-NEXT: v_fmac_f32_e32 v10, v7, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_fmac_f32 v9, v0, v6 :: v_dual_sub_f32 v0, v1, v5
+; GFX11-NEXT: v_mul_f32_e32 v1, v8, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mul_f32_e32 v7, v6, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_fma_f32 v3, -v6, v3, v9
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_add_f32_e32 v4, v4, v10
-; GFX11-NEXT: v_fmac_f32_e32 v7, v3, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_fmac_f32_e32 v5, v0, v6
-; GFX11-NEXT: v_mul_f32_e32 v1, v8, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mul_f32 v3, v4, v6 :: v_dual_fmaak_f32 v4, s0, v5, 0x3ca3d70a
; GFX11-NEXT: v_fma_f32 v0, v2, s26, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_fmac_f32_e32 v7, v3, v6
; GFX11-NEXT: v_fmac_f32_e32 v1, v0, v6
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v6
-; GFX11-NEXT: v_mul_f32_e32 v2, v7, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v4, v4, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mul_f32 v3, v4, v6 :: v_dual_fmaak_f32 v4, s0, v5, 0x3ca3d70a
; GFX11-NEXT: v_mul_f32_e32 v1, v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v2, v7, v4
; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_max_f32_e32 v0, 0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index 87ed1342096574..b2b1cb716ba6d0 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -3276,18 +3276,17 @@ define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, 0x3f80
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v4
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, 0x4000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, 0x4000, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
+; GFX11-SDAG-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, v3, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -3341,20 +3340,20 @@ define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, v5, 0x4000, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, v5, 0x4000, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v1 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, v3, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v1 :: v_dual_mul_f32 v1, v3, v2
; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
@@ -3575,18 +3574,17 @@ define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, 0x3f80
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v4
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, 0x3f00, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, 0x3f00, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
+; GFX11-SDAG-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, v3, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -3640,20 +3638,20 @@ define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, v5, 0x3f00, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, v5, 0x3f00, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v1 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, v3, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v1 :: v_dual_mul_f32 v1, v3, v2
; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
diff --git a/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll b/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
index dc155cdae40362..a03eb7fba28b82 100644
--- a/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
+++ b/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
@@ -27,11 +27,11 @@ define amdgpu_ps void @_amdgpu_ps_main(i32 inreg %PrimMask, <2 x float> %InterpC
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GCN-NEXT: v_interp_p2_f32 v2, v4, v2, v3 wait_exp:7
; GCN-NEXT: v_mov_b32_dpp v5, v5 dpp8:[1,0,3,2,5,4,7,6]
-; GCN-NEXT: v_and_b32_e32 v8, 1, v8
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GCN-NEXT: v_mov_b32_dpp v7, v7 dpp8:[1,0,3,2,5,4,7,6]
+; GCN-NEXT: v_and_b32_e32 v8, 1, v8
; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GCN-NEXT: v_dual_cndmask_b32 v3, v5, v6 :: v_dual_cndmask_b32 v4, v6, v5
; GCN-NEXT: v_dual_cndmask_b32 v5, v2, v7 :: v_dual_cndmask_b32 v2, v7, v2
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
index 043a3361944f49..85d1e02216ea18 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
@@ -618,28 +618,29 @@ define amdgpu_kernel void @v_fabs_fold_self_v2bf16(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v2, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v2.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_dual_mul_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v3, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: global_store_b32 v2, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -657,27 +658,28 @@ define amdgpu_kernel void @v_fabs_fold_self_v2bf16(ptr addrspace(1) %out, ptr ad
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_dual_mul_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0x7fff, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX11-FAKE16-NEXT: global_store_b32 v2, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 07d6db5bb3d271..5ef571082d6274 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -5532,31 +5532,29 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[8:9], v14
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[10:11], v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[12:13], v16
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 1, v14
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[0:1]|, |v[8:9]|
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[4:5], v[10:11]
; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s1, v[2:3], v[12:13]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v8, -1, 1, s3
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[4:5]|, |v[10:11]|
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v9, -1, 1, s3
; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[2:3]|, |v[12:13]|
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s3
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, v16, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 1, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v19
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, v16, v10
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s3
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_and_b32 v17, 1, v15
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s0, s2
; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_and_b32 v18, 1, v16
@@ -5596,58 +5594,59 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[8:9], v14
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[10:11], v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cvt_f64_f32_e32 v[12:13], v16
+; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 1, v14
; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 1, v15
+; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 1, v16
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v17
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v19
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s3, |v[4:5]|, |v[8:9]|
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[4:5], v[8:9]
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s0, v[0:1], v[10:11]
; GFX11FAKE16-NEXT: v_cmp_nlg_f64_e64 s1, v[2:3], v[12:13]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v8, -1, 1, s3
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s3, |v[0:1]|, |v[10:11]|
+; GFX11FAKE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s2
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v9, -1, 1, s3
; GFX11FAKE16-NEXT: v_cmp_gt_f64_e64 s3, |v[2:3]|, |v[12:13]|
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
+; GFX11FAKE16-NEXT: v_add3_u32 v8, v12, v8, 0x7fff
; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s3
; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v10, v16, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 1, v14
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v17
-; GFX11FAKE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s2
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_and_b32 v19, 1, v16
; GFX11FAKE16-NEXT: s_or_b32 vcc_lo, s0, s3
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1
; GFX11FAKE16-NEXT: s_or_b32 vcc_lo, s1, s4
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v12, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v9
; GFX11FAKE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v9, 0x7fff
; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v10, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v15, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc_lo
; GFX11FAKE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[4:5]
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v6
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v14, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v2, 16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v7
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
%mag.trunc = fptrunc <3 x double> %mag to <3 x bfloat>
@@ -6409,22 +6408,23 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f32_sign_v4bf16(<4 x float> %ma
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v10, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v11, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v12, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v11, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
@@ -7066,22 +7066,23 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4bf16_sign_v4f32(<4 x bfloat> %m
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v2, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v2, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v10, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v11, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v9, v12, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v11, v3, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 8b386d61472407..80be6e5ef40ea8 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -1009,8 +1009,9 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v5, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 7, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
@@ -1019,16 +1020,14 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 2, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, 0x7c00, v5 :: v_dual_add_nc_u32 v3, v3, v4
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3197,11 +3196,10 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v5, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v7
@@ -3217,46 +3215,48 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, v8, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v5, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v6, 12, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v11, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0xfffffc10, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v7, 12, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v12, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v6, 12, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v7, 12, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 7, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 7, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 2, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v11
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0x7e00
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, 0x7e00 :: v_dual_add_nc_u32 v8, v8, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, 0x7c00, v8 :: v_dual_add_nc_u32 v5, v5, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, 0x7c00, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v7
@@ -3283,14 +3283,13 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 20, 11
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v3
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, 0x7e00
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, 0x7e00
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v5, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v7
@@ -3306,27 +3305,28 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, v8, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v5, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v6, 12, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0xfffffc10, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v7, 12, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v12, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v6, 12, v0
+; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v7, 12, v2
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 7, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 7, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 2, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
@@ -3340,15 +3340,15 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v13, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, 0x7c00, v13 :: v_dual_add_nc_u32 v5, v5, v10
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v6
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, 0x7c00, v8 :: v_dual_add_nc_u32 v5, v5, v10
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, 0x7c00, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
@@ -4895,9 +4895,9 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0xffe, v8, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v8, 0x3f1, v10
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v11, v11, 0, 13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v10
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v9, v2
; GFX11-TRUE16-NEXT: v_med3_i32 v8, v8, 0, 13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x1000, v4
@@ -4920,63 +4920,65 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, v13, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v10, 12, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, v13, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0xfffffc10, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v5, 12, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v10, 12, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v10
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v13, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v5, 12, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0xfffffc10, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 7, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v15, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 12, v0
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v15, v9 :: v_dual_and_b32 v14, 7, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 2, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v14
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v14
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v12, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, 0x7e00 :: v_dual_and_b32 v15, 7, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 7, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 2, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v14
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, 0x7c00, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, 0x7c00, v12 :: v_dual_add_nc_u32 v11, v11, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v8, v2 :: v_dual_add_nc_u32 v11, v11, v15
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x8000, v3, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, 0x7c00, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v12, vcc_lo
@@ -5062,23 +5064,24 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 12, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 7, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 7, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 2, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 7, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v14
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, 0x7e00 :: v_dual_add_nc_u32 v9, v9, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 7, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 7, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 2, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 2, v11
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
@@ -6144,7 +6147,8 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v18, 0x3f1, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0xfffffc10, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 7, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -6181,38 +6185,37 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 2, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, v17, v21
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, v17, v23
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v18, v16
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, 0x7e00 :: v_dual_lshlrev_b32 v17, v17, v23
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v18, 0x7e00
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v15, v22
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v17, v21
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v20, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v23, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0xfffffc10, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v12, 12, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v23, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v20, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v19, 12, v0
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 0x7c00, v18 :: v_dual_and_b32 v15, 7, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, 0x7c00, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 7, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 7, v17
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, 0x7c00, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
@@ -6308,7 +6311,8 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v18, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v18, 0x3f1, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0xfffffc10, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 7, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
@@ -6345,47 +6349,46 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 2, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, v17, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, v17, v23
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v18, v16
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, 0x7e00 :: v_dual_lshlrev_b32 v17, v17, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v18, 0x7e00
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v22
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v17, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v20, v16
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v23, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0xfffffc10, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v12, 12, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v20, v16, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v19, 12, v2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, 0x7c00, v18 :: v_dual_and_b32 v15, 7, v16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7c00, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v20, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 7, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 7, v17
; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0x8000, v5, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, 0x7c00, v13, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v15
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v11
@@ -6401,11 +6404,11 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v12
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, 0x7c00, v13 :: v_dual_add_nc_u32 v10, v16, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v16, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, 0x7c00, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v19
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, 0x7c00, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v18, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.ll b/llvm/test/CodeGen/AMDGPU/fdiv.ll
index fa22a37b87191f..c5a03901b382dd 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.ll
@@ -1313,7 +1313,8 @@ define amdgpu_kernel void @s_fdiv_v2f32_fast_math(ptr addrspace(1) %out, <2 x fl
; GFX11-NEXT: v_rcp_f32_e32 v2, s2
; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_mul_f32 v1, s1, v0 :: v_dual_mul_f32 v0, s0, v2
+; GFX11-NEXT: v_mul_f32_e32 v1, s1, v0
+; GFX11-NEXT: v_mul_f32_e32 v0, s0, v2
; GFX11-NEXT: global_store_b64 v3, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
;
@@ -1389,7 +1390,8 @@ define amdgpu_kernel void @s_fdiv_v2f32_arcp_math(ptr addrspace(1) %out, <2 x fl
; GFX11-NEXT: v_rcp_f32_e32 v2, s2
; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_mul_f32 v1, s1, v0 :: v_dual_mul_f32 v0, s0, v2
+; GFX11-NEXT: v_mul_f32_e32 v1, s1, v0
+; GFX11-NEXT: v_mul_f32_e32 v0, s0, v2
; GFX11-NEXT: global_store_b64 v3, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
index c228100ab7c0cd..4bd8a83b082ffe 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
@@ -17637,21 +17637,21 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -17688,19 +17688,19 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -17964,21 +17964,21 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -18015,19 +18015,19 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -18643,22 +18643,21 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -18958,22 +18957,21 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
@@ -19286,22 +19284,21 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -19621,21 +19618,21 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -19672,19 +19669,19 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -19958,22 +19955,21 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
@@ -20282,21 +20278,21 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory(
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -20333,19 +20329,19 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory(
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -20610,22 +20606,21 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -20924,21 +20919,21 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -20975,19 +20970,19 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -21252,22 +21247,21 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 84703f1b3c9500..e3fe4b41715174 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -15188,21 +15188,21 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15239,19 +15239,19 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15638,21 +15638,21 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15689,19 +15689,19 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -16560,22 +16560,21 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -16993,22 +16992,21 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
@@ -17442,22 +17440,21 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -17901,21 +17898,21 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -17952,19 +17949,19 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -18357,22 +18354,21 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index 9d8629b0b1d286..1cd0fbe3ebd56d 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -15188,21 +15188,21 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15239,19 +15239,19 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15638,21 +15638,21 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15689,19 +15689,19 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -16560,22 +16560,21 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -16993,22 +16992,21 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
@@ -17442,22 +17440,21 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -17901,21 +17898,21 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -17952,19 +17949,19 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -18357,22 +18354,21 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
index cc5204d00efdda..f8d2bb98155f03 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
@@ -14729,21 +14729,21 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -14780,19 +14780,19 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15179,21 +15179,21 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15230,19 +15230,19 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -16101,22 +16101,21 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -16534,22 +16533,21 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
@@ -16983,22 +16981,21 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
@@ -17442,21 +17439,21 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -17493,19 +17490,19 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -17898,22 +17895,21 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
index 64cb3ada42bdf6..4a4c4fca1a2cb0 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
@@ -1960,26 +1960,25 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v2
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
@@ -2555,29 +2554,30 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6
+; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
@@ -2587,38 +2587,38 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_lshlrev_b32 v1, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v1, v3, v4 :: v_dual_and_b32 v6, 0xffff0000, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v5, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v6, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3242,8 +3242,9 @@ define float @v_min3_f32_maximumnum_fabs_maximumnum__v_v_v_0(float %a, float %b,
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f32_e32 v1, v1, v1
; GFX11-NEXT: v_max_f32_e64 v0, -v0, -v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_max_f32_e32 v1, v2, v2
; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
@@ -3328,8 +3329,9 @@ define float @v_min3_f32_maximumnum_fneg_fabs_maximumnum__v_v_v_0(float %a, floa
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f32_e32 v1, v1, v1
; GFX11-NEXT: v_max_f32_e64 v0, -v0, -v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_max_f32_e32 v1, v2, v2
; GFX11-NEXT: v_or_b32_e32 v0, 0x80000000, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
index 7bb19d3984b892..716bcf3547918c 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
@@ -678,16 +678,15 @@ define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v2, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ugt <8 x half> %a, %b
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll b/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
index 5492ea5111fe99..78dcf7141c8fd4 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
@@ -170,23 +170,23 @@ define <2 x bfloat> @v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum(<2 x bfloat
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v3
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v0, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v2
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v0, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4080, v1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4080, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.ll b/llvm/test/CodeGen/AMDGPU/fmed3.ll
index d0097102f0a7c0..5f23d87bfbe16b 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.ll
@@ -5692,9 +5692,10 @@ define amdgpu_kernel void @v_test_safe_med3_f32_pat0_multi_use0(ptr addrspace(1)
; GFX11-NEXT: global_load_b32 v3, v0, s[6:7] glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v2, v2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_min_f32_e32 v4, v1, v2
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v2 :: v_dual_max_f32 v2, v3, v3
+; GFX11-NEXT: v_max_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_max_f32_e32 v2, v3, v3
; GFX11-NEXT: v_minmax_f32 v1, v1, v2, v4
; GFX11-NEXT: global_store_b32 v[0:1], v4, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -5894,8 +5895,9 @@ define amdgpu_kernel void @v_test_safe_med3_f32_pat0_multi_use1(ptr addrspace(1)
; GFX11-SDAG-NEXT: global_load_b32 v3, v0, s[6:7] glc dlc
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v2, v2, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v1, v2
+; GFX11-SDAG-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_max_f32_e32 v4, v1, v2
; GFX11-SDAG-NEXT: v_min_f32_e32 v3, v4, v3
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_minmax_f32 v1, v1, v2, v3
@@ -5918,9 +5920,10 @@ define amdgpu_kernel void @v_test_safe_med3_f32_pat0_multi_use1(ptr addrspace(1)
; GFX11-GISEL-NEXT: global_load_b32 v3, v0, s[6:7] glc dlc
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v2, v2, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_f32_e32 v4, v1, v2
-; GFX11-GISEL-NEXT: v_dual_max_f32 v1, v1, v2 :: v_dual_max_f32 v2, v3, v3
+; GFX11-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
; GFX11-GISEL-NEXT: v_minmax_f32 v2, v1, v2, v4
; GFX11-GISEL-NEXT: global_store_b32 v[0:1], v1, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -6330,9 +6333,10 @@ define amdgpu_kernel void @v_test_safe_med3_f32_pat0(ptr addrspace(1) %out, ptr
; GFX11-GISEL-NEXT: global_load_b32 v3, v0, s[6:7] glc dlc
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v2, v2, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_f32_e32 v4, v1, v2
-; GFX11-GISEL-NEXT: v_dual_max_f32 v1, v1, v2 :: v_dual_max_f32 v2, v3, v3
+; GFX11-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
; GFX11-GISEL-NEXT: v_minmax_f32 v1, v1, v2, v4
; GFX11-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
index bd67a01da9c7b3..d0eb2ea97bdb5e 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
@@ -1962,26 +1962,25 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v2
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
@@ -2560,29 +2559,30 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v6
+; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v3 :: v_dual_lshlrev_b32 v7, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
@@ -2592,38 +2592,38 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_lshlrev_b32 v1, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v1, v3, v4 :: v_dual_and_b32 v6, 0xffff0000, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v5, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5
; GFX11-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v6, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3247,8 +3247,9 @@ define float @v_min3_f32_minimumnum_fabs_minimumnum__v_v_v_0(float %a, float %b,
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f32_e32 v1, v1, v1
; GFX11-NEXT: v_max_f32_e64 v0, -v0, -v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_max_f32_e32 v1, v2, v2
; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
@@ -3333,8 +3334,9 @@ define float @v_min3_f32_minimumnum_fneg_fabs_minimumnum__v_v_v_0(float %a, floa
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f32_e32 v1, v1, v1
; GFX11-NEXT: v_max_f32_e64 v0, -v0, -v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_max_f32_e32 v1, v2, v2
; GFX11-NEXT: v_or_b32_e32 v0, 0x80000000, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
index 00fc14cdb6ddbe..8c0735175aa1bd 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
@@ -679,16 +679,15 @@ define <8 x half> @test_fmin_legacy_ule_v8f16(<8 x half> %a, <8 x half> %b) #0 {
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v2, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <8 x half> %a, %b
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
index 87c0367e79ce21..861a50a110c598 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
@@ -645,14 +645,14 @@ define half @select_fneg_select_f16(i1 %cond0, i1 %cond1, half %arg0, half %arg1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg0 = fneg half %arg0
@@ -697,14 +697,14 @@ define i16 @select_fneg_xor_select_i16(i1 %cond0, i1 %cond1, i16 %arg0, i16 %arg
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0xffff8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fneg0 = xor i16 %arg0, -32768
@@ -786,25 +786,25 @@ define <2 x half> @select_fneg_select_v2f16(<2 x i1> %cond0, <2 x i1> %cond1, <2
; GFX11-FAKE16-LABEL: select_fneg_select_v2f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -893,25 +893,25 @@ define <2 x i16> @select_fneg_xor_select_v2i16(<2 x i1> %cond0, <2 x i1> %cond1,
; GFX11-FAKE16-LABEL: select_fneg_xor_select_v2i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
index 07d243c393d31c..fd902f59ec80bc 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
@@ -766,28 +766,30 @@ define amdgpu_kernel void @v_fneg_fold_v2bf16(ptr addrspace(1) %out, ptr addrspa
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mul_f32 v3, v3, v4 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v1, v2, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
index 2fb9e0b764391d..1c198e33697f1a 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
@@ -625,8 +625,9 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(ptr addrspace(1) %out, <4 x
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-NEXT: v_fmac_f32_e32 v0, 0xcf800000, v6
; GFX11-SDAG-NEXT: v_fmac_f32_e32 v8, 0xcf800000, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT: v_dual_fmac_f32 v4, 0xcf800000, v7 :: v_dual_fmac_f32 v9, 0xcf800000, v5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-NEXT: v_fmac_f32_e32 v4, 0xcf800000, v7
+; GFX11-SDAG-NEXT: v_fmac_f32_e32 v9, 0xcf800000, v5
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v6
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v5, v5
diff --git a/llvm/test/CodeGen/AMDGPU/fpow.ll b/llvm/test/CodeGen/AMDGPU/fpow.ll
index 780feeaa80725a..59976252bdc743 100644
--- a/llvm/test/CodeGen/AMDGPU/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpow.ll
@@ -207,8 +207,9 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v5, v3
@@ -537,22 +538,23 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v1|
; GFX11-NEXT: v_cmp_class_f32_e64 s6, v1, 24
-; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v3
; GFX11-NEXT: v_trunc_f32_e32 v9, v3
+; GFX11-NEXT: v_cmp_class_f32_e64 s5, v0, 24
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 32, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 32, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s0
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1
-; GFX11-NEXT: v_cmp_class_f32_e64 s5, v0, 24
+; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v9, v3
; GFX11-NEXT: v_ldexp_f32 v5, |v0|, v5
; GFX11-NEXT: v_ldexp_f32 v7, |v1|, v7
-; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v9, v3
; GFX11-NEXT: v_cmp_neq_f32_e64 s4, v9, v3
+; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_log_f32_e32 v5, v5
; GFX11-NEXT: v_log_f32_e32 v7, v7
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_sub_f32 v5, v7, v6
+; GFX11-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX11-NEXT: v_sub_f32_e32 v5, v7, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v4, v2, v4 :: v_dual_mul_dx9_zero_f32 v5, v3, v5
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4
@@ -1330,10 +1332,11 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v8
; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -1346,44 +1349,49 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v11, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v11, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v9
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v1
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s1, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, v6, v10
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v8
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
@@ -1862,59 +1870,61 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v7, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v9
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v9, v1
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v7, v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, s1, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v10
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, v6, v11
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v10, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v8
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v10, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v10, v8
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
@@ -2370,10 +2380,11 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v3|
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, -v8
; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v3, 24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -2386,44 +2397,49 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v11, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v11, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v6, v7, v6 :: v_dual_sub_f32 v5, v5, v9
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v9
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, -v1
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s1, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_add_f32 v6, v6, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, v6, v10
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v11
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v8
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v10, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v11, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v11, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
@@ -2904,59 +2920,61 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 32, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 32, s1
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, |v3|, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42000000, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0.5
-; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s6, v4, 24
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, |v4|, v5
; GFX11-FAKE16-NEXT: v_log_f32_e32 v7, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v5, v5
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v9
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, -v1
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, s1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, s1, neg(0) op_sel_hi:[1,0,0]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v5, v8, v5 :: v_dual_mul_dx9_zero_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v9
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, v12, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v6
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s3, v12, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 0x42800000, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v10
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v7
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, v6, v11
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v10, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_exp_f32_e32 v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0
; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v8
; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v10, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: v_cmp_neq_f32_e64 s4, v10, v8
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s6, s4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
@@ -3687,8 +3705,9 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0.5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v1, v1
; GFX11-NEXT: v_trunc_f32_e32 v4, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
@@ -4909,8 +4928,9 @@ define float @v_pow_f32_nnan(float %x, float %y) {
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v5, v3
diff --git a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
index 4b1a0efa523f92..25461ecd21e086 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -149,90 +149,88 @@ define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; CHECK-NEXT: v_rcp_f32_e32 v11, v8
; CHECK-NEXT: v_rcp_f32_e32 v12, v9
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; CHECK-NEXT: v_trunc_f32_e32 v10, v10
-; CHECK-NEXT: v_dual_mul_f32 v18, 0x3e800000, v3 :: v_dual_mul_f32 v21, 0x3e800000, v4
-; CHECK-NEXT: v_trunc_f32_e32 v18, v18
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; CHECK-NEXT: v_trunc_f32_e32 v21, v21
-; CHECK-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; CHECK-NEXT: v_fma_f32 v15, -v8, v11, 1.0
-; CHECK-NEXT: v_fma_f32 v16, -v9, v12, 1.0
+; CHECK-NEXT: v_mul_f32_e32 v18, 0x3e800000, v3
+; CHECK-NEXT: v_sub_f32_e32 v0, v0, v14
; CHECK-NEXT: v_fmac_f32_e32 v1, -2.0, v10
; CHECK-NEXT: v_trunc_f32_e32 v10, v13
; CHECK-NEXT: v_div_scale_f32 v13, vcc_lo, v2, 0x40400000, v2
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; CHECK-NEXT: v_dual_fmac_f32 v11, v15, v11 :: v_dual_fmac_f32 v12, v16, v12
+; CHECK-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; CHECK-NEXT: v_fma_f32 v15, -v8, v11, 1.0
+; CHECK-NEXT: v_fma_f32 v16, -v9, v12, 1.0
; CHECK-NEXT: v_div_scale_f32 v17, null, 0x40400000, 0x40400000, v1
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; CHECK-NEXT: v_fmac_f32_e32 v6, -2.0, v10
; CHECK-NEXT: v_div_scale_f32 v10, s0, v5, 0x40400000, v5
-; CHECK-NEXT: v_mul_f32_e32 v19, v13, v11
-; CHECK-NEXT: v_div_scale_f32 v25, s1, v1, 0x40400000, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_dual_fmac_f32 v11, v15, v11 :: v_dual_fmac_f32 v12, v16, v12
; CHECK-NEXT: v_rcp_f32_e32 v15, v17
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; CHECK-NEXT: v_div_scale_f32 v16, null, 0x40400000, 0x40400000, v6
-; CHECK-NEXT: v_mul_f32_e32 v20, v10, v12
-; CHECK-NEXT: v_sub_f32_e32 v0, v0, v14
-; CHECK-NEXT: v_fma_f32 v14, -v8, v19, v13
-; CHECK-NEXT: v_fmac_f32_e32 v3, -4.0, v18
+; CHECK-NEXT: v_trunc_f32_e32 v18, v18
+; CHECK-NEXT: v_dual_mul_f32 v19, v13, v11 :: v_dual_mul_f32 v20, v10, v12
+; CHECK-NEXT: v_div_scale_f32 v25, s1, v1, 0x40400000, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; CHECK-NEXT: v_rcp_f32_e32 v22, v16
+; CHECK-NEXT: v_fmac_f32_e32 v3, -4.0, v18
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
+; CHECK-NEXT: v_fma_f32 v14, -v8, v19, v13
; CHECK-NEXT: v_fma_f32 v23, -v9, v20, v10
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_2)
-; CHECK-NEXT: v_fmac_f32_e32 v19, v14, v11
; CHECK-NEXT: v_fma_f32 v24, -v17, v15, 1.0
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; CHECK-NEXT: v_fmac_f32_e32 v20, v23, v12
-; CHECK-NEXT: v_fma_f32 v8, -v8, v19, v13
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; CHECK-NEXT: v_fmac_f32_e32 v15, v24, v15
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; CHECK-NEXT: v_dual_fmac_f32 v19, v14, v11 :: v_dual_fmac_f32 v20, v23, v12
+; CHECK-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; CHECK-NEXT: v_fma_f32 v14, -v16, v22, 1.0
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; CHECK-NEXT: v_fma_f32 v8, -v8, v19, v13
; CHECK-NEXT: v_fma_f32 v9, -v9, v20, v10
; CHECK-NEXT: v_div_scale_f32 v13, s2, v6, 0x40400000, v6
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; CHECK-NEXT: v_fmac_f32_e32 v22, v14, v22
+; CHECK-NEXT: v_fmac_f32_e32 v15, v24, v15
; CHECK-NEXT: v_div_fmas_f32 v8, v8, v11, v19
; CHECK-NEXT: s_mov_b32 vcc_lo, s0
-; CHECK-NEXT: v_mul_f32_e32 v10, v25, v15
; CHECK-NEXT: v_div_fmas_f32 v9, v9, v12, v20
-; CHECK-NEXT: s_mov_b32 vcc_lo, s1
+; CHECK-NEXT: v_mul_f32_e32 v12, v13, v22
+; CHECK-NEXT: v_dual_mul_f32 v21, 0x3e800000, v4 :: v_dual_mul_f32 v10, v25, v15
; CHECK-NEXT: v_div_fixup_f32 v8, v8, 0x40400000, v2
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; CHECK-NEXT: v_fma_f32 v11, -v17, v10, v25
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; CHECK-NEXT: v_div_fixup_f32 v9, v9, 0x40400000, v5
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; CHECK-NEXT: s_mov_b32 vcc_lo, s1
+; CHECK-NEXT: v_trunc_f32_e32 v21, v21
+; CHECK-NEXT: v_fma_f32 v11, -v17, v10, v25
; CHECK-NEXT: v_trunc_f32_e32 v8, v8
; CHECK-NEXT: v_trunc_f32_e32 v9, v9
-; CHECK-NEXT: v_fmac_f32_e32 v22, v14, v22
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; CHECK-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
-; CHECK-NEXT: v_dual_fmac_f32 v10, v11, v15 :: v_dual_fmac_f32 v5, 0xc0400000, v9
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; CHECK-NEXT: v_fmac_f32_e32 v10, v11, v15
+; CHECK-NEXT: v_dual_fmac_f32 v2, 0xc0400000, v8 :: v_dual_fmac_f32 v5, 0xc0400000, v9
; CHECK-NEXT: v_trunc_f32_e32 v9, v7
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; CHECK-NEXT: v_dual_mul_f32 v12, v13, v22 :: v_dual_sub_f32 v7, v7, v9
; CHECK-NEXT: v_fma_f32 v11, -v16, v12, v13
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; CHECK-NEXT: v_fmac_f32_e32 v12, v11, v22
-; CHECK-NEXT: v_mul_f32_e32 v11, 0.5, v2
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; CHECK-NEXT: v_fma_f32 v14, -v17, v10, v25
-; CHECK-NEXT: v_trunc_f32_e32 v11, v11
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; CHECK-NEXT: v_fmac_f32_e32 v4, -4.0, v21
+; CHECK-NEXT: v_sub_f32_e32 v7, v7, v9
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_fmac_f32_e32 v12, v11, v22
; CHECK-NEXT: v_div_fmas_f32 v8, v14, v15, v10
; CHECK-NEXT: v_mul_f32_e32 v10, 0x3e800000, v0
+; CHECK-NEXT: v_mul_f32_e32 v11, 0.5, v2
; CHECK-NEXT: s_mov_b32 vcc_lo, s2
-; CHECK-NEXT: v_fmac_f32_e32 v2, -2.0, v11
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; CHECK-NEXT: v_div_fixup_f32 v8, v8, 0x40400000, v1
; CHECK-NEXT: v_trunc_f32_e32 v9, v10
-; CHECK-NEXT: v_trunc_f32_e32 v11, v3
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; CHECK-NEXT: v_trunc_f32_e32 v8, v8
-; CHECK-NEXT: v_fmac_f32_e32 v4, -4.0, v21
-; CHECK-NEXT: v_dual_fmac_f32 v0, -4.0, v9 :: v_dual_sub_f32 v3, v3, v11
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; CHECK-NEXT: v_dual_fmac_f32 v1, 0xc0400000, v8 :: v_dual_mul_f32 v8, 0.5, v5
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_trunc_f32_e32 v11, v11
+; CHECK-NEXT: v_fma_f32 v10, -v16, v12, v13
; CHECK-NEXT: v_trunc_f32_e32 v8, v8
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; CHECK-NEXT: v_dual_fmac_f32 v0, -4.0, v9 :: v_dual_fmac_f32 v1, 0xc0400000, v8
+; CHECK-NEXT: v_mul_f32_e32 v8, 0.5, v5
+; CHECK-NEXT: v_trunc_f32_e32 v8, v8
+; CHECK-NEXT: v_fmac_f32_e32 v2, -2.0, v11
+; CHECK-NEXT: v_trunc_f32_e32 v11, v3
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_fmac_f32_e32 v5, -2.0, v8
-; CHECK-NEXT: v_fma_f32 v10, -v16, v12, v13
+; CHECK-NEXT: v_sub_f32_e32 v3, v3, v11
; CHECK-NEXT: v_div_fmas_f32 v10, v10, v22, v12
; CHECK-NEXT: v_trunc_f32_e32 v12, v4
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 112cfabd6d4343..486d7c15150bc9 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -10820,21 +10820,21 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1150-FAKE16-NEXT: s_cmp_nge_f16 s8, 0x7c00
; GFX1150-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s2
; GFX1150-FAKE16-NEXT: s_cmp_lg_f16 s9, 0
; GFX1150-FAKE16-NEXT: v_dual_cndmask_b32 v1, 0x7e00, v2 :: v_dual_mov_b32 v2, 0
-; GFX1150-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1150-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1150-FAKE16-NEXT: s_cmp_nge_f16 s7, 0x7c00
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1150-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1150-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s2
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v3, vcc_lo
-; GFX1150-FAKE16-NEXT: v_lshl_or_b32 v0, v4, 16, v0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1150-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT: v_lshl_or_b32 v0, v4, 16, v0
; GFX1150-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1150-FAKE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
index 65d36087440003..c6105e2eda9f38 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
@@ -4115,13 +4115,13 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v19
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v19
-; GFX11-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
-; GFX11-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-NEXT: v_mov_b32_e32 v4, v1
+; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v1, v35
; GFX11-NEXT: v_mov_b32_e32 v12, v3
; GFX11-NEXT: v_mov_b32_e32 v20, v17
-; GFX11-NEXT: v_mov_b32_e32 v24, v18
+; GFX11-NEXT: v_dual_mov_b32 v24, v18 :: v_dual_mov_b32 v3, v37
; GFX11-NEXT: v_mov_b32_e32 v28, v19
-; GFX11-NEXT: v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
+; GFX11-NEXT: v_mov_b32_e32 v2, v36
; GFX11-NEXT: v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
; GFX11-NEXT: v_mov_b32_e32 v19, v34
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -5859,13 +5859,13 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v19
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v19
-; GFX11-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
-; GFX11-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-NEXT: v_mov_b32_e32 v4, v1
+; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v1, v35
; GFX11-NEXT: v_mov_b32_e32 v12, v3
; GFX11-NEXT: v_mov_b32_e32 v20, v17
-; GFX11-NEXT: v_mov_b32_e32 v24, v18
+; GFX11-NEXT: v_dual_mov_b32 v24, v18 :: v_dual_mov_b32 v3, v37
; GFX11-NEXT: v_mov_b32_e32 v28, v19
-; GFX11-NEXT: v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
+; GFX11-NEXT: v_mov_b32_e32 v2, v36
; GFX11-NEXT: v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
; GFX11-NEXT: v_mov_b32_e32 v19, v34
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
index f805b11d35db58..aeaf0b344bab5d 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
@@ -3327,14 +3327,14 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: s_add_i32 s35, s32, 0x80
; GFX11-NEXT: s_add_i32 s36, s32, 0x70
; GFX11-NEXT: s_add_i32 s37, s32, 0x6c
+; GFX11-NEXT: s_waitcnt vmcnt(5)
+; GFX11-NEXT: v_dual_mov_b32 v40, v0 :: v_dual_mov_b32 v41, v1
+; GFX11-NEXT: v_mov_b32_e32 v42, v2
; GFX11-NEXT: s_waitcnt vmcnt(4)
-; GFX11-NEXT: v_dual_mov_b32 v40, v0 :: v_dual_mov_b32 v53, v26
-; GFX11-NEXT: v_dual_mov_b32 v41, v1 :: v_dual_mov_b32 v42, v2
-; GFX11-NEXT: v_mov_b32_e32 v51, v24
+; GFX11-NEXT: v_dual_mov_b32 v51, v24 :: v_dual_mov_b32 v52, v25
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: scratch_store_b128 off, v[20:23], s33 offset:1584 ; 16-byte Folded Spill
; GFX11-NEXT: scratch_load_b128 v[20:23], off, s33 offset:528
-; GFX11-NEXT: v_mov_b32_e32 v52, v25
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: scratch_store_b128 off, v[20:23], s33 offset:1536 ; 16-byte Folded Spill
; GFX11-NEXT: scratch_load_b128 v[20:23], off, s33 offset:544
@@ -3353,6 +3353,7 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: scratch_store_b128 off, v[11:14], s35
; GFX11-NEXT: scratch_store_b128 off, v[7:10], s36
; GFX11-NEXT: s_add_i32 s2, s32, 0x60
+; GFX11-NEXT: v_mov_b32_e32 v53, v26
; GFX11-NEXT: scratch_store_b32 off, v6, s37
; GFX11-NEXT: scratch_store_b96 off, v[3:5], s2
; GFX11-NEXT: s_add_i32 s2, s32, 0x50
@@ -3364,7 +3365,10 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: scratch_store_b128 off, v[31:34], s35
; GFX11-NEXT: scratch_store_b128 off, v[27:30], s36
; GFX11-NEXT: s_add_i32 s2, s32, 16
-; GFX11-NEXT: v_mov_b32_e32 v29, v43
+; GFX11-NEXT: v_dual_mov_b32 v29, v43 :: v_dual_mov_b32 v30, v44
+; GFX11-NEXT: v_mov_b32_e32 v31, v45
+; GFX11-NEXT: s_waitcnt vmcnt(2)
+; GFX11-NEXT: v_mov_b32_e32 v18, v21
; GFX11-NEXT: scratch_store_b128 off, v[50:53], s2
; GFX11-NEXT: s_clause 0x3 ; 64-byte Folded Reload
; GFX11-NEXT: scratch_load_b128 v[1:4], off, s33 offset:1584
@@ -3372,15 +3376,16 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: scratch_load_b128 v[9:12], off, s33 offset:1568
; GFX11-NEXT: scratch_load_b128 v[13:16], off, s33 offset:1552
; GFX11-NEXT: s_add_i32 s2, s33, 0x400
-; GFX11-NEXT: v_dual_mov_b32 v30, v44 :: v_dual_mov_b32 v31, v45
+; GFX11-NEXT: v_dual_mov_b32 v17, v20 :: v_dual_mov_b32 v20, v23
+; GFX11-NEXT: s_waitcnt vmcnt(5)
+; GFX11-NEXT: v_dual_mov_b32 v19, v22 :: v_dual_mov_b32 v22, v59
+; GFX11-NEXT: v_dual_mov_b32 v21, v58 :: v_dual_mov_b32 v24, v61
+; GFX11-NEXT: s_waitcnt vmcnt(4)
+; GFX11-NEXT: v_dual_mov_b32 v23, v60 :: v_dual_mov_b32 v26, v55
+; GFX11-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v28, v57
+; GFX11-NEXT: v_dual_mov_b32 v27, v56 :: v_dual_mov_b32 v0, s2
; GFX11-NEXT: s_waitcnt vmcnt(3)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 42
-; GFX11-NEXT: v_dual_mov_b32 v17, v20 :: v_dual_mov_b32 v18, v21
-; GFX11-NEXT: v_dual_mov_b32 v19, v22 :: v_dual_mov_b32 v20, v23
-; GFX11-NEXT: v_dual_mov_b32 v21, v58 :: v_dual_mov_b32 v22, v59
-; GFX11-NEXT: v_dual_mov_b32 v23, v60 :: v_dual_mov_b32 v24, v61
-; GFX11-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v55
-; GFX11-NEXT: v_dual_mov_b32 v27, v56 :: v_dual_mov_b32 v28, v57
+; GFX11-NEXT: v_mov_b32_e32 v1, 42
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_clause 0xd ; 56-byte Folded Reload
; GFX11-NEXT: scratch_load_b32 v61, off, s33
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index 1430ef6ad9aae2..3c4c6c2b745011 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -21473,21 +21473,21 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -21524,19 +21524,19 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -21870,21 +21870,21 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -21921,19 +21921,19 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -22269,21 +22269,21 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -22320,19 +22320,19 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -22677,22 +22677,21 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
@@ -23058,22 +23057,21 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
@@ -23442,22 +23440,21 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -23834,21 +23831,21 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -23885,19 +23882,19 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -24238,22 +24235,21 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
@@ -24624,21 +24620,21 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -24675,19 +24671,19 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -25022,22 +25018,21 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
@@ -25402,21 +25397,21 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -25453,19 +25448,19 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -25800,22 +25795,21 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
@@ -26180,21 +26174,21 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -26231,19 +26225,19 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -26578,22 +26572,21 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index fe49de1f0d29fd..dcd0e3aa3f4b04 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -14950,21 +14950,21 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15001,19 +15001,19 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15457,21 +15457,21 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15508,19 +15508,19 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15966,21 +15966,21 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -16017,19 +16017,19 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -16479,22 +16479,21 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
@@ -16965,22 +16964,21 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
@@ -17454,22 +17452,21 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -17957,21 +17954,21 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -18008,19 +18005,19 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -18467,22 +18464,21 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index 0095f991e122d3..96d0c1a9e11285 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -14950,21 +14950,21 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15001,19 +15001,19 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15457,21 +15457,21 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15508,19 +15508,19 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15966,21 +15966,21 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -16017,19 +16017,19 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -16479,22 +16479,21 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
@@ -16965,22 +16964,21 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
@@ -17454,22 +17452,21 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -17957,21 +17954,21 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -18008,19 +18005,19 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -18467,22 +18464,21 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
index 42a8596598bce2..9eff7ee37dc54e 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
@@ -15415,21 +15415,21 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15466,19 +15466,19 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -15922,21 +15922,21 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -15973,19 +15973,19 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -16431,21 +16431,21 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -16482,19 +16482,19 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -16944,22 +16944,21 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
@@ -17430,22 +17429,21 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
@@ -17919,22 +17917,21 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
@@ -18422,21 +18419,21 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
@@ -18473,19 +18470,19 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
@@ -18932,22 +18929,21 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v6, v6, v4 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
diff --git a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
index a8b37029649409..d4481fbdd93fef 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
@@ -573,16 +573,16 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
@@ -780,23 +780,23 @@ define amdgpu_ps <3 x i32> @s_uitofp_v3i1_to_v3bf16(<3 x i1> inreg %num) {
; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v5, v5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, v5, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v0
; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: ; return to shader part epilog
;
@@ -971,25 +971,24 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -1229,23 +1228,23 @@ define amdgpu_ps <4 x i32> @s_uitofp_v4i1_to_v4bf16(<4 x i1> inreg %num) {
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s3
; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX11-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v4
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-NEXT: v_add_nc_u32_e32 v7, v7, v4
-; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v3
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-NEXT: v_dual_cndmask_b32 v1, v5, v9 :: v_dual_add_nc_u32 v2, v2, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v5, v9 :: v_dual_add_nc_u32 v6, 0x7fff, v6
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v11, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
@@ -1899,16 +1898,16 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
@@ -2100,30 +2099,29 @@ define amdgpu_ps <3 x i32> @s_sitofp_v3i1_to_v3bf16(<3 x i1> inreg %num) {
; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_add_nc_u32_e32 v5, v5, v2
; GFX11-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-NEXT: v_add_nc_u32_e32 v4, v4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX11-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v0
; GFX11-NEXT: v_readfirstlane_b32 s0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: ; return to shader part epilog
@@ -2300,25 +2298,24 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -2555,45 +2552,42 @@ define amdgpu_ps <4 x i32> @s_sitofp_v4i1_to_v4bf16(<4 x i1> inreg %num) {
; GFX11-NEXT: s_cmp_eq_u32 s0, 1
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, s1
; GFX11-NEXT: s_cselect_b32 s0, -1, 0
-; GFX11-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s0
; GFX11-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s0
+; GFX11-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v7, v7, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v5, v5, v1
; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v0
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v9, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v9 :: v_dual_add_nc_u32 v7, v7, v4
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v6
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX11-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_readfirstlane_b32 s1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s3, v1
; GFX11-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
index e1992331061aa5..8aa06d2f8b674a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
@@ -623,10 +623,16 @@ define float @v_fdot2_f32_bf16_dual_sgpr_src0_y(<2 x bfloat> %a, <2 x bfloat> %b
; GFX950: v_dot2c_f32_bf16_e32 v5, s0, v3
; GFX950: v_add_f32_e32 v0, v2, v5
;
-; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_y:
-; GFX11PLUS: ; %bb.0:
-; GFX11PLUS: v_dual_dot2acc_f32_bf16 v2, v0, v1 :: v_dual_dot2acc_f32_bf16 v5, s0, v3
-; GFX11PLUS: v_add_f32_e32 v0, v2, v5
+; GFX11-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_y:
+; GFX11: ; %bb.0:
+; GFX11: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11: v_dot2_f32_bf16 v5, s0, v3, v5
+; GFX11: v_add_f32_e32 v0, v2, v5
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_y:
+; GFX12: ; %bb.0:
+; GFX12: v_dual_dot2acc_f32_bf16 v2, v0, v1 :: v_dual_dot2acc_f32_bf16 v5, s0, v3
+; GFX12: v_add_f32_e32 v0, v2, v5
%r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
%r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
%r = fadd float %r0, %r1
@@ -1206,6 +1212,3 @@ define float @v_fdot2_f32_bf16_clamp_dual(<2 x bfloat> %a, <2 x bfloat> %b, floa
%r = fadd float %r0, %r1
ret float %r
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11: {{.*}}
-; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
index 086101cd610d20..6a8a60b85ca68e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
@@ -821,10 +821,11 @@ define float @v_fdot2_dual_sgpr_src0_y(<2 x half> %a, <2 x half> %b, float %c, <
; GFX10: v_dot2c_f32_f16 v5, s16, v3
; GFX10: v_add_f32_e32 v0, v2, v5
;
-; GFX11PLUS-LABEL: v_fdot2_dual_sgpr_src0_y:
-; GFX11PLUS: ; %bb.0:
-; GFX11PLUS: v_dual_dot2acc_f32_f16 v2, v0, v1 :: v_dual_dot2acc_f32_f16 v5, s0, v3
-; GFX11PLUS: v_add_f32_e32 v0, v2, v5
+; GFX11-LABEL: v_fdot2_dual_sgpr_src0_y:
+; GFX11: ; %bb.0:
+; GFX11: v_dot2acc_f32_f16 v2, v0, v1
+; GFX11: v_dot2acc_f32_f16 v5, s0, v3
+; GFX11: v_add_f32_e32 v0, v2, v5
%r0 = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
%r1 = call float @llvm.amdgcn.fdot2(<2 x half> %d, <2 x half> %e, float %f, i1 false)
%r = fadd float %r0, %r1
@@ -852,7 +853,8 @@ define float @v_fdot2_dual_sgpr_src1_y(<2 x half> %a, <2 x half> %b, float %c, <
;
; GFX11-LABEL: v_fdot2_dual_sgpr_src1_y:
; GFX11: ; %bb.0:
-; GFX11: v_dual_dot2acc_f32_f16 v2, v0, v1 :: v_dual_dot2acc_f32_f16 v5, s0, v3
+; GFX11: v_dot2acc_f32_f16 v2, v0, v1
+; GFX11: v_dot2acc_f32_f16 v5, s0, v3
; GFX11: v_add_f32_e32 v0, v2, v5
;
; GFX1170-GFX12-LABEL: v_fdot2_dual_sgpr_src1_y:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
index 47e7cb77a84dd2..207d094ca60244 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
@@ -1423,8 +1423,9 @@ define amdgpu_gs <4 x half> @v_fptrunc_round_v4f32_to_v4f16_upward(<4 x float> %
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.h, v1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, v0
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, v3
; GFX11-SDAG-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-LABEL: v_fptrunc_round_v4f32_to_v4f16_upward:
@@ -1489,8 +1490,9 @@ define amdgpu_gs <4 x half> @v_fptrunc_round_v4f32_to_v4f16_downward(<4 x float>
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.h, v1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, v0
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, v3
; GFX11-SDAG-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-LABEL: v_fptrunc_round_v4f32_to_v4f16_downward:
@@ -1565,9 +1567,12 @@ define amdgpu_gs <8 x half> @v_fptrunc_round_v8f32_to_v8f16_upward(<8 x float> %
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v2
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v5.l, v4
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v7.l, v6
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v3
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v3, v7
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, v5
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, v7
; GFX11-SDAG-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-LABEL: v_fptrunc_round_v8f32_to_v8f16_upward:
@@ -1661,9 +1666,12 @@ define amdgpu_gs <8 x half> @v_fptrunc_round_v8f32_to_v8f16_downward(<8 x float>
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v2
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v5.l, v4
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v7.l, v6
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v3
-; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v3, v7
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, v5
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, v7
; GFX11-SDAG-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-LABEL: v_fptrunc_round_v8f32_to_v8f16_downward:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 3de89d00784372..0602af5c213840 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -1007,23 +1007,27 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
; GFX1100-SDAG-NEXT: v_fma_f32 v6, 0x3f317217, v1, -v4
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3f317217, v3, -v5
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v6, 0x3377d1cf, v1 :: v_dual_fmac_f32 v7, 0x3377d1cf, v3
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
-; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_mov_b32 v4, 0
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v6, 0x3377d1cf, v1
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v5, 0x3f317217, v3 :: v_dual_add_f32 v4, v4, v6
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3f317217, v3, -v5
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v7, 0x3377d1cf, v3 :: v_dual_mov_b32 v4, 0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v1, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v5, v5, v7
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v1, v0 :: v_dual_sub_f32 v0, v3, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v3, v2
; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
; GFX1100-SDAG-NEXT: s_endpgm
;
@@ -1639,40 +1643,43 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s6
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x41b17218, s7
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-NEXT: v_dual_mul_f32 v6, 0x3f317217, v2 :: v_dual_mul_f32 v7, 0x3f317217, v4
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v6, 0x3f317217, v2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v7, 0x3f317217, v4 :: v_dual_mul_f32 v8, 0x3f317217, v5
; GFX1100-SDAG-NEXT: v_fma_f32 v9, 0x3f317217, v2, -v6
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v10, 0x3f317217, v4, -v7
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v9, 0x3377d1cf, v2 :: v_dual_fmac_f32 v10, 0x3377d1cf, v4
-; GFX1100-SDAG-NEXT: v_mul_f32_e32 v8, 0x3f317217, v5
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v7, v7, v10
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v11, 0x3f317217, v5, -v8
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v10, 0x3377d1cf, v4 :: v_dual_fmac_f32 v11, 0x3377d1cf, v5
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v9, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v7, v7, v10 :: v_dual_add_f32 v8, v8, v11
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v6, v6, v9
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v11, 0x3377d1cf, v5 :: v_dual_sub_f32 v2, v2, v0
+; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v2, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v8, v11
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v5|
-; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_sub_f32 v1, v4, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v4, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v5, v3
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b96 v6, v[0:2], s[0:1]
@@ -2510,8 +2517,9 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; GFX1100-SDAG-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v8, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 4f1525ffff0a39..809501d0e5db5a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -1007,23 +1007,27 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
; GFX1100-SDAG-NEXT: v_fma_f32 v6, 0x3e9a209a, v1, -v4
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3e9a209a, v3, -v5
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v6, 0x3284fbcf, v1 :: v_dual_fmac_f32 v7, 0x3284fbcf, v3
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
-; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_mov_b32 v4, 0
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v6, 0x3284fbcf, v1
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v3 :: v_dual_add_f32 v4, v4, v6
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3e9a209a, v3, -v5
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v7, 0x3284fbcf, v3 :: v_dual_mov_b32 v4, 0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v1, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v5, v5, v7
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v1, v0 :: v_dual_sub_f32 v0, v3, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v3, v2
; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
; GFX1100-SDAG-NEXT: s_endpgm
;
@@ -1639,40 +1643,43 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s6
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x411a209b, s7
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-NEXT: v_dual_mul_f32 v6, 0x3e9a209a, v2 :: v_dual_mul_f32 v7, 0x3e9a209a, v4
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v7, 0x3e9a209a, v4 :: v_dual_mul_f32 v8, 0x3e9a209a, v5
; GFX1100-SDAG-NEXT: v_fma_f32 v9, 0x3e9a209a, v2, -v6
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v10, 0x3e9a209a, v4, -v7
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v9, 0x3284fbcf, v2 :: v_dual_fmac_f32 v10, 0x3284fbcf, v4
-; GFX1100-SDAG-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v5
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v7, v7, v10
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v11, 0x3e9a209a, v5, -v8
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v10, 0x3284fbcf, v4 :: v_dual_fmac_f32 v11, 0x3284fbcf, v5
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v9, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v7, v7, v10 :: v_dual_add_f32 v8, v8, v11
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v6, v6, v9
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v11, 0x3284fbcf, v5 :: v_dual_sub_f32 v2, v2, v0
+; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v2, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v8, v11
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v5|
-; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_sub_f32 v1, v4, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v4, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v5, v3
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b96 v6, v[0:2], s[0:1]
@@ -2510,8 +2517,9 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; GFX1100-SDAG-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v8, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index 2bcb08745c1e4d..2a5a15220687ee 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -785,11 +785,12 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, 0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v2, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-NEXT: v_dual_sub_f32 v2, v2, v0 :: v_dual_sub_f32 v1, v4, v1
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v4, v1
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v5, v3
; GFX1100-SDAG-NEXT: global_store_b96 v6, v[0:2], s[4:5]
; GFX1100-SDAG-NEXT: s_endpgm
@@ -1249,8 +1250,9 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v6, v6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v9, 0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v8, v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
index 207f1432504c8c..fe452122d788d1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
@@ -2408,12 +2408,12 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: v_pk_max_f16 v14, v1, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11
; GFX11-FAKE16-NEXT: v_pk_max_f16 v11, v0, v4
@@ -2427,18 +2427,17 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v10, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v9, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
index 6d18bb83313c8b..6d757b07bca1a1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
@@ -991,12 +991,12 @@ define <3 x float> @v_maximum_v3f32(<3 x float> %src0, <3 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_max_f32 v6, v0, v3 :: v_dual_max_f32 v7, v1, v4
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v8, v2, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v4
-; GFX11-NEXT: v_dual_max_f32 v8, v2, v5 :: v_dual_cndmask_b32 v1, 0x7fc00000, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1159,12 +1159,12 @@ define <3 x float> @v_maximum_v3f32__nsz(<3 x float> %src0, <3 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_max_f32 v6, v0, v3 :: v_dual_max_f32 v7, v1, v4
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v8, v2, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v4
-; GFX11-NEXT: v_dual_max_f32 v8, v2, v5 :: v_dual_cndmask_b32 v1, 0x7fc00000, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1340,11 +1340,12 @@ define <4 x float> @v_maximum_v4f32(<4 x float> %src0, <4 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_max_f32 v8, v0, v4 :: v_dual_max_f32 v9, v1, v5
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v4, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: v_max_f32_e32 v8, v3, v7
-; GFX11-NEXT: v_dual_max_f32 v4, v2, v6 :: v_dual_cndmask_b32 v1, 0x7fc00000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
@@ -1531,11 +1532,12 @@ define <4 x float> @v_maximum_v4f32__nsz(<4 x float> %src0, <4 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_max_f32 v8, v0, v4 :: v_dual_max_f32 v9, v1, v5
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v4, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: v_max_f32_e32 v8, v3, v7
-; GFX11-NEXT: v_dual_max_f32 v4, v2, v6 :: v_dual_cndmask_b32 v1, 0x7fc00000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
@@ -2119,11 +2121,11 @@ define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v13, v29
; GFX11-NEXT: v_cndmask_b32_e32 v13, 0x7fc00000, v53, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v14, v30
+; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7fc00000, v54, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_max_f32_e32 v16, v15, v31
-; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7fc00000, v54, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v15, v31
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v15, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
index c1d182730d3d98..48a36737ce45ac 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
@@ -1916,12 +1916,12 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: v_pk_min_f16 v14, v1, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11
; GFX11-FAKE16-NEXT: v_pk_min_f16 v11, v0, v4
@@ -1935,18 +1935,17 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v14, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v10, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v9, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
index 8629655ffb6f8b..a579a4be07a76b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
@@ -991,12 +991,12 @@ define <3 x float> @v_minimum_v3f32(<3 x float> %src0, <3 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_min_f32 v6, v0, v3 :: v_dual_min_f32 v7, v1, v4
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v8, v2, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v4
-; GFX11-NEXT: v_dual_min_f32 v8, v2, v5 :: v_dual_cndmask_b32 v1, 0x7fc00000, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1159,12 +1159,12 @@ define <3 x float> @v_minimum_v3f32__nsz(<3 x float> %src0, <3 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_min_f32 v6, v0, v3 :: v_dual_min_f32 v7, v1, v4
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v8, v2, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v4
-; GFX11-NEXT: v_dual_min_f32 v8, v2, v5 :: v_dual_cndmask_b32 v1, 0x7fc00000, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1340,11 +1340,12 @@ define <4 x float> @v_minimum_v4f32(<4 x float> %src0, <4 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_min_f32 v8, v0, v4 :: v_dual_min_f32 v9, v1, v5
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v4, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: v_min_f32_e32 v8, v3, v7
-; GFX11-NEXT: v_dual_min_f32 v4, v2, v6 :: v_dual_cndmask_b32 v1, 0x7fc00000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
@@ -1531,11 +1532,12 @@ define <4 x float> @v_minimum_v4f32__nsz(<4 x float> %src0, <4 x float> %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_min_f32 v8, v0, v4 :: v_dual_min_f32 v9, v1, v5
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v4, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: v_min_f32_e32 v8, v3, v7
-; GFX11-NEXT: v_dual_min_f32 v4, v2, v6 :: v_dual_cndmask_b32 v1, 0x7fc00000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
@@ -2119,11 +2121,11 @@ define <16 x float> @v_minimum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v13, v29
; GFX11-NEXT: v_cndmask_b32_e32 v13, 0x7fc00000, v53, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v14, v30
+; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7fc00000, v54, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_min_f32_e32 v16, v15, v31
-; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7fc00000, v54, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v15, v31
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v15, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
index de9e2e77a1f0bc..508b0ed90097fe 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
@@ -268,7 +268,7 @@ define { i64, i1 } @smulo_i64_v_v(i64 %x, i64 %y) {
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
; GFX11-NEXT: v_mov_b32_e32 v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v6, v4
; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
index fd5ab9296cb7c6..8d730d76123c4e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
@@ -279,8 +279,9 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mul_f32 v3, 0.5, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v2, v2
; GFX11-NEXT: v_trunc_f32_e32 v5, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
index c2776a0439996a..265cbcb9402733 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
@@ -378,16 +378,17 @@ define amdgpu_kernel void @round_v4f32(ptr addrspace(1) %out, <4 x float> %in) #
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s6
; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v6|, 0.5
; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v3, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1.0, s6
; GFX11-NEXT: v_cmp_ge_f32_e64 s6, |v7|, 0.5
-; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfi_b32 v6, 0x7fffffff, v6, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s6
; GFX11-NEXT: s_mov_b32 s6, -1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s0
+; GFX11-NEXT: v_add_f32_e32 v3, v0, v2
+; GFX11-NEXT: v_add_f32_e32 v2, v1, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_dual_add_f32 v1, v4, v6 :: v_dual_add_f32 v0, v5, v7
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[4:7], 0
; GFX11-NEXT: s_endpgm
@@ -668,16 +669,16 @@ define amdgpu_kernel void @round_v8f32(ptr addrspace(1) %out, <8 x float> %in) #
; GFX11-NEXT: v_bfi_b32 v16, 0x7fffffff, v3, s10
; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s2
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v11|, 0.5
-; GFX11-NEXT: v_sub_f32_e32 v13, s14, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v16
+; GFX11-NEXT: v_add_f32_e32 v3, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 1.0, s2
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v12|, 0.5
-; GFX11-NEXT: v_add_f32_e32 v1, v4, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_add_f32 v2, v1, v16 :: v_dual_add_f32 v1, v4, v7
; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, s8
+; GFX11-NEXT: v_sub_f32_e32 v13, s14, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, 1.0, s2
; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v13|, 0.5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -761,6 +762,8 @@ define amdgpu_kernel void @round_v8f32(ptr addrspace(1) %out, <8 x float> %in) #
; R600-NEXT: ADD T0.X, T3.W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT: ADD_INT * T2.X, PS, literal.x,
+; R600-NEXT: 4(5.605194e-45), 0(0.000000e+00)
%result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
store <8 x float> %result, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index c92039e315a89c..dda8572bad850e 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -7089,20 +7089,20 @@ define void @local_atomic_fadd_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-FAKE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7433,20 +7433,20 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 42fe1c92a2ba97..b5d6b93f74460e 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -7225,20 +7225,20 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-FAKE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_max_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_max_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7687,20 +7687,20 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_max_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_max_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_max_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_max_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index aec678a969add4..d1e02f8abfd64d 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -7225,20 +7225,20 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-FAKE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_min_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_min_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7687,20 +7687,20 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_min_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_min_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_min_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_min_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
index 057982b7c1c4c4..5e403e58e2d578 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
@@ -8045,20 +8045,20 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-FAKE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -8507,20 +8507,20 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-FAKE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_sub_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v2
+; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v2 :: v_dual_and_b32 v5, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_sub_f32_e32 v5, v5, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
index 8fe3cea6069b5f..0377ad6dc3492e 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
@@ -620,28 +620,28 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -912,28 +912,27 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v6 :: v_dual_lshlrev_b32 v3, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1328,50 +1327,50 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v6, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v5, v4 :: v_dual_lshlrev_b32 v7, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1738,34 +1737,33 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v10, v9 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v4, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v9 :: v_dual_lshlrev_b32 v7, 16, v3
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s3, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -2271,65 +2269,62 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v9, v8 :: v_dual_lshlrev_b32 v13, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
@@ -2811,45 +2806,45 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v11
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v6, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v7, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3566,104 +3561,107 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_and_b32 v11, 0xffff0000, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_lshlrev_b32 v12, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v15, v14 :: v_dual_lshlrev_b32 v13, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v12, v10, s1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v12
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v14
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
@@ -4740,121 +4738,121 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_and_b32 v11, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_and_b32 v17, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v13, v12 :: v_dual_and_b32 v11, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_lshlrev_b32 v14, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v12, v10 :: v_dual_lshlrev_b32 v12, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v11, v10 :: v_dual_lshlrev_b32 v12, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v13, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v12, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v9, s0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v18, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v12, v9 :: v_dual_lshlrev_b32 v16, 16, v7
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v17, v16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v17, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v17, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v11, 16, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v1 :: v_dual_lshlrev_b32 v16, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v17, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v11, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
@@ -6778,38 +6776,37 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v18, v17 :: v_dual_and_b32 v23, 0xffff0000, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v16 :: v_dual_and_b32 v18, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v19, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v19, v18 :: v_dual_lshlrev_b32 v20, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
@@ -6819,7 +6816,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v21, v20, s0
@@ -6827,76 +6824,73 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v21, v23, v22, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v18
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v22, v21 :: v_dual_lshlrev_b32 v25, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v24, v23, s1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v29, v28, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v25
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s3, v20, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v24, v25, s3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v26, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
@@ -6905,9 +6899,10 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v23
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v25, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v24, v26, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
@@ -6970,7 +6965,8 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
@@ -10856,166 +10852,160 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v30
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v86, v86
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v132, v131, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v132, v131, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v130, v144, v135, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v13
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v86, v86
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v102, 16, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s16, v37, v132
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s17, v49, v133
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v71, v80, s4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v54, v98
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s16, v37, v132
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s18, v53, v134
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s18, v53, v134
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v65, v135
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v69, v144
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v101, v101
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v69, v144
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v87, v99, v100, s7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v113, v113
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v71, v145
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
@@ -11025,109 +11015,115 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v87
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v83, v146
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v112
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v99
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v86, v147
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v97, v54
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v113
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v101, v98
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v128
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v117
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v103, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v130
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v101, v98
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s17, v49, v133
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v115, v132
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v103, v37
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v119, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v131, v133
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v48
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v115, v132
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v52
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v64
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v119, v49
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v68
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v131, v133
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v80
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v38, v38, v34, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v66, v53
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v35
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v39
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v84
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v64
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s15
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s15, v82, v134
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v96
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v53
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v82
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v100
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v68
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s15, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v80
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s16, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v112
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s17, s1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v51, v52, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s18, s2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v84
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s19, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v96
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v68, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s20, s4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v100
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v67, v80, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s21, s5
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v69, v84, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v69, v84 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s22, s6
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v118
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v70, v96, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s23, s7
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v112
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v71, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v118
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v83
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v38
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v128
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v113
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v34
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
@@ -11203,8 +11199,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v36, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v32, v31
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
@@ -11305,7 +11302,8 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
@@ -13194,28 +13192,28 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13645,50 +13643,50 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v6, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v5, v4 :: v_dual_lshlrev_b32 v7, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -14242,65 +14240,62 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16_no_ieee:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v9, v8 :: v_dual_lshlrev_b32 v13, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
index e8c77cb8958279..73e91121185090 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
@@ -629,28 +629,28 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -924,28 +924,27 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v6 :: v_dual_lshlrev_b32 v3, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1343,50 +1342,50 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v6, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v5, v4 :: v_dual_lshlrev_b32 v7, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1755,34 +1754,33 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v10, v9 :: v_dual_lshlrev_b32 v4, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v4, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v7, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v9 :: v_dual_lshlrev_b32 v7, 16, v3
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s3, vcc_lo
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -2291,65 +2289,62 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v9, v8 :: v_dual_lshlrev_b32 v13, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
@@ -2834,45 +2829,45 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v11
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v6, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v7, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v5, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v8, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3592,104 +3587,107 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_and_b32 v11, 0xffff0000, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_lshlrev_b32 v12, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v15, v14 :: v_dual_lshlrev_b32 v13, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v14, v10 :: v_dual_lshlrev_b32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v12, v10, s1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v5, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v12
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v14
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, v2, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v11, 16, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v11
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
@@ -4768,121 +4766,121 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_and_b32 v11, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_and_b32 v17, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v13, v12 :: v_dual_and_b32 v11, 0xffff0000, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v13, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_lshlrev_b32 v14, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v12, v10 :: v_dual_lshlrev_b32 v12, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v11, v10 :: v_dual_lshlrev_b32 v12, 16, v9
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v9, v8 :: v_dual_lshlrev_b32 v13, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v12, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v15, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v14, v9, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v15, v13, s0
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v11, v10 :: v_dual_lshlrev_b32 v15, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v14
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v12, v9, s0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v18, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, v13, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v14
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v6
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v12, v9 :: v_dual_lshlrev_b32 v16, 16, v7
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v17, v16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v17, 16, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v17, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v3, s3
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v11, 16, v5
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v1 :: v_dual_lshlrev_b32 v16, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v17, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v11, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
@@ -6808,38 +6806,37 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v18, v17 :: v_dual_and_b32 v23, 0xffff0000, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v16 :: v_dual_and_b32 v18, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v19, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v18, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v19, v18 :: v_dual_lshlrev_b32 v20, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v19, v18, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
@@ -6849,7 +6846,7 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v24, v24
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v21, v20, s0
@@ -6857,76 +6854,73 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v21, v23, v22, s0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v18
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
-; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v17, v20, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v3
+; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v22, v21, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v22
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v23, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v23, v25, v24, s1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v22, v21 :: v_dual_lshlrev_b32 v25, 16, v24
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v21
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v24, v23, s1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v25, v29, v28, s1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v25
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v25
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, v20, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v24, v25, s3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v26, v29, v28, s3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v28, v26, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
@@ -6935,9 +6929,10 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v23
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v20, v25 :: v_dual_lshlrev_b32 v25, 16, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v25, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, v24, v26, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v27, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
@@ -7000,7 +6995,8 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
@@ -10889,166 +10885,160 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v30
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v86, v86
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v132, v131, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v82, v82
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v128, v119, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v132, v131, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v130, v144, v135, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v70, v70
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v13
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v84, v84, v83, s5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v11
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v86, v86
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v102, v102
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v102, 16, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v96, v96, v87, s6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s16, v37, v132
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v98, v98
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v28
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v29
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s17, v49, v133
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v65, v65
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v82, v82
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v80, v80, v71, s4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v100, v100, v99, s7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s2
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v69, v69
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v53, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v81, v81
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s12, v145, v145
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s15, v98, v98
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v39
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v67, v68, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v64
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v71, v80, s4
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s10, v129, v129
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v129, v135, v130, s12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v55
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v28, v28, v12, s15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v67
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v54, v98
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s16, v37, v132
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s18, v53, v134
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v80
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s5, v85, v85
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v144, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s18, v53, v134
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v35, v35, v36, s15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v39, v39, v48, s16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v65, v135
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v83, v84, s5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s6, v97, v97
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v69, v144
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v84
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s7, v101, v101
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v85, v87, v96, s6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v81
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v55, v55, v64, s18
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v65, v67, v68, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v69, v144
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s9, v114, v114
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v112, v112, v103, s8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v96
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v87, v99, v100, s7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s8, v113, v113
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s13, v38, v38
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v85
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v67, v70, v80, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v71, v145
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v116, v116, v115, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v100
@@ -11058,109 +11048,115 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v87
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v69, v81, v84, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v83, v146
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v112
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v102, v115, v116, s9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v99
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v70, v85, v96, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v86, v147
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v116
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v113, v119, v118, s10
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s11, v133, v133
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v102
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v71, v87, v100, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v97, v54
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v117, v131, v128, s11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v113
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v101, v98
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v128
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v132, 16, v117
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v51
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v103, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v119, 16, v130
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v54, v99, v112, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v101, v98
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s14, v66, v66
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v81, v102, v116, s15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v118
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s17, v49, v133
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v129
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v115, v132
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s14
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v103, v37
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v119, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v29
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v51, v51, v52, s17
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v131, v133
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v55
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v48
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v37, v113, v118, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v115, v132
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v65
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v52
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v64
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v83, v117, v128, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v119, v49
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v68
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v49, v129, v130, s15
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v131, v133
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v80
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v38, v38, v34, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v66, v53
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v35
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v39
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v84
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v87, 16, v67
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v64
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v30, v30, v14, s15
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s15, v82, v134
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v51
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v66
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v96
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v85
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v69
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v29, v29, v13, s15
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v53
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v82
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v100
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v68
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v86
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v98, 16, v70
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s15, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v80
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s16, s0
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v112
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v87
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v39, v48, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s17, s1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v99, 16, v71
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v51, v52, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s18, s2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v84
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v97
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v55, v64, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s19, s3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v96
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v98
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v68, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s20, s4
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v100
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v99
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v67, v80, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s21, s5
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v69, v84, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v69, v84 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s22, s6
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v118
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v54
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v70, v96, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s23, s7
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v112
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v71, v100, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v101
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v37
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v116
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v118
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v113, 16, v83
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v102
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v103
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v115, 16, v49
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v38
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v128
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v113
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v130
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v34
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
@@ -11236,8 +11232,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v36, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v32, v31
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
@@ -11338,7 +11335,8 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s1, s2
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
@@ -13232,28 +13230,28 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13686,50 +13684,50 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v6, 16, v2
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v8, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v5, v4 :: v_dual_lshlrev_b32 v7, 16, v2
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 s0, s1, s2
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -14286,65 +14284,62 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16_no_ieee:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v9, v8 :: v_dual_lshlrev_b32 v13, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v13, 16, v1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v8, v6, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v9, 16, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, v1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, v6, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v0, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6
diff --git a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
index f98d30449fe3d6..4949d917be43ed 100644
--- a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
+++ b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
@@ -676,8 +676,11 @@ define <4 x float> @v_repeat_divisor_v2f32_x2(<2 x float> %x, <2 x float> %y, <2
; GFX11-NEXT: v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9
; GFX11-NEXT: v_div_scale_f32 v10, s0, 1.0, v5, 1.0
; GFX11-NEXT: v_mul_f32_e32 v11, v12, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_f32_e32 v13, v10, v9
; GFX11-NEXT: v_fma_f32 v14, -v6, v11, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_fma_f32 v15, -v7, v13, v10
; GFX11-NEXT: v_fmac_f32_e32 v11, v14, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f32 v6, -v6, v11, v12
@@ -685,16 +688,13 @@ define <4 x float> @v_repeat_divisor_v2f32_x2(<2 x float> %x, <2 x float> %y, <2
; GFX11-NEXT: s_mov_b32 vcc_lo, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_fixup_f32 v4, v6, v4, 1.0
-; GFX11-NEXT: v_dual_mul_f32 v13, v10, v9 :: v_dual_mul_f32 v0, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f32 v15, -v7, v13, v10
-; GFX11-NEXT: v_dual_mul_f32 v2, v2, v4 :: v_dual_fmac_f32 v13, v15, v9
+; GFX11-NEXT: v_dual_fmac_f32 v13, v15, v9 :: v_dual_mul_f32 v0, v0, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f32 v7, -v7, v13, v10
; GFX11-NEXT: v_div_fmas_f32 v7, v7, v9, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_fixup_f32 v5, v7, v5, 1.0
-; GFX11-NEXT: v_mul_f32_e32 v1, v1, v5
+; GFX11-NEXT: v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v1, v1, v5
; GFX11-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
%div0 = fdiv arcp <2 x float> %x, %D
diff --git a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
index 63cd340f45657f..0b0cdabeacee0f 100644
--- a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
+++ b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
@@ -999,8 +999,10 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
@@ -2003,8 +2005,10 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
@@ -3007,8 +3011,10 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
@@ -4008,8 +4014,10 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
@@ -5009,8 +5017,10 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
@@ -6021,8 +6031,10 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
@@ -7032,8 +7044,10 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
diff --git a/llvm/test/CodeGen/AMDGPU/select.f16.ll b/llvm/test/CodeGen/AMDGPU/select.f16.ll
index 8b41ae48c29c77..14ae7ee349e1fb 100644
--- a/llvm/test/CodeGen/AMDGPU/select.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select.f16.ll
@@ -1699,9 +1699,9 @@ define <4 x half> @v_vselect_v4f16(<4 x half> %a, <4 x half> %b, <4 x i32> %cond
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v7, v1, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq <4 x i32> %cond, zeroinitializer
@@ -1850,16 +1850,15 @@ define <8 x half> @v_vselect_v8f16(<8 x half> %a, <8 x half> %b, <8 x i32> %cond
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v13, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v9, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v13, v2, 0x5040100
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v11, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v9, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v15, v3, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq <8 x i32> %cond, zeroinitializer
@@ -2109,31 +2108,31 @@ define <16 x half> @v_vselect_v16f16(<16 x half> %a, <16 x half> %b, <16 x i32>
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v29
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v35, v34, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v8, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v37, v36, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v8, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v9, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v39, v38, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v19
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v10, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v53, v52, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v17
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v10, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v11, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v55, v54, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v21
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v12, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v51, v50, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v23
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v49, v48, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v13, v2, 0x5040100
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v49, v48, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v14, v3, 0x5040100
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v31
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v33, v32, vcc_lo
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v12, v0, 0x5040100
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v7, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq <16 x i32> %cond, zeroinitializer
@@ -2209,8 +2208,9 @@ define <32 x half> @v_select_v32f16(<32 x half> %a, <32 x half> %b, i32 %cond) {
; GFX11-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
; GFX11-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
; GFX11-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_cndmask_b32 v14, v30, v14 :: v_dual_cndmask_b32 v15, v32, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v32, v15, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %cond, 0
%select = select i1 %cmp, <32 x half> %a, <32 x half> %b
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index c0061d4dfb9900..42d6bbc8f03b73 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -2308,10 +2308,11 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v7, v7, v7
; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v1, v1, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v4, v4 :: v_dual_max_f32 v4, v5, v5
+; GFX11-GISEL-NEXT: v_max_f32_e32 v5, v6, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v5, v5 :: v_dual_max_f32 v5, v6, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2335,10 +2336,11 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v4, v4 :: v_dual_max_num_f32 v4, v5, v5
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v5, v6, v7
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_max_num_f32 v5, v6, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: v_max3_num_f32 v1, v3, v4, v5
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2591,25 +2593,27 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: v_max_f32_e32 v8, v8, v8
+; GFX11-GISEL-NEXT: v_dual_max_f32 v8, v8, v8 :: v_dual_max_f32 v9, v9, v9
; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v2, v2, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v6, v6 :: v_dual_max_f32 v6, v7, v7
; GFX11-GISEL-NEXT: v_dual_max_f32 v7, v10, v10 :: v_dual_max_f32 v10, v11, v11
; GFX11-GISEL-NEXT: v_dual_max_f32 v11, v14, v14 :: v_dual_max_f32 v14, v15, v15
-; GFX11-GISEL-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4
; GFX11-GISEL-NEXT: v_max_f32_e32 v3, v3, v6
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v7, v7, v10 :: v_dual_max_f32 v10, v12, v12
-; GFX11-GISEL-NEXT: v_dual_max_f32 v12, v13, v13 :: v_dual_max_f32 v11, v11, v14
+; GFX11-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_max_f32_e32 v7, v7, v10
+; GFX11-GISEL-NEXT: v_dual_max_f32 v10, v12, v12 :: v_dual_max_f32 v5, v5, v5
+; GFX11-GISEL-NEXT: v_max_f32_e32 v12, v13, v13
; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_max3_f32 v6, v8, v9, v7
+; GFX11-GISEL-NEXT: v_max_f32_e32 v11, v11, v14
; GFX11-GISEL-NEXT: v_max3_f32 v1, v4, v5, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max3_f32 v7, v10, v12, v11
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v6, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2634,25 +2638,27 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v8, v8, v8 :: v_dual_max_num_f32 v9, v9, v9
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_max_num_f32 v2, v2, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v3, v3, v6
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_max_num_f32 v11, v11, v14
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v4, v4, v4
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v7, v7, v10
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v10, v12, v12 :: v_dual_max_num_f32 v5, v5, v5
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v12, v13, v13
; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1170-GISEL-NEXT: v_max3_num_f32 v6, v8, v9, v7
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v11, v11, v14
; GFX1170-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max3_num_f32 v7, v10, v12, v11
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v6, v7
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
index 51e78d2f1ed334..93c5ddad7fd219 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
@@ -1011,14 +1011,15 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v8, v1, v5
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v10, v0, v4
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v5, v3, v7
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
@@ -1039,22 +1040,22 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v14, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v7, v4, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v10, v1, v9, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v7, v4, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v15, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v8, v6, v2, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v11, v5, v3, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v7, v7, v8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v8, v10, v11
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v10, v1, v9, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v6
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v8, v10, v11
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v10, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9, v3
@@ -1528,24 +1529,24 @@ define float @test_vector_reduce_fmaximum_v8float(<8 x float> %v) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_dual_max_f32 v8, v0, v4 :: v_dual_cndmask_b32 v3, 0x7fc00000, v9
; GFX11-NEXT: v_max_f32_e32 v6, v1, v5
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_max_f32 v8, v0, v4 :: v_dual_cndmask_b32 v1, 0x7fc00000, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT: v_max_f32_e32 v4, v1, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_max_f32_e32 v5, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f32_e32 v2, v0, v1
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1799,40 +1800,43 @@ define float @test_vector_reduce_fmaximum_v16float(<16 x float> %v) {
; GFX11-LABEL: test_vector_reduce_fmaximum_v16float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v17, v1, v9 :: v_dual_max_f32 v18, v7, v15
-; GFX11-NEXT: v_max_f32_e32 v16, v5, v13
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v18, v7, v15
+; GFX11-NEXT: v_max_f32_e32 v16, v5, v13
+; GFX11-NEXT: v_max_f32_e32 v17, v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v9
-; GFX11-NEXT: v_dual_max_f32 v16, v4, v12 :: v_dual_max_f32 v13, v3, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo
+; GFX11-NEXT: v_dual_max_f32 v16, v4, v12 :: v_dual_cndmask_b32 v1, 0x7fc00000, v17
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v7, v15
-; GFX11-NEXT: v_max_f32_e32 v15, v2, v10
-; GFX11-NEXT: v_max_f32_e32 v9, v6, v14
; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7fc00000, v18, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v15, v2, v10
+; GFX11-NEXT: v_max_f32_e32 v9, v6, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v10
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v15, vcc_lo
+; GFX11-NEXT: v_max_f32_e32 v13, v3, v11
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_max_f32 v10, v2, v6 :: v_dual_cndmask_b32 v3, 0x7fc00000, v13
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v4, v12
; GFX11-NEXT: v_max_f32_e32 v9, v0, v8
; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v8
-; GFX11-NEXT: v_max_f32_e32 v8, v3, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
-; GFX11-NEXT: v_dual_max_f32 v9, v0, v4 :: v_dual_cndmask_b32 v2, 0x7fc00000, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
+; GFX11-NEXT: v_max_f32_e32 v8, v3, v7
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
-; GFX11-NEXT: v_dual_max_f32 v6, v1, v5 :: v_dual_cndmask_b32 v3, 0x7fc00000, v8
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v3, 0x7fc00000, v8 :: v_dual_max_f32 v6, v1, v5
+; GFX11-NEXT: v_max_f32_e32 v9, v0, v4
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_max_f32_e32 v4, v1, v3
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index 7b8a41e1fa99ef..168d188f20132a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -2308,10 +2308,11 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v7, v7, v7
; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v1, v1, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v4, v4 :: v_dual_max_f32 v4, v5, v5
+; GFX11-GISEL-NEXT: v_min_f32_e32 v5, v6, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v5, v5 :: v_dual_min_f32 v5, v6, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2335,10 +2336,11 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v4, v4 :: v_dual_max_num_f32 v4, v5, v5
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v5, v6, v7
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_min_num_f32 v5, v6, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: v_min3_num_f32 v1, v3, v4, v5
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2591,25 +2593,27 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: v_max_f32_e32 v8, v8, v8
+; GFX11-GISEL-NEXT: v_dual_max_f32 v8, v8, v8 :: v_dual_max_f32 v9, v9, v9
; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_min_f32 v2, v2, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v6, v6 :: v_dual_max_f32 v6, v7, v7
; GFX11-GISEL-NEXT: v_dual_max_f32 v7, v10, v10 :: v_dual_max_f32 v10, v11, v11
; GFX11-GISEL-NEXT: v_dual_max_f32 v11, v14, v14 :: v_dual_max_f32 v14, v15, v15
-; GFX11-GISEL-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4
; GFX11-GISEL-NEXT: v_min_f32_e32 v3, v3, v6
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v7, v7, v10 :: v_dual_max_f32 v10, v12, v12
-; GFX11-GISEL-NEXT: v_dual_max_f32 v12, v13, v13 :: v_dual_min_f32 v11, v11, v14
+; GFX11-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_min_f32_e32 v7, v7, v10
+; GFX11-GISEL-NEXT: v_dual_max_f32 v10, v12, v12 :: v_dual_max_f32 v5, v5, v5
+; GFX11-GISEL-NEXT: v_max_f32_e32 v12, v13, v13
; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_min3_f32 v6, v8, v9, v7
+; GFX11-GISEL-NEXT: v_min_f32_e32 v11, v11, v14
; GFX11-GISEL-NEXT: v_min3_f32 v1, v4, v5, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min3_f32 v7, v10, v12, v11
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_f32_e32 v2, v6, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2634,25 +2638,27 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v8, v8, v8 :: v_dual_max_num_f32 v9, v9, v9
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_min_num_f32 v2, v2, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v3, v3, v6
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_min_num_f32 v11, v11, v14
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v4, v4, v4
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v7, v7, v10
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v10, v12, v12 :: v_dual_max_num_f32 v5, v5, v5
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v12, v13, v13
; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1170-GISEL-NEXT: v_min3_num_f32 v6, v8, v9, v7
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v11, v11, v14
; GFX1170-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min3_num_f32 v7, v10, v12, v11
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v6, v7
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index d6c37307bc21b4..312fb59c0d9b54 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -1191,14 +1191,15 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v8, v1, v5
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v10, v0, v4
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v5, v3, v7
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
@@ -1219,22 +1220,22 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v14, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v7, v4, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v10, v1, v9, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v7, v4, v0, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v15, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v8, v6, v2, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v11, v5, v3, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v7, v7, v8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v8, v10, v11
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v10, v1, v9, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v6
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v8, v10, v11
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v10, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9, v3
@@ -1804,24 +1805,24 @@ define float @test_vector_reduce_fminimum_v8float(<8 x float> %v) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_dual_min_f32 v8, v0, v4 :: v_dual_cndmask_b32 v3, 0x7fc00000, v9
; GFX11-NEXT: v_min_f32_e32 v6, v1, v5
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_min_f32 v8, v0, v4 :: v_dual_cndmask_b32 v1, 0x7fc00000, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT: v_min_f32_e32 v4, v1, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_min_f32_e32 v5, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f32_e32 v2, v0, v1
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -2103,40 +2104,43 @@ define float @test_vector_reduce_fminimum_v16float(<16 x float> %v) {
; GFX11-LABEL: test_vector_reduce_fminimum_v16float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_min_f32 v17, v1, v9 :: v_dual_min_f32 v18, v7, v15
-; GFX11-NEXT: v_min_f32_e32 v16, v5, v13
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v18, v7, v15
+; GFX11-NEXT: v_min_f32_e32 v16, v5, v13
+; GFX11-NEXT: v_min_f32_e32 v17, v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v9
-; GFX11-NEXT: v_dual_min_f32 v16, v4, v12 :: v_dual_min_f32 v13, v3, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo
+; GFX11-NEXT: v_dual_min_f32 v16, v4, v12 :: v_dual_cndmask_b32 v1, 0x7fc00000, v17
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v7, v15
-; GFX11-NEXT: v_min_f32_e32 v15, v2, v10
-; GFX11-NEXT: v_min_f32_e32 v9, v6, v14
; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7fc00000, v18, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v15, v2, v10
+; GFX11-NEXT: v_min_f32_e32 v9, v6, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v10
; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v15, vcc_lo
+; GFX11-NEXT: v_min_f32_e32 v13, v3, v11
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_min_f32 v10, v2, v6 :: v_dual_cndmask_b32 v3, 0x7fc00000, v13
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v4, v12
; GFX11-NEXT: v_min_f32_e32 v9, v0, v8
; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v8
-; GFX11-NEXT: v_min_f32_e32 v8, v3, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
-; GFX11-NEXT: v_dual_min_f32 v9, v0, v4 :: v_dual_cndmask_b32 v2, 0x7fc00000, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
+; GFX11-NEXT: v_min_f32_e32 v8, v3, v7
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
-; GFX11-NEXT: v_dual_min_f32 v6, v1, v5 :: v_dual_cndmask_b32 v3, 0x7fc00000, v8
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v3, 0x7fc00000, v8 :: v_dual_min_f32 v6, v1, v5
+; GFX11-NEXT: v_min_f32_e32 v9, v0, v4
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT: v_min_f32_e32 v4, v1, v3
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
index d64d59f39f2739..ea563e99ba6e25 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
@@ -2795,9 +2795,9 @@ define i64 @test_vector_reduce_mul_v2i64(<2 x i64> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_mul_v2i64:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v2
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, v0
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v4, v5, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[7:8], null, v4, v3, v[1:2]
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
index ee346785aee2c5..30b0554fcc482b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
@@ -5459,71 +5459,70 @@ define amdgpu_kernel void @fma_shuffle_v2bf16(ptr addrspace(1) nocapture readonl
; GFX11-TRUE16-NEXT: global_load_b64 v[4:5], v6, s[6:7]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v11, v12, v9 :: v_dual_lshlrev_b32 v8, 16, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v1, v12, v4 :: v_dual_and_b32 v2, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v11, v12, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v7, v8, v9 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v0, v8, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v1, v12, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v4, v2, v5 :: v_dual_cndmask_b32 v1, v15, v16
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v4, v2, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v15, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v0, v2, v10
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v13, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v7, v3, v5 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v0, v2, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v3, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v5, v8 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v1, v3, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
@@ -5553,84 +5552,82 @@ define amdgpu_kernel void @fma_shuffle_v2bf16(ptr addrspace(1) nocapture readonl
; GFX11-FAKE16-NEXT: global_load_b64 v[4:5], v6, s[6:7]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
+; GFX11-FAKE16-NEXT: v_dual_fmac_f32 v11, v12, v9 :: v_dual_lshlrev_b32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v11, v12, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_fmac_f32 v7, v8, v9 :: v_dual_lshlrev_b32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v11, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_dual_fmac_f32 v1, v12, v4 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
-; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v0, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v15, v15, v1, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v1, v12, v4
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v7, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v0
; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v7, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v15, v15, v1, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v9, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v4, v2, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v15, v16, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v0, v2, v10
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_fmac_f32 v7, v3, v5 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v0, v2, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v7, v3, v5
+; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
; GFX11-FAKE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v1, v3, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v4, v2, v5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v2, v1, 0x7060302
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v3, v0, 0x7060302
; GFX11-FAKE16-NEXT: global_store_b64 v6, v[0:1], s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/vopd-combine.mir b/llvm/test/CodeGen/AMDGPU/vopd-combine.mir
index 17416c3471f7a3..e0c558c95a89f7 100644
--- a/llvm/test/CodeGen/AMDGPU/vopd-combine.mir
+++ b/llvm/test/CodeGen/AMDGPU/vopd-combine.mir
@@ -27,6 +27,8 @@
define void @vopd_mov_fixup_fail() { ret void }
define void @vopd_dependent_subreg() { ret void }
define void @vopd_mov_mov_same_src_bank() { ret void }
+ define void @vopd_src0_same_parity_different_banks() { ret void }
+ define void @vopd_src1_same_parity_different_banks() { ret void }
define void @vopd_combine_opy_overwrites_opx() { ret void }
define void @vopd_no_combine_opx_overwrites_opy() { ret void }
...
@@ -164,20 +166,20 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vcc_lo
- ; SCHED-LABEL: name: vopd_cndmask
- ; SCHED: liveins: $vcc_lo
- ; SCHED-NEXT: {{ $}}
- ; SCHED-NEXT: $vgpr2 = IMPLICIT_DEF
- ; SCHED-NEXT: $vgpr0 = IMPLICIT_DEF
- ; SCHED-NEXT: $vgpr1 = IMPLICIT_DEF
- ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF
- ; SCHED-NEXT: $sgpr20 = IMPLICIT_DEF
- ; SCHED-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
- ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 $sgpr20, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
- ; SCHED-NEXT: $vgpr5 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
- ; SCHED-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
- ; SCHED-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
- ; SCHED-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo
+ ; SCHED-GFX11-LABEL: name: vopd_cndmask
+ ; SCHED-GFX11: liveins: $vcc_lo
+ ; SCHED-GFX11-NEXT: {{ $}}
+ ; SCHED-GFX11-NEXT: $vgpr2 = IMPLICIT_DEF
+ ; SCHED-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
+ ; SCHED-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; SCHED-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; SCHED-GFX11-NEXT: $sgpr20 = IMPLICIT_DEF
+ ; SCHED-GFX11-NEXT: $vgpr5 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 $sgpr20, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo
;
; PAIR-GFX1100-LABEL: name: vopd_cndmask
; PAIR-GFX1100: liveins: $vcc_lo
@@ -187,8 +189,9 @@ body: |
; PAIR-GFX1100-NEXT: $vgpr1 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $sgpr20 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr5 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr2 = V_FMAC_F32_e32 $sgpr20, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
; PAIR-GFX1100-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
; PAIR-GFX1100-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo
@@ -201,12 +204,28 @@ body: |
; PAIR-GFX1170-NEXT: $vgpr1 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $sgpr20 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr5 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr2 = V_FMAC_F32_e32 $sgpr20, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx1170 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
; PAIR-GFX1170-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
; PAIR-GFX1170-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo
;
+ ; SCHED-GFX12-LABEL: name: vopd_cndmask
+ ; SCHED-GFX12: liveins: $vcc_lo
+ ; SCHED-GFX12-NEXT: {{ $}}
+ ; SCHED-GFX12-NEXT: $vgpr2 = IMPLICIT_DEF
+ ; SCHED-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+ ; SCHED-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; SCHED-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; SCHED-GFX12-NEXT: $sgpr20 = IMPLICIT_DEF
+ ; SCHED-GFX12-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
+ ; SCHED-GFX12-NEXT: $vgpr2 = V_FMAC_F32_e32 $sgpr20, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+ ; SCHED-GFX12-NEXT: $vgpr5 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX12-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX12-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
+ ; SCHED-GFX12-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo
+ ;
; PAIR-GFX12-LABEL: name: vopd_cndmask
; PAIR-GFX12: liveins: $vcc_lo
; PAIR-GFX12-NEXT: {{ $}}
@@ -506,57 +525,57 @@ body: |
; SCHED-GFX11: liveins: $vcc_lo
; SCHED-GFX11-NEXT: {{ $}}
; SCHED-GFX11-NEXT: $vgpr2 = IMPLICIT_DEF
- ; SCHED-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
; SCHED-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
; SCHED-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; SCHED-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
; SCHED-GFX11-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr3 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr6 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr17 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr3 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr6 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
- ; SCHED-GFX11-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
- ; SCHED-GFX11-NEXT: $vgpr17 = V_MUL_F32_e32 killed $vgpr0, $vgpr0, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr10 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr19 = V_CNDMASK_B32_e32 killed $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
; SCHED-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
- ; SCHED-GFX11-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
;
; PAIR-GFX1100-LABEL: name: vopd_schedule_unconstrained
; PAIR-GFX1100: liveins: $vcc_lo
; PAIR-GFX1100-NEXT: {{ $}}
; PAIR-GFX1100-NEXT: $vgpr2 = IMPLICIT_DEF
- ; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr0 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr2, $vgpr17 = V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx11 10, $vgpr1, killed $vgpr2, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr12, $vgpr11 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1100-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1100-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx11 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1100-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr10, $vgpr11 = V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr2, $vgpr0, $vgpr3, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr19 = V_CNDMASK_B32_e32 killed $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
; PAIR-GFX1100-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
;
; PAIR-GFX1170-LABEL: name: vopd_schedule_unconstrained
; PAIR-GFX1170: liveins: $vcc_lo
; PAIR-GFX1170-NEXT: {{ $}}
; PAIR-GFX1170-NEXT: $vgpr2 = IMPLICIT_DEF
- ; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr0 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr2, $vgpr17 = V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx1170 10, $vgpr1, killed $vgpr2, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr12, $vgpr11 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1170-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1170-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx1170 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1170-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr10, $vgpr11 = V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx1170 $vgpr1, $vgpr2, $vgpr0, $vgpr3, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr19 = V_CNDMASK_B32_e32 killed $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
; PAIR-GFX1170-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
;
; SCHED-GFX12-LABEL: name: vopd_schedule_unconstrained
@@ -629,32 +648,32 @@ body: |
; SCHED-GFX11: liveins: $vcc_lo
; SCHED-GFX11-NEXT: {{ $}}
; SCHED-GFX11-NEXT: $vgpr2 = IMPLICIT_DEF
- ; SCHED-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
; SCHED-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
; SCHED-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; SCHED-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
; SCHED-GFX11-NEXT: $vgpr20 = IMPLICIT_DEF
- ; SCHED-GFX11-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr17 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr35 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr3 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr6 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr29 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
- ; SCHED-GFX11-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
; SCHED-GFX11-NEXT: $vgpr20 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr20, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
; SCHED-GFX11-NEXT: $vgpr10 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
- ; SCHED-GFX11-NEXT: $vgpr17 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
; SCHED-GFX11-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr37 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr14 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr21 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr24 = V_MUL_F32_e32 killed $vgpr0, $vgpr0, implicit $mode, implicit $exec
- ; SCHED-GFX11-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr24 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; SCHED-GFX11-NEXT: $vgpr29 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; SCHED-GFX11-NEXT: $vgpr37 = V_CNDMASK_B32_e32 killed $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
; SCHED-GFX11-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; SCHED-GFX11-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
; SCHED-GFX11-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
@@ -664,24 +683,25 @@ body: |
; PAIR-GFX1100: liveins: $vcc_lo
; PAIR-GFX1100-NEXT: {{ $}}
; PAIR-GFX1100-NEXT: $vgpr2 = IMPLICIT_DEF
- ; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr0 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr20 = IMPLICIT_DEF
- ; PAIR-GFX1100-NEXT: $vgpr16, $vgpr35 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr2, $vgpr17 = V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx11 10, $vgpr1, killed $vgpr2, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr2, $vgpr35 = V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1100-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx11 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1100-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx11 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx11 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr20, $vgpr15 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11 10, $vgpr1, killed $vgpr20, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr10, $vgpr11 = V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr2, $vgpr0, $vgpr3, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr19, $vgpr28 = V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr0, $vgpr3, $vgpr1, $vgpr2, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr14 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
- ; PAIR-GFX1100-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr29 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1100-NEXT: $vgpr37 = V_CNDMASK_B32_e32 killed $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
; PAIR-GFX1100-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; PAIR-GFX1100-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
; PAIR-GFX1100-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
@@ -691,24 +711,25 @@ body: |
; PAIR-GFX1170: liveins: $vcc_lo
; PAIR-GFX1170-NEXT: {{ $}}
; PAIR-GFX1170-NEXT: $vgpr2 = IMPLICIT_DEF
- ; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr0 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr20 = IMPLICIT_DEF
- ; PAIR-GFX1170-NEXT: $vgpr16, $vgpr35 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr2, $vgpr17 = V_DUAL_FMAC_F32_e32_X_MUL_F32_e32_gfx1170 10, $vgpr1, killed $vgpr2, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr2, $vgpr35 = V_DUAL_ADD_F32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1170-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx1170 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
- ; PAIR-GFX1170-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx1170 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx1170 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr20, $vgpr15 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx1170 10, $vgpr1, killed $vgpr20, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr10, $vgpr11 = V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx1170 $vgpr1, $vgpr2, $vgpr0, $vgpr3, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr19, $vgpr28 = V_DUAL_CNDMASK_B32_e32_X_CNDMASK_B32_e32_gfx1170 $vgpr0, $vgpr3, $vgpr1, $vgpr2, implicit $vcc_lo, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr14 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
- ; PAIR-GFX1170-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx1170 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr29 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
+ ; PAIR-GFX1170-NEXT: $vgpr37 = V_CNDMASK_B32_e32 killed $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo
; PAIR-GFX1170-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; PAIR-GFX1170-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo
; PAIR-GFX1170-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
@@ -921,6 +942,96 @@ body: |
$vgpr3 = V_MOV_B32_e32 $vgpr5, implicit $exec
...
+---
+# GFX11 requires opposite source parity to avoid the destination-buffer
+# forwarding defect. VGPR1 and VGPR3 occupy different VGPR banks but have the
+# same parity, so they may only be paired on GFX12.
+name: vopd_src0_same_parity_different_banks
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; SCHED-LABEL: name: vopd_src0_same_parity_different_banks
+ ; SCHED: $vgpr1 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr2 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+ ; SCHED-NEXT: $vgpr5 = V_ADD_F32_e32 killed $vgpr3, $vgpr3, implicit $mode, implicit $exec
+ ;
+ ; PAIR-GFX1100-LABEL: name: vopd_src0_same_parity_different_banks
+ ; PAIR-GFX1100: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr2 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr5 = V_ADD_F32_e32 killed $vgpr3, $vgpr3, implicit $mode, implicit $exec
+ ;
+ ; PAIR-GFX1170-LABEL: name: vopd_src0_same_parity_different_banks
+ ; PAIR-GFX1170: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr2 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr5 = V_ADD_F32_e32 killed $vgpr3, $vgpr3, implicit $mode, implicit $exec
+ ;
+ ; PAIR-GFX12-LABEL: name: vopd_src0_same_parity_different_banks
+ ; PAIR-GFX12: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr2, $vgpr5 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx12 killed $vgpr1, killed $vgpr3, $vgpr3, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ $vgpr1 = IMPLICIT_DEF
+ $vgpr3 = IMPLICIT_DEF
+ $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec
+ $vgpr5 = V_ADD_F32_e32 $vgpr3, $vgpr3, implicit $mode, implicit $exec
+...
+
+---
+# Exercise the same restriction on SRC1 while SRC0 has opposite parity.
+name: vopd_src1_same_parity_different_banks
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; SCHED-LABEL: name: vopd_src1_same_parity_different_banks
+ ; SCHED: $vgpr2 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr7 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr0 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr5 = IMPLICIT_DEF
+ ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 killed $vgpr0, killed $vgpr3, killed $vgpr2, implicit $mode, implicit $exec
+ ; SCHED-NEXT: $vgpr7 = V_FMAC_F32_e32 killed $vgpr1, killed $vgpr5, killed $vgpr7, implicit $mode, implicit $exec
+ ;
+ ; PAIR-GFX1100-LABEL: name: vopd_src1_same_parity_different_banks
+ ; PAIR-GFX1100: $vgpr2 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr7 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr0 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr5 = IMPLICIT_DEF
+ ; PAIR-GFX1100-NEXT: $vgpr2 = V_FMAC_F32_e32 killed $vgpr0, killed $vgpr3, killed $vgpr2, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr7 = V_FMAC_F32_e32 killed $vgpr1, killed $vgpr5, killed $vgpr7, implicit $mode, implicit $exec
+ ;
+ ; PAIR-GFX1170-LABEL: name: vopd_src1_same_parity_different_banks
+ ; PAIR-GFX1170: $vgpr2 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr7 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr0 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr5 = IMPLICIT_DEF
+ ; PAIR-GFX1170-NEXT: $vgpr2 = V_FMAC_F32_e32 killed $vgpr0, killed $vgpr3, killed $vgpr2, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr7 = V_FMAC_F32_e32 killed $vgpr1, killed $vgpr5, killed $vgpr7, implicit $mode, implicit $exec
+ ;
+ ; PAIR-GFX12-LABEL: name: vopd_src1_same_parity_different_banks
+ ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr7 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr5 = IMPLICIT_DEF
+ ; PAIR-GFX12-NEXT: $vgpr2, $vgpr7 = V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx12 killed $vgpr0, killed $vgpr3, killed $vgpr2, killed $vgpr1, killed $vgpr5, killed $vgpr7, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ $vgpr0 = IMPLICIT_DEF
+ $vgpr1 = IMPLICIT_DEF
+ $vgpr2 = IMPLICIT_DEF
+ $vgpr3 = IMPLICIT_DEF
+ $vgpr5 = IMPLICIT_DEF
+ $vgpr7 = IMPLICIT_DEF
+ $vgpr2 = V_FMAC_F32_e32 $vgpr0, $vgpr3, $vgpr2, implicit $mode, implicit $exec
+ $vgpr7 = V_FMAC_F32_e32 $vgpr1, $vgpr5, $vgpr7, implicit $mode, implicit $exec
+...
+
---
# There is no race between mov and add, they are executed at the same time
name: vopd_combine_opy_overwrites_opx
@@ -936,12 +1047,14 @@ body: |
; PAIR-GFX1100-LABEL: name: vopd_combine_opy_overwrites_opx
; PAIR-GFX1100: $vgpr1 = IMPLICIT_DEF
; PAIR-GFX1100-NEXT: $vgpr3 = IMPLICIT_DEF
- ; PAIR-GFX1100-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx11 killed $vgpr1, killed $vgpr3, $vgpr3, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+ ; PAIR-GFX1100-NEXT: $vgpr1 = V_ADD_F32_e32 killed $vgpr3, $vgpr3, implicit $mode, implicit $exec
;
; PAIR-GFX1170-LABEL: name: vopd_combine_opy_overwrites_opx
; PAIR-GFX1170: $vgpr1 = IMPLICIT_DEF
; PAIR-GFX1170-NEXT: $vgpr3 = IMPLICIT_DEF
- ; PAIR-GFX1170-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx1170 killed $vgpr1, killed $vgpr3, $vgpr3, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+ ; PAIR-GFX1170-NEXT: $vgpr1 = V_ADD_F32_e32 killed $vgpr3, $vgpr3, implicit $mode, implicit $exec
;
; PAIR-GFX12-LABEL: name: vopd_combine_opy_overwrites_opx
; PAIR-GFX12: $vgpr1 = IMPLICIT_DEF
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