[llvm] cecd28d - [RISCV] Select the capability ABI by default when the Y extension is enabled
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Mon Sep 14 20:47:13 PDT 2026
Author: Alexander Richardson
Date: 2026-09-14T20:47:08-07:00
New Revision: cecd28d75cf5407287085e4042ef4fc7ed7feadd
URL: https://github.com/llvm/llvm-project/commit/cecd28d75cf5407287085e4042ef4fc7ed7feadd
DIFF: https://github.com/llvm/llvm-project/commit/cecd28d75cf5407287085e4042ef4fc7ed7feadd.diff
LOG: [RISCV] Select the capability ABI by default when the Y extension is enabled
computeDefaultABI() previously had no knowledge of the RVY (CHERI) base,
so a target with Y enabled and no explicit -target-abi
would fall back to the plain integer ABI instead of il32pc64(d)/
l64pc128(d).
This adds explicit non-RVY ABIs to two tests since otherwise those would
hit the assertion that the ABI is not supported yet. As the ABI does not
matter for these tests, we can safely use the non-RVY ones.
This change was created with the help of AI tools
Reviewed By: lenary
Pull Request: https://github.com/llvm/llvm-project/pull/213411
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index baeba580d9ac1..91c56f1e2b9b5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -63,11 +63,13 @@ Expected<ABI> computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName) {
return createStringError(Twine("'") + ABIName +
"' is not a recognized ABI for this target");
}
- if (ABIName.starts_with("ilp32") && IsRV64) {
+ if (IsRV64 &&
+ (ABIName.starts_with("ilp32") || ABIName.starts_with("il32pc64"))) {
return createStringError(
"32-bit ABIs are not supported for 64-bit targets");
}
- if (ABIName.starts_with("lp64") && !IsRV64) {
+ if (!IsRV64 &&
+ (ABIName.starts_with("lp64") || ABIName.starts_with("l64pc128"))) {
return createStringError(
"64-bit ABIs are not supported for 32-bit targets");
}
@@ -81,6 +83,11 @@ Expected<ABI> computeTargetABI(const MCSubtargetInfo &STI, StringRef ABIName) {
"hard-float 'd' ABI can't be used for a target that doesn't "
"support the D instruction set extension");
}
+ if (!FeatureBits[RISCV::FeatureStdExtY] &&
+ (ABIName.starts_with("il32pc64") || ABIName.starts_with("l64pc128"))) {
+ return createStringError(Twine('\'') + ABIName +
+ "' ABI is only supported for RVY targets");
+ }
if (!IsRV64 && IsRVE && !IsXCheriot && TargetABI != ABI_ILP32E &&
TargetABI != ABI_Unknown) {
return createStringError("only the ilp32e ABI is supported for RV32E");
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 9d4ce85efe187..66ce665d3927a 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -1082,24 +1082,26 @@ RISCVISAInfo::postProcessAndChecking(std::unique_ptr<RISCVISAInfo> &&ISAInfo) {
}
StringRef RISCVISAInfo::computeDefaultABI() const {
+ bool HasY = Exts.count("y") != 0;
if (XLen == 32) {
if (Exts.count("xcheriot"))
return "cheriot";
if (Exts.count("e"))
- return "ilp32e";
+ return HasY ? "il32pc64e" : "ilp32e";
if (Exts.count("d"))
- return "ilp32d";
+ return HasY ? "il32pc64d" : "ilp32d";
if (Exts.count("f"))
- return "ilp32f";
- return "ilp32";
+ return HasY ? "il32pc64f" : "ilp32f";
+ return HasY ? "il32pc64" : "ilp32";
} else if (XLen == 64) {
+ // RV64E has no capability ABI (yet).
if (Exts.count("e"))
return "lp64e";
if (Exts.count("d"))
- return "lp64d";
+ return HasY ? "l64pc128d" : "lp64d";
if (Exts.count("f"))
- return "lp64f";
- return "lp64";
+ return HasY ? "l64pc128f" : "lp64f";
+ return HasY ? "l64pc128" : "lp64";
}
llvm_unreachable("Invalid XLEN");
}
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index c9542a563952c..c9b90f5c70c28 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -342,7 +342,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-y %s -o - | FileCheck --check-prefix=RV64Y %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-y -target-abi lp64 %s -o - | FileCheck --check-prefix=RV64Y %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV64ZIBI %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zilx %s -o - | FileCheck --check-prefix=RV64ZILX %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvqwbdota8i %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVQWBDOTA8I %s
diff --git a/llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir b/llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
index 269ba1f4da870..d5939613b9b65 100644
--- a/llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
+++ b/llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
@@ -1,6 +1,6 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+experimental-y -run-pass machineverifier %s -o - 2>&1 \
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+experimental-y -target-abi ilp32 -run-pass machineverifier %s -o - 2>&1 \
# RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-32 --implicit-check-not="Bad machine code"
-# RUN: not --crash llc -mtriple=riscv64 -mattr=+experimental-y -run-pass machineverifier %s -o - 2>&1 \
+# RUN: not --crash llc -mtriple=riscv64 -mattr=+experimental-y -target-abi lp64 -run-pass machineverifier %s -o - 2>&1 \
# RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-64 --implicit-check-not="Bad machine code"
# CHECK: *** Bad machine code: Invalid immediate ***
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
index 28ead3d5740bf..efd17fc4ecc3b 100644
--- a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
@@ -56,6 +56,27 @@ TEST(ComputeTargetABI, SelectsExpectedABI) {
EXPECT_EQ(computeTargetABI("riscv64", "+f"), RISCVABI::ABI_LP64F);
EXPECT_EQ(computeTargetABI("riscv64", "+f,+d"), RISCVABI::ABI_LP64D);
+ // RVY targets default to the capability ABI.
+ EXPECT_EQ(computeTargetABI("riscv32", "+experimental-y"),
+ RISCVABI::ABI_IL32PC64);
+ EXPECT_EQ(computeTargetABI("riscv32", "+experimental-y,+f"),
+ RISCVABI::ABI_IL32PC64F);
+ EXPECT_EQ(computeTargetABI("riscv32", "+experimental-y,+f,+d"),
+ RISCVABI::ABI_IL32PC64D);
+ EXPECT_EQ(computeTargetABI("riscv64", "+experimental-y"),
+ RISCVABI::ABI_L64PC128);
+ EXPECT_EQ(computeTargetABI("riscv64", "+experimental-y,+f"),
+ RISCVABI::ABI_L64PC128F);
+ EXPECT_EQ(computeTargetABI("riscv64", "+experimental-y,+f,+d"),
+ RISCVABI::ABI_L64PC128D);
+
+ // An explicit ABI overrides the default.
+ EXPECT_EQ(computeTargetABI("riscv32", "+experimental-y", /*ABIName=*/"ilp32"),
+ RISCVABI::ABI_ILP32);
+ EXPECT_EQ(computeTargetABI("riscv64", "+experimental-y,+f,+d",
+ /*ABIName=*/"lp64d"),
+ RISCVABI::ABI_LP64D);
+
// CHERIoT always selects the cheriot ABI by default.
EXPECT_EQ(computeTargetABI("riscv32", "+xcheriot"), RISCVABI::ABI_CHERIOT);
}
@@ -85,6 +106,16 @@ TEST(ComputeTargetABI, ReportsInvalidExplicitABI) {
"only the cheriot ABI is supported for XCheriot");
EXPECT_EQ(computeTargetABIError("riscv64", "+e", "lp64"),
"only the lp64e ABI is supported for RV64E");
+ EXPECT_EQ(
+ computeTargetABIError("riscv32", "+experimental-y,+f,+d", "l64pc128d"),
+ "64-bit ABIs are not supported for 32-bit targets");
+ EXPECT_EQ(
+ computeTargetABIError("riscv64", "+experimental-y,+f,+d", "il32pc64f"),
+ "32-bit ABIs are not supported for 64-bit targets");
+ EXPECT_EQ(computeTargetABIError("riscv32", "", "il32pc64"),
+ "'il32pc64' ABI is only supported for RVY targets");
+ EXPECT_EQ(computeTargetABIError("riscv64", "+f,+d", "l64pc128d"),
+ "'l64pc128d' ABI is only supported for RVY targets");
}
} // namespace
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 25d9a573f0ce7..797b7069ac64c 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1259,6 +1259,19 @@ TEST(ComputeDefaultABI, SelectsExpectedABI) {
EXPECT_EQ(GetABIFromFeatures(64, {"+f", "+d"}), "lp64d");
EXPECT_EQ(GetABIFromFeatures(64, {"+e"}), "lp64e");
+ // RVY targets default to the capability ABI.
+ EXPECT_EQ(GetABIFromFeatures(32, {"+experimental-y"}), "il32pc64");
+ EXPECT_EQ(GetABIFromFeatures(32, {"+experimental-y", "+f"}), "il32pc64f");
+ EXPECT_EQ(GetABIFromFeatures(32, {"+experimental-y", "+f", "+d"}),
+ "il32pc64d");
+ EXPECT_EQ(GetABIFromFeatures(32, {"+experimental-y", "+e"}), "il32pc64e");
+ EXPECT_EQ(GetABIFromFeatures(64, {"+experimental-y"}), "l64pc128");
+ EXPECT_EQ(GetABIFromFeatures(64, {"+experimental-y", "+f"}), "l64pc128f");
+ EXPECT_EQ(GetABIFromFeatures(64, {"+experimental-y", "+f", "+d"}),
+ "l64pc128d");
+ // RV64E has no capability ABI (yet).
+ EXPECT_EQ(GetABIFromFeatures(64, {"+experimental-y", "+e"}), "lp64e");
+
// CHERIoT always selects the cheriot ABI by default.
EXPECT_EQ(GetABIFromFeatures(32, {"+xcheriot"}), "cheriot");
}
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