[llvm] [DAGCombiner] Narrow the integer source of uint_to_fp (PR #222899)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 20:01:01 PDT 2026
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/222899
>From 401452ffc2b29104685e3a972da417aa04901d18 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Fri, 11 Sep 2026 16:57:08 +0800
Subject: [PATCH 1/5] [AMDGPU] Optimize i64 uitofp for unsigned byte values
Use v_cvt_f32_ubyte0 when the i64 source is known to fit in an unsigned
byte.
For example:
uitofp (and i64 %x, 255) to float
This avoids the generic i64 to f32 expansion.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 18 ++
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 +
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 305 ++++++++++++++++++
3 files changed, 324 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index aa5cfe38b50fc..1894df489c6bf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3689,6 +3689,8 @@ SDValue AMDGPUTargetLowering::lowerINT_TO_FPImpl(SDValue Op, SelectionDAG &DAG,
SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
+ if (SDValue Result = lowerUCharToF32(Op, DAG))
+ return Result;
return lowerINT_TO_FPImpl(Op, DAG, false);
}
@@ -3697,6 +3699,22 @@ SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
return lowerINT_TO_FPImpl(Op, DAG, true);
}
+SDValue AMDGPUTargetLowering::lowerUCharToF32(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDValue Src = Op.getOperand(0);
+
+ if (Op.getValueType() != MVT::f32 || Src.getValueType() != MVT::i64)
+ return SDValue();
+
+ APInt HighBits = APInt::getHighBitsSet(64, 56);
+ if (!DAG.MaskedValueIsZero(Src, HighBits))
+ return SDValue();
+
+ SDLoc DL(Op);
+ SDValue Src32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Src);
+ return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, MVT::f32, Src32);
+}
+
SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,
bool Signed) const {
SDLoc SL(Op);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index a7696d89515c4..9d785ac57c2ad 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -99,6 +99,7 @@ class AMDGPUTargetLowering : public TargetLowering {
SDValue lowerINT_TO_FPImpl(SDValue Op, SelectionDAG &DAG, bool Signed) const;
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerUCharToF32(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index abeb42213466b..5ba83f54dc7f9 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -912,6 +912,311 @@ define double @v_uitofp_i8_to_f64(i8 %arg0) nounwind {
ret double %cvt
}
+define float @v_uitofp_i64_to_f32_mask255(i64 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_i64_to_f32_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_i64_to_f32_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_i64_to_f32_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_i64_to_f32_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %masked = and i64 %arg0, 255
+ %cvt = uitofp i64 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_i64_to_f32_lshr8_mask255(i64 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_i64_to_f32_lshr8_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_i64_to_f32_lshr8_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_i64_to_f32_lshr8_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_i64_to_f32_lshr8_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %lshr.8 = lshr i64 %arg0, 8
+ %masked = and i64 %lshr.8, 255
+ %cvt = uitofp i64 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_i64_to_f32_lshr16_mask255(i64 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_i64_to_f32_lshr16_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_i64_to_f32_lshr16_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_i64_to_f32_lshr16_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_i64_to_f32_lshr16_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr i64 %arg0, 16
+ %masked = and i64 %lshr.16, 255
+ %cvt = uitofp i64 %masked to float
+ ret float %cvt
+}
+
+define float @v_uitofp_i64_to_f32_lshr24_mask255(i64 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_i64_to_f32_lshr24_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_i64_to_f32_lshr24_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_i64_to_f32_lshr24_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_i64_to_f32_lshr24_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %lshr.24 = lshr i64 %arg0, 24
+ %masked = and i64 %lshr.24, 255
+ %cvt = uitofp i64 %masked to float
+ ret float %cvt
+}
+
+define <3 x float> @v_uitofp_unpack_i64_to_v3f32(i64 %arg0) nounwind {
+; GCN-LABEL: v_uitofp_unpack_i64_to_v3f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v3, v0
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
+; GCN-NEXT: v_mov_b32_e32 v0, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_unpack_i64_to_v3f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, v0
+; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, v3
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_unpack_i64_to_v3f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, v0
+; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GFX9-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_unpack_i64_to_v3f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, v0
+; GFX11-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GFX11-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %mask.byte0 = and i64 %arg0, 255
+ %cvt.byte0 = uitofp i64 %mask.byte0 to float
+ %lshr.byte1 = lshr i64 %arg0, 8
+ %mask.byte1 = and i64 %lshr.byte1, 255
+ %cvt.byte1 = uitofp i64 %mask.byte1 to float
+ %lshr.byte2 = lshr i64 %arg0, 16
+ %mask.byte2 = and i64 %lshr.byte2, 255
+ %cvt.byte2 = uitofp i64 %mask.byte2 to float
+ %insert.byte0 = insertelement <3 x float> poison, float %cvt.byte0, i32 0
+ %insert.byte1 = insertelement <3 x float> %insert.byte0, float %cvt.byte1, i32 1
+ %insert.byte2 = insertelement <3 x float> %insert.byte1, float %cvt.byte2, i32 2
+ ret <3 x float> %insert.byte2
+}
+
+define <2 x float> @v_uitofp_v2i64_to_v2f32_mask255(<2 x i64> %arg0) nounwind {
+; GCN-LABEL: v_uitofp_v2i64_to_v2f32_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_v2i64_to_v2f32_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_v2i64_to_v2f32_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_v2i64_to_v2f32_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %masked = and <2 x i64> %arg0, <i64 255, i64 255>
+ %cvt = uitofp <2 x i64> %masked to <2 x float>
+ ret <2 x float> %cvt
+}
+
+define <2 x float> @v_uitofp_v2i64_to_v2f32_lshr8_mask255(<2 x i64> %arg0) nounwind {
+; GCN-LABEL: v_uitofp_v2i64_to_v2f32_lshr8_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GCN-NEXT: v_cvt_f32_ubyte1_e32 v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_v2i64_to_v2f32_lshr8_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_v2i64_to_v2f32_lshr8_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_v2i64_to_v2f32_lshr8_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte1_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_ubyte1_e32 v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %lshr.8 = lshr <2 x i64> %arg0, <i64 8, i64 8>
+ %masked = and <2 x i64> %lshr.8, <i64 255, i64 255>
+ %cvt = uitofp <2 x i64> %masked to <2 x float>
+ ret <2 x float> %cvt
+}
+
+define <2 x float> @v_uitofp_v2i64_to_v2f32_lshr16_mask255(<2 x i64> %arg0) nounwind {
+; GCN-LABEL: v_uitofp_v2i64_to_v2f32_lshr16_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GCN-NEXT: v_cvt_f32_ubyte2_e32 v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_v2i64_to_v2f32_lshr16_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_v2i64_to_v2f32_lshr16_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_ubyte2_e32 v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_v2i64_to_v2f32_lshr16_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte2_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_ubyte2_e32 v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %lshr.16 = lshr <2 x i64> %arg0, <i64 16, i64 16>
+ %masked = and <2 x i64> %lshr.16, <i64 255, i64 255>
+ %cvt = uitofp <2 x i64> %masked to <2 x float>
+ ret <2 x float> %cvt
+}
+
+define <2 x float> @v_uitofp_v2i64_to_v2f32_lshr24_mask255(<2 x i64> %arg0) nounwind {
+; GCN-LABEL: v_uitofp_v2i64_to_v2f32_lshr24_mask255:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GCN-NEXT: v_cvt_f32_ubyte3_e32 v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_uitofp_v2i64_to_v2f32_lshr24_mask255:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_uitofp_v2i64_to_v2f32_lshr24_mask255:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_ubyte3_e32 v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uitofp_v2i64_to_v2f32_lshr24_mask255:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte3_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_ubyte3_e32 v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %lshr.24 = lshr <2 x i64> %arg0, <i64 24, i64 24>
+ %masked = and <2 x i64> %lshr.24, <i64 255, i64 255>
+ %cvt = uitofp <2 x i64> %masked to <2 x float>
+ ret <2 x float> %cvt
+}
+
define amdgpu_kernel void @load_i8_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
; SI-LABEL: load_i8_to_f32:
; SI: ; %bb.0:
>From 3e8503a6f8551c9da7177fd8b63ff4fe103a756d Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 15 Sep 2026 01:01:11 +0800
Subject: [PATCH 2/5] [DAGCombiner] Fold (uint_to_fp x) -> (uint_to_fp (trunc
x))
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 22 +++++++++++++++
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 18 ------------
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 -
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 20 ++++++-------
.../AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll | 28 +------------------
.../X86/fold-int-pow2-with-fmul-or-fdiv.ll | 8 +++---
6 files changed, 36 insertions(+), 61 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a829d7a34d5a6..66ac8dc7e1576 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20641,6 +20641,28 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
if (SDValue FTrunc = foldFPToIntToFP(N, DL, DAG, TLI))
return FTrunc;
+ // fold (uint_to_fp x) -> (uint_to_fp (trunc x)) when the value of x is known
+ // to fit in a narrower type the target can convert from directly.
+ LLVMContext &Ctx = *DAG.getContext();
+ unsigned ScalarBits = OpVT.getScalarType().getSizeInBits();
+ unsigned ActiveBits = DAG.computeKnownBits(N0).countMaxActiveBits();
+ // Narrowing to i1 turns the conversion into a select, which is not a win.
+ for (unsigned Bits = bit_ceil(std::max(2u, ActiveBits)); Bits < ScalarBits;
+ Bits *= 2) {
+ EVT NarrowVT = OpVT.changeElementType(Ctx, EVT::getIntegerVT(Ctx, Bits));
+
+ // Vector int-to-fp is unrolled to scalars, but the truncate is not.
+ if (!hasOperation(ISD::UINT_TO_FP, NarrowVT.getScalarType()) ||
+ !TLI.isTruncateFree(OpVT, NarrowVT))
+ continue;
+
+ if (LegalTypes && !TLI.isTypeLegal(NarrowVT))
+ continue;
+
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, NarrowVT, N0);
+ return DAG.getNode(ISD::UINT_TO_FP, DL, VT, Trunc);
+ }
+
// fold (uint_to_fp (trunc nuw x)) -> (uint_to_fp x)
if (N0.getOpcode() == ISD::TRUNCATE && N0->getFlags().hasNoUnsignedWrap() &&
TLI.isTypeDesirableForOp(ISD::UINT_TO_FP,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 1894df489c6bf..aa5cfe38b50fc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3689,8 +3689,6 @@ SDValue AMDGPUTargetLowering::lowerINT_TO_FPImpl(SDValue Op, SelectionDAG &DAG,
SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
- if (SDValue Result = lowerUCharToF32(Op, DAG))
- return Result;
return lowerINT_TO_FPImpl(Op, DAG, false);
}
@@ -3699,22 +3697,6 @@ SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
return lowerINT_TO_FPImpl(Op, DAG, true);
}
-SDValue AMDGPUTargetLowering::lowerUCharToF32(SDValue Op,
- SelectionDAG &DAG) const {
- SDValue Src = Op.getOperand(0);
-
- if (Op.getValueType() != MVT::f32 || Src.getValueType() != MVT::i64)
- return SDValue();
-
- APInt HighBits = APInt::getHighBitsSet(64, 56);
- if (!DAG.MaskedValueIsZero(Src, HighBits))
- return SDValue();
-
- SDLoc DL(Op);
- SDValue Src32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Src);
- return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, MVT::f32, Src32);
-}
-
SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,
bool Signed) const {
SDLoc SL(Op);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 9d785ac57c2ad..a7696d89515c4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -99,7 +99,6 @@ class AMDGPUTargetLowering : public TargetLowering {
SDValue lowerINT_TO_FPImpl(SDValue Op, SelectionDAG &DAG, bool Signed) const;
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerUCharToF32(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 5ba83f54dc7f9..2f3c126af99c4 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -2700,26 +2700,24 @@ define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(ptr addrspace(1) noalias %ou
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, 2, v0
+; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v0
+; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v0
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; VI-NEXT: flat_load_ubyte v2, v[2:3]
-; VI-NEXT: flat_load_ubyte v3, v[4:5]
-; VI-NEXT: flat_load_ubyte v4, v[0:1]
-; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v0
+; VI-NEXT: flat_load_ubyte v4, v[4:5]
+; VI-NEXT: flat_load_ubyte v3, v[0:1]
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_ubyte v1, v[0:1]
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v3, v3
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v3
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v3, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v1
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v4
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
index 8ddab5583b9ee..7f3f2fe89f511 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -549,16 +549,8 @@ define float @fmul_fly_pow_mul_min_pow2(i64 %cnt) nounwind {
; VI-NEXT: s_mov_b64 s[4:5], 0x2000
; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
; VI-NEXT: v_mov_b32_e32 v2, 0x2000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-NEXT: v_ffbh_u32_e32 v2, v1
-; VI-NEXT: v_min_u32_e32 v2, 32, v2
-; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
-; VI-NEXT: v_min_u32_e32 v0, 1, v0
-; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_cvt_f32_u32_e32 v0, v0
-; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v2
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
; VI-NEXT: v_mul_f32_e32 v0, 0x41100000, v0
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -567,16 +559,8 @@ define float @fmul_fly_pow_mul_min_pow2(i64 %cnt) nounwind {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v0, 8
; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, 0x2000, v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x2000, v0, vcc_lo
-; GFX10-NEXT: v_ffbh_u32_e32 v2, v1
-; GFX10-NEXT: v_min_u32_e32 v2, 32, v2
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
-; GFX10-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, 32, v2
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x41100000, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -586,18 +570,8 @@ define float @fmul_fly_pow_mul_min_pow2(i64 %cnt) nounwind {
; GFX11-NEXT: v_lshlrev_b64 v[0:1], v0, 8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, 0x2000, v[0:1]
-; GFX11-NEXT: v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0x2000, v0
-; GFX11-NEXT: v_clz_i32_u32_e32 v2, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_min_u32_e32 v2, 32, v2
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_sub_nc_u32_e32 v1, 32, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x2000, v0, vcc_lo
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x41100000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
index f74ada85f177e..534a295d75bb5 100644
--- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -1804,8 +1804,8 @@ define double @fmul_pow_shl_cnt_fail_knownbits_bad_exp(i64 %cnt) nounwind {
; CHECK-SKX: # %bb.0:
; CHECK-SKX-NEXT: andb $15, %dil
; CHECK-SKX-NEXT: movl $1, %eax
-; CHECK-SKX-NEXT: shlxq %rdi, %rax, %rax
-; CHECK-SKX-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; CHECK-SKX-NEXT: shlxl %edi, %eax, %eax
+; CHECK-SKX-NEXT: vcvtsi2sd %eax, %xmm15, %xmm0
; CHECK-SKX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-SKX-NEXT: retq
%cnt_masked = and i64 %cnt, 15
@@ -1857,8 +1857,8 @@ define double @fdiv_pow_shl_cnt_fail_knownbits_bad_exp(i64 %cnt) nounwind {
; CHECK-SKX: # %bb.0:
; CHECK-SKX-NEXT: andb $15, %dil
; CHECK-SKX-NEXT: movl $1, %eax
-; CHECK-SKX-NEXT: shlxq %rdi, %rax, %rax
-; CHECK-SKX-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; CHECK-SKX-NEXT: shlxl %edi, %eax, %eax
+; CHECK-SKX-NEXT: vcvtsi2sd %eax, %xmm15, %xmm0
; CHECK-SKX-NEXT: vmovsd {{.*#+}} xmm1 = [5.4683415146672981E-304,0.0E+0]
; CHECK-SKX-NEXT: vdivsd %xmm0, %xmm1, %xmm0
; CHECK-SKX-NEXT: retq
>From 9a7179ec4b7bd45f1a63f944ecaff067dccff255 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 15 Sep 2026 01:46:30 +0800
Subject: [PATCH 3/5] Fix lit test
---
llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
index 118c627f1041b..fa8a7e030e348 100644
--- a/llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -209,7 +209,7 @@ define float @fmul_fly_pow_mul_min_pow2(i64 %cnt) nounwind {
; CHECK-NEXT: lsl x8, x8, x0
; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
; CHECK-NEXT: csel x8, x8, x9, lo
-; CHECK-NEXT: ucvtf s0, x8
+; CHECK-NEXT: ucvtf s0, w8
; CHECK-NEXT: fmul s0, s0, s1
; CHECK-NEXT: ret
%shl8 = shl nuw i64 8, %cnt
>From 34f4421660c770641a45e2b4bd7732b159a4c4a8 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 15 Sep 2026 02:32:45 +0800
Subject: [PATCH 4/5] Update
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 66ac8dc7e1576..8d92ed3e25b89 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20644,7 +20644,7 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
// fold (uint_to_fp x) -> (uint_to_fp (trunc x)) when the value of x is known
// to fit in a narrower type the target can convert from directly.
LLVMContext &Ctx = *DAG.getContext();
- unsigned ScalarBits = OpVT.getScalarType().getSizeInBits();
+ unsigned ScalarBits = OpVT.getScalarSizeInBits();
unsigned ActiveBits = DAG.computeKnownBits(N0).countMaxActiveBits();
// Narrowing to i1 turns the conversion into a select, which is not a win.
for (unsigned Bits = bit_ceil(std::max(2u, ActiveBits)); Bits < ScalarBits;
>From 047ea07767c3207a753847dd0884c69f9c7697f7 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 15 Sep 2026 11:00:32 +0800
Subject: [PATCH 5/5] Fix lit test failure
---
.../CodeGen/AMDGPU/int_to_fp_narrow_i64.ll | 907 ++++--------------
1 file changed, 203 insertions(+), 704 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll b/llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
index 97959296858c4..e4c131a292384 100644
--- a/llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
@@ -2035,62 +2035,37 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f16(ptr addrspace(1) %ou
; GFX6-LABEL: s_uint_to_fp_63_zero_bits_to_f16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_flbit_i32_b32 s2, 0
-; GFX6-NEXT: s_mov_b32 s5, 0
-; GFX6-NEXT: s_min_u32 s6, s2, 32
-; GFX6-NEXT: s_lshr_b32 s4, s3, 31
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX6-NEXT: s_min_u32 s2, s2, 1
-; GFX6-NEXT: s_or_b32 s2, s3, s2
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_sub_i32 s2, 32, s6
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s2
+; GFX6-NEXT: s_lshr_b32 s2, s3, 31
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, s2
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: s_uint_to_fp_63_zero_bits_to_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_flbit_i32_b32 s2, 0
-; GFX8-NEXT: s_mov_b32 s5, 0
-; GFX8-NEXT: s_min_u32 s6, s2, 32
-; GFX8-NEXT: s_lshr_b32 s4, s3, 31
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX8-NEXT: s_min_u32 s2, s2, 1
-; GFX8-NEXT: s_or_b32 s2, s3, s2
-; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX8-NEXT: s_sub_i32 s2, 32, s6
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX8-NEXT: s_lshr_b32 s2, s3, 31
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, s2
; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: s_uint_to_fp_63_zero_bits_to_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-TRUE16-NEXT: s_mov_b32 s5, 0
-; GFX11-TRUE16-NEXT: s_min_u32 s6, s2, 32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s3, 31
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX11-TRUE16-NEXT: s_min_u32 s2, s2, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-TRUE16-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-TRUE16-NEXT: s_sub_i32 s2, 32, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s3, 31
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v0, s2
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -2098,22 +2073,11 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f16(ptr addrspace(1) %ou
; GFX11-FAKE16-LABEL: s_uint_to_fp_63_zero_bits_to_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-FAKE16-NEXT: s_mov_b32 s5, 0
-; GFX11-FAKE16-NEXT: s_min_u32 s6, s2, 32
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s3, 31
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX11-FAKE16-NEXT: s_min_u32 s2, s2, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-FAKE16-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-FAKE16-NEXT: s_sub_i32 s2, 32, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s3, 31
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, s2
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -2122,19 +2086,11 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f16(ptr addrspace(1) %ou
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: s_flbit_i32_b32 s2, 0
-; GFX701-NEXT: s_mov_b32 s5, 0
-; GFX701-NEXT: s_min_u32 s6, s2, 32
-; GFX701-NEXT: s_lshr_b32 s4, s3, 31
-; GFX701-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX701-NEXT: s_min_u32 s2, s2, 1
-; GFX701-NEXT: s_or_b32 s2, s3, s2
-; GFX701-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX701-NEXT: s_sub_i32 s2, 32, s6
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX701-NEXT: v_ldexp_f32_e64 v0, v0, s2
+; GFX701-NEXT: s_waitcnt lgkmcnt(0)
+; GFX701-NEXT: s_lshr_b32 s2, s3, 31
+; GFX701-NEXT: v_cvt_f32_ubyte0_e32 v0, s2
; GFX701-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX701-NEXT: v_mov_b32_e32 v0, s0
; GFX701-NEXT: v_mov_b32_e32 v1, s1
@@ -2145,19 +2101,11 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f16(ptr addrspace(1) %ou
; GFX803: ; %bb.0:
; GFX803-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_flbit_i32_b32 s2, 0
-; GFX803-NEXT: s_mov_b32 s5, 0
-; GFX803-NEXT: s_min_u32 s6, s2, 32
-; GFX803-NEXT: s_lshr_b32 s4, s3, 31
-; GFX803-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX803-NEXT: s_min_u32 s2, s2, 1
-; GFX803-NEXT: s_or_b32 s2, s3, s2
-; GFX803-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX803-NEXT: s_sub_i32 s2, 32, s6
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX803-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: s_lshr_b32 s2, s3, 31
+; GFX803-NEXT: v_cvt_f32_ubyte0_e32 v0, s2
; GFX803-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX803-NEXT: v_mov_b32_e32 v0, s0
; GFX803-NEXT: v_mov_b32_e32 v1, s1
@@ -2167,18 +2115,10 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f16(ptr addrspace(1) %ou
; GFX942-LABEL: s_uint_to_fp_63_zero_bits_to_f16:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_flbit_i32_b32 s2, 0
-; GFX942-NEXT: s_mov_b32 s5, 0
-; GFX942-NEXT: s_min_u32 s6, s2, 32
; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: s_lshr_b32 s4, s3, 31
-; GFX942-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX942-NEXT: s_min_u32 s2, s2, 1
-; GFX942-NEXT: s_or_b32 s2, s3, s2
-; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX942-NEXT: s_sub_i32 s2, 32, s6
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX942-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-NEXT: s_lshr_b32 s2, s3, 31
+; GFX942-NEXT: v_cvt_f32_ubyte0_e32 v0, s2
; GFX942-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX942-NEXT: global_store_short v1, v0, s[0:1]
; GFX942-NEXT: s_endpgm
@@ -2192,21 +2132,13 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f32(ptr addrspace(1) %ou
; GFX6-LABEL: s_uint_to_fp_63_zero_bits_to_f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_flbit_i32_b32 s2, 0
-; GFX6-NEXT: s_mov_b32 s5, 0
-; GFX6-NEXT: s_min_u32 s8, s2, 32
; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: s_lshr_b32 s4, s3, 31
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[4:5], s8
-; GFX6-NEXT: s_min_u32 s2, s2, 1
-; GFX6-NEXT: s_or_b32 s2, s3, s2
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_mov_b32 s4, s0
-; GFX6-NEXT: s_sub_i32 s0, 32, s8
; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_lshr_b32 s0, s3, 31
; GFX6-NEXT: s_mov_b32 s5, s1
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s0
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, s0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
@@ -2214,61 +2146,35 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f32(ptr addrspace(1) %ou
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_flbit_i32_b32 s2, 0
-; GFX8-NEXT: s_mov_b32 s5, 0
-; GFX8-NEXT: s_min_u32 s6, s2, 32
-; GFX8-NEXT: s_lshr_b32 s4, s3, 31
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX8-NEXT: s_min_u32 s2, s2, 1
-; GFX8-NEXT: s_or_b32 s2, s3, s2
-; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_sub_i32 s0, 32, s6
+; GFX8-NEXT: s_lshr_b32 s0, s3, 31
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_ldexp_f32 v2, v2, s0
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX11-LABEL: s_uint_to_fp_63_zero_bits_to_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-NEXT: s_mov_b32 s5, 0
-; GFX11-NEXT: s_min_u32 s6, s2, 32
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: s_lshr_b32 s4, s3, 31
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX11-NEXT: s_min_u32 s2, s2, 1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s2, s3, s2
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s2, 32, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_lshr_b32 s2, s3, 31
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
;
; GFX701-LABEL: s_uint_to_fp_63_zero_bits_to_f32:
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: s_flbit_i32_b32 s2, 0
-; GFX701-NEXT: s_mov_b32 s5, 0
-; GFX701-NEXT: s_min_u32 s6, s2, 32
-; GFX701-NEXT: s_lshr_b32 s4, s3, 31
-; GFX701-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX701-NEXT: s_min_u32 s2, s2, 1
-; GFX701-NEXT: s_or_b32 s2, s3, s2
-; GFX701-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX701-NEXT: v_mov_b32_e32 v0, s0
-; GFX701-NEXT: s_sub_i32 s0, 32, s6
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX701-NEXT: s_waitcnt lgkmcnt(0)
+; GFX701-NEXT: v_mov_b32_e32 v0, s0
+; GFX701-NEXT: s_lshr_b32 s0, s3, 31
; GFX701-NEXT: v_mov_b32_e32 v1, s1
-; GFX701-NEXT: v_ldexp_f32_e64 v2, v2, s0
+; GFX701-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
; GFX701-NEXT: flat_store_dword v[0:1], v2
; GFX701-NEXT: s_endpgm
;
@@ -2276,40 +2182,24 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f32(ptr addrspace(1) %ou
; GFX803: ; %bb.0:
; GFX803-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_flbit_i32_b32 s2, 0
-; GFX803-NEXT: s_mov_b32 s5, 0
-; GFX803-NEXT: s_min_u32 s6, s2, 32
-; GFX803-NEXT: s_lshr_b32 s4, s3, 31
-; GFX803-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX803-NEXT: s_min_u32 s2, s2, 1
-; GFX803-NEXT: s_or_b32 s2, s3, s2
-; GFX803-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX803-NEXT: v_mov_b32_e32 v0, s0
-; GFX803-NEXT: s_sub_i32 s0, 32, s6
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_mov_b32_e32 v0, s0
+; GFX803-NEXT: s_lshr_b32 s0, s3, 31
; GFX803-NEXT: v_mov_b32_e32 v1, s1
-; GFX803-NEXT: v_ldexp_f32 v2, v2, s0
+; GFX803-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
; GFX803-NEXT: flat_store_dword v[0:1], v2
; GFX803-NEXT: s_endpgm
;
; GFX942-LABEL: s_uint_to_fp_63_zero_bits_to_f32:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_flbit_i32_b32 s2, 0
-; GFX942-NEXT: s_mov_b32 s5, 0
-; GFX942-NEXT: s_min_u32 s6, s2, 32
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: s_lshr_b32 s4, s3, 31
-; GFX942-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX942-NEXT: s_min_u32 s2, s2, 1
-; GFX942-NEXT: s_or_b32 s2, s3, s2
-; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX942-NEXT: s_sub_i32 s2, 32, s6
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX942-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX942-NEXT: s_lshr_b32 s2, s3, 31
+; GFX942-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX942-NEXT: global_store_dword v0, v1, s[0:1]
; GFX942-NEXT: s_endpgm
%narrow = lshr i64 %in, 63
%result = uitofp i64 %narrow to float
@@ -2321,7 +2211,6 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f64(ptr addrspace(1) %ou
; GFX6-LABEL: s_uint_to_fp_63_zero_bits_to_f64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GFX6-NEXT: v_ldexp_f64 v[2:3], 0, 32
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
@@ -2329,18 +2218,15 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f64(ptr addrspace(1) %ou
; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s5, s1
-; GFX6-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: s_uint_to_fp_63_zero_bits_to_f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX8-NEXT: v_ldexp_f64 v[0:1], 0, 32
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_lshr_b32 s2, s3, 31
-; GFX8-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX8-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2349,13 +2235,11 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f64(ptr addrspace(1) %ou
; GFX11-LABEL: s_uint_to_fp_63_zero_bits_to_f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_ldexp_f64 v[0:1], 0, 32
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_lshr_b32 s2, s3, 31
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -2363,29 +2247,25 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f64(ptr addrspace(1) %ou
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: v_ldexp_f64 v[2:3], 0, 32
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX701-NEXT: s_waitcnt lgkmcnt(0)
; GFX701-NEXT: s_lshr_b32 s2, s3, 31
; GFX701-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
-; GFX701-NEXT: v_mov_b32_e32 v4, s0
-; GFX701-NEXT: v_mov_b32_e32 v5, s1
-; GFX701-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
-; GFX701-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
+; GFX701-NEXT: v_mov_b32_e32 v2, s0
+; GFX701-NEXT: v_mov_b32_e32 v3, s1
+; GFX701-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX701-NEXT: s_endpgm
;
; GFX803-LABEL: s_uint_to_fp_63_zero_bits_to_f64:
; GFX803: ; %bb.0:
; GFX803-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
-; GFX803-NEXT: v_ldexp_f64 v[0:1], 0, 32
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: s_lshr_b32 s2, s3, 31
-; GFX803-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX803-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX803-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX803-NEXT: v_mov_b32_e32 v2, s0
; GFX803-NEXT: v_mov_b32_e32 v3, s1
; GFX803-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2394,13 +2274,11 @@ define amdgpu_kernel void @s_uint_to_fp_63_zero_bits_to_f64(ptr addrspace(1) %ou
; GFX942-LABEL: s_uint_to_fp_63_zero_bits_to_f64:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX942-NEXT: v_ldexp_f64 v[0:1], 0, 32
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_lshr_b32 s2, s3, 31
-; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_endpgm
%narrow = lshr i64 %in, 63
%result = uitofp i64 %narrow to double
@@ -2412,21 +2290,13 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f16(ptr addrspace(1) %out, i
; GFX6-LABEL: s_uint_to_fp_zext_i16_to_f16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb
-; GFX6-NEXT: s_flbit_i32_b32 s2, 0
-; GFX6-NEXT: s_mov_b32 s1, 0
-; GFX6-NEXT: s_min_u32 s2, s2, 32
; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX6-NEXT: s_min_u32 s0, s0, 1
-; GFX6-NEXT: s_or_b32 s0, s1, s0
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX6-NEXT: s_sub_i32 s2, 32, s2
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s2
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
@@ -2434,18 +2304,10 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f16(ptr addrspace(1) %out, i
; GFX8-LABEL: s_uint_to_fp_zext_i16_to_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX8-NEXT: s_flbit_i32_b32 s2, 0
-; GFX8-NEXT: s_mov_b32 s1, 0
-; GFX8-NEXT: s_min_u32 s2, s2, 32
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX8-NEXT: s_min_u32 s0, s0, 1
-; GFX8-NEXT: s_or_b32 s0, s1, s0
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8-NEXT: s_sub_i32 s2, 32, s2
-; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
@@ -2455,71 +2317,43 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f16(ptr addrspace(1) %out, i
;
; GFX11-TRUE16-LABEL: s_uint_to_fp_zext_i16_to_f16:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0
-; GFX11-TRUE16-NEXT: s_min_u32 s6, s2, 32
-; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_lshl_b64 s[0:1], s[0:1], s6
-; GFX11-TRUE16-NEXT: s_min_u32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX11-TRUE16-NEXT: s_sub_i32 s0, 32, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v0, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: s_uint_to_fp_zext_i16_to_f16:
; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0
-; GFX11-FAKE16-NEXT: s_min_u32 s6, s2, 32
-; GFX11-FAKE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_lshl_b64 s[0:1], s[0:1], s6
-; GFX11-FAKE16-NEXT: s_min_u32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX11-FAKE16-NEXT: s_sub_i32 s0, 32, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v0, v0, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX701-LABEL: s_uint_to_fp_zext_i16_to_f16:
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dword s0, s[8:9], 0x2
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_flbit_i32_b32 s2, 0
-; GFX701-NEXT: s_mov_b32 s1, 0
-; GFX701-NEXT: s_min_u32 s2, s2, 32
+; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX701-NEXT: s_waitcnt lgkmcnt(0)
; GFX701-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX701-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX701-NEXT: s_min_u32 s0, s0, 1
-; GFX701-NEXT: s_or_b32 s0, s1, s0
; GFX701-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX701-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX701-NEXT: s_sub_i32 s2, 32, s2
-; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GFX701-NEXT: v_ldexp_f32_e64 v0, v0, s2
; GFX701-NEXT: v_cvt_f16_f32_e32 v2, v0
-; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX701-NEXT: s_waitcnt lgkmcnt(0)
; GFX701-NEXT: v_mov_b32_e32 v0, s0
; GFX701-NEXT: v_mov_b32_e32 v1, s1
@@ -2530,21 +2364,13 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f16(ptr addrspace(1) %out, i
; GFX803: ; %bb.0:
; GFX803-NEXT: s_load_dword s0, s[8:9], 0x8
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_flbit_i32_b32 s2, 0
-; GFX803-NEXT: s_mov_b32 s1, 0
-; GFX803-NEXT: s_min_u32 s2, s2, 32
+; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX803-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX803-NEXT: s_min_u32 s0, s0, 1
-; GFX803-NEXT: s_or_b32 s0, s1, s0
; GFX803-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX803-NEXT: s_sub_i32 s2, 32, s2
-; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GFX803-NEXT: v_ldexp_f32 v0, v0, s2
; GFX803-NEXT: v_cvt_f16_f32_e32 v2, v0
-; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v0, s0
; GFX803-NEXT: v_mov_b32_e32 v1, s1
@@ -2554,19 +2380,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f16(ptr addrspace(1) %out, i
; GFX942-LABEL: s_uint_to_fp_zext_i16_to_f16:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s0, s[4:5], 0x8
-; GFX942-NEXT: s_flbit_i32_b32 s2, 0
-; GFX942-NEXT: s_mov_b32 s1, 0
-; GFX942-NEXT: s_min_u32 s2, s2, 32
; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX942-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX942-NEXT: s_min_u32 s0, s0, 1
-; GFX942-NEXT: s_or_b32 s0, s1, s0
; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX942-NEXT: s_sub_i32 s2, 32, s2
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s2
; GFX942-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_store_short v1, v0, s[0:1]
@@ -2582,19 +2400,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f32(ptr addrspace(1) %out, i
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s2, s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: s_flbit_i32_b32 s4, 0
-; GFX6-NEXT: s_mov_b32 s3, 0
-; GFX6-NEXT: s_min_u32 s4, s4, 32
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX6-NEXT: s_min_u32 s2, s2, 1
-; GFX6-NEXT: s_or_b32 s2, s3, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_sub_i32 s4, 32, s4
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s4
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
@@ -2602,19 +2412,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f32(ptr addrspace(1) %out, i
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8-NEXT: s_flbit_i32_b32 s4, 0
-; GFX8-NEXT: s_mov_b32 s3, 0
-; GFX8-NEXT: s_min_u32 s4, s4, 32
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX8-NEXT: s_min_u32 s2, s2, 1
-; GFX8-NEXT: s_or_b32 s2, s3, s2
-; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX8-NEXT: s_sub_i32 s2, 32, s4
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_ldexp_f32 v2, v0, s2
+; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -2623,22 +2425,12 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f32(ptr addrspace(1) %out, i
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_clz_i32_u32 s4, 0
-; GFX11-NEXT: s_mov_b32 s3, 0
-; GFX11-NEXT: s_min_u32 s4, s4, 32
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX11-NEXT: s_min_u32 s2, s2, 1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s2, s3, s2
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s2, 32, s4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
;
; GFX701-LABEL: s_uint_to_fp_zext_i16_to_f32:
@@ -2646,19 +2438,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f32(ptr addrspace(1) %out, i
; GFX701-NEXT: s_load_dword s2, s[8:9], 0x2
; GFX701-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_flbit_i32_b32 s4, 0
-; GFX701-NEXT: s_mov_b32 s3, 0
-; GFX701-NEXT: s_min_u32 s4, s4, 32
-; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX701-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX701-NEXT: s_min_u32 s2, s2, 1
-; GFX701-NEXT: s_or_b32 s2, s3, s2
-; GFX701-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX701-NEXT: s_sub_i32 s2, 32, s4
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX701-NEXT: v_ldexp_f32_e64 v2, v0, s2
+; GFX701-NEXT: s_waitcnt lgkmcnt(0)
+; GFX701-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX701-NEXT: v_cvt_f32_u32_e32 v2, s2
; GFX701-NEXT: v_mov_b32_e32 v0, s0
; GFX701-NEXT: v_mov_b32_e32 v1, s1
; GFX701-NEXT: flat_store_dword v[0:1], v2
@@ -2669,19 +2453,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f32(ptr addrspace(1) %out, i
; GFX803-NEXT: s_load_dword s2, s[8:9], 0x8
; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_flbit_i32_b32 s4, 0
-; GFX803-NEXT: s_mov_b32 s3, 0
-; GFX803-NEXT: s_min_u32 s4, s4, 32
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX803-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX803-NEXT: s_min_u32 s2, s2, 1
-; GFX803-NEXT: s_or_b32 s2, s3, s2
-; GFX803-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX803-NEXT: s_sub_i32 s2, 32, s4
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX803-NEXT: v_ldexp_f32 v2, v0, s2
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX803-NEXT: v_cvt_f32_u32_e32 v2, s2
; GFX803-NEXT: v_mov_b32_e32 v0, s0
; GFX803-NEXT: v_mov_b32_e32 v1, s1
; GFX803-NEXT: flat_store_dword v[0:1], v2
@@ -2691,18 +2467,10 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f32(ptr addrspace(1) %out, i
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GFX942-NEXT: s_flbit_i32_b32 s4, 0
-; GFX942-NEXT: s_mov_b32 s3, 0
-; GFX942-NEXT: s_min_u32 s4, s4, 32
+; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX942-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX942-NEXT: s_min_u32 s2, s2, 1
-; GFX942-NEXT: s_or_b32 s2, s3, s2
; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX942-NEXT: s_sub_i32 s2, 32, s4
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s2
; GFX942-NEXT: global_store_dword v1, v0, s[0:1]
; GFX942-NEXT: s_endpgm
%wide = zext i16 %in to i64
@@ -2714,31 +2482,23 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f32(ptr addrspace(1) %out, i
define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f64(ptr addrspace(1) %out, i16 %in) #0 {
; GFX6-LABEL: s_uint_to_fp_zext_i16_to_f64:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb
-; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX6-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
+; GFX6-NEXT: s_load_dword s2, s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: s_uint_to_fp_zext_i16_to_f64:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX8-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX8-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX8-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
+; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX8-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2746,17 +2506,13 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f64(ptr addrspace(1) %out, i
;
; GFX11-LABEL: s_uint_to_fp_zext_i16_to_f64:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
@@ -2766,14 +2522,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f64(ptr addrspace(1) %out, i
; GFX701-NEXT: s_load_dword s2, s[8:9], 0x2
; GFX701-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX701-NEXT: s_waitcnt lgkmcnt(0)
; GFX701-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX701-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX701-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX701-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX701-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX701-NEXT: v_mov_b32_e32 v3, s1
; GFX701-NEXT: v_mov_b32_e32 v2, s0
; GFX701-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2781,18 +2534,14 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f64(ptr addrspace(1) %out, i
;
; GFX803-LABEL: s_uint_to_fp_zext_i16_to_f64:
; GFX803: ; %bb.0:
-; GFX803-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX803-NEXT: s_load_dword s0, s[8:9], 0x8
+; GFX803-NEXT: s_load_dword s2, s[8:9], 0x8
+; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GFX803-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX803-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
-; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX803-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX803-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX803-NEXT: v_mov_b32_e32 v3, s1
; GFX803-NEXT: v_mov_b32_e32 v2, s0
; GFX803-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2802,14 +2551,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i16_to_f64(ptr addrspace(1) %out, i
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX942-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_endpgm
%wide = zext i16 %in to i64
%result = uitofp i64 %wide to double
@@ -2821,20 +2567,12 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f16(ptr addrspace(1) %out, i
; GFX6-LABEL: s_uint_to_fp_zext_i32_to_f16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb
-; GFX6-NEXT: s_flbit_i32_b32 s2, 0
-; GFX6-NEXT: s_mov_b32 s1, 0
-; GFX6-NEXT: s_min_u32 s2, s2, 32
; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX6-NEXT: s_min_u32 s0, s0, 1
-; GFX6-NEXT: s_or_b32 s0, s1, s0
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX6-NEXT: s_sub_i32 s2, 32, s2
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s2
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
@@ -2842,17 +2580,9 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f16(ptr addrspace(1) %out, i
; GFX8-LABEL: s_uint_to_fp_zext_i32_to_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX8-NEXT: s_flbit_i32_b32 s2, 0
-; GFX8-NEXT: s_mov_b32 s1, 0
-; GFX8-NEXT: s_min_u32 s2, s2, 32
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX8-NEXT: s_min_u32 s0, s0, 1
-; GFX8-NEXT: s_or_b32 s0, s1, s0
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8-NEXT: s_sub_i32 s2, 32, s2
-; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
@@ -2862,68 +2592,40 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f16(ptr addrspace(1) %out, i
;
; GFX11-TRUE16-LABEL: s_uint_to_fp_zext_i32_to_f16:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0
-; GFX11-TRUE16-NEXT: s_min_u32 s6, s2, 32
-; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_lshl_b64 s[0:1], s[0:1], s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_min_u32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_or_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX11-TRUE16-NEXT: s_sub_i32 s0, 32, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v0, s0
+; GFX11-TRUE16-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: s_uint_to_fp_zext_i32_to_f16:
; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0
-; GFX11-FAKE16-NEXT: s_min_u32 s6, s2, 32
-; GFX11-FAKE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_lshl_b64 s[0:1], s[0:1], s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_min_u32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_or_b32 s0, s1, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX11-FAKE16-NEXT: s_sub_i32 s0, 32, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v0, v0, s0
+; GFX11-FAKE16-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX701-LABEL: s_uint_to_fp_zext_i32_to_f16:
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dword s0, s[8:9], 0x2
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_flbit_i32_b32 s2, 0
-; GFX701-NEXT: s_mov_b32 s1, 0
-; GFX701-NEXT: s_min_u32 s2, s2, 32
+; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX701-NEXT: s_min_u32 s0, s0, 1
-; GFX701-NEXT: s_or_b32 s0, s1, s0
; GFX701-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX701-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX701-NEXT: s_sub_i32 s2, 32, s2
-; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GFX701-NEXT: v_ldexp_f32_e64 v0, v0, s2
; GFX701-NEXT: v_cvt_f16_f32_e32 v2, v0
-; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX701-NEXT: s_waitcnt lgkmcnt(0)
; GFX701-NEXT: v_mov_b32_e32 v0, s0
; GFX701-NEXT: v_mov_b32_e32 v1, s1
@@ -2934,20 +2636,12 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f16(ptr addrspace(1) %out, i
; GFX803: ; %bb.0:
; GFX803-NEXT: s_load_dword s0, s[8:9], 0x8
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_flbit_i32_b32 s2, 0
-; GFX803-NEXT: s_mov_b32 s1, 0
-; GFX803-NEXT: s_min_u32 s2, s2, 32
+; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX803-NEXT: s_min_u32 s0, s0, 1
-; GFX803-NEXT: s_or_b32 s0, s1, s0
; GFX803-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX803-NEXT: s_sub_i32 s2, 32, s2
-; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GFX803-NEXT: v_ldexp_f32 v0, v0, s2
; GFX803-NEXT: v_cvt_f16_f32_e32 v2, v0
-; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v0, s0
; GFX803-NEXT: v_mov_b32_e32 v1, s1
@@ -2957,18 +2651,10 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f16(ptr addrspace(1) %out, i
; GFX942-LABEL: s_uint_to_fp_zext_i32_to_f16:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s0, s[4:5], 0x8
-; GFX942-NEXT: s_flbit_i32_b32 s2, 0
-; GFX942-NEXT: s_mov_b32 s1, 0
-; GFX942-NEXT: s_min_u32 s2, s2, 32
; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
-; GFX942-NEXT: s_min_u32 s0, s0, 1
-; GFX942-NEXT: s_or_b32 s0, s1, s0
; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX942-NEXT: s_sub_i32 s2, 32, s2
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s2
; GFX942-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_store_short v1, v0, s[0:1]
@@ -2984,122 +2670,71 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f32(ptr addrspace(1) %out, i
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s2, s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: s_flbit_i32_b32 s4, 0
-; GFX6-NEXT: s_mov_b32 s3, 0
-; GFX6-NEXT: s_min_u32 s4, s4, 32
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GFX6-NEXT: s_min_u32 s2, s2, 1
-; GFX6-NEXT: s_or_b32 s2, s3, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_sub_i32 s4, 32, s4
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s4
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: s_uint_to_fp_zext_i32_to_f32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX8-NEXT: s_flbit_i32_b32 s4, 0
-; GFX8-NEXT: s_mov_b32 s1, 0
-; GFX8-NEXT: s_min_u32 s4, s4, 32
+; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX8-NEXT: s_min_u32 s0, s0, 1
-; GFX8-NEXT: s_or_b32 s0, s1, s0
-; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX8-NEXT: s_sub_i32 s0, 32, s4
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_ldexp_f32 v2, v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX11-LABEL: s_uint_to_fp_zext_i32_to_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX11-NEXT: s_clz_i32_u32 s4, 0
-; GFX11-NEXT: s_mov_b32 s1, 0
-; GFX11-NEXT: s_min_u32 s4, s4, 32
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_min_u32 s0, s0, 1
-; GFX11-NEXT: s_or_b32 s0, s1, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX11-NEXT: s_sub_i32 s0, 32, s4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s0
-; GFX11-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s2
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
;
; GFX701-LABEL: s_uint_to_fp_zext_i32_to_f32:
; GFX701: ; %bb.0:
-; GFX701-NEXT: s_load_dword s0, s[8:9], 0x2
-; GFX701-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
+; GFX701-NEXT: s_load_dword s2, s[8:9], 0x2
+; GFX701-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_flbit_i32_b32 s4, 0
-; GFX701-NEXT: s_mov_b32 s1, 0
-; GFX701-NEXT: s_min_u32 s4, s4, 32
-; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX701-NEXT: s_min_u32 s0, s0, 1
-; GFX701-NEXT: s_or_b32 s0, s1, s0
-; GFX701-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX701-NEXT: s_sub_i32 s0, 32, s4
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX701-NEXT: v_ldexp_f32_e64 v2, v0, s0
-; GFX701-NEXT: v_mov_b32_e32 v0, s2
-; GFX701-NEXT: v_mov_b32_e32 v1, s3
+; GFX701-NEXT: s_waitcnt lgkmcnt(0)
+; GFX701-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX701-NEXT: v_mov_b32_e32 v0, s0
+; GFX701-NEXT: v_mov_b32_e32 v1, s1
; GFX701-NEXT: flat_store_dword v[0:1], v2
; GFX701-NEXT: s_endpgm
;
; GFX803-LABEL: s_uint_to_fp_zext_i32_to_f32:
; GFX803: ; %bb.0:
-; GFX803-NEXT: s_load_dword s0, s[8:9], 0x8
-; GFX803-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
+; GFX803-NEXT: s_load_dword s2, s[8:9], 0x8
+; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_flbit_i32_b32 s4, 0
-; GFX803-NEXT: s_mov_b32 s1, 0
-; GFX803-NEXT: s_min_u32 s4, s4, 32
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX803-NEXT: s_min_u32 s0, s0, 1
-; GFX803-NEXT: s_or_b32 s0, s1, s0
-; GFX803-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX803-NEXT: s_sub_i32 s0, 32, s4
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX803-NEXT: v_ldexp_f32 v2, v0, s0
-; GFX803-NEXT: v_mov_b32_e32 v0, s2
-; GFX803-NEXT: v_mov_b32_e32 v1, s3
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX803-NEXT: v_mov_b32_e32 v0, s0
+; GFX803-NEXT: v_mov_b32_e32 v1, s1
; GFX803-NEXT: flat_store_dword v[0:1], v2
; GFX803-NEXT: s_endpgm
;
; GFX942-LABEL: s_uint_to_fp_zext_i32_to_f32:
; GFX942: ; %bb.0:
-; GFX942-NEXT: s_load_dword s0, s[4:5], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0
-; GFX942-NEXT: s_flbit_i32_b32 s4, 0
-; GFX942-NEXT: s_mov_b32 s1, 0
-; GFX942-NEXT: s_min_u32 s4, s4, 32
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
-; GFX942-NEXT: s_min_u32 s0, s0, 1
-; GFX942-NEXT: s_or_b32 s0, s1, s0
-; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX942-NEXT: s_sub_i32 s0, 32, s4
+; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8
+; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s0
-; GFX942-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX942-NEXT: global_store_dword v1, v0, s[0:1]
; GFX942-NEXT: s_endpgm
%wide = zext i32 %in to i64
%result = uitofp i64 %wide to float
@@ -3110,29 +2745,21 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f32(ptr addrspace(1) %out, i
define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f64(ptr addrspace(1) %out, i32 %in) #0 {
; GFX6-LABEL: s_uint_to_fp_zext_i32_to_f64:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb
-; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
+; GFX6-NEXT: s_load_dword s2, s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: s_uint_to_fp_zext_i32_to_f64:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX8-NEXT: s_load_dword s0, s[4:5], 0x2c
-; GFX8-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
+; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -3140,15 +2767,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f64(ptr addrspace(1) %out, i
;
; GFX11-LABEL: s_uint_to_fp_zext_i32_to_f64:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
+; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
@@ -3157,14 +2780,11 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f64(ptr addrspace(1) %out, i
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dword s2, s[8:9], 0x2
; GFX701-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX701-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
; GFX701-NEXT: s_add_i32 s12, s12, s17
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX701-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX701-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX701-NEXT: s_waitcnt lgkmcnt(0)
+; GFX701-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX701-NEXT: v_mov_b32_e32 v3, s1
; GFX701-NEXT: v_mov_b32_e32 v2, s0
; GFX701-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -3172,17 +2792,13 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f64(ptr addrspace(1) %out, i
;
; GFX803-LABEL: s_uint_to_fp_zext_i32_to_f64:
; GFX803: ; %bb.0:
-; GFX803-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX803-NEXT: s_load_dword s0, s[8:9], 0x8
+; GFX803-NEXT: s_load_dword s2, s[8:9], 0x8
+; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GFX803-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_cvt_f64_u32_e32 v[2:3], s0
-; GFX803-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX803-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
; GFX803-NEXT: v_mov_b32_e32 v3, s1
; GFX803-NEXT: v_mov_b32_e32 v2, s0
; GFX803-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -3192,13 +2808,10 @@ define amdgpu_kernel void @s_uint_to_fp_zext_i32_to_f64(ptr addrspace(1) %out, i
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], 0
-; GFX942-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s2
-; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_endpgm
%wide = zext i32 %in to i64
%result = uitofp i64 %wide to double
@@ -3210,21 +2823,12 @@ define amdgpu_kernel void @s_uint_to_fp_32_zero_bits_to_f32(ptr addrspace(1) %ou
; GFX6-LABEL: s_uint_to_fp_32_zero_bits_to_f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_flbit_i32_b32 s2, 0
-; GFX6-NEXT: s_mov_b32 s5, 0
-; GFX6-NEXT: s_min_u32 s8, s2, 32
; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: s_mov_b32 s4, s3
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[4:5], s8
-; GFX6-NEXT: s_min_u32 s2, s2, 1
-; GFX6-NEXT: s_or_b32 s2, s3, s2
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_mov_b32 s4, s0
-; GFX6-NEXT: s_sub_i32 s0, 32, s8
; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s5, s1
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
@@ -3232,61 +2836,31 @@ define amdgpu_kernel void @s_uint_to_fp_32_zero_bits_to_f32(ptr addrspace(1) %ou
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_flbit_i32_b32 s2, 0
-; GFX8-NEXT: s_mov_b32 s5, 0
-; GFX8-NEXT: s_min_u32 s6, s2, 32
-; GFX8-NEXT: s_mov_b32 s4, s3
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX8-NEXT: s_min_u32 s2, s2, 1
-; GFX8-NEXT: s_or_b32 s2, s3, s2
-; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_sub_i32 s0, 32, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_ldexp_f32 v2, v2, s0
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX11-LABEL: s_uint_to_fp_32_zero_bits_to_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-NEXT: s_mov_b32 s5, 0
-; GFX11-NEXT: s_min_u32 s6, s2, 32
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: s_mov_b32 s4, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX11-NEXT: s_min_u32 s2, s2, 1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s2, s3, s2
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s2, 32, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
;
; GFX701-LABEL: s_uint_to_fp_32_zero_bits_to_f32:
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: s_flbit_i32_b32 s2, 0
-; GFX701-NEXT: s_mov_b32 s5, 0
-; GFX701-NEXT: s_min_u32 s6, s2, 32
-; GFX701-NEXT: s_mov_b32 s4, s3
-; GFX701-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX701-NEXT: s_min_u32 s2, s2, 1
-; GFX701-NEXT: s_or_b32 s2, s3, s2
-; GFX701-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX701-NEXT: v_mov_b32_e32 v0, s0
-; GFX701-NEXT: s_sub_i32 s0, 32, s6
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX701-NEXT: s_waitcnt lgkmcnt(0)
+; GFX701-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX701-NEXT: v_mov_b32_e32 v0, s0
; GFX701-NEXT: v_mov_b32_e32 v1, s1
-; GFX701-NEXT: v_ldexp_f32_e64 v2, v2, s0
; GFX701-NEXT: flat_store_dword v[0:1], v2
; GFX701-NEXT: s_endpgm
;
@@ -3294,39 +2868,21 @@ define amdgpu_kernel void @s_uint_to_fp_32_zero_bits_to_f32(ptr addrspace(1) %ou
; GFX803: ; %bb.0:
; GFX803-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_flbit_i32_b32 s2, 0
-; GFX803-NEXT: s_mov_b32 s5, 0
-; GFX803-NEXT: s_min_u32 s6, s2, 32
-; GFX803-NEXT: s_mov_b32 s4, s3
-; GFX803-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX803-NEXT: s_min_u32 s2, s2, 1
-; GFX803-NEXT: s_or_b32 s2, s3, s2
-; GFX803-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX803-NEXT: v_mov_b32_e32 v0, s0
-; GFX803-NEXT: s_sub_i32 s0, 32, s6
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX803-NEXT: v_mov_b32_e32 v0, s0
; GFX803-NEXT: v_mov_b32_e32 v1, s1
-; GFX803-NEXT: v_ldexp_f32 v2, v2, s0
; GFX803-NEXT: flat_store_dword v[0:1], v2
; GFX803-NEXT: s_endpgm
;
; GFX942-LABEL: s_uint_to_fp_32_zero_bits_to_f32:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_flbit_i32_b32 s2, 0
-; GFX942-NEXT: s_mov_b32 s5, 0
-; GFX942-NEXT: s_min_u32 s6, s2, 32
; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: s_mov_b32 s4, s3
-; GFX942-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX942-NEXT: s_min_u32 s2, s2, 1
-; GFX942-NEXT: s_or_b32 s2, s3, s2
-; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX942-NEXT: s_sub_i32 s2, 32, s6
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX942-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX942-NEXT: global_store_dword v1, v0, s[0:1]
; GFX942-NEXT: s_endpgm
%narrow = lshr i64 %in, 32
@@ -3711,21 +3267,12 @@ define amdgpu_kernel void @s_uint_to_fp_nneg_32_zero_bits_to_f32(ptr addrspace(1
; GFX6-LABEL: s_uint_to_fp_nneg_32_zero_bits_to_f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_flbit_i32_b32 s2, 0
-; GFX6-NEXT: s_mov_b32 s5, 0
-; GFX6-NEXT: s_min_u32 s8, s2, 32
; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: s_mov_b32 s4, s3
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[4:5], s8
-; GFX6-NEXT: s_min_u32 s2, s2, 1
-; GFX6-NEXT: s_or_b32 s2, s3, s2
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_mov_b32 s4, s0
-; GFX6-NEXT: s_sub_i32 s0, 32, s8
; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s5, s1
-; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
@@ -3733,61 +3280,31 @@ define amdgpu_kernel void @s_uint_to_fp_nneg_32_zero_bits_to_f32(ptr addrspace(1
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_flbit_i32_b32 s2, 0
-; GFX8-NEXT: s_mov_b32 s5, 0
-; GFX8-NEXT: s_min_u32 s6, s2, 32
-; GFX8-NEXT: s_mov_b32 s4, s3
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX8-NEXT: s_min_u32 s2, s2, 1
-; GFX8-NEXT: s_or_b32 s2, s3, s2
-; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_sub_i32 s0, 32, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_ldexp_f32 v2, v2, s0
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX11-LABEL: s_uint_to_fp_nneg_32_zero_bits_to_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_clz_i32_u32 s2, 0
-; GFX11-NEXT: s_mov_b32 s5, 0
-; GFX11-NEXT: s_min_u32 s6, s2, 32
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: s_mov_b32 s4, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX11-NEXT: s_min_u32 s2, s2, 1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s2, s3, s2
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s2, 32, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
-; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
;
; GFX701-LABEL: s_uint_to_fp_nneg_32_zero_bits_to_f32:
; GFX701: ; %bb.0:
; GFX701-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX701-NEXT: s_add_i32 s12, s12, s17
-; GFX701-NEXT: s_waitcnt lgkmcnt(0)
-; GFX701-NEXT: s_flbit_i32_b32 s2, 0
-; GFX701-NEXT: s_mov_b32 s5, 0
-; GFX701-NEXT: s_min_u32 s6, s2, 32
-; GFX701-NEXT: s_mov_b32 s4, s3
-; GFX701-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX701-NEXT: s_min_u32 s2, s2, 1
-; GFX701-NEXT: s_or_b32 s2, s3, s2
-; GFX701-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX701-NEXT: v_mov_b32_e32 v0, s0
-; GFX701-NEXT: s_sub_i32 s0, 32, s6
; GFX701-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX701-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX701-NEXT: s_waitcnt lgkmcnt(0)
+; GFX701-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX701-NEXT: v_mov_b32_e32 v0, s0
; GFX701-NEXT: v_mov_b32_e32 v1, s1
-; GFX701-NEXT: v_ldexp_f32_e64 v2, v2, s0
; GFX701-NEXT: flat_store_dword v[0:1], v2
; GFX701-NEXT: s_endpgm
;
@@ -3795,39 +3312,21 @@ define amdgpu_kernel void @s_uint_to_fp_nneg_32_zero_bits_to_f32(ptr addrspace(1
; GFX803: ; %bb.0:
; GFX803-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX803-NEXT: s_add_i32 s12, s12, s17
-; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: s_flbit_i32_b32 s2, 0
-; GFX803-NEXT: s_mov_b32 s5, 0
-; GFX803-NEXT: s_min_u32 s6, s2, 32
-; GFX803-NEXT: s_mov_b32 s4, s3
-; GFX803-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX803-NEXT: s_min_u32 s2, s2, 1
-; GFX803-NEXT: s_or_b32 s2, s3, s2
-; GFX803-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX803-NEXT: v_mov_b32_e32 v0, s0
-; GFX803-NEXT: s_sub_i32 s0, 32, s6
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX803-NEXT: v_mov_b32_e32 v0, s0
; GFX803-NEXT: v_mov_b32_e32 v1, s1
-; GFX803-NEXT: v_ldexp_f32 v2, v2, s0
; GFX803-NEXT: flat_store_dword v[0:1], v2
; GFX803-NEXT: s_endpgm
;
; GFX942-LABEL: s_uint_to_fp_nneg_32_zero_bits_to_f32:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_flbit_i32_b32 s2, 0
-; GFX942-NEXT: s_mov_b32 s5, 0
-; GFX942-NEXT: s_min_u32 s6, s2, 32
; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: s_mov_b32 s4, s3
-; GFX942-NEXT: s_lshl_b64 s[2:3], s[4:5], s6
-; GFX942-NEXT: s_min_u32 s2, s2, 1
-; GFX942-NEXT: s_or_b32 s2, s3, s2
-; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX942-NEXT: s_sub_i32 s2, 32, s6
-; GFX942-NEXT: v_ldexp_f32 v0, v0, s2
+; GFX942-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX942-NEXT: global_store_dword v1, v0, s[0:1]
; GFX942-NEXT: s_endpgm
%narrow = lshr i64 %in, 32
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