[llvm] [AMDGPU] Fix uniform fcopysign pattern (PR #218644)

[via llvm-commits]

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@@ -2469,8 +2469,12 @@ let True16Predicate = UseRealTrue16Insts in {
 def : GCNPat <
   (fcopysign fp16vt:$src0, fp16vt:$src1),
   (EXTRACT_SUBREG (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)),
-    (REG_SEQUENCE VGPR_32, $src0, lo16, (i16 (IMPLICIT_DEF)), hi16),
-    (REG_SEQUENCE VGPR_32, $src1, lo16, (i16 (IMPLICIT_DEF)), hi16)), lo16)
+    (REG_SEQUENCE VGPR_32,
+      (fp16vt (COPY_TO_REGCLASS $src0, VGPR_16)), lo16,
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Shoreshen wrote:

Hi @arsenm , I tested, it seems like the register class info will not pass to MachineSDNode:
<img width="2501" height="1003" alt="image" src="https://github.com/user-attachments/assets/da26b14a-0c3e-45c9-916e-3dd75fa2920d" />
And final MIR is:
<img width="1160" height="393" alt="image" src="https://github.com/user-attachments/assets/07d3111b-eb5e-4e98-9735-51220ffa386c" />

https://github.com/llvm/llvm-project/pull/218644