[llvm] [AArch64] Add test coverage for constant mask and extract of a vector store. NFC (PR #223552)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 15:58:17 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/223552
None
>From 68dab3c5d6b0b34793943d4f0ee1f7274d9fcffb Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 14 Sep 2026 23:58:05 +0100
Subject: [PATCH] [AArch64] Add test coverage for constant mask and extract of
a vector store. NFC
---
llvm/test/CodeGen/AArch64/lowmaskedlanes.ll | 272 +++++++++++++++++++
llvm/test/CodeGen/AArch64/neon-truncstore.ll | 62 +++++
2 files changed, 334 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
diff --git a/llvm/test/CodeGen/AArch64/lowmaskedlanes.ll b/llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
new file mode 100644
index 0000000000000..99905726a5cf4
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
@@ -0,0 +1,272 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 | FileCheck %s
+
+define <2 x double> @load_low2_v2f64(ptr %p) vscale_range(2, 2) {
+; CHECK-LABEL: load_low2_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl2
+; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: sshll v0.2d, v0.2s, #0
+; CHECK-NEXT: cmpne p1.d, p0/z, z0.d, #0
+; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %m = tail call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 0, i32 2)
+ %l = tail call <2 x double> @llvm.masked.load.v2f64.p0(ptr align 1 %p, <2 x i1> %m, <2 x double> zeroinitializer)
+ ret <2 x double> %l
+}
+
+define <4 x i32> @load_low2_v4i32(ptr %p) vscale_range(1, 1) {
+; CHECK-LABEL: load_low2_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl2
+; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0
+; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %m = tail call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 2)
+ %l = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 1 %p, <4 x i1> %m, <4 x i32> zeroinitializer)
+ ret <4 x i32> %l
+}
+
+define <4 x i32> @load_low2c_v4i32(ptr %p) vscale_range(1, 1) {
+; CHECK-LABEL: load_low2c_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI2_0]
+; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0
+; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %l = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 1 %p, <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> zeroinitializer)
+ ret <4 x i32> %l
+}
+
+define <vscale x 4 x double> @load_low2_nxv4f64(ptr %p) {
+; CHECK-LABEL: load_low2_nxv4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl2
+; CHECK-NEXT: punpklo p1.h, p0.b
+; CHECK-NEXT: punpkhi p0.h, p0.b
+; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 2)
+ %l = tail call <vscale x 4 x double> @llvm.masked.load.nxv4f64.p0(ptr align 1 %p, <vscale x 4 x i1> %m, <vscale x 4 x double> zeroinitializer)
+ ret <vscale x 4 x double> %l
+}
+
+define <vscale x 2 x double> @load_low2_nxv2f64(ptr %p) {
+; CHECK-LABEL: load_low2_nxv2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 0, i32 2)
+ %l = tail call <vscale x 2 x double> @llvm.masked.load.nxv2f64.p0(ptr align 1 %p, <vscale x 2 x i1> %m, <vscale x 2 x double> zeroinitializer)
+ ret <vscale x 2 x double> %l
+}
+
+define <vscale x 4 x double> @load_low4_nxv4f64(ptr %p) {
+; CHECK-LABEL: load_low4_nxv4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: punpklo p1.h, p0.b
+; CHECK-NEXT: punpkhi p0.h, p0.b
+; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
+ %l = tail call <vscale x 4 x double> @llvm.masked.load.nxv4f64.p0(ptr align 1 %p, <vscale x 4 x i1> %m, <vscale x 4 x double> zeroinitializer)
+ ret <vscale x 4 x double> %l
+}
+
+define <8 x i16> @load_low2_v8i16(ptr %p) vscale_range(2, 2) {
+; CHECK-LABEL: load_low2_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl2
+; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.h, vl8
+; CHECK-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-NEXT: cmpne p1.h, p0/z, z0.h, #0
+; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %m = tail call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 2)
+ %l = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 1 %p, <8 x i1> %m, <8 x i16> zeroinitializer)
+ ret <8 x i16> %l
+}
+
+define <vscale x 8 x i16> @load_low2_nxv8i16(ptr %p) {
+; CHECK-LABEL: load_low2_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl2
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 0, i32 2)
+ %l = tail call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr align 1 %p, <vscale x 8 x i1> %m, <vscale x 8 x i16> zeroinitializer)
+ ret <vscale x 8 x i16> %l
+}
+
+define <vscale x 2 x i16> @load_low2_nxv2i16(ptr %p) {
+; CHECK-LABEL: load_low2_nxv2i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 0, i32 2)
+ %l = tail call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0(ptr align 1 %p, <vscale x 2 x i1> %m, <vscale x 2 x i16> zeroinitializer)
+ ret <vscale x 2 x i16> %l
+}
+
+define <vscale x 8 x i16> @load_low4_nxv8i16(ptr %p) {
+; CHECK-LABEL: load_low4_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl4
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 0, i32 4)
+ %l = tail call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr align 1 %p, <vscale x 8 x i1> %m, <vscale x 8 x i16> zeroinitializer)
+ ret <vscale x 8 x i16> %l
+}
+
+
+define void @store_low2_v4f64(ptr %p, <4 x double> %a) vscale_range(2, 2) {
+; CHECK-LABEL: store_low2_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ptrue p1.h, vl2
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; CHECK-NEXT: splice z0.d, p0, { z0.d, z1.d }
+; CHECK-NEXT: punpklo p0.h, p1.b
+; CHECK-NEXT: punpklo p0.h, p0.b
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 2)
+ tail call void @llvm.masked.store(<4 x double> %a, ptr align 1 %p, <4 x i1> %m)
+ ret void
+}
+
+define void @store_low2_v4i32(ptr %p, <4 x i32> %a) vscale_range(1, 1) {
+; CHECK-LABEL: store_low2_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl2
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sshll v1.4s, v1.4h, #0
+; CHECK-NEXT: cmpne p1.s, p0/z, z1.s, #0
+; CHECK-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 2)
+ tail call void @llvm.masked.store(<4 x i32> %a, ptr align 1 %p, <4 x i1> %m)
+ ret void
+}
+
+define void @store_low2c_v4i32(ptr %p, <4 x i32> %a) vscale_range(1, 1) {
+; CHECK-LABEL: store_low2c_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI12_0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]
+; CHECK-NEXT: cmpne p1.s, p0/z, z1.s, #0
+; CHECK-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-NEXT: ret
+ tail call void @llvm.masked.store(<4 x i32> %a, ptr align 1 %p, <4 x i1> <i1 true, i1 true, i1 false, i1 false>)
+ ret void
+}
+
+define void @store_low2_nxv4f64(ptr %p, <vscale x 4 x double> %a) {
+; CHECK-LABEL: store_low2_nxv4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl2
+; CHECK-NEXT: punpkhi p1.h, p0.b
+; CHECK-NEXT: punpklo p0.h, p0.b
+; CHECK-NEXT: st1d { z1.d }, p1, [x0, #1, mul vl]
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 2)
+ tail call void @llvm.masked.store(<vscale x 4 x double> %a, ptr align 1 %p, <vscale x 4 x i1> %m)
+ ret void
+}
+
+define void @store_low2_nxv2f64(ptr %p, <vscale x 2 x double> %a) {
+; CHECK-LABEL: store_low2_nxv2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 0, i32 2)
+ tail call void @llvm.masked.store(<vscale x 2 x double> %a, ptr align 1 %p, <vscale x 2 x i1> %m)
+ ret void
+}
+
+define void @store_low4_nxv4f64(ptr %p, <vscale x 4 x double> %a) {
+; CHECK-LABEL: store_low4_nxv4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: punpkhi p1.h, p0.b
+; CHECK-NEXT: punpklo p0.h, p0.b
+; CHECK-NEXT: st1d { z1.d }, p1, [x0, #1, mul vl]
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
+ tail call void @llvm.masked.store(<vscale x 4 x double> %a, ptr align 1 %p, <vscale x 4 x i1> %m)
+ ret void
+}
+
+define void @store_low2_v8i16(ptr %p, <8 x i16> %a) vscale_range(2, 2) {
+; CHECK-LABEL: store_low2_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl2
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.h, vl8
+; CHECK-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-NEXT: cmpne p1.h, p0/z, z1.h, #0
+; CHECK-NEXT: st1h { z0.h }, p1, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 2)
+ tail call void @llvm.masked.store(<8 x i16> %a, ptr align 1 %p, <8 x i1> %m)
+ ret void
+}
+
+define void @store_low2_nxv8i16(ptr %p, <vscale x 8 x i16> %a) {
+; CHECK-LABEL: store_low2_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl2
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 0, i32 2)
+ tail call void @llvm.masked.store(<vscale x 8 x i16> %a, ptr align 1 %p, <vscale x 8 x i1> %m)
+ ret void
+}
+
+define void @store_low2_nxv2i16(ptr %p, <vscale x 2 x i16> %a) {
+; CHECK-LABEL: store_low2_nxv2i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: st1h { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 0, i32 2)
+ tail call void @llvm.masked.store(<vscale x 2 x i16> %a, ptr align 1 %p, <vscale x 2 x i1> %m)
+ ret void
+}
+
+define void @store_low4_nxv8i16(ptr %p, <vscale x 8 x i16> %a) {
+; CHECK-LABEL: store_low4_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl4
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %m = tail call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 0, i32 4)
+ tail call void @llvm.masked.store(<vscale x 8 x i16> %a, ptr align 1 %p, <vscale x 8 x i1> %m)
+ ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/neon-truncstore.ll b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
index f25c90af7968e..9666cd705cbf6 100644
--- a/llvm/test/CodeGen/AArch64/neon-truncstore.ll
+++ b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
@@ -208,3 +208,65 @@ define void @v32i16_v32i8(<32 x i16> %a, ptr %result) {
store <32 x i8> %b, ptr %result
ret void
}
+
+
+define void @extract_v2i16_v8i16(<8 x i16> %a, ptr %p) {
+; CHECK-LABEL: extract_v2i16_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov h1, v0.h[1]
+; CHECK-NEXT: str h0, [x0]
+; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: ret
+ %c = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
+ store <2 x i16> %c, ptr %p
+ ret void
+}
+
+define void @extract_v4i16_v8i16(<8 x i16> %a, ptr %p) {
+; CHECK-LABEL: extract_v4i16_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: ret
+ %c = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x i16> %c, ptr %p
+ ret void
+}
+
+define void @extract_v2i16_v4i16(<4 x i16> %a, ptr %p) {
+; CHECK-LABEL: extract_v2i16_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-NEXT: mov s1, v0.s[1]
+; CHECK-NEXT: str h0, [x0]
+; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: ret
+ %c = shufflevector <4 x i16> %a, <4 x i16> poison, <2 x i32> <i32 0, i32 1>
+ store <2 x i16> %c, ptr %p
+ ret void
+}
+
+define void @extract_v2i8_v8i8(<8 x i8> %a, ptr %p) {
+; CHECK-LABEL: extract_v2i8_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov b1, v0.b[1]
+; CHECK-NEXT: str b0, [x0]
+; CHECK-NEXT: stur b1, [x0, #1]
+; CHECK-NEXT: ret
+ %c = shufflevector <8 x i8> %a, <8 x i8> poison, <2 x i32> <i32 0, i32 1>
+ store <2 x i8> %c, ptr %p
+ ret void
+}
+
+define void @extract_v4i8_v8i8(<8 x i8> %a, ptr %p) {
+; CHECK-LABEL: extract_v4i8_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: zip1 v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: str s0, [x0]
+; CHECK-NEXT: ret
+ %c = shufflevector <8 x i8> %a, <8 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x i8> %c, ptr %p
+ ret void
+}
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