[llvm] [ISel] Improve `clmul` fallback implementation (PR #204802)

[Folkert de Vries via llvm-commits]

folkertdev wrote:

I refined the cost calculation, picking the naive version more often for the weirder integer widths. All test files show a decrease in line count now, though there are a couple of functions using `rvv` that still regress instruction count. 

I believe that is just the scalar spilling (it uses `# vscale x 32-byte Folded Spill` a bunch), here is a diff for `clmul_nxv16i16_vv`:

<details>

```diff
--- clmul_nxv16i16_vv (upstream/main)
+++ clmul_nxv16i16_vv (with patch)
@@ -1,62 +1,108 @@
-li a0, 16
+addi sp, sp, -16
+csrr a0, vlenb
+slli a0, a0, 2
+mv a1, a0
+slli a0, a0, 2
+add a0, a0, a1
+sub sp, sp, a0
+lui a0, 9
+addi a0, a0, 585
 vsetvli a1, zero, e16, m4, ta, ma
-vand.vi v16, v12, 2
-vand.vi v20, v12, 1
-vmul.vv v16, v8, v16
-vmul.vv v20, v8, v20
-vxor.vv v16, v20, v16
-vand.vi v20, v12, 4
-vmul.vv v20, v8, v20
-vand.vi v24, v12, 8
-vmul.vv v24, v8, v24
-vxor.vv v16, v16, v20
-vxor.vv v16, v16, v24
-vand.vx v20, v12, a0
-vmul.vv v20, v8, v20
-li a0, 32
-vand.vx v24, v12, a0
-vmul.vv v24, v8, v24
-vxor.vv v16, v16, v20
-vxor.vv v16, v16, v24
-li a0, 64
-vand.vx v20, v12, a0
-vmul.vv v20, v8, v20
-li a0, 128
-vand.vx v24, v12, a0
-vmul.vv v24, v8, v24
-vxor.vv v16, v16, v20
-vxor.vv v16, v16, v24
-li a0, 256
-vand.vx v20, v12, a0
-vmul.vv v20, v8, v20
-li a0, 512
-vand.vx v24, v12, a0
-vmul.vv v24, v8, v24
-vxor.vv v16, v16, v20
-vxor.vv v16, v16, v24
-li a0, 1024
-vand.vx v20, v12, a0
-vmul.vv v20, v8, v20
-li a0, 1
-slli a0, a0, 11
-vand.vx v24, v12, a0
-vmul.vv v24, v8, v24
-vxor.vv v16, v16, v20
-vxor.vv v16, v16, v24
-lui a0, 1
-vand.vx v20, v12, a0
-vmul.vv v20, v8, v20
-lui a0, 2
-vand.vx v24, v12, a0
-vmul.vv v24, v8, v24
-vxor.vv v16, v16, v20
-vxor.vv v16, v16, v24
-lui a0, 4
-vand.vx v20, v12, a0
-vmul.vv v20, v8, v20
-lui a0, 8
-vand.vx v12, v12, a0
-vmul.vv v8, v8, v12
-vxor.vv v12, v16, v20
+vand.vx v16, v12, a0
+csrr a1, vlenb
+slli a1, a1, 2
+mv a2, a1
+slli a1, a1, 1
+add a1, a1, a2
+add a1, sp, a1
+addi a1, a1, 16
+vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+lui a1, 2
+addi a1, a1, 1170
+vand.vx v20, v8, a1
+vand.vx v24, v12, a1
+vand.vx v28, v8, a0
+lui a2, 5
+addi a2, a2, -1756
+vand.vx v12, v12, a2
+vmul.vv v16, v20, v16
+csrr a3, vlenb
+slli a3, a3, 4
+add a3, sp, a3
+addi a3, a3, 16
+vs4r.v v16, (a3) # vscale x 32-byte Folded Spill
+vmul.vv v0, v28, v24
+vand.vx v8, v8, a2
+vmul.vv v16, v8, v12
+csrr a3, vlenb
+slli a3, a3, 4
+add a3, sp, a3
+addi a3, a3, 16
+vl4r.v v4, (a3) # vscale x 32-byte Folded Reload
+vxor.vv v0, v0, v4
+vxor.vv v16, v0, v16
+csrr a3, vlenb
+slli a3, a3, 4
+add a3, sp, a3
+addi a3, a3, 16
+vs4r.v v16, (a3) # vscale x 32-byte Folded Spill
+vmul.vv v16, v20, v12
+csrr a3, vlenb
+slli a3, a3, 3
+add a3, sp, a3
+addi a3, a3, 16
+vs4r.v v16, (a3) # vscale x 32-byte Folded Spill
+csrr a3, vlenb
+slli a3, a3, 2
+mv a4, a3
+slli a3, a3, 1
+add a3, a3, a4
+add a3, sp, a3
+addi a3, a3, 16
+vl4r.v v4, (a3) # vscale x 32-byte Folded Reload
+vmul.vv v16, v28, v4
+csrr a3, vlenb
+slli a3, a3, 2
+add a3, sp, a3
+addi a3, a3, 16
+vs4r.v v16, (a3) # vscale x 32-byte Folded Spill
+vmul.vv v16, v8, v24
+addi a3, sp, 16
+vs4r.v v16, (a3) # vscale x 32-byte Folded Spill
+csrr a3, vlenb
+slli a3, a3, 3
+add a3, sp, a3
+addi a3, a3, 16
+vl4r.v v0, (a3) # vscale x 32-byte Folded Reload
+csrr a3, vlenb
+slli a3, a3, 2
+add a3, sp, a3
+addi a3, a3, 16
+vl4r.v v16, (a3) # vscale x 32-byte Folded Reload
+vxor.vv v0, v16, v0
+addi a3, sp, 16
+vl4r.v v16, (a3) # vscale x 32-byte Folded Reload
+vxor.vv v16, v0, v16
+csrr a3, vlenb
+slli a3, a3, 4
+add a3, sp, a3
+addi a3, a3, 16
+vl4r.v v0, (a3) # vscale x 32-byte Folded Reload
+vand.vx v0, v0, a1
+vand.vx v16, v16, a0
+vor.vv v16, v16, v0
+vmul.vv v20, v20, v24
+vmul.vv v12, v28, v12
+vmul.vv v8, v8, v4
+vxor.vv v12, v12, v20
 vxor.vv v8, v12, v8
+vand.vx v8, v8, a2
+vor.vv v8, v16, v8
+csrr a0, vlenb
+slli a0, a0, 2
+mv a1, a0
+slli a0, a0, 2
+add a0, a0, a1
+add sp, sp, a0
+addi sp, sp, 16
 ret
```

</details>



https://github.com/llvm/llvm-project/pull/204802