[llvm] [AMDGPU] Treat rematerialized SALU/SMEM instructions as part of the BB prolog (PR #223508)
Gabriel Baraldi via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 12:46:24 PDT 2026
https://github.com/gbaraldi created https://github.com/llvm/llvm-project/pull/223508
AI note. This PR was written with AI help. I've reviewed it myself to the best of my abilities though the diff is kind of big which is annoying.
@arsenm did mention that using lr-split as a way to "extend" what we consider the prologue is maybe not great but doing a refactor of this is above my pay-grade. This does fix my originally hit issue
llvm/test/CodeGen/AMDGPU/sgpr-remat-in-bb-prolog.mir is the actual test added. The rest is just churn
The sgpr-regalloc pipeline inserts its split copies and rematerialized instructions at the top of a basic block, ahead of any EXEC manipulation (SIInstrInfo::isBasicBlockPrologue returns false for SGPR registers, so SkipPHIsLabelsAndDebug stops at MBB.begin()). That is fine for exec-independent instructions, but the subsequent vgpr-regalloc pipeline has to recognize them as part of the prolog so that its own copies and spills land after the exec restore of an if/else %Flow block.
#117544 taught the prolog walk to skip the live-range split COPYs by flagging them MachineInstr::LRSplit, but rematerialized instructions (e.g. an S_LOAD_DWORDX8_IMM kernarg reload rematerialized by SplitKit into the %Flow block) were not flagged. The prolog walk stopped at the remat and the vgpr-regalloc pipeline inserted VGPR->AGPR split copies and spills above the S_OR_SAVEEXEC. Those copies then only executed for the lanes of the first branch arm, and the lanes of the else arm later read never-written AGPRs. In the original XLA kernel the copied value was a pointer and the kernel faulted.
Set the LRSplit flag in LiveRangeEdit::rematerializeAt, which is the common path for the remats done by SplitKit and InlineSpiller, and let SIInstrInfo::canAddToBBProlog accept flagged SGPR-defining instructions only when they are exec independent (COPY, SALU or SMEM). A VALU instruction defining an SGPR is never part of the prolog.
Fixes #222368
>From 84f2b1ad1364eff42bfc5d2981059d9f4e9588b5 Mon Sep 17 00:00:00 2001
From: Gabriel Baraldi <baraldigabriel at gmail.com>
Date: Mon, 14 Sep 2026 18:08:06 +0000
Subject: [PATCH] [AMDGPU] Treat rematerialized SALU/SMEM instructions as part
of the BB prolog
The sgpr-regalloc pipeline inserts its split copies and rematerialized
instructions at the top of a basic block, ahead of any EXEC manipulation
(SIInstrInfo::isBasicBlockPrologue returns false for SGPR registers, so
SkipPHIsLabelsAndDebug stops at MBB.begin()). That is fine for
exec-independent instructions, but the subsequent vgpr-regalloc pipeline
has to recognize them as part of the prolog so that its own copies and
spills land after the exec restore of an if/else %Flow block.
#117544 taught the prolog walk to skip the live-range split COPYs by
flagging them MachineInstr::LRSplit, but rematerialized instructions
(e.g. an S_LOAD_DWORDX8_IMM kernarg reload rematerialized by SplitKit
into the %Flow block) were not flagged. The prolog walk stopped at the
remat and the vgpr-regalloc pipeline inserted VGPR->AGPR split copies
and spills above the S_OR_SAVEEXEC. Those copies then only executed for
the lanes of the first branch arm, and the lanes of the else arm later
read never-written AGPRs. In the original XLA kernel the copied value
was a pointer and the kernel faulted.
Set the LRSplit flag in LiveRangeEdit::rematerializeAt, which is the
common path for the remats done by SplitKit and InlineSpiller, and let
SIInstrInfo::canAddToBBProlog accept flagged SGPR-defining instructions
only when they are exec independent (COPY, SALU or SMEM). A VALU
instruction defining an SGPR is never part of the prolog.
Fixes #222368
Co-Authored-By: Claude Fable 5.1 <noreply at anthropic.com>
---
llvm/include/llvm/CodeGen/MachineInstr.h | 2 +-
llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 +
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 9 +-
.../clear-dead-implicit-def-impdef.mir | 4 +-
.../CodeGen/AArch64/nested-iv-regalloc.mir | 8 +-
...egalloc-last-chance-recolor-with-split.mir | 20 +-
...gister-coalesce-update-subranges-remat.mir | 2 +-
.../CodeGen/AArch64/remat-fmov-vector-imm.mir | 10 +-
...oalescer-verifier-error-empty-subrange.mir | 4 +-
.../branch-folding-implicit-def-subreg.ll | 76 ++--
.../CodeGen/AMDGPU/bug-undef-spilled-agpr.mir | 2 +-
.../AMDGPU/coalescer-remat-dead-use.mir | 2 +-
llvm/test/CodeGen/AMDGPU/dead_bundle.mir | 2 +-
.../CodeGen/AMDGPU/inflate-av-remat-imm.mir | 8 +-
...nfloop-subrange-spill-inspect-subrange.mir | 6 +-
.../CodeGen/AMDGPU/infloop-subrange-spill.mir | 8 +-
.../CodeGen/AMDGPU/insert-waitcnts-merge.ll | 6 +-
.../CodeGen/AMDGPU/no-fold-accvgpr-mov.mir | 4 +-
.../ra-inserted-scalar-instructions.mir | 8 +-
.../AMDGPU/reg-coalescer-subreg-liveness.mir | 10 +-
.../AMDGPU/regalloc-sgpr128-partial-def.mir | 10 +-
.../CodeGen/AMDGPU/regcoal-subrange-join.mir | 2 +-
.../test/CodeGen/AMDGPU/remat-dead-subreg.mir | 4 +-
...xtract-already-live-at-def-issue120970.mir | 4 +-
llvm/test/CodeGen/AMDGPU/remat-smrd.mir | 54 +--
llvm/test/CodeGen/AMDGPU/remat-sop.mir | 60 +--
.../CodeGen/AMDGPU/remat-through-copy.mir | 12 +-
.../AMDGPU/sgpr-remat-in-bb-prolog.mir | 82 +++++
.../AMDGPU/snippet-copy-bundle-regression.mir | 6 +-
.../split-liverange-overlapping-copies.mir | 2 +-
.../AMDGPU/splitkit-copy-live-lanes.mir | 10 +-
...-do-not-undo-subclass-split-with-remat.mir | 4 +-
...-last-chance-recoloring-alloc-succeeds.mir | 6 +-
.../AMDGPU/vgpr-remat-v_pk_mov_b32.mir | 4 +-
llvm/test/CodeGen/AMDGPU/vgpr-remat.mir | 8 +-
llvm/test/CodeGen/AMDGPU/vopc-remat.mir | 2 +-
.../test/CodeGen/ARM/machine-outliner-tail.ll | 24 +-
.../CodeGen/ARM/machine-outliner-thunk.ll | 24 +-
.../register-coalescer-crash-pr79718.mir | 2 +-
llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll | 342 +++++++++---------
llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll | 40 +-
.../test/CodeGen/PowerPC/aix-indirect-call.ll | 14 +-
.../PowerPC/aix-lower-jump-table-mir.ll | 8 +-
.../CodeGen/PowerPC/aix-vec-arg-spills-mir.ll | 108 +++---
llvm/test/CodeGen/PowerPC/aix-vector-byval.ll | 4 +-
.../PowerPC/remove-copy-crunsetcrbit.mir | 2 +-
llvm/test/CodeGen/RISCV/pr176001.ll | 8 +-
llvm/test/CodeGen/RISCV/zilsd-spill.ll | 8 +-
.../X86/AMX/amx-greedy-ra-spill-shape.ll | 6 +-
llvm/test/CodeGen/X86/apx/foldmemory.mir | 2 +-
...esce-commute-partial-def-implicit-read.mir | 10 +-
.../X86/coalesce-dbg-value-subreg-rewrite.mir | 2 +-
...icit-def-regression-imp-operand-assert.mir | 2 +-
...-remat-with-undef-implicit-def-operand.mir | 4 +-
llvm/test/CodeGen/X86/early-clobber.mir | 2 +-
llvm/test/CodeGen/X86/late-remat-update-2.mir | 2 +-
llvm/test/CodeGen/X86/remat-phys-dead.ll | 2 +-
.../X86/rematerialize-sub-super-reg.mir | 12 +-
...plitkit-remat-broken-subreg-constraint.mir | 6 +-
.../X86/statepoint-invoke-ra-enter-at-end.mir | 8 +-
.../statepoint-invoke-ra-inline-spiller.mir | 8 +-
.../test/CodeGen/X86/statepoint-invoke-ra.mir | 10 +-
llvm/test/CodeGen/X86/statepoint-ra.ll | 6 +-
.../CodeGen/X86/statepoint-vreg-details.ll | 4 +-
64 files changed, 610 insertions(+), 523 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/sgpr-remat-in-bb-prolog.mir
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 87e40501b3f3c..4a2be438645e9 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -128,7 +128,7 @@ class MachineInstr
SameSign = 1 << 21, // Both operands have the same sign.
InBounds = 1 << 22, // Pointer arithmetic remains inbounds.
// Implies NoUSWrap.
- LRSplit = 1 << 23, // Instruction for live range split.
+ LRSplit = 1 << 23, // RA inserted copy or remat for live range split.
NonNull = 1 << 24 // Address space cast source is not the null
// value of the source address space.
};
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index 1d6b835f16468..7e4d8502b923f 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -91,6 +91,8 @@ SlotIndex LiveRangeEdit::rematerializeAt(
// to false anyway in case the isDead flag of RM.OrigMI's dest register
// is true.
(*--MI).clearRegisterDeads(DestReg);
+ // Mark as RA inserted, like the split copies (see isBasicBlockPrologue).
+ MI->setFlag(MachineInstr::LRSplit);
Rematted.insert(RM.ParentVNI);
++NumReMaterialization;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c5474ac38ee31..49e07574a9161 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -10444,7 +10444,7 @@ bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
const MachineRegisterInfo &MRI = MF->getRegInfo();
const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
- // See if this is Liverange split instruction inserted for SGPR or
+ // See if this is a liverange split COPY or remat inserted for SGPR or
// wwm-register. The implicit def inserted for wwm-registers should also be
// included as they can appear at the bb begin.
bool IsLRSplitInst = MI.getFlag(MachineInstr::LRSplit);
@@ -10452,8 +10452,11 @@ bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
return false;
Register Reg = MI.getOperand(0).getReg();
- if (RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg)))
- return IsLRSplitInst;
+ if (RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg))) {
+ // sgpr-regalloc inserts these above any EXEC write at the bb begin; only
+ // exec independent instructions can be part of the prolog there.
+ return IsLRSplitInst && (MI.isCopy() || isSALU(MI) || isSMRD(MI));
+ }
return MFI->isWWMReg(Reg);
}
diff --git a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
index 1592c86e267f5..e7a13cf9f82d4 100644
--- a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
+++ b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
@@ -33,7 +33,7 @@ body: |
; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr64 = IMPLICIT_DEF
; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: undef [[DEF3:%[0-9]+]].sub_32:gpr64 = IMPLICIT_DEF implicit-def [[DEF3]]
+ ; CHECK-NEXT: undef [[DEF3:%[0-9]+]].sub_32:gpr64 = lr-split IMPLICIT_DEF implicit-def [[DEF3]]
; CHECK-NEXT: STRXui [[DEF3]], [[DEF]], 1 :: (store (s64) into stack + 8)
; CHECK-NEXT: BL 0, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
@@ -61,7 +61,7 @@ body: |
; CHECK-NEXT: $x0 = COPY [[COPY1]]
; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: undef [[DEF4:%[0-9]+]].sub_32:gpr64 = IMPLICIT_DEF implicit-def [[DEF4]]
+ ; CHECK-NEXT: undef [[DEF4:%[0-9]+]].sub_32:gpr64 = lr-split IMPLICIT_DEF implicit-def [[DEF4]]
; CHECK-NEXT: STRXui [[DEF4]], undef [[DEF]], 1 :: (store (s64) into stack + 8)
; CHECK-NEXT: ADJCALLSTACKUP 24, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir b/llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
index ef48ff55ac973..443bea6089dc0 100644
--- a/llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
+++ b/llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
@@ -219,9 +219,9 @@ body: |
; CHECK-NEXT: liveins: $w10, $w11, $x2, $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: STRXui renamable $x8, %stack.1, 0 :: (store (s64) into %stack.1)
- ; CHECK-NEXT: renamable $w9 = MOVi32imm 36
+ ; CHECK-NEXT: renamable $w9 = lr-split MOVi32imm 36
; CHECK-NEXT: renamable $x8 = MADDXrrr killed renamable $x8, killed renamable $x9, $xzr
- ; CHECK-NEXT: renamable $x9 = MOVaddr target-flags(aarch64-page) @g, target-flags(aarch64-pageoff, aarch64-nc) @g
+ ; CHECK-NEXT: renamable $x9 = lr-split MOVaddr target-flags(aarch64-page) @g, target-flags(aarch64-pageoff, aarch64-nc) @g
; CHECK-NEXT: renamable $w8 = LDRWroX killed renamable $x9, killed renamable $x8, 0, 0 :: (load (s32) from %ir.arrayidx9)
; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w8, 1, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 10, %bb.3, implicit $nzcv
@@ -244,9 +244,9 @@ body: |
; CHECK-NEXT: successors: %bb.5(0x50000000), %bb.8(0x30000000)
; CHECK-NEXT: liveins: $w10, $w11, $x2, $x12
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = MOVi32imm 36
+ ; CHECK-NEXT: renamable $w8 = lr-split MOVi32imm 36
; CHECK-NEXT: renamable $x8 = MADDXrrr renamable $x12, killed renamable $x8, $xzr
- ; CHECK-NEXT: renamable $x9 = MOVaddr target-flags(aarch64-page) @g, target-flags(aarch64-pageoff, aarch64-nc) @g
+ ; CHECK-NEXT: renamable $x9 = lr-split MOVaddr target-flags(aarch64-page) @g, target-flags(aarch64-pageoff, aarch64-nc) @g
; CHECK-NEXT: renamable $w8 = LDRWroX killed renamable $x9, killed renamable $x8, 0, 0 :: (load (s32) from %ir.arrayidx14)
; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w8, 1, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 11, %bb.8, implicit $nzcv
diff --git a/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir b/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
index 73a22b71980cb..5cb63e25dbf44 100644
--- a/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
+++ b/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
@@ -316,7 +316,7 @@ body: |
; CHECK-NEXT: KILL killed renamable $x8
; CHECK-NEXT: renamable $x8 = IMPLICIT_DEF
; CHECK-NEXT: KILL killed renamable $x8
- ; CHECK-NEXT: renamable $w10 = MOVi32imm 2, implicit-def $x10
+ ; CHECK-NEXT: renamable $w10 = lr-split MOVi32imm 2, implicit-def $x10
; CHECK-NEXT: B %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb23:
@@ -324,7 +324,7 @@ body: |
; CHECK-NEXT: liveins: $x19
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: renamable $w20 = MOVi32imm 95
+ ; CHECK-NEXT: renamable $w20 = lr-split MOVi32imm 95
; CHECK-NEXT: STATEPOINT 2882400000, 0, 0, @wombat, 2, 0, 2, 0, 2, 39, 2, 0, 2, 1, 2, 0, 2, 117, 2, 2, 2, 14, 2, 0, 2, 3, 2, 3, 2, 3, 2, 109, 2, 0, 1, 8, %stack.0, 0, 2, 7, 2, 0, 2, 3, killed renamable $w20, 2, 3, renamable $w19, 2, 3, 2, 3, 2, 3, 2, -8280, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 5, 2, 7, 2, 0, 2, 3, 2, 1, 2, 0, 2, 4278124286, 2, 7, 2, 0, 2, 2, 1, 8, %stack.0, 0, 2, 4278124286, 2, 0, 2, 2, 0, 0, 1, 1, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x19 :: (load store (s64) on %stack.0)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: {{ $}}
@@ -354,10 +354,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x19 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
- ; CHECK-NEXT: renamable $w22 = MOVi32imm 2, implicit-def $x22
- ; CHECK-NEXT: renamable $w26 = MOVi32imm 95
+ ; CHECK-NEXT: renamable $w22 = lr-split MOVi32imm 2, implicit-def $x22
+ ; CHECK-NEXT: renamable $w26 = lr-split MOVi32imm 95
; CHECK-NEXT: renamable $x27, dead renamable $x19 = STATEPOINT 2882400000, 0, 0, @wombat, 2, 0, 2, 0, 2, 35, 2, 0, 2, 1, 2, 0, 2, 125, 2, 0, 2, 14, 2, 0, 2, 0, killed renamable $x19, 2, 7, 2, 0, 2, 3, killed renamable $w26, 2, 3, renamable $w22, 2, 3, 2, 4278124286, 2, 3, killed renamable $w21, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 2, 2, 7, 2, 0, 2, 3, 2, 4278124286, 2, 0, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 3, killed renamable $x27(tied-def 0), 1, 8, %stack.1, 0, renamable $x19(tied-def 1), 2, 0, 2, 3, 0, 0, 1, 1, 2, 2, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x22 :: (load store (s64) on %stack.1)
- ; CHECK-NEXT: renamable $w10 = MOVi32imm 2, implicit-def $x10
+ ; CHECK-NEXT: renamable $w10 = lr-split MOVi32imm 2, implicit-def $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x19 = COPY $xzr
; CHECK-NEXT: renamable $x8 = LDRXui %stack.1, 0 :: (load (s64) from %stack.1)
@@ -392,7 +392,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: BL @blam.1, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
- ; CHECK-NEXT: renamable $w10 = MOVi32imm 2, implicit-def $x10
+ ; CHECK-NEXT: renamable $w10 = lr-split MOVi32imm 2, implicit-def $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.11.bb83:
@@ -428,7 +428,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: $w0 = MOVi32imm 12
- ; CHECK-NEXT: renamable $w8 = MOVi32imm 95
+ ; CHECK-NEXT: renamable $w8 = lr-split MOVi32imm 95
; CHECK-NEXT: STATEPOINT 2882400000, 0, 1, @blam, $w0, 2, 129, 2, 0, 2, 43, 2, 0, 2, 1, 2, 0, 2, 201, 2, 4, 2, 14, 2, 0, 2, 0, 2, 4278124286, 2, 3, renamable $w29, 2, 0, 2, 4278124286, 2, 3, renamable $w29, 2, 0, 1, 8, %stack.0, 0, 2, 7, 2, 0, 2, 3, killed renamable $w8, 2, 3, renamable $w10, 2, 3, 2, 4278124286, 2, 3, killed renamable $w21, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 2, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 3, 2, 4278124286, 1, 8, %stack.0, 0, 1, 8, %stack.1, 0, 2, 0, 2, 3, 0, 0, 1, 1, 2, 2, csr_aarch64_allregs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x10, implicit killed $fp :: (load store (s64) on %stack.0), (load store (s64) on %stack.1)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: {{ $}}
@@ -446,10 +446,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x19 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
- ; CHECK-NEXT: renamable $w21 = MOVi32imm 2, implicit-def $x21
- ; CHECK-NEXT: renamable $w22 = MOVi32imm 95
+ ; CHECK-NEXT: renamable $w21 = lr-split MOVi32imm 2, implicit-def $x21
+ ; CHECK-NEXT: renamable $w22 = lr-split MOVi32imm 95
; CHECK-NEXT: renamable $x27, dead renamable $x19 = STATEPOINT 2882400000, 0, 0, @wombat, 2, 0, 2, 0, 2, 35, 2, 0, 2, 1, 2, 0, 2, 250, 2, 0, 2, 14, 2, 0, 2, 0, killed renamable $x19, 2, 7, 2, 0, 2, 3, killed renamable $w22, 2, 3, renamable $w21, 2, 3, 2, 4278124286, 2, 3, renamable $w21, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 0, 2, 7, 2, 0, 2, 3, 2, 4278124286, 2, 0, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.2, 0, killed renamable $x27(tied-def 0), 1, 8, %stack.1, 0, renamable $x19(tied-def 1), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x21 :: (load store (s64) on %stack.1), (load store (s64) on %stack.2)
- ; CHECK-NEXT: renamable $w10 = MOVi32imm 2, implicit-def $x10
+ ; CHECK-NEXT: renamable $w10 = lr-split MOVi32imm 2, implicit-def $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x8 = LDRXui %stack.1, 0 :: (load (s64) from %stack.1)
; CHECK-NEXT: dead renamable $x8 = nuw ADDXri killed renamable $x8, 24, 0
diff --git a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
index 2861933350d2e..311f95cb283fc 100644
--- a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
+++ b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
@@ -23,7 +23,7 @@ body: |
; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64common = nuw ADDXri [[ADDXri]], 64, 0
; CHECK-NEXT: undef [[MOVi32imm:%[0-9]+]].sub_32:gpr64 = MOVi32imm 64
- ; CHECK-NEXT: undef [[MOVi32imm1:%[0-9]+]].sub_32:gpr64 = MOVi32imm 64
+ ; CHECK-NEXT: undef [[MOVi32imm1:%[0-9]+]].sub_32:gpr64 = lr-split MOVi32imm 64
; CHECK-NEXT: dead [[ADDXri1]]:gpr64common, dead early-clobber [[MOVi32imm1]]:gpr64 = MOPSMemorySetPseudo [[ADDXri1]], [[MOVi32imm1]], [[MOVi32imm]], implicit-def dead $nzcv
; CHECK-NEXT: RET_ReallyLR
%1:gpr64sp = ADDXri %stack.0, 0, 0
diff --git a/llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir b/llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
index 8289ed80eae43..97e60dce19c9e 100644
--- a/llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
+++ b/llvm/test/CodeGen/AArch64/remat-fmov-vector-imm.mir
@@ -47,7 +47,7 @@ body: |
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $q0, clobber, implicit-def dead early-clobber $q1, clobber, implicit-def dead early-clobber $q2, clobber, implicit-def dead early-clobber $q3, clobber, implicit-def dead early-clobber $q4, clobber, implicit-def dead early-clobber $q5, clobber, implicit-def dead early-clobber $q6, clobber, implicit-def dead early-clobber $q7, clobber, implicit-def dead early-clobber $q8, clobber, implicit-def dead early-clobber $q9, clobber, implicit-def dead early-clobber $q10, clobber, implicit-def dead early-clobber $q11, clobber, implicit-def dead early-clobber $q12, clobber, implicit-def dead early-clobber $q13, clobber, implicit-def dead early-clobber $q14, clobber, implicit-def dead early-clobber $q15, clobber, implicit-def dead early-clobber $q16, clobber, implicit-def dead early-clobber $q17, clobber, implicit-def dead early-clobber $q18, clobber, implicit-def dead early-clobber $q19, clobber, implicit-def dead early-clobber $q20, clobber, implicit-def dead early-clobber $q21, clobber, implicit-def dead early-clobber $q22, clobber, implicit-def dead early-clobber $q23, clobber, implicit-def dead early-clobber $q24, clobber, implicit-def dead early-clobber $q25, clobber, implicit-def dead early-clobber $q26, clobber, implicit-def dead early-clobber $q27, clobber, implicit-def dead early-clobber $q28, clobber, implicit-def dead early-clobber $q29, clobber, implicit-def dead early-clobber $q30, clobber, implicit-def dead early-clobber $q31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: [[FMOVv2f64_ns1:%[0-9]+]]:fpr128 = FMOVv2f64_ns 127
+ ; CHECK-NEXT: [[FMOVv2f64_ns1:%[0-9]+]]:fpr128 = lr-split FMOVv2f64_ns 127
; CHECK-NEXT: $q0 = COPY [[FMOVv2f64_ns1]]
; CHECK-NEXT: BL @bar_v2f64, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $q0, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
@@ -79,7 +79,7 @@ body: |
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $q0, clobber, implicit-def dead early-clobber $q1, clobber, implicit-def dead early-clobber $q2, clobber, implicit-def dead early-clobber $q3, clobber, implicit-def dead early-clobber $q4, clobber, implicit-def dead early-clobber $q5, clobber, implicit-def dead early-clobber $q6, clobber, implicit-def dead early-clobber $q7, clobber, implicit-def dead early-clobber $q8, clobber, implicit-def dead early-clobber $q9, clobber, implicit-def dead early-clobber $q10, clobber, implicit-def dead early-clobber $q11, clobber, implicit-def dead early-clobber $q12, clobber, implicit-def dead early-clobber $q13, clobber, implicit-def dead early-clobber $q14, clobber, implicit-def dead early-clobber $q15, clobber, implicit-def dead early-clobber $q16, clobber, implicit-def dead early-clobber $q17, clobber, implicit-def dead early-clobber $q18, clobber, implicit-def dead early-clobber $q19, clobber, implicit-def dead early-clobber $q20, clobber, implicit-def dead early-clobber $q21, clobber, implicit-def dead early-clobber $q22, clobber, implicit-def dead early-clobber $q23, clobber, implicit-def dead early-clobber $q24, clobber, implicit-def dead early-clobber $q25, clobber, implicit-def dead early-clobber $q26, clobber, implicit-def dead early-clobber $q27, clobber, implicit-def dead early-clobber $q28, clobber, implicit-def dead early-clobber $q29, clobber, implicit-def dead early-clobber $q30, clobber, implicit-def dead early-clobber $q31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: [[FMOVv4f32_ns1:%[0-9]+]]:fpr128 = FMOVv4f32_ns 112
+ ; CHECK-NEXT: [[FMOVv4f32_ns1:%[0-9]+]]:fpr128 = lr-split FMOVv4f32_ns 112
; CHECK-NEXT: $q0 = COPY [[FMOVv4f32_ns1]]
; CHECK-NEXT: BL @bar_v4f32, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $q0, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
@@ -111,7 +111,7 @@ body: |
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $q0, clobber, implicit-def dead early-clobber $q1, clobber, implicit-def dead early-clobber $q2, clobber, implicit-def dead early-clobber $q3, clobber, implicit-def dead early-clobber $q4, clobber, implicit-def dead early-clobber $q5, clobber, implicit-def dead early-clobber $q6, clobber, implicit-def dead early-clobber $q7, clobber, implicit-def dead early-clobber $q8, clobber, implicit-def dead early-clobber $q9, clobber, implicit-def dead early-clobber $q10, clobber, implicit-def dead early-clobber $q11, clobber, implicit-def dead early-clobber $q12, clobber, implicit-def dead early-clobber $q13, clobber, implicit-def dead early-clobber $q14, clobber, implicit-def dead early-clobber $q15, clobber, implicit-def dead early-clobber $q16, clobber, implicit-def dead early-clobber $q17, clobber, implicit-def dead early-clobber $q18, clobber, implicit-def dead early-clobber $q19, clobber, implicit-def dead early-clobber $q20, clobber, implicit-def dead early-clobber $q21, clobber, implicit-def dead early-clobber $q22, clobber, implicit-def dead early-clobber $q23, clobber, implicit-def dead early-clobber $q24, clobber, implicit-def dead early-clobber $q25, clobber, implicit-def dead early-clobber $q26, clobber, implicit-def dead early-clobber $q27, clobber, implicit-def dead early-clobber $q28, clobber, implicit-def dead early-clobber $q29, clobber, implicit-def dead early-clobber $q30, clobber, implicit-def dead early-clobber $q31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: [[FMOVv2f32_ns1:%[0-9]+]]:fpr64 = FMOVv2f32_ns 115
+ ; CHECK-NEXT: [[FMOVv2f32_ns1:%[0-9]+]]:fpr64 = lr-split FMOVv2f32_ns 115
; CHECK-NEXT: $d0 = COPY [[FMOVv2f32_ns1]]
; CHECK-NEXT: BL @bar_v2f32, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $d0, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
@@ -143,7 +143,7 @@ body: |
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $q0, clobber, implicit-def dead early-clobber $q1, clobber, implicit-def dead early-clobber $q2, clobber, implicit-def dead early-clobber $q3, clobber, implicit-def dead early-clobber $q4, clobber, implicit-def dead early-clobber $q5, clobber, implicit-def dead early-clobber $q6, clobber, implicit-def dead early-clobber $q7, clobber, implicit-def dead early-clobber $q8, clobber, implicit-def dead early-clobber $q9, clobber, implicit-def dead early-clobber $q10, clobber, implicit-def dead early-clobber $q11, clobber, implicit-def dead early-clobber $q12, clobber, implicit-def dead early-clobber $q13, clobber, implicit-def dead early-clobber $q14, clobber, implicit-def dead early-clobber $q15, clobber, implicit-def dead early-clobber $q16, clobber, implicit-def dead early-clobber $q17, clobber, implicit-def dead early-clobber $q18, clobber, implicit-def dead early-clobber $q19, clobber, implicit-def dead early-clobber $q20, clobber, implicit-def dead early-clobber $q21, clobber, implicit-def dead early-clobber $q22, clobber, implicit-def dead early-clobber $q23, clobber, implicit-def dead early-clobber $q24, clobber, implicit-def dead early-clobber $q25, clobber, implicit-def dead early-clobber $q26, clobber, implicit-def dead early-clobber $q27, clobber, implicit-def dead early-clobber $q28, clobber, implicit-def dead early-clobber $q29, clobber, implicit-def dead early-clobber $q30, clobber, implicit-def dead early-clobber $q31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: [[FMOVv4f16_ns1:%[0-9]+]]:fpr64 = FMOVv4f16_ns 124
+ ; CHECK-NEXT: [[FMOVv4f16_ns1:%[0-9]+]]:fpr64 = lr-split FMOVv4f16_ns 124
; CHECK-NEXT: $d0 = COPY [[FMOVv4f16_ns1]]
; CHECK-NEXT: BL @bar_v4f16, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $d0, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
@@ -175,7 +175,7 @@ body: |
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $q0, clobber, implicit-def dead early-clobber $q1, clobber, implicit-def dead early-clobber $q2, clobber, implicit-def dead early-clobber $q3, clobber, implicit-def dead early-clobber $q4, clobber, implicit-def dead early-clobber $q5, clobber, implicit-def dead early-clobber $q6, clobber, implicit-def dead early-clobber $q7, clobber, implicit-def dead early-clobber $q8, clobber, implicit-def dead early-clobber $q9, clobber, implicit-def dead early-clobber $q10, clobber, implicit-def dead early-clobber $q11, clobber, implicit-def dead early-clobber $q12, clobber, implicit-def dead early-clobber $q13, clobber, implicit-def dead early-clobber $q14, clobber, implicit-def dead early-clobber $q15, clobber, implicit-def dead early-clobber $q16, clobber, implicit-def dead early-clobber $q17, clobber, implicit-def dead early-clobber $q18, clobber, implicit-def dead early-clobber $q19, clobber, implicit-def dead early-clobber $q20, clobber, implicit-def dead early-clobber $q21, clobber, implicit-def dead early-clobber $q22, clobber, implicit-def dead early-clobber $q23, clobber, implicit-def dead early-clobber $q24, clobber, implicit-def dead early-clobber $q25, clobber, implicit-def dead early-clobber $q26, clobber, implicit-def dead early-clobber $q27, clobber, implicit-def dead early-clobber $q28, clobber, implicit-def dead early-clobber $q29, clobber, implicit-def dead early-clobber $q30, clobber, implicit-def dead early-clobber $q31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: [[FMOVv8f16_ns1:%[0-9]+]]:fpr128 = FMOVv8f16_ns 128
+ ; CHECK-NEXT: [[FMOVv8f16_ns1:%[0-9]+]]:fpr128 = lr-split FMOVv8f16_ns 128
; CHECK-NEXT: $q0 = COPY [[FMOVv8f16_ns1]]
; CHECK-NEXT: BL @bar_v8f16, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $q0, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
diff --git a/llvm/test/CodeGen/AMDGPU/blender-coalescer-verifier-error-empty-subrange.mir b/llvm/test/CodeGen/AMDGPU/blender-coalescer-verifier-error-empty-subrange.mir
index 282a62c10ddd8..de95b1c2b3f77 100644
--- a/llvm/test/CodeGen/AMDGPU/blender-coalescer-verifier-error-empty-subrange.mir
+++ b/llvm/test/CodeGen/AMDGPU/blender-coalescer-verifier-error-empty-subrange.mir
@@ -28,7 +28,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF
- ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF
+ ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = lr-split IMPLICIT_DEF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: S_NOP 0, implicit [[DEF]]
@@ -75,7 +75,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 123
- ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 123
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = lr-split S_MOV_B32 123
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
index 5752fde325d0c..ff524c1b3ea08 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
@@ -48,7 +48,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr23 = IMPLICIT_DEF implicit-def $vgpr22
; GFX90A-NEXT: renamable $vgpr25 = IMPLICIT_DEF implicit-def $vgpr24
; GFX90A-NEXT: renamable $vgpr27 = IMPLICIT_DEF implicit-def $vgpr26
- ; GFX90A-NEXT: renamable $sgpr36_sgpr37 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr36_sgpr37 = lr-split S_MOV_B64 0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3.Flow17:
; GFX90A-NEXT: successors: %bb.4(0x40000000), %bb.57(0x40000000)
@@ -78,16 +78,16 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr34_sgpr35 = S_MOV_B64 -1
- ; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr46_sgpr47 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr44_sgpr45 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr42_sgpr43 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr54_sgpr55 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr52_sgpr53 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr48_sgpr49 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr38_sgpr39 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr54_vgpr55 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
@@ -368,17 +368,17 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr42 = V_ADD_CO_U32_e32 1024, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $sgpr34_sgpr35 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_MOV_B64 -1
- ; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr46_sgpr47 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr44_sgpr45 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr42_sgpr43 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr54_sgpr55 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr52_sgpr53 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr43, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_LT_I16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr48_sgpr49 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr54_vgpr55 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
@@ -415,8 +415,8 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr44 = V_ADD_CO_U32_e32 2048, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr58_sgpr59 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $sgpr60_sgpr61 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr60_sgpr61 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr62_sgpr63 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr45, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
@@ -468,10 +468,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr56 = V_ADD_CO_U32_e32 3072, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $sgpr58_sgpr59 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr58_sgpr59 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr57, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr68_sgpr69 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr54_vgpr55 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
@@ -590,7 +590,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF implicit-def $vgpr16
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = lr-split S_MOV_B64 0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.45.Flow26:
; GFX90A-NEXT: successors: %bb.47(0x80000000)
@@ -619,7 +619,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr0 = FLAT_LOAD_UBYTE killed renamable $vgpr0_vgpr1, 1024, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i51)
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $sgpr70_sgpr71 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr70_sgpr71 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr61, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $sgpr18_sgpr19, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
@@ -793,16 +793,16 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr18 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr10 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr14 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr46_sgpr47 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr44_sgpr45 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr42_sgpr43 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr54_sgpr55 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr52_sgpr53 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr50_sgpr51 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr48_sgpr49 = lr-split S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr38_sgpr39 = lr-split S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr54_vgpr55 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
@@ -816,8 +816,8 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr40_vgpr41 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr46_vgpr47 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr20 = COPY renamable $vgpr5, implicit $exec
- ; GFX90A-NEXT: renamable $sgpr23 = S_MOV_B32 0
- ; GFX90A-NEXT: renamable $sgpr34_sgpr35 = S_MOV_B64 0
+ ; GFX90A-NEXT: renamable $sgpr23 = lr-split S_MOV_B32 0
+ ; GFX90A-NEXT: renamable $sgpr34_sgpr35 = lr-split S_MOV_B64 0
; GFX90A-NEXT: S_BRANCH %bb.7
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.58.bb105:
diff --git a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
index 5c564decd1e7d..c6355e98b2cfb 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
@@ -36,7 +36,7 @@ body: |
; GCN-NEXT: $noreg = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: renamable $agpr0 = lr-split COPY killed renamable $vgpr62
; GCN-NEXT: $exec = S_MOV_B64 killed $noreg
- ; GCN-NEXT: renamable $vgpr62 = IMPLICIT_DEF
+ ; GCN-NEXT: renamable $vgpr62 = lr-split IMPLICIT_DEF
; GCN-NEXT: dead renamable $vgpr62 = V_AND_B32_e32 1, killed $vgpr62, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir b/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
index be841ea70c6e2..ea5292eb4b306 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
@@ -88,7 +88,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 1, [[COPY]], implicit $exec
- ; GCN-NEXT: $vgpr0 = V_MOV_B32_e32 [[V_ADD_U32_e32_]], implicit $exec
+ ; GCN-NEXT: $vgpr0 = lr-split V_MOV_B32_e32 [[V_ADD_U32_e32_]], implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG $vgpr0, implicit [[V_ADD_U32_e32_]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = V_ADD_U32_e32 1, %0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/dead_bundle.mir b/llvm/test/CodeGen/AMDGPU/dead_bundle.mir
index 77d4a437d167d..752aee782c584 100644
--- a/llvm/test/CodeGen/AMDGPU/dead_bundle.mir
+++ b/llvm/test/CodeGen/AMDGPU/dead_bundle.mir
@@ -21,7 +21,7 @@ body: |
; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_BUFFER_LOAD_DWORDX8_IMM undef renamable $sgpr0_sgpr1_sgpr2_sgpr3, 416, 0 :: (dereferenceable invariant load (s256), align 4)
; CHECK-NEXT: dead [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, $sgpr4, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: dead renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF
- ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_BUFFER_LOAD_DWORDX8_IMM undef renamable $sgpr0_sgpr1_sgpr2_sgpr3, 416, 0 :: (dereferenceable invariant load (s256), align 4)
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_BUFFER_LOAD_DWORDX8_IMM undef renamable $sgpr0_sgpr1_sgpr2_sgpr3, 416, 0 :: (dereferenceable invariant load (s256), align 4)
; CHECK-NEXT: renamable $sgpr3 = lr-split COPY killed renamable $sgpr7
; CHECK-NEXT: renamable $sgpr5 = lr-split COPY renamable $sgpr9
; CHECK-NEXT: dead undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY renamable $sgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir b/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
index 498a5cea9c3f2..73cb55460cc3e 100644
--- a/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
+++ b/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
@@ -24,9 +24,9 @@ body: |
; CHECK-NEXT: renamable $agpr0 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
; CHECK-NEXT: renamable $agpr1 = V_ACCVGPR_WRITE_B32_e64 1, implicit $exec
; CHECK-NEXT: renamable $agpr2 = V_ACCVGPR_WRITE_B32_e64 2, implicit $exec
- ; CHECK-NEXT: renamable $vgpr0 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: renamable $vgpr0 = lr-split V_MOV_B32_e32 3, implicit $exec
; CHECK-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
- ; CHECK-NEXT: renamable $vgpr0 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: renamable $vgpr0 = lr-split V_MOV_B32_e32 4, implicit $exec
; CHECK-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $agpr0
; CHECK-NEXT: S_NOP 0, implicit killed renamable $agpr1
@@ -78,9 +78,9 @@ body: |
; CHECK-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec
; CHECK-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $exec
; CHECK-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $exec
- ; CHECK-NEXT: renamable $vgpr0 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: renamable $vgpr0 = lr-split V_MOV_B32_e32 3, implicit $exec
; CHECK-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
- ; CHECK-NEXT: renamable $vgpr0 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: renamable $vgpr0 = lr-split V_MOV_B32_e32 4, implicit $exec
; CHECK-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $agpr0
; CHECK-NEXT: S_NOP 0, implicit killed renamable $agpr1
diff --git a/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
index 63ee4473a56e5..af61fad946b32 100644
--- a/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
+++ b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
@@ -56,10 +56,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $sgpr12 = IMPLICIT_DEF
; CHECK-NEXT: SI_SPILL_S512_SAVE renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s512) into %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = lr-split IMPLICIT_DEF
; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_2:%[0-9]+]].sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = SI_SPILL_S512_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s512) from %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = lr-split IMPLICIT_DEF
; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_3:%[0-9]+]].sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], undef renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
@@ -67,7 +67,7 @@ body: |
; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = lr-split COPY killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
- ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = lr-split IMPLICIT_DEF
; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_4:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], killed renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = lr-split COPY killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27
; CHECK-NEXT: S_BRANCH %bb.7
diff --git a/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
index a8419a4bfc749..7387532f03ddd 100644
--- a/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
+++ b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
@@ -53,10 +53,10 @@ body: |
; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $sgpr12 = IMPLICIT_DEF
- ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = lr-split IMPLICIT_DEF
; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_2:%[0-9]+]].sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
- ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
- ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = lr-split S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
+ ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = lr-split IMPLICIT_DEF
; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_3:%[0-9]+]].sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], undef renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
@@ -64,7 +64,7 @@ body: |
; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = lr-split COPY killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
- ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = lr-split IMPLICIT_DEF
; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_4:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], killed renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = lr-split COPY killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27
; CHECK-NEXT: S_BRANCH %bb.6
diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
index fadb15dd2fb79..55359bec1aec8 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
@@ -34,7 +34,7 @@ define amdgpu_kernel void @widget(ptr addrspace(1) %arg, i1 %arg1) #0 {
; CHECK-NEXT: liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5, $vgpr0_vgpr1:0x000000000000000C, $vgpr2_vgpr3, $sgpr20_sgpr21_sgpr22_sgpr23
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = S_MOV_B64 0
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = lr-split S_MOV_B64 0
; CHECK-NEXT: renamable $sgpr6_sgpr7 = IMPLICIT_DEF
; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.11, implicit killed $vcc
; CHECK-NEXT: {{ $}}
@@ -114,7 +114,7 @@ define amdgpu_kernel void @widget(ptr addrspace(1) %arg, i1 %arg1) #0 {
; CHECK-NEXT: successors: %bb.7(0x80000000)
; CHECK-NEXT: liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr6_sgpr7, $vgpr0_vgpr1:0x000000000000000C, $vgpr2_vgpr3, $sgpr20_sgpr21_sgpr22_sgpr23
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr8 = S_MOV_B32 0
+ ; CHECK-NEXT: renamable $sgpr8 = lr-split S_MOV_B32 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.Flow:
; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)
@@ -124,7 +124,7 @@ define amdgpu_kernel void @widget(ptr addrspace(1) %arg, i1 %arg1) #0 {
; CHECK-NEXT: renamable $sgpr6 = S_CSELECT_B32 1, 0, implicit killed $scc
; CHECK-NEXT: renamable $sgpr4_sgpr5 = S_MOV_B64 -1
; CHECK-NEXT: S_CMP_LG_U32 killed renamable $sgpr6, 1, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr6_sgpr7 = S_MOV_B64 -1
+ ; CHECK-NEXT: renamable $sgpr6_sgpr7 = lr-split S_MOV_B64 -1
; CHECK-NEXT: S_CBRANCH_SCC1 %bb.9, implicit killed $scc
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.bb11:
diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
index 6b46a7817e1c8..854ab1da5e626 100644
--- a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
+++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
@@ -84,7 +84,7 @@ body: |
; COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec
; COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec
; COALESCE-NEXT: undef [[AV_MOV_1:%[0-9]+]].sub1:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = lr-split S_MOV_B32 0
; COALESCE-NEXT: {{ $}}
; COALESCE-NEXT: bb.1:
; COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
@@ -138,7 +138,7 @@ body: |
; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec
; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec
; GFX908-COALESCE-NEXT: undef [[AV_MOV_1:%[0-9]+]].sub1:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = lr-split S_MOV_B32 0
; GFX908-COALESCE-NEXT: {{ $}}
; GFX908-COALESCE-NEXT: bb.1:
; GFX908-COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
diff --git a/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir b/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
index c670df94f616e..f03bad5fa8526 100644
--- a/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+++ b/llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
@@ -186,7 +186,7 @@ body: |
; GCN-NEXT: SI_SPILL_S32_SAVE [[S_LOAD_DWORD_IMM]], %stack.11, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.11, addrspace 5)
; GCN-NEXT: [[S_LOAD_DWORDX8_IMM2:%[0-9]+]]:sgpr_256 = S_LOAD_DWORDX8_IMM undef [[V_READFIRSTLANE_B32_2]], 652, 0 :: ("amdgpu-noclobber" load (s256), align 8, addrspace 1)
; GCN-NEXT: SI_SPILL_S256_SAVE [[S_LOAD_DWORDX8_IMM2]], %stack.6, implicit $exec, implicit $sgpr32 :: (store (s256) into %stack.6, align 4, addrspace 5)
- ; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
+ ; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = lr-split S_MOV_B64 0
; GCN-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S_MOV_B64_]], 0, 0 :: ("amdgpu-noclobber" load (s32), align 8, addrspace 1)
; GCN-NEXT: SI_SPILL_S32_SAVE [[S_LOAD_DWORD_IMM1]], %stack.3, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.3, addrspace 5)
; GCN-NEXT: SI_SPILL_S64_SAVE [[V_READFIRSTLANE_B32_2]], %stack.1, implicit $exec, implicit $sgpr32 :: (store (s64) into %stack.1, align 4, addrspace 5)
@@ -224,7 +224,7 @@ body: |
; GCN-NEXT: SI_SPILL_S64_SAVE [[V_READFIRSTLANE_B32_]], %stack.0, implicit $exec, implicit $sgpr32 :: (store (s64) into %stack.0, align 4, addrspace 5)
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = lr-split COPY [[V_READFIRSTLANE_B32_]]
; GCN-NEXT: dead [[S_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY1]], 0, 0 :: ("amdgpu-noclobber" load (s32), addrspace 1)
- ; GCN-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0
+ ; GCN-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = lr-split S_MOV_B64 0
; GCN-NEXT: [[S_LOAD_DWORD_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S_MOV_B64_1]], 0, 0 :: ("amdgpu-noclobber" load (s32), addrspace 1)
; GCN-NEXT: [[SI_SPILL_S64_RESTORE1:%[0-9]+]]:sgpr_64 = SI_SPILL_S64_RESTORE %stack.2, implicit $exec, implicit $sgpr32 :: (load (s64) from %stack.2, align 4, addrspace 5)
; GCN-NEXT: undef [[COPY2:%[0-9]+]].sub1:sgpr_64 = lr-split COPY [[SI_SPILL_S64_RESTORE1]].sub1
@@ -289,7 +289,7 @@ body: |
; GCN-NEXT: dead [[V_CMP_GT_F32_e64_10:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, 0, 0, [[COPY4]].sub0, 0, implicit $mode, implicit $exec
; GCN-NEXT: dead [[V_CMP_GT_F32_e64_11:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, 0, 0, [[COPY4]].sub1, 0, implicit $mode, implicit $exec
; GCN-NEXT: dead [[V_CMP_GT_F32_e64_12:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, 0, 0, [[COPY4]].sub2, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[DEF6:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF6:%[0-9]+]]:sreg_32 = lr-split IMPLICIT_DEF
; GCN-NEXT: dead [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 undef [[DEF5]], [[DEF6]], implicit-def dead $scc
; GCN-NEXT: dead [[DEF7:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: dead [[DEF8:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
@@ -397,7 +397,7 @@ body: |
; GCN-NEXT: S_CMP_EQ_U32 [[SI_SPILL_S256_RESTORE6]].sub7, 0, implicit-def $scc
; GCN-NEXT: [[SI_SPILL_S32_RESTORE6:%[0-9]+]]:sgpr_32 = SI_SPILL_S32_RESTORE %stack.7, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.7, addrspace 5)
; GCN-NEXT: dead [[V_CMP_GT_F32_e64_45:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, 0, 0, [[SI_SPILL_S32_RESTORE6]], 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[DEF19:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF19:%[0-9]+]]:sreg_32 = lr-split IMPLICIT_DEF
; GCN-NEXT: dead [[S_AND_B32_10:%[0-9]+]]:sreg_32 = S_AND_B32 [[DEF19]], undef [[S_LOAD_DWORD_IMM6]], implicit-def dead $scc
; GCN-NEXT: dead [[S_AND_B32_11:%[0-9]+]]:sreg_32 = S_AND_B32 undef [[S_AND_B32_10]], [[S_MOV_B32_2]], implicit-def dead $scc
; GCN-NEXT: $vcc = COPY undef [[S_AND_B32_11]]
diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir b/llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
index 31b8e91830bee..2f1e77f330998 100644
--- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
+++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
@@ -17,9 +17,9 @@ body: |
; CHECK-NEXT: undef [[S_LOAD_DWORD_IMM:%[0-9]+]].sub1:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 1
; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 0
- ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 0
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = lr-split S_MOV_B32 0
; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2 [[S_MOV_B32_]], [[S_MOV_B32_1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
- ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = lr-split S_MOV_B32 1
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -30,8 +30,8 @@ body: |
; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2 [[S_MOV_B32_]], [[S_MOV_B32_1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
; CHECK-NEXT: $vcc_lo = COPY $exec_lo
- ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 0
- ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = lr-split S_MOV_B32 0
+ ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = lr-split S_MOV_B32 1
; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc_lo, implicit $vcc_lo, implicit $vcc_lo
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
@@ -89,7 +89,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK-NEXT: undef [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub1:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]], 24, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = lr-split S_MOV_B32 1
; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir b/llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
index 16dd33326213b..ea4a03359f957 100644
--- a/llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
@@ -33,30 +33,30 @@ body: |
S_NOP 0, implicit %2.sub1
; %1: both lanes used after barrier, rematerialized as S_MOV_B64, not shrunk.
- ; CHECK: renamable $[[REG1LO:sgpr[0-9]+]]_[[REG1HI:sgpr[0-9]+]] = S_MOV_B64 180388627769
+ ; CHECK: renamable $[[REG1LO:sgpr[0-9]+]]_[[REG1HI:sgpr[0-9]+]] = lr-split S_MOV_B64 180388627769
; CHECK-NEXT: S_NOP 0, implicit renamable $[[REG1HI]]
; CHECK-NEXT: S_NOP 0, implicit killed renamable $[[REG1LO]]
S_NOP 0, implicit %1.sub1
S_NOP 0, implicit %1.sub0
; %3: only sub3 used - shrink to S_MOV_B32 with Hi_32(0x0000000700000065) = 7.
- ; CHECK: renamable $[[REG3:sgpr[0-9]+]] = S_MOV_B32 7
+ ; CHECK: renamable $[[REG3:sgpr[0-9]+]] = lr-split S_MOV_B32 7
; CHECK-NEXT: S_NOP 0, implicit renamable $[[REG3]]
; CHECK-NEXT: S_NOP 0, implicit killed renamable $[[REG3]]
S_NOP 0, implicit %3.sub3
S_NOP 0, implicit %3.sub3
; %4: only sub2 used - shrink to S_MOV_B32 with Lo_32(0x0000002A00000539) = 1337.
- ; CHECK: renamable $[[REG4:sgpr[0-9]+]] = S_MOV_B32 1337
+ ; CHECK: renamable $[[REG4:sgpr[0-9]+]] = lr-split S_MOV_B32 1337
; CHECK-NEXT: S_NOP 0, implicit killed renamable $[[REG4]]
S_NOP 0, implicit %4.sub2
; %5: sub0_sub1 def, only sub1 used - shrink to S_MOV_B32 with Hi_32(0x0000002A00000539) = 42.
- ; CHECK: renamable $[[REG5:sgpr[0-9]+]] = S_MOV_B32 42
+ ; CHECK: renamable $[[REG5:sgpr[0-9]+]] = lr-split S_MOV_B32 42
; CHECK-NEXT: S_NOP 0, implicit killed renamable $[[REG5]]
S_NOP 0, implicit %5.sub1
- ; CHECK: renamable $[[REG6:sgpr[0-9]+]] = S_MOV_B32 65536
+ ; CHECK: renamable $[[REG6:sgpr[0-9]+]] = lr-split S_MOV_B32 65536
; CHECK-NEXT: S_NOP 0, implicit killed renamable $[[REG6]]
S_NOP 0, implicit %6.sub0
diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
index 06ba87dd7653a..2b6ccc30eea80 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
@@ -7,7 +7,7 @@
# GCN-DAG: undef %[[REG0:[0-9]+]].sub0:sgpr_64 = COPY $sgpr5
# GCN-DAG: undef %[[REG1:[0-9]+]].sub0:sgpr_64 = COPY $sgpr2
# GCN-DAG: %[[REG0]].sub1:sgpr_64 = S_MOV_B32 1
-# GCN-DAG: %[[REG1]].sub1:sgpr_64 = S_MOV_B32 1
+# GCN-DAG: %[[REG1]].sub1:sgpr_64 = lr-split S_MOV_B32 1
--- |
define amdgpu_vs void @regcoal-subrange-join(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 %arg6) local_unnamed_addr #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir b/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
index 29373f9df5d30..32a60123dd431 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
@@ -42,7 +42,7 @@ body: |
; GCN-NEXT: renamable $sgpr2 = S_MOV_B32 3, implicit $m0
; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.0, addrspace 5)
; GCN-NEXT: dead [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit killed $sgpr0, implicit killed $sgpr2
- ; GCN-NEXT: renamable $sgpr0 = S_MUL_I32 renamable $sgpr5, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_MUL_I32 renamable $sgpr5, 3
; GCN-NEXT: dead [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 killed $sgpr0, implicit $exec
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr5
$m0 = IMPLICIT_DEF
@@ -65,7 +65,7 @@ body: |
; GCN-NEXT: renamable $sgpr4_sgpr5 = S_MOV_B64 renamable $sgpr10_sgpr11
; GCN-NEXT: SI_SPILL_S64_SAVE killed renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sp_reg :: (store (s64) into %stack.0, align 4, addrspace 5)
; GCN-NEXT: renamable $sgpr4_sgpr5 = S_MOV_B64 3, implicit $m0
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_MOV_B64 2, implicit $m0
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_MOV_B64 2, implicit $m0
; GCN-NEXT: dead [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit killed $sgpr0_sgpr1, implicit killed $sgpr4_sgpr5
; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s64) from %stack.0, align 4, addrspace 5)
; GCN-NEXT: dead [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO killed $sgpr4_sgpr5, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir b/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
index f2d4e02061ab9..8855614d40cfe 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
@@ -58,7 +58,7 @@ body: |
; CHECK-LABEL: name: rematerialize_physreg_sub_def_no_live_sub_def_0
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1
+ ; CHECK-NEXT: dead $vgpr0_vgpr1 = lr-split V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1
; CHECK-NEXT: SI_RETURN implicit killed $vgpr1
%0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec
%1:vgpr_32 = COPY %0.sub1
@@ -76,7 +76,7 @@ body: |
; CHECK-LABEL: name: rematerialize_physreg_sub_def_no_live_sub_def_1
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $vgpr1_vgpr2 = V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1
+ ; CHECK-NEXT: dead $vgpr1_vgpr2 = lr-split V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1
; CHECK-NEXT: SI_RETURN implicit killed $vgpr1
%0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec
%1:vgpr_32 = COPY %0.sub0
diff --git a/llvm/test/CodeGen/AMDGPU/remat-smrd.mir b/llvm/test/CodeGen/AMDGPU/remat-smrd.mir
index efd9893c604fd..42beaedd84c70 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-smrd.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-smrd.mir
@@ -13,10 +13,10 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr2_sgpr3 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 4, 0 :: (dereferenceable invariant load (s32), addrspace 4)
- ; GCN-NEXT: renamable $sgpr0 = S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 8, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 8, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr2_sgpr3
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -41,9 +41,9 @@ body: |
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s64), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr2_sgpr3 = lr-split S_LOAD_DWORDX2_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s64), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr2_sgpr3 = lr-split S_LOAD_DWORDX2_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s64), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -68,9 +68,9 @@ body: |
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s128), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s128), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = lr-split S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s128), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s128), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = lr-split S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s128), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -95,9 +95,9 @@ body: |
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s256), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s256), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s256), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s256), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s256), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -122,9 +122,9 @@ body: |
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s512), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s512), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = lr-split S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 4, 0 :: (dereferenceable invariant load (s512), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s512), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = lr-split S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 8, 0 :: (dereferenceable invariant load (s512), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -148,11 +148,11 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 128, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 32, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 32, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
; GCN-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = COPY killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 128, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -178,11 +178,11 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 128, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = lr-split S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
; GCN-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = KILL killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19, implicit renamable $sgpr4_sgpr5_sgpr6_sgpr7
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 128, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = KILL killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, implicit renamable $sgpr0_sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
@@ -208,7 +208,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 128, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = lr-split S_LOAD_DWORDX16_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s512), align 4, addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -233,11 +233,11 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr0_sgpr1 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 128, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 16, 0 :: (dereferenceable invariant load (s128), align 4, addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = lr-split S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 16, 0 :: (dereferenceable invariant load (s128), align 4, addrspace 4)
; GCN-NEXT: renamable $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed renamable $sgpr4_sgpr5_sgpr6_sgpr7
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr8_sgpr9_sgpr10_sgpr11
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 128, 0 :: (dereferenceable invariant load (s256), align 4, addrspace 4)
- ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s128), align 4, addrspace 4)
+ ; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = lr-split S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 0, 0 :: (dereferenceable invariant load (s128), align 4, addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr0_sgpr1
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -298,9 +298,9 @@ body: |
; GCN-NEXT: renamable $sgpr0 = COPY $sgpr10
; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_SGPR renamable $sgpr2_sgpr3, renamable $sgpr0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_SGPR renamable $sgpr2_sgpr3, renamable $sgpr0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr1 = lr-split S_LOAD_DWORD_SGPR renamable $sgpr2_sgpr3, renamable $sgpr0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_SGPR renamable $sgpr2_sgpr3, renamable $sgpr0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr1 = lr-split S_LOAD_DWORD_SGPR renamable $sgpr2_sgpr3, renamable $sgpr0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr2_sgpr3, implicit killed renamable $sgpr0
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -327,9 +327,9 @@ body: |
; GCN-NEXT: renamable $sgpr0 = COPY $sgpr10
; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_SGPR_IMM renamable $sgpr2_sgpr3, renamable $sgpr0, 0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_SGPR_IMM renamable $sgpr2_sgpr3, renamable $sgpr0, 4, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr1 = lr-split S_LOAD_DWORD_SGPR_IMM renamable $sgpr2_sgpr3, renamable $sgpr0, 4, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_SGPR_IMM renamable $sgpr2_sgpr3, renamable $sgpr0, 8, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr1 = lr-split S_LOAD_DWORD_SGPR_IMM renamable $sgpr2_sgpr3, renamable $sgpr0, 8, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr2_sgpr3, implicit killed renamable $sgpr0
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -385,10 +385,10 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
; GCN-NEXT: renamable $sgpr1 = S_BUFFER_LOAD_DWORD_IMM renamable $sgpr4_sgpr5_sgpr6_sgpr7, 4, 0 :: (dereferenceable invariant load (s32), addrspace 4)
- ; GCN-NEXT: renamable $sgpr0 = S_BUFFER_LOAD_DWORD_IMM renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_BUFFER_LOAD_DWORD_IMM renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_BUFFER_LOAD_DWORD_IMM renamable $sgpr4_sgpr5_sgpr6_sgpr7, 8, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_BUFFER_LOAD_DWORD_IMM renamable $sgpr4_sgpr5_sgpr6_sgpr7, 8, 0 :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7
%0:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
@@ -412,10 +412,10 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr2_sgpr3 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr1 = S_SCRATCH_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 4, 0, implicit $flat_scr :: (dereferenceable invariant load (s32), addrspace 4)
- ; GCN-NEXT: renamable $sgpr0 = S_SCRATCH_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 0, 0, implicit $flat_scr :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_SCRATCH_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 0, 0, implicit $flat_scr :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_SCRATCH_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 8, 0, implicit $flat_scr :: (dereferenceable invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_SCRATCH_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 8, 0, implicit $flat_scr :: (dereferenceable invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr2_sgpr3
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
@@ -439,10 +439,10 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $sgpr2_sgpr3 = COPY $sgpr8_sgpr9
; GCN-NEXT: renamable $sgpr1 = S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 4, 0 :: (invariant load (s32), addrspace 4)
- ; GCN-NEXT: renamable $sgpr0 = S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 0, 0 :: (invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 0, 0 :: (invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 8, 0 :: (invariant load (s32), addrspace 4)
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_LOAD_DWORD_IMM renamable $sgpr2_sgpr3, 8, 0 :: (invariant load (s32), addrspace 4)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0, implicit killed renamable $sgpr2_sgpr3
%0:sreg_64_xexec = COPY $sgpr8_sgpr9
diff --git a/llvm/test/CodeGen/AMDGPU/remat-sop.mir b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
index 4cf0f7a2722bd..9bd4b383e9130 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-sop.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
@@ -11,7 +11,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_MOV_B32 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_MOV_B32 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_MOV_B32 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_MOV_B32 1
@@ -64,9 +64,9 @@ body: |
; GCN: renamable $sgpr0 = IMPLICIT_DEF
; GCN-NEXT: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
+ ; GCN-NEXT: renamable $sgpr1 = lr-split S_MOV_B32 renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
+ ; GCN-NEXT: renamable $sgpr1 = lr-split S_MOV_B32 renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
@@ -92,10 +92,10 @@ body: |
; GCN-LABEL: name: test_no_remat_s_mov_b32_vreg_src_short_lr
; GCN: renamable $sgpr0 = IMPLICIT_DEF
; GCN-NEXT: renamable $sgpr1 = S_MOV_B32 killed renamable $sgpr0
- ; GCN-NEXT: renamable $sgpr0 = IMPLICIT_DEF
+ ; GCN-NEXT: renamable $sgpr0 = lr-split IMPLICIT_DEF
; GCN-NEXT: renamable $sgpr0 = S_MOV_B32 killed renamable $sgpr0
; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr0, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.1, addrspace 5)
- ; GCN-NEXT: renamable $sgpr0 = IMPLICIT_DEF
+ ; GCN-NEXT: renamable $sgpr0 = lr-split IMPLICIT_DEF
; GCN-NEXT: renamable $sgpr0 = S_MOV_B32 killed renamable $sgpr0
; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr0, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.0, addrspace 5)
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
@@ -123,7 +123,7 @@ body: |
; GCN-NEXT: renamable $sgpr2_sgpr3 = S_MOV_B64 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_MOV_B64 3
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_MOV_B64 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_ENDPGM 0
%0:sgpr_64 = S_MOV_B64 1
@@ -144,7 +144,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_BREV_B32 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_BREV_B32 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_BREV_B32 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_BREV_B32 1
@@ -165,7 +165,7 @@ body: |
; GCN-NEXT: renamable $sgpr2_sgpr3 = S_BREV_B64 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_BREV_B64 3
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_BREV_B64 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_ENDPGM 0
%0:sgpr_64 = S_BREV_B64 1
@@ -186,7 +186,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FF0_I32_B32 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FF0_I32_B32 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FF0_I32_B32 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FF0_I32_B32 1
@@ -207,7 +207,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FF1_I32_B32 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FF1_I32_B32 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FF1_I32_B32 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FF1_I32_B32 1
@@ -228,7 +228,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FF0_I32_B64 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FF0_I32_B64 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FF0_I32_B64 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FF0_I32_B64 1
@@ -249,7 +249,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FF1_I32_B64 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FF1_I32_B64 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FF1_I32_B64 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FF1_I32_B64 1
@@ -270,7 +270,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FLBIT_I32_B32 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FLBIT_I32_B32 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FLBIT_I32_B32 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FLBIT_I32_B32 1
@@ -291,7 +291,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FLBIT_I32_B64 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FLBIT_I32_B64 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FLBIT_I32_B64 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FLBIT_I32_B64 1
@@ -312,7 +312,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FLBIT_I32 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FLBIT_I32 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FLBIT_I32 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FLBIT_I32 1
@@ -333,7 +333,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_FLBIT_I32_I64 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_FLBIT_I32_I64 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_FLBIT_I32_I64 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_FLBIT_I32_I64 1
@@ -354,7 +354,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_SEXT_I32_I8 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_SEXT_I32_I8 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_SEXT_I32_I8 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_SEXT_I32_I8 1
@@ -375,7 +375,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_SEXT_I32_I16 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_SEXT_I32_I16 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_SEXT_I32_I16 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_SEXT_I32_I16 1
@@ -396,7 +396,7 @@ body: |
; GCN-NEXT: renamable $sgpr2_sgpr3 = S_BITREPLICATE_B64_B32 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_BITREPLICATE_B64_B32 3
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_BITREPLICATE_B64_B32 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_ENDPGM 0
%0:sgpr_64 = S_BITREPLICATE_B64_B32 1
@@ -417,7 +417,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_BFM_B32 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_BFM_B32 3, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_BFM_B32 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_BFM_B32 1, 1
@@ -438,7 +438,7 @@ body: |
; GCN-NEXT: renamable $sgpr2_sgpr3 = S_BFM_B64 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_BFM_B64 3, 3
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_BFM_B64 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_ENDPGM 0
%0:sgpr_64 = S_BFM_B64 1, 1
@@ -459,7 +459,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_MUL_I32 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_MUL_I32 3, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_MUL_I32 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_MUL_I32 1, 1
@@ -480,7 +480,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_MUL_HI_I32 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_MUL_HI_I32 3, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_MUL_HI_I32 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_MUL_HI_I32 1, 1
@@ -501,7 +501,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_MUL_HI_U32 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_MUL_HI_U32 3, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_MUL_HI_U32 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_MUL_HI_U32 1, 1
@@ -522,7 +522,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_PACK_LL_B32_B16 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_PACK_LL_B32_B16 3, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_PACK_LL_B32_B16 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_PACK_LL_B32_B16 1, 1
@@ -543,7 +543,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_PACK_LH_B32_B16 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_PACK_LH_B32_B16 3, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_PACK_LH_B32_B16 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_PACK_LH_B32_B16 1, 1
@@ -564,7 +564,7 @@ body: |
; GCN-NEXT: renamable $sgpr1 = S_PACK_HH_B32_B16 2, 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN-NEXT: renamable $sgpr0 = S_PACK_HH_B32_B16 3, 3
+ ; GCN-NEXT: renamable $sgpr0 = lr-split S_PACK_HH_B32_B16 3, 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_PACK_HH_B32_B16 1, 1
@@ -587,7 +587,7 @@ body: |
; GCN-NEXT: renamable $sgpr2_sgpr3 = S_GETPC_B64_pseudo
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_GETPC_B64_pseudo
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_GETPC_B64_pseudo
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_ENDPGM 0
%0:sgpr_64 = S_GETPC_B64_pseudo
@@ -614,7 +614,7 @@ body: |
; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.1, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.1, addrspace 5)
; GCN-NEXT: renamable $sgpr1 = COPY killed renamable $sgpr3
; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.2, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.2, addrspace 5)
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_GETPC_B64_pseudo
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_GETPC_B64_pseudo
; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr0, %stack.4, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.4, addrspace 5)
; GCN-NEXT: renamable $sgpr0 = COPY killed renamable $sgpr1
; GCN-NEXT: SI_SPILL_S32_SAVE killed renamable $sgpr0, %stack.5, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.5, addrspace 5)
@@ -665,7 +665,7 @@ body: |
; GCN-NEXT: renamable $sgpr2_sgpr3 = S_MOV_B64_IMM_PSEUDO 2
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
- ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_MOV_B64_IMM_PSEUDO 3
+ ; GCN-NEXT: renamable $sgpr0_sgpr1 = lr-split S_MOV_B64_IMM_PSEUDO 3
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
; GCN-NEXT: S_ENDPGM 0
%0:sgpr_64 = S_MOV_B64_IMM_PSEUDO 1
diff --git a/llvm/test/CodeGen/AMDGPU/remat-through-copy.mir b/llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
index d47e70b8a9024..1042f020ff313 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
@@ -21,17 +21,17 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $sgpr2, $vgpr0, $vgpr2, $sgpr0_sgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = lr-split V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = lr-split V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = lr-split V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = lr-split V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = lr-split V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = lr-split V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
; CHECK-NEXT: renamable $sgpr2 = S_ADD_U32 killed renamable $sgpr2, 1, implicit-def $scc
; CHECK-NEXT: S_CMP_LT_U32 renamable $sgpr2, 10, implicit-def $scc
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-remat-in-bb-prolog.mir b/llvm/test/CodeGen/AMDGPU/sgpr-remat-in-bb-prolog.mir
new file mode 100644
index 0000000000000..3f0f1aeb22c60
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-remat-in-bb-prolog.mir
@@ -0,0 +1,82 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -start-before=greedy,2 -stop-after=greedy,2 -stress-regalloc=3 -o - %s | FileCheck %s
+
+# The sgpr-regalloc pipeline placed a rematerialized SMEM load (flagged
+# lr-split) at the top of the Flow block, before the exec restore of the
+# if/else region. The vgpr-regalloc pipeline must treat it as part of the block
+# prolog: the spill it inserts in bb.3 has to be placed after the
+# S_OR_SAVEEXEC_B64, otherwise it is only executed for the lanes of the first
+# branch arm.
+
+# CHECK-LABEL: name: sgpr_remat_in_bb_prolog
+# CHECK: bb.3:
+# CHECK: lr-split S_LOAD_DWORDX8_IMM_ec
+# CHECK-NEXT: S_OR_SAVEEXEC_B64
+# CHECK-NEXT: SI_SPILL_AV64_SAVE
+# CHECK-NEXT: V_LSHL_ADD_U64_e64
+
+--- |
+ define amdgpu_kernel void @sgpr_remat_in_bb_prolog() { ret void }
+...
+---
+name: sgpr_remat_in_bb_prolog
+tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
+body: |
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr4_sgpr5, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr64_sgpr65, $sgpr68_sgpr69, $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ %0:vreg_64_align2 = COPY $vgpr0_vgpr1
+ %1:vreg_64_align2 = COPY $vgpr2_vgpr3
+ $exec = S_MOV_B64_term killed renamable $sgpr30_sgpr31
+ S_CBRANCH_EXECZ %bb.2, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+ liveins: $sgpr4_sgpr5, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr64_sgpr65, $sgpr68_sgpr69
+
+ bb.2:
+ successors: %bb.5(0x40000000), %bb.3(0x40000000)
+ liveins: $sgpr4_sgpr5, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr64_sgpr65, $sgpr68_sgpr69
+
+ %2:vreg_64_align2 = COPY $sgpr68_sgpr69, implicit $exec
+ $exec = S_MOV_B64_term killed renamable $sgpr34_sgpr35
+ S_CBRANCH_EXECZ %bb.3, implicit $exec
+ S_BRANCH %bb.5
+
+ bb.3:
+ successors: %bb.4(0x40000000), %bb.6(0x40000000)
+ liveins: $sgpr4_sgpr5, $sgpr28_sgpr29, $sgpr64_sgpr65
+
+ early-clobber renamable $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = lr-split S_LOAD_DWORDX8_IMM_ec renamable $sgpr4_sgpr5, 32, 0 :: (dereferenceable invariant load (s256), align 16, addrspace 4)
+ renamable $sgpr28_sgpr29 = S_OR_SAVEEXEC_B64 killed renamable $sgpr28_sgpr29, implicit-def $exec, implicit-def $scc, implicit $exec
+ %3:vreg_64_align2 = V_LSHL_ADD_U64_e64 $sgpr64_sgpr65, 0, %1, implicit $exec
+ $exec = S_XOR_B64_term $exec, renamable $sgpr28_sgpr29, implicit-def $scc
+ S_CBRANCH_EXECZ %bb.6, implicit $exec
+ S_BRANCH %bb.4
+
+ bb.4:
+ successors: %bb.6(0x80000000)
+ liveins: $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+
+ S_BRANCH %bb.6
+
+ bb.5:
+ successors: %bb.3(0x80000000)
+ liveins: $sgpr4_sgpr5, $sgpr28_sgpr29, $sgpr64_sgpr65
+
+ %2:vreg_64_align2 = COPY $sgpr64_sgpr65, implicit $exec
+ S_BRANCH %bb.3
+
+ bb.6:
+ liveins: $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+
+ %4:vreg_64_align2 = IMPLICIT_DEF
+ %5:vreg_64_align2 = IMPLICIT_DEF
+ %4:vreg_64_align2 = V_FMAC_F64_e32 %4, %5, %4, implicit $mode, implicit $exec
+ %6:vreg_64_align2 = V_FMA_F64_e64 1, %3, 0, %4, 0, 4607182418800017408, 0, 0, implicit $mode, implicit $exec
+ %7:vreg_64_align2 = V_LSHL_ADD_U64_e64 %2, 0, %0, implicit $exec
+ S_ENDPGM 0, implicit %6, implicit %7
+...
diff --git a/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir b/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
index 3c99fab308ad0..0a03c67ae9712 100644
--- a/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
+++ b/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
@@ -52,14 +52,14 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55:0x000000000000FC00
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr38_sgpr39, 56, 0 :: (dereferenceable invariant load (s256), align 8, addrspace 4)
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_LOAD_DWORDX8_IMM renamable $sgpr38_sgpr39, 56, 0 :: (dereferenceable invariant load (s256), align 8, addrspace 4)
; CHECK-NEXT: S_BRANCH %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55:0x000000000000FC00
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX8_IMM renamable $sgpr38_sgpr39, 56, 0 :: (dereferenceable invariant load (s256), align 8, addrspace 4)
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11 = lr-split S_LOAD_DWORDX8_IMM renamable $sgpr38_sgpr39, 56, 0 :: (dereferenceable invariant load (s256), align 8, addrspace 4)
; CHECK-NEXT: S_CMP_LG_U64 renamable $sgpr4_sgpr5, 0, implicit-def $scc
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
@@ -83,7 +83,7 @@ body: |
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed renamable $sgpr53
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; CHECK-NEXT: $sgpr6_sgpr7 = COPY killed renamable $sgpr36_sgpr37
- ; CHECK-NEXT: renamable $sgpr10_sgpr11 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr10_sgpr11 = lr-split IMPLICIT_DEF
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; CHECK-NEXT: S_ENDPGM 0
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir b/llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
index 2ceda1b9e16ac..ca855ed03ccb9 100644
--- a/llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
@@ -103,7 +103,7 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:av_1024 = IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_1024 = COPY [[DEF1]]
- ; CHECK-NEXT: [[DEF2:%[0-9]+]]:av_1024 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:av_1024 = lr-split IMPLICIT_DEF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir b/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
index 0bfd490a0ae68..e670e41d826f5 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
@@ -176,28 +176,28 @@ body: |
; CHECK-NEXT: undef [[COPY41:%[0-9]+]].sub0:vreg_128 = lr-split COPY [[COPY40]].sub0 {
; CHECK-NEXT: internal [[COPY41]].sub2:vreg_128 = lr-split COPY [[COPY40]].sub2
; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_27:%[0-9]+]].sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_27:%[0-9]+]].sub2:vreg_128 = lr-split V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub1, implicit $exec
; CHECK-NEXT: undef [[COPY42:%[0-9]+]].sub2:vreg_128 = lr-split COPY [[V_LSHRREV_B32_e32_27]].sub2
; CHECK-NEXT: [[COPY42:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e32 [[S_MOV_B32_1]], [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub1, implicit $exec
; CHECK-NEXT: undef [[COPY43:%[0-9]+]].sub0:vreg_128 = lr-split COPY [[COPY42]].sub0 {
; CHECK-NEXT: internal [[COPY43]].sub2:vreg_128 = lr-split COPY [[COPY42]].sub2
; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_28:%[0-9]+]].sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub0, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_28:%[0-9]+]].sub2:vreg_128 = lr-split V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub0, implicit $exec
; CHECK-NEXT: undef [[COPY44:%[0-9]+]].sub2:vreg_128 = lr-split COPY [[V_LSHRREV_B32_e32_28]].sub2
; CHECK-NEXT: [[COPY44:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e32 [[S_MOV_B32_1]], [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub0, implicit $exec
; CHECK-NEXT: undef [[COPY45:%[0-9]+]].sub0:vreg_128 = lr-split COPY [[COPY44]].sub0 {
; CHECK-NEXT: internal [[COPY45]].sub2:vreg_128 = lr-split COPY [[COPY44]].sub2
; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_29:%[0-9]+]].sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub3, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_29:%[0-9]+]].sub2:vreg_128 = lr-split V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub3, implicit $exec
; CHECK-NEXT: undef [[COPY46:%[0-9]+]].sub2:vreg_128 = lr-split COPY [[V_LSHRREV_B32_e32_29]].sub2
; CHECK-NEXT: [[COPY46:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e32 [[S_MOV_B32_1]], [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub3, implicit $exec
; CHECK-NEXT: undef [[COPY47:%[0-9]+]].sub0:vreg_128 = lr-split COPY [[COPY46]].sub0 {
; CHECK-NEXT: internal [[COPY47]].sub2:vreg_128 = lr-split COPY [[COPY46]].sub2
; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_30:%[0-9]+]].sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub2, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_30:%[0-9]+]].sub2:vreg_128 = lr-split V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub2, implicit $exec
; CHECK-NEXT: undef [[COPY48:%[0-9]+]].sub2:vreg_128 = lr-split COPY [[V_LSHRREV_B32_e32_30]].sub2
; CHECK-NEXT: [[COPY48:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e32 [[S_MOV_B32_1]], [[BUFFER_LOAD_DWORDX4_OFFSET5]].sub2, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_31:%[0-9]+]].sub2:vreg_128 = V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET6]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B32_e32_31:%[0-9]+]].sub2:vreg_128 = lr-split V_LSHRREV_B32_e32 16, [[BUFFER_LOAD_DWORDX4_OFFSET6]].sub1, implicit $exec
; CHECK-NEXT: undef [[COPY49:%[0-9]+]].sub2:vreg_128 = lr-split COPY [[V_LSHRREV_B32_e32_31]].sub2
; CHECK-NEXT: [[COPY49:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e32 [[S_MOV_B32_1]], [[BUFFER_LOAD_DWORDX4_OFFSET6]].sub1, implicit $exec
; CHECK-NEXT: [[V_LSHRREV_B32_e32_20:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e32 [[S_MOV_B32_1]], [[BUFFER_LOAD_DWORDX4_OFFSET6]].sub0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir b/llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
index 70d6975dad8f3..56962e1f9e141 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
@@ -193,8 +193,8 @@ body: |
; CHECK-NEXT: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 1065353216, implicit $exec
; CHECK-NEXT: [[AV_MOV_1:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 1073741824, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]]:vreg_1024_align2 = V_MFMA_F32_32X32X1F32_mac_vgprcd_e64 [[AV_MOV_]], [[AV_MOV_1]], [[GLOBAL_LOAD_DWORDX4_SADDR]], 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[AV_MOV_2:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 1073741824, implicit $exec
- ; CHECK-NEXT: [[AV_MOV_3:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 1065353216, implicit $exec
+ ; CHECK-NEXT: [[AV_MOV_2:%[0-9]+]]:av_32 = lr-split AV_MOV_B32_IMM_PSEUDO 1073741824, implicit $exec
+ ; CHECK-NEXT: [[AV_MOV_3:%[0-9]+]]:av_32 = lr-split AV_MOV_B32_IMM_PSEUDO 1065353216, implicit $exec
; CHECK-NEXT: early-clobber %5:vreg_1024_align2 = V_MFMA_F32_32X32X1F32_vgprcd_e64 [[AV_MOV_3]], [[AV_MOV_2]], [[GLOBAL_LOAD_DWORDX4_SADDR]], 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]].sub2:vreg_1024_align2 = COPY %5.sub0
; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX4_SADDR:%[0-9]+]].sub3:vreg_1024_align2 = COPY %5.sub1
diff --git a/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir b/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
index 2ef6908d3701d..0421e2daa9d19 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
+++ b/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
@@ -39,18 +39,18 @@ body: |
; CHECK-NEXT: renamable $vgpr0 = V_TRUNC_F32_e32 killed $vgpr0, implicit $mode, implicit $exec
; CHECK-NEXT: SI_SPILL_AV32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_AV128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5)
- ; CHECK-NEXT: renamable $vgpr0 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $vgpr0 = lr-split IMPLICIT_DEF
; CHECK-NEXT: renamable $vgpr7 = nofpexcept V_DIV_FIXUP_F32_e64 0, killed $vgpr0, 0, $vgpr7, 0, killed $vgpr3, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_AV128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5)
; CHECK-NEXT: renamable $vgpr0 = SI_SPILL_AV32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
; CHECK-NEXT: renamable $vgpr6 = nofpexcept V_FMA_F32_e64 1, killed $vgpr0, 0, $vgpr6, 0, killed $vgpr2, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: renamable $vgpr2_vgpr3 = lr-split COPY killed renamable $vgpr6_vgpr7
; CHECK-NEXT: renamable $vgpr6_vgpr7_vgpr8_vgpr9 = SI_SPILL_AV128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5)
- ; CHECK-NEXT: renamable $vgpr0 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $vgpr0 = lr-split IMPLICIT_DEF
; CHECK-NEXT: renamable $vgpr0 = nofpexcept V_DIV_FIXUP_F32_e64 0, killed $vgpr0, 0, $vgpr4, 0, $vgpr6, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: dead renamable $vgpr1 = V_FMA_F32_e64 0, killed $vgpr5, 0, $vgpr5, 0, killed $vgpr7, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: dead renamable $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load (s128), addrspace 5)
- ; CHECK-NEXT: renamable $vgpr4_vgpr5 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $vgpr4_vgpr5 = lr-split IMPLICIT_DEF
; CHECK-NEXT: GLOBAL_STORE_DWORDX4 killed renamable $vgpr4_vgpr5, renamable $vgpr0_vgpr1_vgpr2_vgpr3, 0, 0, implicit $exec :: (volatile store (s128), addrspace 1)
; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_AV128_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.1, align 4, addrspace 5)
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir b/llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
index 5cae8abc203b5..83b324734b0a0 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
@@ -11,8 +11,8 @@ body: |
; CHECK-NEXT: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
- ; CHECK-NEXT: [[V_PK_MOV_B32_1:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
- ; CHECK-NEXT: [[V_PK_MOV_B32_2:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: [[V_PK_MOV_B32_1:%[0-9]+]]:vreg_64_align2 = lr-split V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: [[V_PK_MOV_B32_2:%[0-9]+]]:vreg_64_align2 = lr-split V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0
; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
index d6c387838f1f6..4a6afacd239b0 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
@@ -13,7 +13,7 @@ body: |
; CHECK-NEXT: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = lr-split V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0
; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
@@ -57,7 +57,7 @@ body: |
; CHECK-NEXT: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[V_MOV_B:%[0-9]+]].sub0_sub1:vreg_192_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
- ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub2_sub3:vreg_192_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub2_sub3:vreg_192_align2 = lr-split V_MOV_B64_PSEUDO 0, implicit $exec
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
@@ -101,7 +101,7 @@ body: |
; CHECK-NEXT: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0:vreg_96 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub1:vreg_96 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub1:vreg_96 = lr-split AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0
; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
@@ -146,7 +146,7 @@ body: |
; CHECK-NEXT: liveins: $sgpr0_sgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0_sub1:vreg_192 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
- ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub2_sub3:vreg_192 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
+ ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub2_sub3:vreg_192 = lr-split AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/vopc-remat.mir b/llvm/test/CodeGen/AMDGPU/vopc-remat.mir
index d15ed36b1b1fe..d8803cfe0ba35 100644
--- a/llvm/test/CodeGen/AMDGPU/vopc-remat.mir
+++ b/llvm/test/CodeGen/AMDGPU/vopc-remat.mir
@@ -26,7 +26,7 @@ body: |
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5
; GCN-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr6_sgpr7, $exec, implicit-def $scc
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5
- ; GCN-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GCN-NEXT: renamable $sgpr4_sgpr5 = lr-split V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit [[COPY]], implicit [[COPY1]]
; GCN-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-tail.ll b/llvm/test/CodeGen/ARM/machine-outliner-tail.ll
index 407681bb795d2..acce472b510dc 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-tail.ll
+++ b/llvm/test/CodeGen/ARM/machine-outliner-tail.ll
@@ -11,24 +11,24 @@
; RUN: --stop-after=machine-outliner < %s | FileCheck %s --check-prefix=THUMB
; ARM-LABEL: name: OUTLINED_FUNCTION_0
-; ARM: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
-; ARM-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
-; ARM-NEXT: $r2 = MOVi 3, 14 /* CC::al */, $noreg, $noreg
-; ARM-NEXT: $r3 = MOVi 4, 14 /* CC::al */, $noreg, $noreg
+; ARM: $r0 = lr-split MOVi 1, 14 /* CC::al */, $noreg, $noreg
+; ARM-NEXT: $r1 = lr-split MOVi 2, 14 /* CC::al */, $noreg, $noreg
+; ARM-NEXT: $r2 = lr-split MOVi 3, 14 /* CC::al */, $noreg, $noreg
+; ARM-NEXT: $r3 = lr-split MOVi 4, 14 /* CC::al */, $noreg, $noreg
; ARM-NEXT: TAILJMPd @z
; THUMB-LABEL: name: OUTLINED_FUNCTION_0
-; THUMB: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; THUMB: $r0, dead $cpsr = lr-split tMOVi8 1, 14 /* CC::al */, $noreg
+; THUMB-NEXT: $r1, dead $cpsr = lr-split tMOVi8 2, 14 /* CC::al */, $noreg
+; THUMB-NEXT: $r2, dead $cpsr = lr-split tMOVi8 3, 14 /* CC::al */, $noreg
+; THUMB-NEXT: $r3, dead $cpsr = lr-split tMOVi8 4, 14 /* CC::al */, $noreg
; THUMB-NEXT: tTAILJMPdND @z, 14 /* CC::al */, $noreg
; MACHO-LABEL: name: OUTLINED_FUNCTION_0
-; MACHO: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
-; MACHO-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
-; MACHO-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
-; MACHO-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; MACHO: $r0, dead $cpsr = lr-split tMOVi8 1, 14 /* CC::al */, $noreg
+; MACHO-NEXT: $r1, dead $cpsr = lr-split tMOVi8 2, 14 /* CC::al */, $noreg
+; MACHO-NEXT: $r2, dead $cpsr = lr-split tMOVi8 3, 14 /* CC::al */, $noreg
+; MACHO-NEXT: $r3, dead $cpsr = lr-split tMOVi8 4, 14 /* CC::al */, $noreg
; MACHO-NEXT: tTAILJMPd @z, 14 /* CC::al */, $noreg
; THUMB1-NOT: OUTLINED_FUNCTION_0
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-thunk.ll b/llvm/test/CodeGen/ARM/machine-outliner-thunk.ll
index 807e16202f2c5..81a2175019b81 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-thunk.ll
+++ b/llvm/test/CodeGen/ARM/machine-outliner-thunk.ll
@@ -96,28 +96,28 @@ entry:
; ARM-LABEL: name: OUTLINED_FUNCTION_0
; ARM: bb.0:
; ARM-NEXT: liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
-; ARM: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
-; ARM-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
-; ARM-NEXT: $r2 = MOVi 3, 14 /* CC::al */, $noreg, $noreg
-; ARM-NEXT: $r3 = MOVi 4, 14 /* CC::al */, $noreg, $noreg
+; ARM: $r0 = lr-split MOVi 1, 14 /* CC::al */, $noreg, $noreg
+; ARM-NEXT: $r1 = lr-split MOVi 2, 14 /* CC::al */, $noreg, $noreg
+; ARM-NEXT: $r2 = lr-split MOVi 3, 14 /* CC::al */, $noreg, $noreg
+; ARM-NEXT: $r3 = lr-split MOVi 4, 14 /* CC::al */, $noreg, $noreg
; ARM-NEXT: TAILJMPd @thunk_called_fn, implicit $sp
; THUMB-LABEL: name: OUTLINED_FUNCTION_0
; THUMB: bb.0:
; THUMB-NEXT: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
-; THUMB: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
-; THUMB-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; THUMB: $r0, dead $cpsr = lr-split tMOVi8 1, 14 /* CC::al */, $noreg
+; THUMB-NEXT: $r1, dead $cpsr = lr-split tMOVi8 2, 14 /* CC::al */, $noreg
+; THUMB-NEXT: $r2, dead $cpsr = lr-split tMOVi8 3, 14 /* CC::al */, $noreg
+; THUMB-NEXT: $r3, dead $cpsr = lr-split tMOVi8 4, 14 /* CC::al */, $noreg
; THUMB-NEXT: tTAILJMPdND @thunk_called_fn, 14 /* CC::al */, $noreg, implicit $sp
; MACHO-LABEL: name: OUTLINED_FUNCTION_0
; MACHO: bb.0:
; MACHO-NEXT: liveins: $r7, $r6, $r5, $r4, $r11, $r10, $r8, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
-; MACHO: $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
-; MACHO-NEXT: $r1, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
-; MACHO-NEXT: $r2, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
-; MACHO-NEXT: $r3, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
+; MACHO: $r0, dead $cpsr = lr-split tMOVi8 1, 14 /* CC::al */, $noreg
+; MACHO-NEXT: $r1, dead $cpsr = lr-split tMOVi8 2, 14 /* CC::al */, $noreg
+; MACHO-NEXT: $r2, dead $cpsr = lr-split tMOVi8 3, 14 /* CC::al */, $noreg
+; MACHO-NEXT: $r3, dead $cpsr = lr-split tMOVi8 4, 14 /* CC::al */, $noreg
; MACHO-NEXT: tTAILJMPd @thunk_called_fn, 14 /* CC::al */, $noreg, implicit $sp
attributes #0 = { minsize optsize }
diff --git a/llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir b/llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
index be62b73b14c3f..b86fc03d5dd43 100644
--- a/llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
+++ b/llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
@@ -78,7 +78,7 @@ body: |
; CHECK-NEXT: successors: %bb.11(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = ADDI_D [[COPY6]], 1
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = ORI $r0, 1
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = lr-split ORI $r0, 1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.11:
; CHECK-NEXT: successors: %bb.12(0x80000000)
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
index 176199bd3b3ab..83b00007c3e30 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
@@ -9,10 +9,10 @@ define void @call_test_chars() {
; 32BIT-LABEL: name: call_test_chars
; 32BIT: bb.0.entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 97
- ; 32BIT-NEXT: $r4 = LI 97
- ; 32BIT-NEXT: $r5 = LI 97
- ; 32BIT-NEXT: $r6 = LI 97
+ ; 32BIT-NEXT: $r3 = lr-split LI 97
+ ; 32BIT-NEXT: $r4 = lr-split LI 97
+ ; 32BIT-NEXT: $r5 = lr-split LI 97
+ ; 32BIT-NEXT: $r6 = lr-split LI 97
; 32BIT-NEXT: BL_NOP <mcsymbol .test_chars>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -20,10 +20,10 @@ define void @call_test_chars() {
; 64BIT-LABEL: name: call_test_chars
; 64BIT: bb.0.entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 97
- ; 64BIT-NEXT: $x4 = LI8 97
- ; 64BIT-NEXT: $x5 = LI8 97
- ; 64BIT-NEXT: $x6 = LI8 97
+ ; 64BIT-NEXT: $x3 = lr-split LI8 97
+ ; 64BIT-NEXT: $x4 = lr-split LI8 97
+ ; 64BIT-NEXT: $x5 = lr-split LI8 97
+ ; 64BIT-NEXT: $x6 = lr-split LI8 97
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_chars>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -68,10 +68,10 @@ define void @call_test_chars_mix() {
; 32BIT-LABEL: name: call_test_chars_mix
; 32BIT: bb.0.entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 97
- ; 32BIT-NEXT: $r4 = LI 225
- ; 32BIT-NEXT: $r5 = LI 97
- ; 32BIT-NEXT: $r6 = LI -31
+ ; 32BIT-NEXT: $r3 = lr-split LI 97
+ ; 32BIT-NEXT: $r4 = lr-split LI 225
+ ; 32BIT-NEXT: $r5 = lr-split LI 97
+ ; 32BIT-NEXT: $r6 = lr-split LI -31
; 32BIT-NEXT: BL_NOP <mcsymbol .test_chars_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -79,10 +79,10 @@ define void @call_test_chars_mix() {
; 64BIT-LABEL: name: call_test_chars_mix
; 64BIT: bb.0.entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 97
- ; 64BIT-NEXT: $x4 = LI8 225
- ; 64BIT-NEXT: $x5 = LI8 97
- ; 64BIT-NEXT: $x6 = LI8 -31
+ ; 64BIT-NEXT: $x3 = lr-split LI8 97
+ ; 64BIT-NEXT: $x4 = lr-split LI8 225
+ ; 64BIT-NEXT: $x5 = lr-split LI8 97
+ ; 64BIT-NEXT: $x6 = lr-split LI8 -31
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_chars_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -153,7 +153,7 @@ define void @call_test_i1() {
; 32BIT-LABEL: name: call_test_i1
; 32BIT: bb.0.entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 1
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
; 32BIT-NEXT: BL_NOP <mcsymbol .test_i1>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -161,7 +161,7 @@ define void @call_test_i1() {
; 64BIT-LABEL: name: call_test_i1
; 64BIT: bb.0.entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 1
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_i1>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -233,14 +233,14 @@ define void @call_test_ints() {
; 32BIT-LABEL: name: call_test_ints
; 32BIT: bb.0.entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 1
- ; 32BIT-NEXT: $r5 = LIS 32768
- ; 32BIT-NEXT: $r6 = LIS 32768
- ; 32BIT-NEXT: $r7 = LI 1
- ; 32BIT-NEXT: $r8 = LI 1
- ; 32BIT-NEXT: $r9 = LI 1
- ; 32BIT-NEXT: $r10 = LI 1
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 1
+ ; 32BIT-NEXT: $r5 = lr-split LIS 32768
+ ; 32BIT-NEXT: $r6 = lr-split LIS 32768
+ ; 32BIT-NEXT: $r7 = lr-split LI 1
+ ; 32BIT-NEXT: $r8 = lr-split LI 1
+ ; 32BIT-NEXT: $r9 = lr-split LI 1
+ ; 32BIT-NEXT: $r10 = lr-split LI 1
; 32BIT-NEXT: BL_NOP <mcsymbol .test_ints>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -250,13 +250,13 @@ define void @call_test_ints() {
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x3 = LI8 1
; 64BIT-NEXT: renamable $x5 = RLDIC killed renamable $x3, 31, 32
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 1
- ; 64BIT-NEXT: $x6 = LIS8 32768
- ; 64BIT-NEXT: $x7 = LI8 1
- ; 64BIT-NEXT: $x8 = LI8 1
- ; 64BIT-NEXT: $x9 = LI8 1
- ; 64BIT-NEXT: $x10 = LI8 1
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 1
+ ; 64BIT-NEXT: $x6 = lr-split LIS8 32768
+ ; 64BIT-NEXT: $x7 = lr-split LI8 1
+ ; 64BIT-NEXT: $x8 = lr-split LI8 1
+ ; 64BIT-NEXT: $x9 = lr-split LI8 1
+ ; 64BIT-NEXT: $x10 = lr-split LI8 1
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_ints>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -269,14 +269,14 @@ define void @call_test_i64() {
; 32BIT-LABEL: name: call_test_i64
; 32BIT: bb.0.entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 0
- ; 32BIT-NEXT: $r4 = LI 1
- ; 32BIT-NEXT: $r5 = LI 0
- ; 32BIT-NEXT: $r6 = LI 2
- ; 32BIT-NEXT: $r7 = LI 0
- ; 32BIT-NEXT: $r8 = LI 3
- ; 32BIT-NEXT: $r9 = LI 0
- ; 32BIT-NEXT: $r10 = LI 4
+ ; 32BIT-NEXT: $r3 = lr-split LI 0
+ ; 32BIT-NEXT: $r4 = lr-split LI 1
+ ; 32BIT-NEXT: $r5 = lr-split LI 0
+ ; 32BIT-NEXT: $r6 = lr-split LI 2
+ ; 32BIT-NEXT: $r7 = lr-split LI 0
+ ; 32BIT-NEXT: $r8 = lr-split LI 3
+ ; 32BIT-NEXT: $r9 = lr-split LI 0
+ ; 32BIT-NEXT: $r10 = lr-split LI 4
; 32BIT-NEXT: BL_NOP <mcsymbol .test_i64>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3, implicit-def dead $r4
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -284,10 +284,10 @@ define void @call_test_i64() {
; 64BIT-LABEL: name: call_test_i64
; 64BIT: bb.0.entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_i64>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -590,8 +590,8 @@ define void @call_test_mix() {
; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f1)
; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r4 :: (dereferenceable load (s64) from @d1)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r4 = LI 1
- ; 32BIT-NEXT: $r7 = LI 97
+ ; 32BIT-NEXT: $r4 = lr-split LI 1
+ ; 32BIT-NEXT: $r7 = lr-split LI 97
; 32BIT-NEXT: BL_NOP <mcsymbol .test_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r4, implicit $f2, implicit killed $r7, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -603,8 +603,8 @@ define void @call_test_mix() {
; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f1)
; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x4 :: (dereferenceable load (s64) from @d1)
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x4 = LI8 1
- ; 64BIT-NEXT: $x6 = LI8 97
+ ; 64BIT-NEXT: $x4 = lr-split LI8 1
+ ; 64BIT-NEXT: $x6 = lr-split LI8 97
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -719,7 +719,7 @@ define void @call_test_vararg() {
; 32BIT-NEXT: renamable $r6 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8)
; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 42
+ ; 32BIT-NEXT: $r3 = lr-split LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -735,7 +735,7 @@ define void @call_test_vararg() {
; 64BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0)
; 64BIT-NEXT: renamable $x5 = LD 0, %stack.0 :: (load (s64) from %stack.0)
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 42
+ ; 64BIT-NEXT: $x3 = lr-split LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -763,8 +763,8 @@ define void @call_test_vararg2() {
; 32BIT-NEXT: renamable $r7 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8)
; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 42
- ; 32BIT-NEXT: $r6 = LI 42
+ ; 32BIT-NEXT: $r3 = lr-split LI 42
+ ; 32BIT-NEXT: $r6 = lr-split LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -780,8 +780,8 @@ define void @call_test_vararg2() {
; 64BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0)
; 64BIT-NEXT: renamable $x6 = LD 0, %stack.0 :: (load (s64) from %stack.0)
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 42
- ; 64BIT-NEXT: $x5 = LI8 42
+ ; 64BIT-NEXT: $x3 = lr-split LI8 42
+ ; 64BIT-NEXT: $x5 = lr-split LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -807,9 +807,9 @@ define void @call_test_vararg3() {
; 32BIT-NEXT: renamable $r8 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8)
; 32BIT-NEXT: renamable $r9 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 42
- ; 32BIT-NEXT: $r6 = LI 0
- ; 32BIT-NEXT: $r7 = LI 42
+ ; 32BIT-NEXT: $r3 = lr-split LI 42
+ ; 32BIT-NEXT: $r6 = lr-split LI 0
+ ; 32BIT-NEXT: $r7 = lr-split LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -825,8 +825,8 @@ define void @call_test_vararg3() {
; 64BIT-NEXT: STFD renamable $f2, 0, %stack.0 :: (store (s64) into %stack.0)
; 64BIT-NEXT: renamable $x6 = LD 0, %stack.0 :: (load (s64) from %stack.0)
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 42
- ; 64BIT-NEXT: $x5 = LI8 42
+ ; 64BIT-NEXT: $x3 = lr-split LI8 42
+ ; 64BIT-NEXT: $x5 = lr-split LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -846,7 +846,7 @@ define void @call_test_vararg4() {
; 32BIT-NEXT: STFS renamable $f1, 0, %stack.0 :: (store (s32) into %stack.0)
; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.0 :: (load (s32) from %stack.0)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 42
+ ; 32BIT-NEXT: $r3 = lr-split LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -858,7 +858,7 @@ define void @call_test_vararg4() {
; 64BIT-NEXT: STFS renamable $f1, 0, %stack.0 :: (store (s32) into %stack.0)
; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.0 :: (load (s32) from %stack.0)
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 42
+ ; 64BIT-NEXT: $x3 = lr-split LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -894,14 +894,14 @@ define void @call_test_stackarg_int() {
; 32BIT-NEXT: STW killed renamable $r6, 68, $r1 :: (store (s32) into stack + 68, basealign 16)
; 32BIT-NEXT: STW killed renamable $r5, 64, $r1 :: (store (s32) into stack + 64, align 16)
; 32BIT-NEXT: STW killed renamable $r4, 60, $r1 :: (store (s32) into stack + 60, basealign 16)
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: $r9 = LI 7
- ; 32BIT-NEXT: $r10 = LI 8
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
+ ; 32BIT-NEXT: $r9 = lr-split LI 7
+ ; 32BIT-NEXT: $r10 = lr-split LI 8
; 32BIT-NEXT: STW killed renamable $r11, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_int[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 80, 0, implicit-def dead $r1, implicit $r1
@@ -918,14 +918,14 @@ define void @call_test_stackarg_int() {
; 64BIT-NEXT: renamable $x0 = LWZ8 0, killed renamable $x5 :: (dereferenceable load (s32) from @i)
; 64BIT-NEXT: renamable $x31 = LD 0, killed renamable $x6 :: (dereferenceable load (s64) from @lli)
; 64BIT-NEXT: ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: $x9 = LI8 7
- ; 64BIT-NEXT: $x10 = LI8 8
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
+ ; 64BIT-NEXT: $x9 = lr-split LI8 7
+ ; 64BIT-NEXT: $x10 = lr-split LI8 8
; 64BIT-NEXT: STD killed renamable $x31, 136, $x1 :: (store (s64) into stack + 136, basealign 16)
; 64BIT-NEXT: STD renamable $x0, 144, $x1 :: (store (s64) into stack + 144, align 16)
; 64BIT-NEXT: STD killed renamable $x0, 128, $x1 :: (store (s64) into stack + 128, align 16)
@@ -957,14 +957,14 @@ define void @call_test_stackarg_float() {
; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r4 :: (dereferenceable load (s64) from @d)
; 32BIT-NEXT: ADJCALLSTACKDOWN 68, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: STFD renamable $f2, 60, $r1 :: (store (s64) into stack + 60, align 4, basealign 16)
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: $r9 = LI 7
- ; 32BIT-NEXT: $r10 = LI 8
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
+ ; 32BIT-NEXT: $r9 = lr-split LI 7
+ ; 32BIT-NEXT: $r10 = lr-split LI 8
; 32BIT-NEXT: STFS renamable $f1, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1
@@ -978,14 +978,14 @@ define void @call_test_stackarg_float() {
; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x4 :: (dereferenceable load (s64) from @d)
; 64BIT-NEXT: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: STFD renamable $f2, 120, $x1 :: (store (s64) into stack + 120, basealign 16)
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: $x9 = LI8 7
- ; 64BIT-NEXT: $x10 = LI8 8
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
+ ; 64BIT-NEXT: $x9 = lr-split LI8 7
+ ; 64BIT-NEXT: $x10 = lr-split LI8 8
; 64BIT-NEXT: STFS renamable $f1, 112, $x1 :: (store (s32) into stack + 112, align 16)
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
@@ -1008,12 +1008,12 @@ define void @call_test_stackarg_float2() {
; 32BIT-NEXT: renamable $r9 = LWZ 0, %stack.0 :: (load (s32) from %stack.0, align 8)
; 32BIT-NEXT: renamable $r10 = LWZ 4, %stack.0 :: (load (s32) from %stack.0 + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -1025,12 +1025,12 @@ define void @call_test_stackarg_float2() {
; 64BIT-NEXT: STFD renamable $f1, 0, %stack.0 :: (store (s64) into %stack.0)
; 64BIT-NEXT: renamable $x9 = LD 0, %stack.0 :: (load (s64) from %stack.0)
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -1054,13 +1054,13 @@ define void @call_test_stackarg_float3() {
; 32BIT-NEXT: renamable $f2 = LFS 0, killed renamable $r3 :: (dereferenceable load (s32) from @f)
; 32BIT-NEXT: ADJCALLSTACKDOWN 64, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: STFS renamable $f2, 60, $r1 :: (store (s32) into stack + 60, basealign 16)
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: $r9 = LI 7
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
+ ; 32BIT-NEXT: $r9 = lr-split LI 7
; 32BIT-NEXT: STFD renamable $f1, 52, $r1 :: (store (s64) into stack + 52, align 4, basealign 16)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1
@@ -1075,13 +1075,13 @@ define void @call_test_stackarg_float3() {
; 64BIT-NEXT: renamable $x10 = LD 0, %stack.0 :: (load (s64) from %stack.0)
; 64BIT-NEXT: renamable $f2 = LFS 0, killed renamable $x3 :: (dereferenceable load (s32) from @f)
; 64BIT-NEXT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: $x9 = LI8 7
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
+ ; 64BIT-NEXT: $x9 = lr-split LI8 7
; 64BIT-NEXT: STFS renamable $f2, 112, $x1 :: (store (s32) into stack + 112, align 16)
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
@@ -1234,14 +1234,14 @@ define void @caller_ints_stack() {
; 32BIT-NEXT: STW killed renamable $r5, 68, $r1 :: (store (s32) into stack + 68, basealign 16)
; 32BIT-NEXT: STW killed renamable $r4, 64, $r1 :: (store (s32) into stack + 64, align 16)
; 32BIT-NEXT: STW killed renamable $r3, 60, $r1 :: (store (s32) into stack + 60, basealign 16)
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: $r9 = LI 7
- ; 32BIT-NEXT: $r10 = LI 8
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
+ ; 32BIT-NEXT: $r9 = lr-split LI 7
+ ; 32BIT-NEXT: $r10 = lr-split LI 8
; 32BIT-NEXT: STW killed renamable $r11, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_ints_stack>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3, implicit-def dead $r4
; 32BIT-NEXT: ADJCALLSTACKUP 96, 0, implicit-def dead $r1, implicit $r1
@@ -1266,14 +1266,14 @@ define void @caller_ints_stack() {
; 64BIT-NEXT: renamable $x28 = LD 0, killed renamable $x6 :: (dereferenceable load (s64) from @ll2)
; 64BIT-NEXT: renamable $x27 = LWZ8 0, killed renamable $x7 :: (dereferenceable load (s32) from @i1)
; 64BIT-NEXT: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: $x9 = LI8 7
- ; 64BIT-NEXT: $x10 = LI8 8
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
+ ; 64BIT-NEXT: $x9 = lr-split LI8 7
+ ; 64BIT-NEXT: $x10 = lr-split LI8 8
; 64BIT-NEXT: STD killed renamable $x27, 168, $x1 :: (store (s64) into stack + 168, basealign 16)
; 64BIT-NEXT: STD killed renamable $x30, 160, $x1 :: (store (s64) into stack + 160, align 16)
; 64BIT-NEXT: STD killed renamable $x28, 152, $x1 :: (store (s64) into stack + 152, basealign 16)
@@ -1325,14 +1325,14 @@ define void @call_test_i1_stack() {
; 32BIT: bb.0.entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 60, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: renamable $r11 = LI 1
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: $r9 = LI 7
- ; 32BIT-NEXT: $r10 = LI 8
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
+ ; 32BIT-NEXT: $r9 = lr-split LI 7
+ ; 32BIT-NEXT: $r10 = lr-split LI 8
; 32BIT-NEXT: STW killed renamable $r11, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_i1_stack>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 60, 0, implicit-def dead $r1, implicit $r1
@@ -1342,14 +1342,14 @@ define void @call_test_i1_stack() {
; 64BIT: bb.0.entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x11 = LI8 1
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: $x9 = LI8 7
- ; 64BIT-NEXT: $x10 = LI8 8
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
+ ; 64BIT-NEXT: $x9 = lr-split LI8 7
+ ; 64BIT-NEXT: $x10 = lr-split LI8 8
; 64BIT-NEXT: STD killed renamable $x11, 112, $x1 :: (store (s64) into stack + 112, align 16)
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_i1_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
@@ -1729,9 +1729,9 @@ define void @caller_mix() {
; 64BIT-NEXT: renamable $f4 = LFD 0, killed renamable $x3 :: (load (s64) from constant-pool)
; 64BIT-NEXT: renamable $x3 = LIS8 457
; 64BIT-NEXT: renamable $x9 = ORI8 killed renamable $x3, 50048
- ; 64BIT-NEXT: $x7 = LI8 1
- ; 64BIT-NEXT: $x8 = LI8 2
- ; 64BIT-NEXT: $x10 = LI8 40
+ ; 64BIT-NEXT: $x7 = lr-split LI8 1
+ ; 64BIT-NEXT: $x8 = lr-split LI8 2
+ ; 64BIT-NEXT: $x10 = lr-split LI8 40
; 64BIT-NEXT: STD killed renamable $x4, 120, $x1 :: (store (s64) into stack + 120, basealign 16)
; 64BIT-NEXT: STD killed renamable $x5, 112, $x1 :: (store (s64) into stack + 112, align 16)
; 64BIT-NEXT: BL8_NOP <mcsymbol .mix_callee>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit killed $x7, implicit killed $x8, implicit $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
@@ -1935,14 +1935,14 @@ define void @caller_mix() {
; 32BIT-NEXT: renamable $f5 = LFS 0, killed renamable $r3 :: (load (s32) from constant-pool)
; 32BIT-NEXT: renamable $r11 = ORI killed renamable $r4, 26214
; 32BIT-NEXT: renamable $f10 = LFS 0, killed renamable $r5 :: (load (s32) from constant-pool)
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: $r9 = LI 7
- ; 32BIT-NEXT: $r10 = LI 8
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
+ ; 32BIT-NEXT: $r9 = lr-split LI 7
+ ; 32BIT-NEXT: $r10 = lr-split LI 8
; 32BIT-NEXT: STW killed renamable $r11, 160, $r1 :: (store (s32) into stack + 160, align 16)
; 32BIT-NEXT: BL_NOP <mcsymbol .mix_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 168, 0, implicit-def dead $r1, implicit $r1
@@ -2036,14 +2036,14 @@ define void @caller_mix() {
; 64BIT-NEXT: renamable $f5 = LFS 0, killed renamable $x16 :: (load (s32) from constant-pool)
; 64BIT-NEXT: renamable $x20 = ORI8 killed renamable $x9, 39322
; 64BIT-NEXT: renamable $f10 = LFS 0, killed renamable $x26 :: (load (s32) from constant-pool)
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: $x9 = LI8 7
- ; 64BIT-NEXT: $x10 = LI8 8
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
+ ; 64BIT-NEXT: $x9 = lr-split LI8 7
+ ; 64BIT-NEXT: $x10 = lr-split LI8 8
; 64BIT-NEXT: STD killed renamable $x29, 184, $x1 :: (store (s64) into stack + 184, basealign 16)
; 64BIT-NEXT: STD killed renamable $x28, 144, $x1 :: (store (s64) into stack + 144, align 16)
; 64BIT-NEXT: STD killed renamable $x11, 216, $x1 :: (store (s64) into stack + 216, basealign 16)
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
index 162ffc9e1df2b..21cea51c8ead3 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
@@ -76,9 +76,9 @@ define void @call_test_byval_2Byte() {
; 32BIT-NEXT: renamable $r3 = LWZtoc @gS2, $r2 :: (load (s32) from got)
; 32BIT-NEXT: renamable $r3 = LHZ 0, killed renamable $r3 :: (load (s16))
; 32BIT-NEXT: renamable $r5 = RLWINM killed renamable $r3, 16, 0, 15
- ; 32BIT-NEXT: $r3 = LI 42
+ ; 32BIT-NEXT: $r3 = lr-split LI 42
; 32BIT-NEXT: $f2 = COPY renamable $f1
- ; 32BIT-NEXT: $r7 = LI 43
+ ; 32BIT-NEXT: $r7 = lr-split LI 43
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit killed $f2, implicit killed $r7, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -91,9 +91,9 @@ define void @call_test_byval_2Byte() {
; 64BIT-NEXT: renamable $x3 = LDtoc @gS2, $x2 :: (load (s64) from got)
; 64BIT-NEXT: renamable $x3 = LHZ8 0, killed renamable $x3 :: (load (s16))
; 64BIT-NEXT: renamable $x5 = RLDICR killed renamable $x3, 48, 15
- ; 64BIT-NEXT: $x3 = LI8 42
+ ; 64BIT-NEXT: $x3 = lr-split LI8 42
; 64BIT-NEXT: $f2 = COPY renamable $f1
- ; 64BIT-NEXT: $x7 = LI8 43
+ ; 64BIT-NEXT: $x7 = lr-split LI8 43
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -139,13 +139,13 @@ define void @call_test_byval_3Byte() {
; 32BIT-NEXT: renamable $r4 = LHZ 0, killed renamable $r4 :: (load (s16))
; 32BIT-NEXT: renamable $r10 = RLWINM killed renamable $r3, 8, 16, 23
; 32BIT-NEXT: renamable $r10 = RLWIMI killed renamable $r10, killed renamable $r4, 16, 0, 15
- ; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: $r4 = LI 2
- ; 32BIT-NEXT: $r5 = LI 3
- ; 32BIT-NEXT: $r6 = LI 4
- ; 32BIT-NEXT: $r7 = LI 5
- ; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: $r9 = LI 7
+ ; 32BIT-NEXT: $r3 = lr-split LI 1
+ ; 32BIT-NEXT: $r4 = lr-split LI 2
+ ; 32BIT-NEXT: $r5 = lr-split LI 3
+ ; 32BIT-NEXT: $r6 = lr-split LI 4
+ ; 32BIT-NEXT: $r7 = lr-split LI 5
+ ; 32BIT-NEXT: $r8 = lr-split LI 6
+ ; 32BIT-NEXT: $r9 = lr-split LI 7
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_3Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 60, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
@@ -160,13 +160,13 @@ define void @call_test_byval_3Byte() {
; 64BIT-NEXT: renamable $x4 = LHZ8 0, killed renamable $x4 :: (load (s16))
; 64BIT-NEXT: renamable $x10 = RLDIC killed renamable $x3, 40, 16
; 64BIT-NEXT: renamable $x10 = RLDIMI killed renamable $x10, killed renamable $x4, 48, 0
- ; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: $x4 = LI8 2
- ; 64BIT-NEXT: $x5 = LI8 3
- ; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: $x7 = LI8 5
- ; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: $x9 = LI8 7
+ ; 64BIT-NEXT: $x3 = lr-split LI8 1
+ ; 64BIT-NEXT: $x4 = lr-split LI8 2
+ ; 64BIT-NEXT: $x5 = lr-split LI8 3
+ ; 64BIT-NEXT: $x6 = lr-split LI8 4
+ ; 64BIT-NEXT: $x7 = lr-split LI8 5
+ ; 64BIT-NEXT: $x8 = lr-split LI8 6
+ ; 64BIT-NEXT: $x9 = lr-split LI8 7
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_3Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
@@ -559,7 +559,7 @@ define i32 @call_test_byval_homogeneous_float_struct() {
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: renamable $r5 = LWZ 8, %stack.0.s :: (load (s32) from %stack.0.s + 8, align 8)
; 32BIT-NEXT: renamable $r4 = LWZ 4, %stack.0.s :: (load (s32) from %stack.0.s + 4)
- ; 32BIT-NEXT: $r3 = LI 0
+ ; 32BIT-NEXT: $r3 = lr-split LI 0
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
@@ -572,7 +572,7 @@ define i32 @call_test_byval_homogeneous_float_struct() {
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x3 = LWZ8 8, %stack.0.s :: (load (s32) from %stack.0.s + 8, align 8)
; 64BIT-NEXT: renamable $x4 = RLDICR killed renamable $x3, 32, 31
- ; 64BIT-NEXT: $x3 = LI8 0
+ ; 64BIT-NEXT: $x3 = lr-split LI8 0
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
diff --git a/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll b/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll
index 1f3868558a08e..9382678f26f9f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll
@@ -93,10 +93,10 @@ define void @callThroughPtrWithArgs(ptr nocapture) {
; MIR32-DAG: STW $r2, 20, $r1 :: (store (s32) into stack + 20)
; MIR32-DAG: renamable $r11 = LWZ 8, renamable $r3 :: (dereferenceable invariant load (s32) from %ir.0 + 8)
; MIR32-DAG: $r2 = LWZ 4, killed renamable $r3 :: (dereferenceable invariant load (s32) from %ir.0 + 4)
-; MIR32-DAG: $r3 = LI 1
-; MIR32-DAG: $r4 = LI 2
-; MIR32-DAG: $r5 = LI 0
-; MIR32-DAG: $r6 = LI 3
+; MIR32-DAG: $r3 = lr-split LI 1
+; MIR32-DAG: $r4 = lr-split LI 2
+; MIR32-DAG: $r5 = lr-split LI 0
+; MIR32-DAG: $r6 = lr-split LI 3
; MIR32-NEXT: BCTRL_LWZinto_toc 20, $r1, csr_aix32, implicit-def dead $lr, implicit-def dead $r2, implicit $ctr, implicit $rm, implicit $r11, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r2, implicit-def $r1
; MIR32-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
@@ -107,9 +107,9 @@ define void @callThroughPtrWithArgs(ptr nocapture) {
; MIR64-DAG: STD $x2, 40, $x1 :: (store (s64) into stack + 40)
; MIR64-DAG: renamable $x11 = LD 16, renamable $x3 :: (dereferenceable invariant load (s64) from %ir.0 + 16)
; MIR64-DAG: $x2 = LD 8, killed renamable $x3 :: (dereferenceable invariant load (s64) from %ir.0 + 8)
-; MIR64-DAG: $x3 = LI8 1
-; MIR64-DAG: $x4 = LI8 2
-; MIR64-DAG: $x5 = LI8 3
+; MIR64-DAG: $x3 = lr-split LI8 1
+; MIR64-DAG: $x4 = lr-split LI8 2
+; MIR64-DAG: $x5 = lr-split LI8 3
; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_ppc64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1
; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
index 5f8eb2b95706b..c611fcc6e82da 100644
--- a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
@@ -60,7 +60,7 @@ define i32 @jump_table(i32 %a) {
; 32SMALL-MIR-NEXT: INLINEASM &"", sideeffect attdialect
; 32SMALL-MIR-NEXT: {{ $}}
; 32SMALL-MIR-NEXT: bb.6.sw.epilog:
- ; 32SMALL-MIR-NEXT: $r3 = LI 0
+ ; 32SMALL-MIR-NEXT: $r3 = lr-split LI 0
; 32SMALL-MIR-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; 32LARGE-MIR-LABEL: name: jump_table
@@ -108,7 +108,7 @@ define i32 @jump_table(i32 %a) {
; 32LARGE-MIR-NEXT: INLINEASM &"", sideeffect attdialect
; 32LARGE-MIR-NEXT: {{ $}}
; 32LARGE-MIR-NEXT: bb.6.sw.epilog:
- ; 32LARGE-MIR-NEXT: $r3 = LI 0
+ ; 32LARGE-MIR-NEXT: $r3 = lr-split LI 0
; 32LARGE-MIR-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; 64SMALL-MIR-LABEL: name: jump_table
@@ -155,7 +155,7 @@ define i32 @jump_table(i32 %a) {
; 64SMALL-MIR-NEXT: INLINEASM &"", sideeffect attdialect
; 64SMALL-MIR-NEXT: {{ $}}
; 64SMALL-MIR-NEXT: bb.6.sw.epilog:
- ; 64SMALL-MIR-NEXT: $x3 = LI8 0
+ ; 64SMALL-MIR-NEXT: $x3 = lr-split LI8 0
; 64SMALL-MIR-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
;
; 64LARGE-MIR-LABEL: name: jump_table
@@ -203,7 +203,7 @@ define i32 @jump_table(i32 %a) {
; 64LARGE-MIR-NEXT: INLINEASM &"", sideeffect attdialect
; 64LARGE-MIR-NEXT: {{ $}}
; 64LARGE-MIR-NEXT: bb.6.sw.epilog:
- ; 64LARGE-MIR-NEXT: $x3 = LI8 0
+ ; 64LARGE-MIR-NEXT: $x3 = lr-split LI8 0
; 64LARGE-MIR-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
switch i32 %a, label %sw.epilog [
diff --git a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
index 1127bcc64c354..29b8fdfdbfec4 100644
--- a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
@@ -45,33 +45,33 @@ define double @caller() {
; MIR32-NEXT: renamable $r4 = LWZtoc %const.0, $r2 :: (load (s32) from got)
; MIR32-NEXT: renamable $vsl0 = LXVD2X $zero, killed renamable $r4 :: (load (s128) from constant-pool)
; MIR32-NEXT: STXVD2X killed renamable $vsl0, $r1, killed renamable $r3 :: (store (s128) into stack + 48)
- ; MIR32-NEXT: $f1 = XXLXORdpz
- ; MIR32-NEXT: $f2 = XXLXORdpz
- ; MIR32-NEXT: $v2 = XXLXORz
- ; MIR32-NEXT: $v3 = XXLXORz
- ; MIR32-NEXT: $v4 = XXLXORz
- ; MIR32-NEXT: $v5 = XXLXORz
- ; MIR32-NEXT: $v6 = XXLXORz
- ; MIR32-NEXT: $v7 = XXLXORz
- ; MIR32-NEXT: $v8 = XXLXORz
- ; MIR32-NEXT: $r3 = LI 128
- ; MIR32-NEXT: $r4 = LI 256
- ; MIR32-NEXT: $v9 = XXLXORz
- ; MIR32-NEXT: $v10 = XXLXORz
- ; MIR32-NEXT: $v11 = XXLXORz
- ; MIR32-NEXT: $v12 = XXLXORz
- ; MIR32-NEXT: $v13 = XXLXORz
- ; MIR32-NEXT: $f3 = XXLXORdpz
- ; MIR32-NEXT: $f4 = XXLXORdpz
- ; MIR32-NEXT: $f5 = XXLXORdpz
- ; MIR32-NEXT: $f6 = XXLXORdpz
- ; MIR32-NEXT: $f7 = XXLXORdpz
- ; MIR32-NEXT: $f8 = XXLXORdpz
- ; MIR32-NEXT: $f9 = XXLXORdpz
- ; MIR32-NEXT: $f10 = XXLXORdpz
- ; MIR32-NEXT: $f11 = XXLXORdpz
- ; MIR32-NEXT: $f12 = XXLXORdpz
- ; MIR32-NEXT: $f13 = XXLXORdpz
+ ; MIR32-NEXT: $f1 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f2 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $v2 = lr-split XXLXORz
+ ; MIR32-NEXT: $v3 = lr-split XXLXORz
+ ; MIR32-NEXT: $v4 = lr-split XXLXORz
+ ; MIR32-NEXT: $v5 = lr-split XXLXORz
+ ; MIR32-NEXT: $v6 = lr-split XXLXORz
+ ; MIR32-NEXT: $v7 = lr-split XXLXORz
+ ; MIR32-NEXT: $v8 = lr-split XXLXORz
+ ; MIR32-NEXT: $r3 = lr-split LI 128
+ ; MIR32-NEXT: $r4 = lr-split LI 256
+ ; MIR32-NEXT: $v9 = lr-split XXLXORz
+ ; MIR32-NEXT: $v10 = lr-split XXLXORz
+ ; MIR32-NEXT: $v11 = lr-split XXLXORz
+ ; MIR32-NEXT: $v12 = lr-split XXLXORz
+ ; MIR32-NEXT: $v13 = lr-split XXLXORz
+ ; MIR32-NEXT: $f3 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f4 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f5 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f6 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f7 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f8 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f9 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f10 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f11 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f12 = lr-split XXLXORdpz
+ ; MIR32-NEXT: $f13 = lr-split XXLXORdpz
; MIR32-NEXT: BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $f1, implicit killed $f2, implicit killed $v2, implicit killed $v3, implicit killed $v4, implicit killed $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def $f1
; MIR32-NEXT: ADJCALLSTACKUP 188, 0, implicit-def dead $r1, implicit $r1
; MIR32-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
@@ -104,33 +104,33 @@ define double @caller() {
; MIR64-NEXT: renamable $x4 = LDtocCPT %const.0, $x2 :: (load (s64) from got)
; MIR64-NEXT: renamable $vsl0 = LXVD2X $zero8, killed renamable $x4 :: (load (s128) from constant-pool)
; MIR64-NEXT: STXVD2X killed renamable $vsl0, $x1, killed renamable $x3 :: (store (s128) into stack + 80)
- ; MIR64-NEXT: $f1 = XXLXORdpz
- ; MIR64-NEXT: $f2 = XXLXORdpz
- ; MIR64-NEXT: $v2 = XXLXORz
- ; MIR64-NEXT: $v3 = XXLXORz
- ; MIR64-NEXT: $v4 = XXLXORz
- ; MIR64-NEXT: $v5 = XXLXORz
- ; MIR64-NEXT: $v6 = XXLXORz
- ; MIR64-NEXT: $x3 = LI8 128
- ; MIR64-NEXT: $x4 = LI8 256
- ; MIR64-NEXT: $v7 = XXLXORz
- ; MIR64-NEXT: $v8 = XXLXORz
- ; MIR64-NEXT: $v9 = XXLXORz
- ; MIR64-NEXT: $v10 = XXLXORz
- ; MIR64-NEXT: $v11 = XXLXORz
- ; MIR64-NEXT: $v12 = XXLXORz
- ; MIR64-NEXT: $v13 = XXLXORz
- ; MIR64-NEXT: $f3 = XXLXORdpz
- ; MIR64-NEXT: $f4 = XXLXORdpz
- ; MIR64-NEXT: $f5 = XXLXORdpz
- ; MIR64-NEXT: $f6 = XXLXORdpz
- ; MIR64-NEXT: $f7 = XXLXORdpz
- ; MIR64-NEXT: $f8 = XXLXORdpz
- ; MIR64-NEXT: $f9 = XXLXORdpz
- ; MIR64-NEXT: $f10 = XXLXORdpz
- ; MIR64-NEXT: $f11 = XXLXORdpz
- ; MIR64-NEXT: $f12 = XXLXORdpz
- ; MIR64-NEXT: $f13 = XXLXORdpz
+ ; MIR64-NEXT: $f1 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f2 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $v2 = lr-split XXLXORz
+ ; MIR64-NEXT: $v3 = lr-split XXLXORz
+ ; MIR64-NEXT: $v4 = lr-split XXLXORz
+ ; MIR64-NEXT: $v5 = lr-split XXLXORz
+ ; MIR64-NEXT: $v6 = lr-split XXLXORz
+ ; MIR64-NEXT: $x3 = lr-split LI8 128
+ ; MIR64-NEXT: $x4 = lr-split LI8 256
+ ; MIR64-NEXT: $v7 = lr-split XXLXORz
+ ; MIR64-NEXT: $v8 = lr-split XXLXORz
+ ; MIR64-NEXT: $v9 = lr-split XXLXORz
+ ; MIR64-NEXT: $v10 = lr-split XXLXORz
+ ; MIR64-NEXT: $v11 = lr-split XXLXORz
+ ; MIR64-NEXT: $v12 = lr-split XXLXORz
+ ; MIR64-NEXT: $v13 = lr-split XXLXORz
+ ; MIR64-NEXT: $f3 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f4 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f5 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f6 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f7 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f8 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f9 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f10 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f11 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f12 = lr-split XXLXORdpz
+ ; MIR64-NEXT: $f13 = lr-split XXLXORdpz
; MIR64-NEXT: BL8_NOP <mcsymbol .callee[PR]>, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $f1, implicit killed $f2, implicit killed $v2, implicit killed $v3, implicit killed $v4, implicit killed $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1, implicit-def $f1
; MIR64-NEXT: ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1
; MIR64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-byval.ll b/llvm/test/CodeGen/PowerPC/aix-vector-byval.ll
index 8fcac7b6a5921..e0719b8ad91f9 100644
--- a/llvm/test/CodeGen/PowerPC/aix-vector-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vector-byval.ll
@@ -24,7 +24,7 @@ define i32 @caller() {
; 32BIT-NEXT: renamable $r7 = LWZ 8, %stack.0.vs :: (load (s32) from %stack.0.vs + 8, align 8)
; 32BIT-NEXT: renamable $r6 = LWZ 4, %stack.0.vs :: (load (s32) from %stack.0.vs + 4)
; 32BIT-NEXT: renamable $r5 = LWZ 0, %stack.0.vs :: (load (s32) from %stack.0.vs, align 16)
- ; 32BIT-NEXT: $r3 = LI 0
+ ; 32BIT-NEXT: $r3 = lr-split LI 0
; 32BIT-NEXT: BL_NOP <mcsymbol .vec_struct_test[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
@@ -36,7 +36,7 @@ define i32 @caller() {
; 64BIT-NEXT: renamable $x7 = LD 16, %stack.0.vs :: (load (s64) from %stack.0.vs + 16, align 16)
; 64BIT-NEXT: renamable $x6 = LD 8, %stack.0.vs :: (load (s64) from %stack.0.vs + 8)
; 64BIT-NEXT: renamable $x5 = LD 0, %stack.0.vs :: (load (s64) from %stack.0.vs, align 16)
- ; 64BIT-NEXT: $x3 = LI8 0
+ ; 64BIT-NEXT: $x3 = lr-split LI8 0
; 64BIT-NEXT: BL8_NOP <mcsymbol .vec_struct_test[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x2, implicit-def $r1, implicit-def $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
diff --git a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
index 05b30569a2c10..64a689c0cf00d 100644
--- a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
+++ b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
@@ -174,5 +174,5 @@ body: |
#CHECK-NOT: %9:crbitrc = CRUNSET
#CHECK: bb.2.while.body:
#CHECK-NOT: %24:crbitrc = COPY %9
-#CHECK: %24:crbitrc = CRUNSET
+#CHECK: %24:crbitrc = lr-split CRUNSET
#CHECK: B %bb.3
diff --git a/llvm/test/CodeGen/RISCV/pr176001.ll b/llvm/test/CodeGen/RISCV/pr176001.ll
index ffc1658558975..130a530428eb5 100644
--- a/llvm/test/CodeGen/RISCV/pr176001.ll
+++ b/llvm/test/CodeGen/RISCV/pr176001.ll
@@ -55,7 +55,7 @@ define <32 x i64> @main(i1 %tobool93.not, <32 x i64> %0, <32 x i64> %1) #0 {
; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)
; CHECK-NEXT: liveins: $v0m8:0x0000000000000002, $v16m8:0x0000000000000006
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
+ ; CHECK-NEXT: renamable $v8m8 = lr-split PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
; CHECK-NEXT: renamable $v24m8 = COPY renamable $v8m8
; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_V_M8 killed renamable $v24m8, killed renamable $v8m8, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */
; CHECK-NEXT: renamable $v8m2 = PseudoVSLIDEDOWN_VI_M2 undef renamable $v8m2, killed renamable $v16m2, 2, 1 /* vl */, 6 /* e64 */, 3 /* ta, ma */
@@ -70,7 +70,7 @@ define <32 x i64> @main(i1 %tobool93.not, <32 x i64> %0, <32 x i64> %1) #0 {
; CHECK-NEXT: bb.9.cond.end133:
; CHECK-NEXT: liveins: $v0m8:0x0000000000000002, $v24m8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $v16m8 = PseudoVMV_V_I_M8 undef renamable $v16m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
+ ; CHECK-NEXT: renamable $v16m8 = lr-split PseudoVMV_V_I_M8 undef renamable $v16m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber renamable $v8 = PseudoVMSLEU_VV_M8 renamable $v16m8, killed renamable $v24m8, 16 /* vl */, 6 /* e64 */
; CHECK-NEXT: [[PseudoVMV_X_S2:%[0-9]+]]:gpr = PseudoVMV_X_S killed renamable $v0, 5 /* e32 */
; CHECK-NEXT: renamable $v24 = COPY renamable $v16
@@ -79,10 +79,10 @@ define <32 x i64> @main(i1 %tobool93.not, <32 x i64> %0, <32 x i64> %1) #0 {
; CHECK-NEXT: $v0 = COPY killed renamable $v8
; CHECK-NEXT: renamable $v8m8 = COPY renamable $v16m8
; CHECK-NEXT: renamable $v8 = COPY killed renamable $v24
- ; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_I_M8 undef renamable $v24m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
+ ; CHECK-NEXT: renamable $v24m8 = lr-split PseudoVMV_V_I_M8 undef renamable $v24m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
; CHECK-NEXT: renamable $v24m8 = PseudoVMERGE_VIM_M8 undef renamable $v24m8, killed renamable $v24m8, -1, $v0, 16 /* vl */, 6 /* e64 */
; CHECK-NEXT: early-clobber renamable $v0 = PseudoVMSLEU_VV_M8 killed renamable $v16m8, killed renamable $v8m8, 16 /* vl */, 6 /* e64 */
- ; CHECK-NEXT: renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
+ ; CHECK-NEXT: renamable $v8m8 = lr-split PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */
; CHECK-NEXT: renamable $v8m8 = PseudoVMERGE_VIM_M8 undef renamable $v8m8, killed renamable $v8m8, -1, $v0, 16 /* vl */, 6 /* e64 */
; CHECK-NEXT: $v16m8 = COPY killed renamable $v24m8
; CHECK-NEXT: PseudoRET implicit $v8m8, implicit $v16m8
diff --git a/llvm/test/CodeGen/RISCV/zilsd-spill.ll b/llvm/test/CodeGen/RISCV/zilsd-spill.ll
index 67a20ac5f7c4c..9117bd7e97855 100644
--- a/llvm/test/CodeGen/RISCV/zilsd-spill.ll
+++ b/llvm/test/CodeGen/RISCV/zilsd-spill.ll
@@ -29,7 +29,7 @@ define i64 @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwi
; RV32I-NEXT: frame-setup SW killed $x27, $x2, 12 :: (store (s32) into %stack.13)
; RV32I-NEXT: SW killed renamable $x11, $x2, 0 :: (store (s32) into %ir.1, align 8)
; RV32I-NEXT: SW killed renamable $x12, $x2, 4 :: (store (s32) into %ir.1 + 4, basealign 8)
- ; RV32I-NEXT: $x11 = ADDI $x2, 0
+ ; RV32I-NEXT: $x11 = lr-split ADDI $x2, 0
; RV32I-NEXT: $x12 = COPY killed renamable $x13
; RV32I-NEXT: $x13 = COPY killed renamable $x14
; RV32I-NEXT: $x14 = COPY $x0
@@ -75,7 +75,7 @@ define i64 @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwi
; RV32I-ZILSD-NEXT: renamable $x17 = COPY $x12
; RV32I-ZILSD-NEXT: renamable $x16 = COPY $x11
; RV32I-ZILSD-NEXT: SD_RV32 killed renamable $x16_x17, $x2, 16 :: (store (s64) into %ir.1)
- ; RV32I-ZILSD-NEXT: $x11 = ADDI $x2, 16
+ ; RV32I-ZILSD-NEXT: $x11 = lr-split ADDI $x2, 16
; RV32I-ZILSD-NEXT: $x12 = COPY killed renamable $x13
; RV32I-ZILSD-NEXT: $x13 = COPY killed renamable $x14
; RV32I-ZILSD-NEXT: $x14 = COPY $x0
@@ -114,7 +114,7 @@ define i64 @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwi
; RV32I-ZILSD-UNALIGNED-NEXT: renamable $x17 = COPY $x12
; RV32I-ZILSD-UNALIGNED-NEXT: renamable $x16 = COPY $x11
; RV32I-ZILSD-UNALIGNED-NEXT: SD_RV32 killed renamable $x16_x17, $x2, 16 :: (store (s64) into %ir.1)
- ; RV32I-ZILSD-UNALIGNED-NEXT: $x11 = ADDI $x2, 16
+ ; RV32I-ZILSD-UNALIGNED-NEXT: $x11 = lr-split ADDI $x2, 16
; RV32I-ZILSD-UNALIGNED-NEXT: $x12 = COPY killed renamable $x13
; RV32I-ZILSD-UNALIGNED-NEXT: $x13 = COPY killed renamable $x14
; RV32I-ZILSD-UNALIGNED-NEXT: $x14 = COPY $x0
@@ -153,7 +153,7 @@ define i64 @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwi
; RV32I-ZILSD-4BYTEALIGN-NEXT: renamable $x17 = COPY $x12
; RV32I-ZILSD-4BYTEALIGN-NEXT: renamable $x16 = COPY $x11
; RV32I-ZILSD-4BYTEALIGN-NEXT: SD_RV32 killed renamable $x16_x17, $x2, 16 :: (store (s64) into %ir.1)
- ; RV32I-ZILSD-4BYTEALIGN-NEXT: $x11 = ADDI $x2, 16
+ ; RV32I-ZILSD-4BYTEALIGN-NEXT: $x11 = lr-split ADDI $x2, 16
; RV32I-ZILSD-4BYTEALIGN-NEXT: $x12 = COPY killed renamable $x13
; RV32I-ZILSD-4BYTEALIGN-NEXT: $x13 = COPY killed renamable $x14
; RV32I-ZILSD-4BYTEALIGN-NEXT: $x14 = COPY $x0
diff --git a/llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll b/llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
index 0e2b6769f7010..e27d45f545575 100644
--- a/llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
@@ -85,12 +85,12 @@ define void @foo(i32 %M, i32 %N, i32 %K, ptr %A, ptr %B_rcr4, ptr %C, i32 %c_row
; CHECK-NEXT: bb.2.for.cond14.preheader:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[MOV32rm4:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.2, align 8)
+ ; CHECK-NEXT: [[MOV32rm4:%[0-9]+]]:gr32 = lr-split MOV32rm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.2, align 8)
; CHECK-NEXT: CMP32rm [[MOV32rm4]], %fixed-stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load (s32) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[MOV32rm5:%[0-9]+]]:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (load (s32) from %stack.2)
; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64_nosp = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %stack.3)
; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64 = MOV64rm %stack.11, 1, $noreg, 0, $noreg :: (load (s64) from %stack.11)
- ; CHECK-NEXT: [[MOV32rm6:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.3, align 16)
+ ; CHECK-NEXT: [[MOV32rm6:%[0-9]+]]:gr32 = lr-split MOV32rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.3, align 16)
; CHECK-NEXT: [[COPY9:%[0-9]+]]:gr32 = lr-split COPY [[MOV32rm6]]
; CHECK-NEXT: JCC_1 %bb.5, 13, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.3
@@ -141,7 +141,7 @@ define void @foo(i32 %M, i32 %N, i32 %K, ptr %A, ptr %B_rcr4, ptr %C, i32 %c_row
; CHECK-NEXT: [[MOVSX64rr32_2:%[0-9]+]]:gr64_nosp = lr-split COPY [[COPY13]]
; CHECK-NEXT: [[MOVSX64rr32_3:%[0-9]+]]:gr64_nosp = lr-split COPY [[COPY12]]
; CHECK-NEXT: [[MOVSX64rm32_1:%[0-9]+]]:gr64 = lr-split COPY [[COPY11]]
- ; CHECK-NEXT: [[MOV32rm8:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.3, align 16)
+ ; CHECK-NEXT: [[MOV32rm8:%[0-9]+]]:gr32 = lr-split MOV32rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s32) from %fixed-stack.3, align 16)
; CHECK-NEXT: [[COPY9:%[0-9]+]]:gr32 = lr-split COPY [[MOV32rm8]]
; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTDPBSSDV [[COPY9]].sub_16bit, [[LEA64_32r1]].sub_16bit, [[COPY4]].sub_16bit, [[PTILEZEROV]], [[PTILELOADDV]], [[PTILELOADDV1]]
; CHECK-NEXT: PTILESTOREDV [[COPY9]].sub_16bit, [[COPY7]].sub_16bit, [[MOV64rm3]], 1, [[MOVSX64rr32_2]], 0, $noreg, [[PTILEZEROV]]
diff --git a/llvm/test/CodeGen/X86/apx/foldmemory.mir b/llvm/test/CodeGen/X86/apx/foldmemory.mir
index 80b100c8d6215..62ac04e5ed720 100644
--- a/llvm/test/CodeGen/X86/apx/foldmemory.mir
+++ b/llvm/test/CodeGen/X86/apx/foldmemory.mir
@@ -57,7 +57,7 @@ body: |
; CHECK-NEXT: dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
; CHECK-NEXT: [[COPY8:%[0-9]+]]:gr32 = lr-split COPY [[COPY]]
; CHECK-NEXT: dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
- ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: CALL64r [[MOV32r0_1]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit killed $xmm0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = lr-split COPY [[COPY5]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = lr-split COPY [[COPY6]]
diff --git a/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir b/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
index ca087b17eab3f..77a0256b94689 100644
--- a/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
+++ b/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
@@ -23,18 +23,18 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri 204983918657971834
- ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.6(0x3efbefbf), %bb.3(0x41041041)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; CHECK-NEXT: dead $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
+ ; CHECK-NEXT: dead $edi = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rdi
; CHECK-NEXT: $rsi = COPY [[MOV32r0_1]]
; CHECK-NEXT: CALL64r [[MOV32r0_]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -47,7 +47,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr64_with_sub_8bit = MOV32ri64 1
; CHECK-NEXT: CMP64rr [[COPY1]], [[MOV64ri]], implicit-def $eflags
- ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32ri 0
+ ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32ri 0
; CHECK-NEXT: JCC_1 %bb.5, 4, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
@@ -56,7 +56,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_8bit:gr64_with_sub_8bit = MOV8rm $noreg, 1, $noreg, 0, $noreg
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr64_with_sub_8bit = COPY [[MOV32r0_2]]
- ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]]:gr64_with_sub_8bit = MOV32ri64 1
+ ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]]:gr64_with_sub_8bit = lr-split MOV32ri64 1
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
diff --git a/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir b/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir
index ed89609b143a3..3e03b4c3e15c9 100644
--- a/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir
+++ b/llvm/test/CodeGen/X86/coalesce-dbg-value-subreg-rewrite.mir
@@ -47,5 +47,5 @@ body: |
# subregister index for physical register").
#
# CHECK: bb.0.entry:
-# CHECK-NEXT: $dx = MOV16ri 0
+# CHECK-NEXT: $dx = lr-split MOV16ri 0
# CHECK-NEXT: DBG_VALUE $dl,
diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
index a5f1f3d6d6268..6d8051367eb56 100644
--- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
+++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
@@ -28,7 +28,7 @@ body: |
; CHECK-NEXT: JCC_1 %bb.5, 5, implicit killed undef $eflags
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
- ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
+ ; CHECK-NEXT: dead $eax = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $al
; CHECK-NEXT: RET 0, killed undef $al
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
diff --git a/llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir b/llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
index a09e751ce3ffb..11d48c30c3fe5 100644
--- a/llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
+++ b/llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]]
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_1]]
- ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_32bit, implicit-def [[MOV32r0_2]]
+ ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_32bit, implicit-def [[MOV32r0_2]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
@@ -75,7 +75,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]]
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_1]].sub_8bit
- ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_8bit, implicit-def [[MOV32r0_2]]
+ ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_8bit, implicit-def [[MOV32r0_2]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
diff --git a/llvm/test/CodeGen/X86/early-clobber.mir b/llvm/test/CodeGen/X86/early-clobber.mir
index 57025be5636b7..a52932de21b9d 100644
--- a/llvm/test/CodeGen/X86/early-clobber.mir
+++ b/llvm/test/CodeGen/X86/early-clobber.mir
@@ -32,7 +32,7 @@ body: |
; CHECK-NEXT: frame-setup PUSH32r killed $esi, implicit-def $esp, implicit $esp
; CHECK-NEXT: $esp = frame-setup SUB32ri $esp, 12, implicit-def dead $eflags
; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $ebp, clobber, implicit-def dead early-clobber $eax, clobber, implicit-def dead early-clobber $ebx, clobber, implicit-def dead early-clobber $ecx, clobber, implicit-def dead early-clobber $edx, clobber, implicit-def dead early-clobber $esi, clobber, implicit-def dead early-clobber $edi, clobber, implicit-def dead early-clobber $df, clobber, implicit-def early-clobber $fpsw, clobber, implicit-def dead early-clobber $eflags
- ; CHECK-NEXT: early-clobber renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
+ ; CHECK-NEXT: early-clobber renamable $eax = lr-split XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
; CHECK-NEXT: TEST8rr renamable $al, renamable $al, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.2, 5, implicit $eflags
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/X86/late-remat-update-2.mir b/llvm/test/CodeGen/X86/late-remat-update-2.mir
index 3ffcb2fdf9e40..5565914540711 100644
--- a/llvm/test/CodeGen/X86/late-remat-update-2.mir
+++ b/llvm/test/CodeGen/X86/late-remat-update-2.mir
@@ -22,7 +22,7 @@
# CHECK: bb.0.entry:
# CHECK: $rax = MOV64ri32 -11
# CHECK: bb.1:
-# CHECK: $rax = MOV64ri32 -11
+# CHECK: $rax = lr-split MOV64ri32 -11
# CHECK: $rax = ADD64ri8 killed renamable $rax, 5
# CHECK: CMP64ri8 renamable $rax
# CHECK: RET 0, $rax
diff --git a/llvm/test/CodeGen/X86/remat-phys-dead.ll b/llvm/test/CodeGen/X86/remat-phys-dead.ll
index 9a0a219869353..02fb9f0185d3a 100644
--- a/llvm/test/CodeGen/X86/remat-phys-dead.ll
+++ b/llvm/test/CodeGen/X86/remat-phys-dead.ll
@@ -9,7 +9,7 @@
define i8 @test_remat() {
ret i8 0
; CHECK: REGISTER COALESCER
-; CHECK: Remat: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
+; CHECK: Remat: dead $eax = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $al
}
; On the other hand, if it's already the correct width, we really shouldn't be
diff --git a/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir b/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir
index 44a2aecdc3672..dc726daaaa629 100644
--- a/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir
+++ b/llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir
@@ -24,7 +24,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $rax = MOV64ri32 -11, implicit-def $eax
+ ; CHECK-NEXT: dead $rax = lr-split MOV64ri32 -11, implicit-def $eax
; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
; CHECK-NEXT: RET 0, $eax
@@ -78,7 +78,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $eax = MOV32ri -11, implicit-def $rax
+ ; CHECK-NEXT: dead $eax = lr-split MOV32ri -11, implicit-def $rax
; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
; CHECK-NEXT: RET 0, $rax
@@ -132,7 +132,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $eax = MOV32ri -11, implicit-def $rax
+ ; CHECK-NEXT: dead $eax = lr-split MOV32ri -11, implicit-def $rax
; CHECK-NEXT: CMP64ri8 %t3, 1, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit killed $eflags
; CHECK-NEXT: RET 0, $rax
@@ -171,10 +171,10 @@ name: rematerialize_superregister_into_subregister_def_with_impdef_physreg
body: |
bb.0.entry:
; CHECK-LABEL: name: rematerialize_superregister_into_subregister_def_with_impdef_physreg
- ; CHECK: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
- ; CHECK-NEXT: dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ ; CHECK: dead $esi = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+ ; CHECK-NEXT: dead $edx = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rdx
; CHECK-NEXT: FAKE_USE implicit killed $rsi, implicit killed $rdx
- ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def dead $rax, implicit-def $al
+ ; CHECK-NEXT: dead $eax = lr-split MOV32r0 implicit-def dead $eflags, implicit-def dead $rax, implicit-def $al
; CHECK-NEXT: FAKE_USE implicit killed $al
; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: RET 0, $eax
diff --git a/llvm/test/CodeGen/X86/splitkit-remat-broken-subreg-constraint.mir b/llvm/test/CodeGen/X86/splitkit-remat-broken-subreg-constraint.mir
index 7af6e676644df..7d50c02bd1fc2 100644
--- a/llvm/test/CodeGen/X86/splitkit-remat-broken-subreg-constraint.mir
+++ b/llvm/test/CodeGen/X86/splitkit-remat-broken-subreg-constraint.mir
@@ -19,13 +19,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rcx
; CHECK-NEXT: MOV64mr %stack.0, 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %stack.0)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: dead [[COPY3:%[0-9]+]]:gr64 = CMOV64rr [[COPY3]], [[MOV32r0_]], 10, implicit undef $eflags
- ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0)
; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = CMOV64rr [[MOV64rm]], [[MOV32r0_1]], 10, implicit undef $eflags
; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[MOV64rm]], [[MOV32r0_2]], 10, implicit undef $eflags
; CHECK-NEXT: $rax = COPY [[CMOV64rr]]
; CHECK-NEXT: RET 0, $rax
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
index 4accaab7f6172..41887223ec78b 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
@@ -310,7 +310,7 @@ body: |
; CHECK-NEXT: bb.5.bb21:
; CHECK-NEXT: successors: %bb.9(0x7c000000), %bb.6(0x04000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @global, $noreg :: (load (s64) from got)
+ ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = lr-split MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @global, $noreg :: (load (s64) from got)
; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64 = MOV64rm [[MOV64rm]], 1, $noreg, 0, $noreg :: (dereferenceable load unordered (s64) from @global)
; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64 = NOT64r [[MOV64rm1]]
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -324,7 +324,7 @@ body: |
; CHECK-NEXT: bb.6.bb33.preheader:
; CHECK-NEXT: successors: %bb.7(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[MOV64rm2:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @global.1, $noreg :: (load (s64) from got)
+ ; CHECK-NEXT: [[MOV64rm2:%[0-9]+]]:gr64 = lr-split MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @global.1, $noreg :: (load (s64) from got)
; CHECK-NEXT: [[MOV64rm3:%[0-9]+]]:gr64 = MOV64rm [[MOV64rm2]], 1, $noreg, 0, $noreg :: (dereferenceable load unordered (s64) from @global.1)
; CHECK-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 660, $gs :: (load (s32) from `ptr addrspace(256) inttoptr (i64 660 to ptr addrspace(256))`, addrspace 256)
; CHECK-NEXT: [[MOV64rm3:%[0-9]+]]:gr64 = NOT64r [[MOV64rm3]]
@@ -342,7 +342,7 @@ body: |
; CHECK-NEXT: [[MOV64rm4:%[0-9]+]]:gr64 = MOV64rm undef %59:gr64, 1, $noreg, 0, $noreg :: (load unordered (s64) from `ptr addrspace(1) undef`, addrspace 1)
; CHECK-NEXT: [[MOV64rm4:%[0-9]+]]:gr64 = NOT64r [[MOV64rm4]]
; CHECK-NEXT: CMP64rr [[MOV64rm4]], [[COPY7]], implicit-def $eflags
- ; CHECK-NEXT: undef [[MOV32ri1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32ri 0
+ ; CHECK-NEXT: undef [[MOV32ri1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = lr-split MOV32ri 0
; CHECK-NEXT: [[MOV64rm4:%[0-9]+]]:gr64 = CMOV64rr [[MOV64rm4]], [[MOV32ri1]], 4, implicit killed $eflags
; CHECK-NEXT: INLINEASM &"lock btsq $0,($1)", sideeffect attdialect, reguse:GR64, [[MOV32ri1]], reguse:GR64, undef %56:gr64, clobber, implicit-def dead early-clobber $df, clobber, implicit-def early-clobber $fpsw, clobber, implicit-def dead early-clobber $eflags
; CHECK-NEXT: LCMPXCHG32 undef %67:gr64, 1, $noreg, 0, $noreg, [[COPY6]], implicit-def dead $eax, implicit-def dead $eflags, implicit undef $eax :: (load store acquire monotonic (s32) on `ptr addrspace(1) undef`, addrspace 1)
@@ -350,7 +350,7 @@ body: |
; CHECK-NEXT: $rdi = COPY [[COPY5]]
; CHECK-NEXT: CALL64pcrel32 target-flags(x86-plt) @wobble, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; CHECK-NEXT: [[MOV64rm5:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @global, $noreg :: (load (s64) from got)
+ ; CHECK-NEXT: [[MOV64rm5:%[0-9]+]]:gr64 = lr-split MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @global, $noreg :: (load (s64) from got)
; CHECK-NEXT: [[MOV64rm6:%[0-9]+]]:gr64 = MOV64rm [[MOV64rm5]], 1, $noreg, 0, $noreg :: (dereferenceable load unordered (s64) from @global)
; CHECK-NEXT: [[MOV64rm6:%[0-9]+]]:gr64 = NOT64r [[MOV64rm6]]
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
index 8d38d687edaad..fc187974e10d2 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
@@ -206,14 +206,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
- ; CHECK-NEXT: dead $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
+ ; CHECK-NEXT: dead $edi = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rdi
; CHECK-NEXT: STATEPOINT 2, 5, 2, undef %24:gr64, $rdi, undef $rsi, 2, 0, 2, 0, 2, 37, 2, 0, 2, 2, 2, 0, 2, 43, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 1, 2, 6, 2, 0, 2, 4, 2, 1, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 2, 2, 4, 2, 5, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 1, 2, 0, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF2:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF3:%[0-9]+]]:gr64 = IMPLICIT_DEF
- ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.bb1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
@@ -252,7 +252,7 @@ body: |
; CHECK-NEXT: MOV32mr %stack.0, 1, $noreg, 0, $noreg, [[LEA64_32r]] :: (store (s32) into %stack.0)
; CHECK-NEXT: EH_LABEL <mcsymbol .Ltmp0>
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; CHECK-NEXT: $ecx = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: $ecx = lr-split MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = lr-split COPY [[LEA64_32r]]
; CHECK-NEXT: [[DEF3:%[0-9]+]]:gr64, [[MOV32r0_:%[0-9]+]]:gr64_with_sub_8bit, [[DEF1:%[0-9]+]]:gr64, dead [[DEF2:%[0-9]+]]:gr64 = STATEPOINT 1, 16, 5, undef %47:gr64, undef $edi, undef $rsi, undef $rdx, $ecx, undef $r8d, 2, 0, 2, 0, 2, 99, 2, 0, 2, 2, 2, 0, 2, 43, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 1, 2, 10, 2, 0, 2, 4, 2, 1, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[MOV32r0_]], 2, 7, 2, 0, 2, 0, [[MOV32r0_]], 2, 10, 2, 5, 2, 12, 2, 0, 2, 3, 2, 1, 2, 0, [[MOV32r0_]], 2, 0, [[MOV32r0_]], 2, 7, 2, 0, 2, 0, [[MOV32r0_]], 2, 2, 2, 11, 2, 4, 2, 0, 2, 1, 2, 0, 2, 7, 2, 0, 2, 2, 2, 15, 2, 7, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 21, 2, 96, 2, 0, 2, 9, 2, 1, 2, 0, [[DEF3]], 2, 0, [[DEF2]], 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[DEF1]], 2, 3, 1, 4, %stack.0, 0, 2, 3, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[DEF1]], 2, 8, 2, 12, 2, 34, 2, 0, 2, 3, 2, 1, 2, 0, [[DEF3]], 2, 0, 2, 4278124286, 2, 7, 2, 0, 2, 0, 2, 4278124286, 2, 5, [[DEF3]](tied-def 0), [[MOV32r0_]](tied-def 1), [[DEF1]](tied-def 2), [[DEF2]](tied-def 3), 2, 4278124286, 2, 0, 2, 5, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s32) on %stack.0)
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -277,7 +277,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: EH_LABEL <mcsymbol .Ltmp2>
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; CHECK-NEXT: $edi = MOV32ri 3
+ ; CHECK-NEXT: $edi = lr-split MOV32ri 3
; CHECK-NEXT: dead [[MOV32r0_:%[0-9]+]]:gr64_with_sub_8bit, dead [[DEF1:%[0-9]+]]:gr64 = STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @wombat, $edi, 2, 0, 2, 2, 2, 97, 2, 0, 2, 2, 2, 0, 2, 43, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 1, 2, 10, 2, 0, 2, 4, 2, 1, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[MOV32r0_]], 2, 7, 2, 0, 2, 0, [[MOV32r0_]], 2, 10, 2, 5, 2, 12, 2, 0, 2, 3, 2, 1, 2, 0, [[MOV32r0_]], 2, 0, [[MOV32r0_]], 2, 7, 2, 0, 2, 0, [[MOV32r0_]], 2, 2, 2, 11, 2, 4, 2, 0, 2, 1, 2, 0, 2, 7, 2, 0, 2, 2, 2, 15, 2, 7, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 21, 2, 96, 2, 0, 2, 9, 2, 1, 2, 0, 2, 4278124286, 2, 0, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[DEF1]], 2, 3, [[MOV32r0_1]], 2, 3, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 0, 2, 0, [[DEF1]], 2, 0, 2, 12, 2, 51, 2, 0, 2, 3, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 3, [[MOV32r0_]](tied-def 0), 2, 4278124286, [[DEF1]](tied-def 1), 2, 0, 2, 3, 0, 0, 1, 1, 2, 2, csr_64, implicit-def $rsp, implicit-def $ssp
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
bb.0.bb:
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
index 01e5966e8d6a3..0793761087b2b 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
@@ -30,10 +30,10 @@
# CHECK: MOV32mr %stack.5, 1, $noreg, 0, $noreg, %40 :: (store (s32) into %stack.5)
# CHECK: EH_LABEL <mcsymbol .Ltmp0>
# CHECK: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-# CHECK: $edi = MOV32r0 implicit-def dead $eflags
-# CHECK: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+# CHECK: $edi = lr-split MOV32r0 implicit-def dead $eflags
+# CHECK: dead $esi = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rsi
# CHECK: $ecx = COPY %7
-# CHECK: $r8d = MOV32r0 implicit-def dead $eflags
+# CHECK: $r8d = lr-split MOV32r0 implicit-def dead $eflags
# CHECK: %37:gr64 = lr-split COPY %38
# CHECK: %17:gr64, %16:gr64, %13:gr64, %37:gr64 = STATEPOINT 1, 16, 5, undef %23:gr64, $edi, $rsi, undef $edx, $ecx, $r8d, 2, 0, 2, 0, 2, 11, 1, 4, %stack.0, 0, %13, 1, 4, %stack.1, 0, 1, 4, %stack.2, 0, 1, 4, %stack.3, 0, 1, 4, %stack.4, 0, 1, 4, %stack.2, 0, %37, 1, 4, %stack.5, 0, %16, %17, 2, 4, %17(tied-def 0), %16(tied-def 1), %13(tied-def 2), %37(tied-def 3), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_64, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax :: (volatile load store (s32) on %stack.0), (volatile load store (s32) on %stack.1), (volatile load store (s32) on %stack.2), (volatile load store (s32) on %stack.3), (volatile load store (s32) on %stack.4), (volatile load store (s32) on %stack.5)
# CHECK: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -41,7 +41,7 @@
# CHECK: JMP_1 %bb.1
# CHECK: bb.1.bb21:
# CHECK: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-# CHECK: $edi = MOV32ri 10
+# CHECK: $edi = lr-split MOV32ri 10
# CHECK: dead %13:gr64, dead %16:gr64, dead %17:gr64 = STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @quux, $edi, 2, 0, 2, 2, 2, 10, 1, 4, %stack.9, 0, %13, %7, %33.sub_32bit, 1, 4, %stack.6, 0, 1, 4, %stack.8, 0, %33.sub_32bit, 1, 4, %stack.7, 0, %16, %17, 2, 3, %13(tied-def 0), %16(tied-def 1), %17(tied-def 2), 2, 0, 2, 3, 0, 0, 1, 1, 2, 2, csr_64, implicit-def $rsp, implicit-def $ssp :: (load (s32) from %stack.6), (load (s32) from %stack.7), (load (s32) from %stack.8), (load (s32) from %stack.9)
# CHECK: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
# CHECK: RET 0
@@ -56,7 +56,7 @@
# CHECK: %41:gr32 = MOV32rm %stack.7, 1, $noreg, 0, $noreg :: (load (s32) from %stack.7)
# CHECK: MOV32mr %stack.4, 1, $noreg, 0, $noreg, %41 :: (store (s32) into %stack.4)
# CHECK: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-# CHECK: $edi = MOV32ri -271
+# CHECK: $edi = lr-split MOV32ri -271
# CHECK: dead %37:gr64 = STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @quux, $edi, 2, 0, 2, 0, 2, 6, 1, 4, %stack.0, 0, 1, 4, %stack.1, 0, 1, 4, %stack.2, 0, 1, 4, %stack.3, 0, %37, 1, 4, %stack.4, 0, 2, 1, %37(tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store (s32) on %stack.0), (volatile load store (s32) on %stack.1), (volatile load store (s32) on %stack.2), (volatile load store (s32) on %stack.3), (volatile load store (s32) on %stack.4)
# CHECK: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
diff --git a/llvm/test/CodeGen/X86/statepoint-ra.ll b/llvm/test/CodeGen/X86/statepoint-ra.ll
index 5a4e04dd70553..a43dec88bdc33 100644
--- a/llvm/test/CodeGen/X86/statepoint-ra.ll
+++ b/llvm/test/CodeGen/X86/statepoint-ra.ll
@@ -100,7 +100,7 @@ declare token @llvm.experimental.gc.statepoint.p0(i64 , i32 , ptr, i32 , i32 , .
;CHECK: successors: %bb.3(0x80000000)
;CHECK: ADJCALLSTACKDOWN64 8, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
;CHECK: MOVSDmr $rsp, 1, $noreg, 0, $noreg, %14 :: (store (s64) into stack)
-;CHECK: dead $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
+;CHECK: dead $edi = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rdi
;CHECK: $xmm0 = COPY %68
;CHECK: $xmm1 = COPY %64
;CHECK: $xmm2 = COPY %6
@@ -140,10 +140,10 @@ declare token @llvm.experimental.gc.statepoint.p0(i64 , i32 , ptr, i32 , i32 , .
;CHECK: $xmm3 = MOVSDrm_alt %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %stack.2)
;CHECK: $xmm4 = MOVSDrm_alt %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %stack.1)
;CHECK: $xmm5 = MOVSDrm_alt %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %stack.3)
-;CHECK: %80:fr64 = MOVSDrm_alt %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.3, align 16)
+;CHECK: %80:fr64 = lr-split MOVSDrm_alt %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.3, align 16)
;CHECK: $xmm6 = COPY %80
;CHECK: $esi = MOV32ri 51
-;CHECK: %75:fr64 = MOVSDrm_alt %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.2)
+;CHECK: %75:fr64 = lr-split MOVSDrm_alt %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.2)
;CHECK: $xmm7 = COPY %75
;CHECK: STATEPOINT 2, 5, 10, undef %36:gr64, undef $rdi, $xmm0, $xmm1, $xmm2, $xmm3, $xmm4, $xmm5, $xmm6, $xmm7, killed $esi, 2, 0, 2, 0, 2, 105, 2, 0, 2, 2, 2, 0, 2, 97, 2, 0, 2, 26, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 2, 2, 2, 2, 46, 2, 0, 2, 20, 2, 0, 2, 0, 2, 4278124286, 2, 4, 1, 8, %stack.6, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.5, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.4, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.2, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.3, 0, 2, 7, 2, 0, 2, 4, 1, 8, %fixed-stack.3, 0, 2, 7, 2, 0, 2, 4, 1, 8, %fixed-stack.2, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.7, 0, 2, 7, 2, 0, 2, 3, 2, 51, 2, 1, 2, 4278124286, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp :: (load (s64) from %stack.1), (load (s64) from %stack.2), (load (s64) from %stack.3), (load (s64) from %stack.4), (load (s64) from %stack.5), (load (s64) from %stack.6), (load (s64) from %fixed-stack.2), (load (s64) from %fixed-stack.3, align 16), (load (s64) from %stack.7)
;CHECK: ADJCALLSTACKUP64 8, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll
index 2a0710e3249a6..e81bef5c34d4c 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll
@@ -64,9 +64,9 @@ define void @test_mixed(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(
; CHECK-PREG: renamable $r15 = COPY $rdi
; CHECK-PREG: renamable $rbx, renamable $r14, renamable $r15 = STATEPOINT 0, 0, 0, @func, 2, 0, 2, 0, 2, 0, 2, 4, killed renamable $rbx(tied-def 0), 2, 0, killed renamable $r14(tied-def 1), killed renamable $r15(tied-def 2), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_64, implicit-def $rsp, implicit-def $ssp
; CHECK-PREG: $rdi = COPY killed renamable $r15
-; CHECK-PREG: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+; CHECK-PREG: dead $esi = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rsi
; CHECK-PREG: $rdx = COPY killed renamable $r14
-; CHECK-PREG: dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
+; CHECK-PREG: dead $ecx = lr-split MOV32r0 implicit-def dead $eflags, implicit-def $rcx
; CHECK-PREG: $r8 = COPY killed renamable $rbx
; CHECK-PREG: CALL64pcrel32 @consume5, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit killed $rcx, implicit killed $r8, implicit-def $rsp, implicit-def $ssp
More information about the llvm-commits
mailing list