[llvm] [IR] Implementation and lowering of bitinsert and bitextract (PR #200605)
Alexis Engelke via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 12:05:19 PDT 2026
================
@@ -0,0 +1,908 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefix=AARCH64
+
+define i16 @test_bitextract_var(b32 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsr w0, w0, w1
+; AARCH64-NEXT: ret
+ %result = bitextract i16, b32 %src, i32 %off
+ ret i16 %result
+}
+
+define i16 @test_bitextract_const(b32 %src) {
+; AARCH64-LABEL: test_bitextract_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsr w0, w0, #8
+; AARCH64-NEXT: ret
+ %result = bitextract i16, b32 %src, i32 8
+ ret i16 %result
+}
+
+define i8 @test_bitextract_narrow(b64 %src) {
+; AARCH64-LABEL: test_bitextract_narrow:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: // kill: def $w0 killed $w0 killed $x0
+; AARCH64-NEXT: ret
+ %result = bitextract i8, b64 %src, i32 0
+ ret i8 %result
+}
+
+define i1 @test_bitextract_b1(b1 %src) {
+; AARCH64-LABEL: test_bitextract_b1:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and w0, w0, #0x1
+; AARCH64-NEXT: ret
+ %result = bitextract i1, b1 %src, i32 0
+ ret i1 %result
+}
+
+define i8 @test_bitextract_b37(b37 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_b37:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and x8, x0, #0x1fffffffff
+; AARCH64-NEXT: // kill: def $w1 killed $w1 def $x1
+; AARCH64-NEXT: lsr x0, x8, x1
+; AARCH64-NEXT: // kill: def $w0 killed $w0 killed $x0
+; AARCH64-NEXT: ret
+ %result = bitextract i8, b37 %src, i32 %off
+ ret i8 %result
+}
+
+define i8 @test_bitextract_b37_const(b37 %src) {
+; AARCH64-LABEL: test_bitextract_b37_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: ubfx x0, x0, #20, #17
+; AARCH64-NEXT: // kill: def $w0 killed $w0 killed $x0
+; AARCH64-NEXT: ret
+ %result = bitextract i8, b37 %src, i32 20
+ ret i8 %result
+}
+
+define i16 @test_bitextract_b87(b87 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_b87:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and x8, x1, #0x7fffff
+; AARCH64-NEXT: mov w10, w2
+; AARCH64-NEXT: mvn w11, w2
+; AARCH64-NEXT: lsl x9, x8, #1
+; AARCH64-NEXT: lsr x12, x0, x10
+; AARCH64-NEXT: lsr x8, x8, x10
+; AARCH64-NEXT: tst x10, #0x40
+; AARCH64-NEXT: lsl x9, x9, x11
+; AARCH64-NEXT: orr x9, x9, x12
+; AARCH64-NEXT: csel x0, x8, x9, ne
+; AARCH64-NEXT: // kill: def $w0 killed $w0 killed $x0
+; AARCH64-NEXT: ret
+ %result = bitextract i16, b87 %src, i32 %off
+ ret i16 %result
+}
+
+
+define i32 @test_bitextract_b128(b128 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_b128:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsl x8, x1, #1
+; AARCH64-NEXT: mov w9, w2
+; AARCH64-NEXT: mvn w10, w2
+; AARCH64-NEXT: lsr x11, x0, x9
+; AARCH64-NEXT: tst x9, #0x40
+; AARCH64-NEXT: lsl x8, x8, x10
+; AARCH64-NEXT: lsr x10, x1, x9
+; AARCH64-NEXT: orr x8, x8, x11
+; AARCH64-NEXT: csel x0, x10, x8, ne
+; AARCH64-NEXT: // kill: def $w0 killed $w0 killed $x0
+; AARCH64-NEXT: ret
+ %result = bitextract i32, b128 %src, i32 %off
+ ret i32 %result
+}
+
+define i32 @test_bitextract_b231(b231 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_b231:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: stp x0, x1, [sp, #-64]!
+; AARCH64-NEXT: .cfi_def_cfa_offset 64
+; AARCH64-NEXT: movi v0.2d, #0000000000000000
+; AARCH64-NEXT: mov w8, w4
+; AARCH64-NEXT: and x10, x3, #0x7fffffffff
+; AARCH64-NEXT: lsr x9, x8, #3
+; AARCH64-NEXT: mov x11, sp
+; AARCH64-NEXT: stp x2, x10, [sp, #16]
+; AARCH64-NEXT: and x9, x9, #0x18
+; AARCH64-NEXT: stp q0, q0, [sp, #32]
+; AARCH64-NEXT: add x9, x11, x9
+; AARCH64-NEXT: mvn w11, w4
+; AARCH64-NEXT: ldp x9, x10, [x9]
+; AARCH64-NEXT: lsl x10, x10, #1
+; AARCH64-NEXT: lsr x8, x9, x8
+; AARCH64-NEXT: lsl x10, x10, x11
+; AARCH64-NEXT: orr w0, w10, w8
+; AARCH64-NEXT: add sp, sp, #64
+; AARCH64-NEXT: ret
+ %result = bitextract i32, b231 %src, i32 %off
+ ret i32 %result
+}
+
+
+
+; Bitinsert
+define b32 @test_bitinsert_var(b32 %base, i16 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: neg w8, w2
+; AARCH64-NEXT: mov w9, #-65536 // =0xffff0000
+; AARCH64-NEXT: and w10, w1, #0xffff
+; AARCH64-NEXT: ror w8, w9, w8
+; AARCH64-NEXT: lsl w9, w10, w2
+; AARCH64-NEXT: and w8, w0, w8
+; AARCH64-NEXT: orr w0, w8, w9
+; AARCH64-NEXT: ret
+ %result = bitinsert b32 %base, i16 %val, i32 %off
+ ret b32 %result
+}
+
+define b1 @test_bitinsert_b1(b1 %base, i1 %val) {
+; AARCH64-LABEL: test_bitinsert_b1:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and w0, w1, #0x1
+; AARCH64-NEXT: ret
+ %result = bitinsert b1 %base, i1 %val, i32 0
+ ret b1 %result
+}
+
+define b37 @test_bitinsert_b37_var(b37 %base, i8 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_b37_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: mov x9, #46053 // =0xb3e5
+; AARCH64-NEXT: // kill: def $w2 killed $w2 def $x2
+; AARCH64-NEXT: mov w8, w2
+; AARCH64-NEXT: mov w10, #37 // =0x25
+; AARCH64-NEXT: movk x9, #12398, lsl #16
+; AARCH64-NEXT: mov x11, #68719476608 // =0xfffffff80
+; AARCH64-NEXT: // kill: def $w1 killed $w1 def $x1
+; AARCH64-NEXT: movk x9, #15941, lsl #32
+; AARCH64-NEXT: movk x9, #1771, lsl #48
+; AARCH64-NEXT: umulh x9, x8, x9
+; AARCH64-NEXT: umsubl x8, w9, w10, x8
+; AARCH64-NEXT: mov w9, #36 // =0x24
+; AARCH64-NEXT: mov x10, #137438953216 // =0x1fffffff00
+; AARCH64-NEXT: sub x9, x9, x8
+; AARCH64-NEXT: lsl x8, x10, x8
+; AARCH64-NEXT: and x10, x1, #0xff
+; AARCH64-NEXT: lsr x9, x11, x9
+; AARCH64-NEXT: orr x8, x8, x9
+; AARCH64-NEXT: lsl x9, x10, x2
+; AARCH64-NEXT: and x8, x0, x8
+; AARCH64-NEXT: orr x0, x8, x9
+; AARCH64-NEXT: ret
+ %result = bitinsert b37 %base, i8 %val, i32 %off
+ ret b37 %result
+}
+
+define b87 @test_bitinsert_b87_var(b87 %base, i16 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_b87_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: mov x9, #39171 // =0x9903
+; AARCH64-NEXT: mov w8, w3
+; AARCH64-NEXT: mov w10, #87 // =0x57
+; AARCH64-NEXT: movk x9, #12052, lsl #16
+; AARCH64-NEXT: mov x11, #9223372036854743040 // =0x7fffffffffff8000
+; AARCH64-NEXT: mov w13, #8388607 // =0x7fffff
+; AARCH64-NEXT: movk x9, #18832, lsl #32
+; AARCH64-NEXT: mov w14, #86 // =0x56
+; AARCH64-NEXT: // kill: def $w2 killed $w2 def $x2
+; AARCH64-NEXT: mvn w15, w3
+; AARCH64-NEXT: movk x9, #753, lsl #48
+; AARCH64-NEXT: and x16, x2, #0xffff
+; AARCH64-NEXT: umulh x9, x8, x9
+; AARCH64-NEXT: lsl x16, x16, x8
+; AARCH64-NEXT: umsubl x9, w9, w10, x8
+; AARCH64-NEXT: mov x10, #-65536 // =0xffffffffffff0000
+; AARCH64-NEXT: mvn w12, w9
+; AARCH64-NEXT: lsl x13, x13, x9
+; AARCH64-NEXT: sub x14, x14, x9
+; AARCH64-NEXT: lsr x11, x11, x12
+; AARCH64-NEXT: mov w12, #8388606 // =0x7ffffe
+; AARCH64-NEXT: lsl x10, x10, x9
+; AARCH64-NEXT: tst x9, #0x40
+; AARCH64-NEXT: mvn w9, w14
+; AARCH64-NEXT: orr x11, x13, x11
+; AARCH64-NEXT: mov x13, #-32768 // =0xffffffffffff8000
+; AARCH64-NEXT: lsl x9, x12, x9
+; AARCH64-NEXT: mov w12, #4194303 // =0x3fffff
+; AARCH64-NEXT: lsr x13, x13, x14
+; AARCH64-NEXT: csel x11, x10, x11, ne
+; AARCH64-NEXT: lsr x12, x12, x14
+; AARCH64-NEXT: csel x10, xzr, x10, ne
+; AARCH64-NEXT: tst x14, #0x40
+; AARCH64-NEXT: ubfx x14, x2, #1, #15
+; AARCH64-NEXT: orr x9, x9, x13
+; AARCH64-NEXT: csel x13, xzr, x12, ne
+; AARCH64-NEXT: csel x9, x12, x9, ne
+; AARCH64-NEXT: tst x8, #0x40
+; AARCH64-NEXT: lsr x14, x14, x15
+; AARCH64-NEXT: orr x11, x11, x13
+; AARCH64-NEXT: orr x8, x10, x9
+; AARCH64-NEXT: and x9, x1, x11
+; AARCH64-NEXT: and x8, x0, x8
+; AARCH64-NEXT: csel x11, xzr, x16, ne
+; AARCH64-NEXT: csel x10, x16, x14, ne
+; AARCH64-NEXT: orr x0, x8, x11
+; AARCH64-NEXT: orr x1, x9, x10
+; AARCH64-NEXT: ret
+ %result = bitinsert b87 %base, i16 %val, i32 %off
+ ret b87 %result
+}
+
+define b128 @test_bitinsert_b128_var(b128 %base, i32 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_b128_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: mov w8, w3
+; AARCH64-NEXT: mov x9, #-4294967296 // =0xffffffff00000000
+; AARCH64-NEXT: mov w10, w2
+; AARCH64-NEXT: tst x8, #0x40
+; AARCH64-NEXT: lsr x12, x10, #1
+; AARCH64-NEXT: mvn w14, w3
+; AARCH64-NEXT: csinv x11, x9, xzr, eq
+; AARCH64-NEXT: csinv x9, x9, xzr, ne
+; AARCH64-NEXT: lsl x10, x10, x8
+; AARCH64-NEXT: lsr x13, x11, #1
+; AARCH64-NEXT: lsr x15, x9, #1
+; AARCH64-NEXT: lsr x12, x12, x14
+; AARCH64-NEXT: lsl x9, x9, x8
+; AARCH64-NEXT: lsl x8, x11, x8
+; AARCH64-NEXT: lsr x13, x13, x14
+; AARCH64-NEXT: lsr x14, x15, x14
+; AARCH64-NEXT: csel x11, x10, x12, ne
+; AARCH64-NEXT: csel x10, xzr, x10, ne
+; AARCH64-NEXT: orr x9, x9, x13
+; AARCH64-NEXT: orr x8, x8, x14
+; AARCH64-NEXT: and x9, x1, x9
+; AARCH64-NEXT: and x8, x0, x8
+; AARCH64-NEXT: orr x0, x8, x10
+; AARCH64-NEXT: orr x1, x9, x11
+; AARCH64-NEXT: ret
+ %result = bitinsert b128 %base, i32 %val, i32 %off
+ ret b128 %result
+}
+
+define b231 @test_bitinsert_b231_var(b231 %base, i32 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_b231_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: sub sp, sp, #256
+; AARCH64-NEXT: stp x24, x23, [sp, #208] // 16-byte Folded Spill
+; AARCH64-NEXT: stp x22, x21, [sp, #224] // 16-byte Folded Spill
+; AARCH64-NEXT: stp x20, x19, [sp, #240] // 16-byte Folded Spill
+; AARCH64-NEXT: .cfi_def_cfa_offset 256
+; AARCH64-NEXT: .cfi_offset w19, -8
+; AARCH64-NEXT: .cfi_offset w20, -16
+; AARCH64-NEXT: .cfi_offset w21, -24
+; AARCH64-NEXT: .cfi_offset w22, -32
+; AARCH64-NEXT: .cfi_offset w23, -40
+; AARCH64-NEXT: .cfi_offset w24, -48
+; AARCH64-NEXT: .cfi_offset w25, -64
+; AARCH64-NEXT: mov x9, #53905 // =0xd291
+; AARCH64-NEXT: mov x8, #549755813887 // =0x7fffffffff
+; AARCH64-NEXT: mov w12, #231 // =0xe7
+; AARCH64-NEXT: movk x9, #1134, lsl #16
+; AARCH64-NEXT: stp x8, x25, [sp, #184] // 8-byte Folded Spill
+; AARCH64-NEXT: mov x8, #-4294967296 // =0xffffffff00000000
+; AARCH64-NEXT: movk x9, #46244, lsl #32
+; AARCH64-NEXT: str x8, [sp, #160]
+; AARCH64-NEXT: mov w8, w5
+; AARCH64-NEXT: movk x9, #283, lsl #48
+; AARCH64-NEXT: mov x10, #-1 // =0xffffffffffffffff
+; AARCH64-NEXT: mov x11, #274877906943 // =0x3fffffffff
+; AARCH64-NEXT: umulh x9, x8, x9
+; AARCH64-NEXT: stp x10, x11, [sp, #80]
+; AARCH64-NEXT: mov x11, #-2147483648 // =0xffffffff80000000
+; AARCH64-NEXT: stp x10, x10, [sp, #168]
+; AARCH64-NEXT: mov w13, #230 // =0xe6
+; AARCH64-NEXT: movi v0.2d, #0000000000000000
+; AARCH64-NEXT: stp x11, x10, [sp, #64]
+; AARCH64-NEXT: mov w11, w4
+; AARCH64-NEXT: lsr x19, x8, #3
+; AARCH64-NEXT: stp xzr, xzr, [sp, #112]
+; AARCH64-NEXT: mov x21, sp
+; AARCH64-NEXT: stp xzr, xzr, [sp, #96]
+; AARCH64-NEXT: add x21, x21, #32
+; AARCH64-NEXT: and x19, x19, #0x18
+; AARCH64-NEXT: umsubl x9, w9, w12, x8
+; AARCH64-NEXT: add x12, sp, #128
+; AARCH64-NEXT: stur q0, [sp, #40]
+; AARCH64-NEXT: add x12, x12, #32
+; AARCH64-NEXT: stp q0, q0, [sp]
+; AARCH64-NEXT: sub x19, x21, x19
+; AARCH64-NEXT: stp q0, q0, [sp, #128]
+; AARCH64-NEXT: lsr x10, x9, #3
+; AARCH64-NEXT: str xzr, [sp, #56]
+; AARCH64-NEXT: and x16, x9, #0x3f
+; AARCH64-NEXT: str x11, [sp, #32]
+; AARCH64-NEXT: and x10, x10, #0x18
+; AARCH64-NEXT: sub x14, x12, x10
+; AARCH64-NEXT: sub x10, x13, x9
+; AARCH64-NEXT: add x13, sp, #64
+; AARCH64-NEXT: lsr x12, x10, #3
+; AARCH64-NEXT: ldp x11, x15, [x14]
+; AARCH64-NEXT: mvn w7, w10
+; AARCH64-NEXT: ldp x21, x14, [x14, #16]
+; AARCH64-NEXT: and x12, x12, #0x18
+; AARCH64-NEXT: and x23, x10, #0x3f
+; AARCH64-NEXT: add x4, x13, x12
+; AARCH64-NEXT: eor x12, x16, #0x3f
+; AARCH64-NEXT: lsr x18, x11, #1
+; AARCH64-NEXT: ldp x13, x16, [x4, #8]
+; AARCH64-NEXT: lsl x17, x15, x9
+; AARCH64-NEXT: lsr x6, x18, x12
+; AARCH64-NEXT: ldr x18, [x4, #24]
+; AARCH64-NEXT: lsr x15, x15, #1
+; AARCH64-NEXT: lsl x25, x21, x9
+; AARCH64-NEXT: ldr x4, [x4]
+; AARCH64-NEXT: lsl x14, x14, x9
+; AARCH64-NEXT: lsl x20, x16, #1
+; AARCH64-NEXT: lsr x22, x13, x10
+; AARCH64-NEXT: orr x17, x17, x6
+; AARCH64-NEXT: lsl x24, x18, #1
+; AARCH64-NEXT: lsr x16, x16, x10
+; AARCH64-NEXT: lsl x13, x13, #1
+; AARCH64-NEXT: lsl x7, x20, x7
+; AARCH64-NEXT: lsr x18, x18, x10
+; AARCH64-NEXT: lsr x10, x4, x10
+; AARCH64-NEXT: orr x6, x22, x7
+; AARCH64-NEXT: mvn w22, w9
+; AARCH64-NEXT: lsl x9, x11, x9
+; AARCH64-NEXT: lsr x15, x15, x22
+; AARCH64-NEXT: eor x22, x23, #0x3f
+; AARCH64-NEXT: orr x17, x17, x6
+; AARCH64-NEXT: ldp x20, x7, [x19]
+; AARCH64-NEXT: lsl x24, x24, x22
+; AARCH64-NEXT: orr x15, x25, x15
+; AARCH64-NEXT: and x23, x8, #0x3f
+; AARCH64-NEXT: and x17, x1, x17
+; AARCH64-NEXT: orr x16, x24, x16
+; AARCH64-NEXT: eor x1, x23, #0x3f
+; AARCH64-NEXT: lsl x13, x13, x22
+; AARCH64-NEXT: orr x15, x15, x16
+; AARCH64-NEXT: lsr x16, x7, #1
+; AARCH64-NEXT: lsl x23, x7, x8
+; AARCH64-NEXT: and x15, x2, x15
+; AARCH64-NEXT: mvn w2, w5
+; AARCH64-NEXT: lsr x6, x20, #1
+; AARCH64-NEXT: lsr x16, x16, x2
+; AARCH64-NEXT: ldp x7, x2, [x19, #16]
+; AARCH64-NEXT: lsr x19, x21, #1
+; AARCH64-NEXT: lsr x6, x6, x1
+; AARCH64-NEXT: orr x14, x14, x18
+; AARCH64-NEXT: orr x9, x9, x10
+; AARCH64-NEXT: ldp x22, x21, [sp, #224] // 16-byte Folded Reload
+; AARCH64-NEXT: lsr x11, x19, x12
+; AARCH64-NEXT: lsr x12, x7, #1
+; AARCH64-NEXT: lsl x5, x7, x8
+; AARCH64-NEXT: lsl x18, x2, x8
+; AARCH64-NEXT: orr x6, x23, x6
+; AARCH64-NEXT: orr x9, x9, x13
+; AARCH64-NEXT: lsr x10, x12, x1
+; AARCH64-NEXT: lsl x8, x20, x8
+; AARCH64-NEXT: orr x11, x14, x11
+; AARCH64-NEXT: ldp x20, x19, [sp, #240] // 16-byte Folded Reload
+; AARCH64-NEXT: orr x12, x5, x16
+; AARCH64-NEXT: ldp x24, x23, [sp, #208] // 16-byte Folded Reload
+; AARCH64-NEXT: and x9, x0, x9
+; AARCH64-NEXT: and x11, x3, x11
+; AARCH64-NEXT: orr x10, x18, x10
+; AARCH64-NEXT: ldr x25, [sp, #192] // 8-byte Reload
+; AARCH64-NEXT: orr x0, x9, x8
+; AARCH64-NEXT: orr x1, x17, x6
+; AARCH64-NEXT: orr x2, x15, x12
+; AARCH64-NEXT: orr x3, x11, x10
+; AARCH64-NEXT: add sp, sp, #256
+; AARCH64-NEXT: ret
+ %result = bitinsert b231 %base, i32 %val, i32 %off
+ ret b231 %result
+}
+
+
+; different inserted value widths
+
+define b1 @test_bitinsert_b1_var(b1 %base, i1 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_b1_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and w0, w1, #0x1
+; AARCH64-NEXT: ret
+ %result = bitinsert b1 %base, i1 %val, i32 %off
+ ret b1 %result
+}
+
+define b8 @test_bitinsert_b8_var(b8 %base, i4 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_b8_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: mov w8, w2
+; AARCH64-NEXT: mov w9, #-3856 // =0xfffff0f0
+; AARCH64-NEXT: and x8, x8, #0x7
+; AARCH64-NEXT: lsl w8, w9, w8
+; AARCH64-NEXT: and w9, w1, #0xf
+; AARCH64-NEXT: lsl w9, w9, w2
+; AARCH64-NEXT: and w8, w0, w8, lsr #8
+; AARCH64-NEXT: orr w0, w8, w9
+; AARCH64-NEXT: ret
+ %result = bitinsert b8 %base, i4 %val, i32 %off
+ ret b8 %result
+}
+
+define b8 @test_bitinsert_b8_const(b8 %base, i4 %val) {
+; AARCH64-LABEL: test_bitinsert_b8_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: bfi w0, w1, #3, #4
+; AARCH64-NEXT: ret
+ %result = bitinsert b8 %base, i4 %val, i32 3
+ ret b8 %result
+}
+
+define b21 @test_bitinsert_b21_var(b21 %base, i6 %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_b21_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: mov x9, #3121 // =0xc31
+; AARCH64-NEXT: mov w8, w2
+; AARCH64-NEXT: mov w10, #21 // =0x15
+; AARCH64-NEXT: movk x9, #12483, lsl #16
+; AARCH64-NEXT: mov w11, #1048544 // =0xfffe0
+; AARCH64-NEXT: movk x9, #49932, lsl #32
+; AARCH64-NEXT: movk x9, #3120, lsl #48
+; AARCH64-NEXT: umulh x9, x8, x9
+; AARCH64-NEXT: umsubl x8, w9, w10, x8
+; AARCH64-NEXT: mov w9, #20 // =0x14
+; AARCH64-NEXT: mov w10, #2097088 // =0x1fffc0
+; AARCH64-NEXT: sub x9, x9, x8
+; AARCH64-NEXT: lsl w8, w10, w8
+; AARCH64-NEXT: and w10, w1, #0x3f
+; AARCH64-NEXT: lsr w9, w11, w9
+; AARCH64-NEXT: orr w8, w8, w9
+; AARCH64-NEXT: lsl w9, w10, w2
+; AARCH64-NEXT: and w8, w0, w8
+; AARCH64-NEXT: orr w0, w8, w9
+; AARCH64-NEXT: ret
+ %result = bitinsert b21 %base, i6 %val, i32 %off
+ ret b21 %result
+}
+
+define b21 @test_bitinsert_b21_const(b21 %base, i6 %val) {
+; AARCH64-LABEL: test_bitinsert_b21_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and w8, w0, #0x1fffff
+; AARCH64-NEXT: and w0, w8, #0xfff03fff
+; AARCH64-NEXT: bfi w0, w1, #14, #6
----------------
aengelke wrote:
Ands are unnecessary?
https://github.com/llvm/llvm-project/pull/200605
More information about the llvm-commits
mailing list