[llvm] [AMDGPU] Fix maximum physical LDS reporting for gfx6 (PR #223185)
Chinmay Deshpande via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 11:56:31 PDT 2026
https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/223185
>From 9f58bae2dda197ac0cf2f36461e895eb453f2bf5 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Sat, 12 Sep 2026 18:21:29 -0400
Subject: [PATCH 1/5] [AMDGPU] Fix LDS reporting for gfx6
Change-Id: Idaa597f95d7a3028e3848726948892b1f66a220d
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 9 +++++----
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 7 ++++---
llvm/test/CodeGen/AMDGPU/occupancy-levels.ll | 14 +++++++-------
.../unittests/Target/AMDGPU/AMDGPUUnitTests.cpp | 17 +++++++++++++++++
.../unittests/TargetParser/TargetParserTest.cpp | 6 +++++-
5 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 30db12b565082..5eaa5df801690 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -270,9 +270,9 @@ defm LDSMisalignedBug : AMDGPUSubtargetFeature<"lds-misaligned-bug",
/*GenPredicate=*/0
>;
-// Set for gfx10/11/12 where a work-group can address only half of the physical
-// LDS block. So the physical block is twice the addressable size, for example
-// 128k physical and 64k addressable.
+// Set where a work-group can address only half of the physical LDS block:
+// gfx6 has 64 KiB physical and 32 KiB addressable, while gfx10/11/12 have
+// 128 KiB physical and 64 KiB addressable.
defm HalfAddressablePhysicalLocalMemory : AMDGPUSubtargetFeature<"half-addressable-physical-local-memory",
"A work-group can address only half of the physical LDS block",
/*GenPredicate=*/0
@@ -1619,7 +1619,8 @@ class GCNSubtargetFeatureGeneration <string Value,
def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
"southern-islands",
- [FeatureFP64, FeatureAddressableLocalMemorySize32768, FeatureMIMG_R128,
+ [FeatureFP64, FeatureAddressableLocalMemorySize32768,
+ FeatureHalfAddressablePhysicalLocalMemory, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureSupportsWave64, FeatureSMemTimeInst,
FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 88e2d2f485262..58ca7e69cecf8 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1130,8 +1130,9 @@ static unsigned getMaxHWAddressableLocalMemorySize(const MCSubtargetInfo &STI) {
// Total physical size of LDS on the block, in bytes. On targets with
// FeatureHalfAddressablePhysicalLocalMemory the physical block is twice the
-// addressable size (gfx10/11/12, 128k physical and 64k addressable). On other
-// targets it is equal to the addressable size.
+// addressable size (gfx6: 64 KiB physical and 32 KiB addressable;
+// gfx10/11/12: 128 KiB physical and 64 KiB addressable). On other targets it is
+// equal to the addressable size.
static unsigned getPhysicalLocalMemorySize(const MCSubtargetInfo &STI) {
unsigned Addressable = getMaxHWAddressableLocalMemorySize(STI);
if (STI.getFeatureBits().test(FeatureHalfAddressablePhysicalLocalMemory))
@@ -1140,7 +1141,7 @@ static unsigned getPhysicalLocalMemorySize(const MCSubtargetInfo &STI) {
}
// Sizes in use, by generation (addressable / physical block):
-// gfx6 : 32 KiB
+// gfx6 : 32 KiB addressable, 64 KiB physical block
// gfx7 / gfx8 / gfx9: 64 KiB
// gfx9.5 (gfx950) : 160 KiB
// gfx10 / 11 / 12 : 64 KiB addressable, 128 KiB physical block
diff --git a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
index b7ee93228e7aa..3299f9d1ce2f6 100644
--- a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+++ b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
@@ -656,7 +656,7 @@ define amdgpu_kernel void @used_lds_13112() {
}
; GCN-LABEL: {{^}}used_lds_8252_max_group_size_64:
-; GFX6: ; Occupancy: 1{{$}}
+; GFX6: ; Occupancy: 2{{$}}
; GFX7: ; Occupancy: 2{{$}}
; GFX8: ; Occupancy: 2{{$}}
; GFX9: ; Occupancy: 2{{$}}
@@ -680,7 +680,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_64() #3 {
}
; GCN-LABEL: {{^}}used_lds_8252_max_group_size_96:
-; GFX6: ; Occupancy: 2{{$}}
+; GFX6: ; Occupancy: 4{{$}}
; GFX7: ; Occupancy: 4{{$}}
; GFX8: ; Occupancy: 4{{$}}
; GFX9: ; Occupancy: 4{{$}}
@@ -704,7 +704,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_96() #4 {
}
; GCN-LABEL: {{^}}used_lds_8252_max_group_size_128:
-; GFX6: ; Occupancy: 2{{$}}
+; GFX6: ; Occupancy: 4{{$}}
; GFX7: ; Occupancy: 4{{$}}
; GFX8: ; Occupancy: 4{{$}}
; GFX9: ; Occupancy: 4{{$}}
@@ -727,7 +727,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_128() #5 {
}
; GCN-LABEL: {{^}}used_lds_8252_max_group_size_192:
-; GFX6: ; Occupancy: 3{{$}}
+; GFX6: ; Occupancy: 6{{$}}
; GFX7: ; Occupancy: 6{{$}}
; GFX8: ; Occupancy: 6{{$}}
; GFX9: ; Occupancy: 6{{$}}
@@ -750,7 +750,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_192() #6 {
}
; GCN-LABEL: {{^}}used_lds_8252_max_group_size_256:
-; GFX6: ; Occupancy: 3{{$}}
+; GFX6: ; Occupancy: 7{{$}}
; GFX7: ; Occupancy: 7{{$}}
; GFX8: ; Occupancy: 7{{$}}
; GFX9: ; Occupancy: 7{{$}}
@@ -771,7 +771,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_256() #7 {
}
; GCN-LABEL: {{^}}used_lds_8252_max_group_size_512:
-; GFX6: ; Occupancy: 6{{$}}
+; GFX6: ; Occupancy: 10{{$}}
; GFX7: ; Occupancy: 10{{$}}
; GFX8: ; Occupancy: 10{{$}}
; GFX9: ; Occupancy: 10{{$}}
@@ -806,7 +806,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_1024() #9 {
}
; GCN-LABEL: {{^}}used_lds_8252_max_group_size_32:
-; GFX6: ; Occupancy: 1{{$}}
+; GFX6: ; Occupancy: 2{{$}}
; GFX7: ; Occupancy: 2{{$}}
; GFX8: ; Occupancy: 2{{$}}
; GFX9: ; Occupancy: 2{{$}}
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index 51fda88e66eca..33b4eca0a1dd3 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -276,6 +276,23 @@ TEST_F(AMDGPUTestBase, TestOccupancyAbsoluteLimits) {
256);
}
+TEST_F(AMDGPUTestBase, TestGFX6LocalMemorySize) {
+ for (StringRef CPU : {"gfx600", "gfx601", "gfx602"}) {
+ SCOPED_TRACE(CPU.str());
+ auto TM = createAMDGPUTargetMachine(Triple("amdgcn-amd-amdhsa"), CPU, "");
+ ASSERT_NE(TM, nullptr);
+ GCNSubtarget ST(TM->getTargetTriple(), CPU.str(), "", *TM);
+
+ EXPECT_EQ(ST.getLocalMemorySize(), 65536u);
+ EXPECT_EQ(ST.getAddressableLocalMemorySize(), 32768u);
+
+ // Two workgroups using 32 KiB each fit in a CU. With 256 threads per
+ // workgroup, each SIMD can therefore hold two waves, limited only by LDS.
+ EXPECT_EQ(ST.getOccupancyWithWorkGroupSizes(32768, {256, 256}),
+ std::make_pair(2u, 2u));
+ }
+}
+
static const char *printSubReg(const TargetRegisterInfo &TRI, unsigned SubReg) {
return SubReg ? TRI.getSubRegIndexName(SubReg) : "<none>";
}
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 0037bc63e7b0e..550185ebe820d 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2867,7 +2867,11 @@ TEST(TargetParserTest, testAMDGPUHalfAddressableLDSFeature) {
AMDGPU::FEAT_HALF_ADDRESSABLE_PHYSICAL_LOCAL_MEMORY);
};
- // Only gfx10/11/12 address half of the physical LDS block.
+ // Gfx6 and gfx10/11/12 address half of the physical LDS block.
+ EXPECT_TRUE(Has(AMDGPU::GK_GFX600));
+ EXPECT_TRUE(Has(AMDGPU::GK_GFX601));
+ EXPECT_TRUE(Has(AMDGPU::GK_GFX602));
+ EXPECT_FALSE(Has(AMDGPU::GK_GFX700));
EXPECT_FALSE(Has(AMDGPU::GK_GFX900));
EXPECT_TRUE(Has(AMDGPU::GK_GFX1030));
EXPECT_TRUE(Has(AMDGPU::GK_GFX1100));
>From dafb5193120f992186f630d3f18eb5d6fad354d4 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Mon, 14 Sep 2026 08:35:51 -0700
Subject: [PATCH 2/5] Update llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
---
llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index 33b4eca0a1dd3..beb967b779ae9 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -277,9 +277,9 @@ TEST_F(AMDGPUTestBase, TestOccupancyAbsoluteLimits) {
}
TEST_F(AMDGPUTestBase, TestGFX6LocalMemorySize) {
- for (StringRef CPU : {"gfx600", "gfx601", "gfx602"}) {
+ for (Triple::SubArchType SubArch : {Triple::AMDGPUSubArch_600, Triple::AMDGPUSubArch_601, Triple::AMDGPUSubArch_602}) {
SCOPED_TRACE(CPU.str());
- auto TM = createAMDGPUTargetMachine(Triple("amdgcn-amd-amdhsa"), CPU, "");
+ auto TM = createAMDGPUTargetMachine(Triple(Triple::amdgpu, SubArch), "", "");
ASSERT_NE(TM, nullptr);
GCNSubtarget ST(TM->getTargetTriple(), CPU.str(), "", *TM);
>From 4d3ba9d2549506999f54a6f388fefee712ac99d7 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Mon, 14 Sep 2026 11:55:02 -0400
Subject: [PATCH 3/5] Fix formatting
Change-Id: Ib227509423da1087aaf7457bf6f94c8423009d8a
---
llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index beb967b779ae9..20cd3a7b865cc 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -277,9 +277,12 @@ TEST_F(AMDGPUTestBase, TestOccupancyAbsoluteLimits) {
}
TEST_F(AMDGPUTestBase, TestGFX6LocalMemorySize) {
- for (Triple::SubArchType SubArch : {Triple::AMDGPUSubArch_600, Triple::AMDGPUSubArch_601, Triple::AMDGPUSubArch_602}) {
+ for (Triple::SubArchType SubArch :
+ {Triple::AMDGPUSubArch_600, Triple::AMDGPUSubArch_601,
+ Triple::AMDGPUSubArch_602}) {
SCOPED_TRACE(CPU.str());
- auto TM = createAMDGPUTargetMachine(Triple(Triple::amdgpu, SubArch), "", "");
+ auto TM =
+ createAMDGPUTargetMachine(Triple(Triple::amdgpu, SubArch), "", "");
ASSERT_NE(TM, nullptr);
GCNSubtarget ST(TM->getTargetTriple(), CPU.str(), "", *TM);
>From 6ae66f06a0b8e298e4d062835383ee2b1e73d715 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Mon, 14 Sep 2026 13:06:13 -0400
Subject: [PATCH 4/5] Fix tests
Change-Id: Iaff68defd33bae339592b4da78314718c7893285
---
llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index 20cd3a7b865cc..7ed1ef3d3aaf2 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -278,13 +278,13 @@ TEST_F(AMDGPUTestBase, TestOccupancyAbsoluteLimits) {
TEST_F(AMDGPUTestBase, TestGFX6LocalMemorySize) {
for (Triple::SubArchType SubArch :
- {Triple::AMDGPUSubArch_600, Triple::AMDGPUSubArch_601,
- Triple::AMDGPUSubArch_602}) {
- SCOPED_TRACE(CPU.str());
- auto TM =
- createAMDGPUTargetMachine(Triple(Triple::amdgpu, SubArch), "", "");
+ {Triple::AMDGPUSubArch600, Triple::AMDGPUSubArch601,
+ Triple::AMDGPUSubArch602}) {
+ SCOPED_TRACE(AMDGPU::getArchNameFromSubArch(SubArch));
+ Triple TT(Triple::amdgpu, SubArch);
+ auto TM = createAMDGPUTargetMachine(TT, /*CPU=*/"", /*FS=*/"");
ASSERT_NE(TM, nullptr);
- GCNSubtarget ST(TM->getTargetTriple(), CPU.str(), "", *TM);
+ GCNSubtarget ST(TT, TM->getTargetCPU(), /*FS=*/"", *TM);
EXPECT_EQ(ST.getLocalMemorySize(), 65536u);
EXPECT_EQ(ST.getAddressableLocalMemorySize(), 32768u);
>From e245f1698198a6ab8b2eb3054a9565b73d882519 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Mon, 14 Sep 2026 11:52:16 -0700
Subject: [PATCH 5/5] Incorporate comments, update docs based on merged PR
---
.../llvm/TargetParser/AMDGPUTargetParser.h | 5 ++--
llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 2 +-
.../Target/AMDGPU/AMDGPUUnitTests.cpp | 20 -------------
.../TargetParser/TargetParserTest.cpp | 29 +++++++++++++++----
4 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
index 3c2037c90be51..4b0fa417c6b10 100644
--- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
@@ -209,12 +209,13 @@ LLVM_ABI unsigned getAddressableNumVGPRs(Triple::SubArchType SubArch,
/// min(getMaxHWAddressableLocalMemorySize(), getLocalMemorySize())
///
/// The physical LDS block belongs to a WGP on gfx10/11/12 and to a CU
-/// otherwise. On gfx10/11/12, the block is twice the address limit, so a
-/// work-group cannot address the entire block in full-SIMD mode.
+/// otherwise. On gfx6 and gfx10/11/12, the block is twice the address limit, so
+/// a work-group cannot address the entire block in full-SIMD mode.
///
/// The mode columns below show local/addressable LDS, in KiB:
///
/// GPU address limit full-SIMD half-SIMD
+/// gfx600 32 64/32 n/a (always full-SIMD)
/// gfx900 64 64/64 n/a (always full-SIMD)
/// gfx1030 64 128/64 64/64
/// gfx1250 320 320/320 n/a (always full-SIMD)
diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
index c4f0d8deba089..fc027c48ca354 100644
--- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
@@ -479,7 +479,7 @@ AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::SubArchType SubArch) {
}
unsigned AMDGPU::getLocalMemorySize(GPUKind AK, bool FullSIMDMode) {
- // gfx10/11/12 address half of the physical block, e.g. 64 KiB of 128 KiB.
+ // gfx6 and gfx10/11/12 address half of the physical block.
unsigned Size = getMaxHWAddressableLocalMemorySize(AK);
if (getFeatureBitset(AK).test(FEAT_HALF_ADDRESSABLE_PHYSICAL_LOCAL_MEMORY))
Size *= 2;
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index 7ed1ef3d3aaf2..51fda88e66eca 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -276,26 +276,6 @@ TEST_F(AMDGPUTestBase, TestOccupancyAbsoluteLimits) {
256);
}
-TEST_F(AMDGPUTestBase, TestGFX6LocalMemorySize) {
- for (Triple::SubArchType SubArch :
- {Triple::AMDGPUSubArch600, Triple::AMDGPUSubArch601,
- Triple::AMDGPUSubArch602}) {
- SCOPED_TRACE(AMDGPU::getArchNameFromSubArch(SubArch));
- Triple TT(Triple::amdgpu, SubArch);
- auto TM = createAMDGPUTargetMachine(TT, /*CPU=*/"", /*FS=*/"");
- ASSERT_NE(TM, nullptr);
- GCNSubtarget ST(TT, TM->getTargetCPU(), /*FS=*/"", *TM);
-
- EXPECT_EQ(ST.getLocalMemorySize(), 65536u);
- EXPECT_EQ(ST.getAddressableLocalMemorySize(), 32768u);
-
- // Two workgroups using 32 KiB each fit in a CU. With 256 threads per
- // workgroup, each SIMD can therefore hold two waves, limited only by LDS.
- EXPECT_EQ(ST.getOccupancyWithWorkGroupSizes(32768, {256, 256}),
- std::make_pair(2u, 2u));
- }
-}
-
static const char *printSubReg(const TargetRegisterInfo &TRI, unsigned SubReg) {
return SubReg ? TRI.getSubRegIndexName(SubReg) : "<none>";
}
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 43925ae257b16..3cf07ca5b0202 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -3263,10 +3263,19 @@ TEST(TargetParserTest, testAMDGPUgetBufferResourceNumRecordsWidth) {
}
TEST(TargetParserTest, testAMDGPUgetLocalMemorySize) {
+ // gfx6 addresses 32 KiB of a 64 KiB block.
+ for (Triple::SubArchType SubArch :
+ {Triple::AMDGPUSubArch600, Triple::AMDGPUSubArch601,
+ Triple::AMDGPUSubArch602}) {
+ SCOPED_TRACE(AMDGPU::getArchNameFromSubArch(SubArch));
+ EXPECT_EQ(AMDGPU::getLocalMemorySize(SubArch, true), 65536u);
+ EXPECT_EQ(AMDGPU::getLocalMemorySize(SubArch, false), 32768u);
+ }
+
// Without a half-addressable physical block the total matches the
// addressable cap, and running on two SIMDs halves it.
- EXPECT_EQ(AMDGPU::getLocalMemorySize(AMDGPU::GK_GFX600, true), 32768u);
- EXPECT_EQ(AMDGPU::getLocalMemorySize(AMDGPU::GK_GFX600, false), 16384u);
+ EXPECT_EQ(AMDGPU::getLocalMemorySize(AMDGPU::GK_GFX700, true), 65536u);
+ EXPECT_EQ(AMDGPU::getLocalMemorySize(AMDGPU::GK_GFX700, false), 32768u);
EXPECT_EQ(AMDGPU::getLocalMemorySize(AMDGPU::GK_GFX900, true), 65536u);
EXPECT_EQ(AMDGPU::getLocalMemorySize(AMDGPU::GK_GFX950, true), 163840u);
@@ -3290,7 +3299,15 @@ TEST(TargetParserTest, testAMDGPUgetLocalMemorySize) {
TEST(TargetParserTest, testAMDGPUgetAddressableLocalMemorySize) {
// A work-group never allocates past the hardware cap, so the doubled
- // gfx10/11/12 block is capped back to the addressable size.
+ // gfx6 and gfx10/11/12 blocks are capped back to the addressable size.
+ for (Triple::SubArchType SubArch :
+ {Triple::AMDGPUSubArch600, Triple::AMDGPUSubArch601,
+ Triple::AMDGPUSubArch602}) {
+ SCOPED_TRACE(AMDGPU::getArchNameFromSubArch(SubArch));
+ EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(SubArch, true), 32768u);
+ EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(SubArch, false), 32768u);
+ }
+
EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX1030, true),
65536u);
EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX1030, false),
@@ -3299,10 +3316,10 @@ TEST(TargetParserTest, testAMDGPUgetAddressableLocalMemorySize) {
65536u);
// Without a doubled block the cap is only reached in full-SIMD mode.
- EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX600, true),
+ EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX700, true),
+ 65536u);
+ EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX700, false),
32768u);
- EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX600, false),
- 16384u);
EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX950, true),
163840u);
EXPECT_EQ(AMDGPU::getAddressableLocalMemorySize(AMDGPU::GK_GFX1250, true),
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