[llvm] [WIP][DAG] visitFREEZE - always allow freezing multiple operands (PR #152107)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 10:04:24 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/152107
>From 4cdb362ad72e8e6c4cb1c74b407edec06ef7f25b Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Tue, 5 Aug 2025 10:31:10 +0100
Subject: [PATCH] [WIP][DAG] visitFREEZE - always allow freezing multiple
operands
Remove the limited freeze multiple operand handling, always freeze all operands and rely on later visitFREEZE calls to merge frozen/unfrozen versions of each node to prevent infinite loops.
This also removes the special handling of frozen SRA/SRL nodes as most of the regressions are related
Fixes #149798
Fixes #150204
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 30 +-
llvm/test/CodeGen/AArch64/div-i256.ll | 64 +-
llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll | 32 +-
llvm/test/CodeGen/AArch64/neon-dotreduce.ll | 868 +-
.../test/CodeGen/AMDGPU/carryout-selection.ll | 51 +-
.../AMDGPU/divergence-driven-trunc-to-i1.ll | 9 +-
.../AMDGPU/float-to-arbitrary-fp-e5m3fnu.ll | 33 +-
.../float-to-arbitrary-fp-fp8-f16-hw.ll | 897 +-
.../AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll | 20 +-
.../AMDGPU/float-to-arbitrary-fp-fp8-hw.ll | 2077 +--
.../AMDGPU/float-to-arbitrary-fp-widen.ll | 3642 ++--
.../CodeGen/AMDGPU/float-to-arbitrary-fp.ll | 286 +-
llvm/test/CodeGen/AMDGPU/sad.ll | 19 +-
llvm/test/CodeGen/AMDGPU/srem64.ll | 14 +-
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 12 +-
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 12 +-
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 12 +-
.../test/CodeGen/AMDGPU/vector-reduce-umin.ll | 12 +-
.../CodeGen/NVPTX/float-to-arbitrary-fp.ll | 294 +-
llvm/test/CodeGen/NVPTX/i1-select.ll | 66 +-
llvm/test/CodeGen/NVPTX/i128.ll | 180 +-
llvm/test/CodeGen/RISCV/abds-neg.ll | 88 +-
llvm/test/CodeGen/RISCV/abds.ll | 24 +-
llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll | 76 +-
llvm/test/CodeGen/RISCV/clmul.ll | 14103 ++++++++--------
llvm/test/CodeGen/RISCV/clmulh.ll | 4469 ++---
llvm/test/CodeGen/RISCV/clmulr.ll | 4757 +++---
llvm/test/CodeGen/RISCV/idiv_large.ll | 464 +-
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 15 +-
llvm/test/CodeGen/RISCV/rv64zbb.ll | 15 +-
.../RISCV/wide-scalar-shift-legalization.ll | 1885 +--
llvm/test/CodeGen/SystemZ/pr60413.ll | 36 +-
llvm/test/CodeGen/Thumb2/mve-clmul.ll | 348 +-
llvm/test/CodeGen/X86/abds-neg.ll | 92 +-
llvm/test/CodeGen/X86/avg-mask.ll | 29 +-
llvm/test/CodeGen/X86/avg.ll | 156 +-
llvm/test/CodeGen/X86/bit-manip-i256.ll | 563 +-
llvm/test/CodeGen/X86/bit-manip-i512.ll | 867 +-
llvm/test/CodeGen/X86/bmi.ll | 48 +-
llvm/test/CodeGen/X86/clmul-vector.ll | 148 +-
llvm/test/CodeGen/X86/div_i129_v_pow2k.ll | 16 +-
.../test/CodeGen/X86/float-to-arbitrary-fp.ll | 43 +-
llvm/test/CodeGen/X86/freeze-binary.ll | 21 +-
llvm/test/CodeGen/X86/freeze-vector.ll | 91 +-
llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 126 +-
llvm/test/CodeGen/X86/pdep-vector-128.ll | 94 +-
llvm/test/CodeGen/X86/pdep-vector-256.ll | 10 +-
.../test/CodeGen/X86/setcc-non-simple-type.ll | 4 +-
llvm/test/CodeGen/X86/shift-i128.ll | 10 +-
llvm/test/CodeGen/X86/vector-fshr-128.ll | 196 +-
llvm/test/CodeGen/X86/vector-fshr-256.ll | 60 +-
llvm/test/CodeGen/X86/vector-fshr-512.ll | 52 +-
.../CodeGen/X86/vector-shuffle-combining.ll | 18 +-
llvm/test/CodeGen/X86/vector-trunc-packus.ll | 262 +-
llvm/test/CodeGen/X86/vshift-6.ll | 3 +-
.../zero_extend_vector_inreg_of_broadcast.ll | 10 +-
56 files changed, 18940 insertions(+), 18889 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a829d7a34d5a6..f727cb193161a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18535,12 +18535,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
return FrozenN0;
}
- // We currently avoid folding freeze over SRL, due to the problems seen
- // with (freeze (assert ext)) blocking simplifications of SRL. See for
- // example https://reviews.llvm.org/D136529#4120959.
- if (N0.getOpcode() == ISD::SRL)
- return SDValue();
-
// Fold freeze(op(x, ...)) -> op(freeze(x), ...).
// Try to push freeze through instructions that propagate but don't produce
// poison as far as possible. If an operand of freeze follows three
@@ -18553,19 +18547,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
N0->getNumValues() != 1 || !N0->hasOneUse())
return SDValue();
- // TOOD: we should always allow multiple operands, however this increases the
- // likelihood of infinite loops due to the ReplaceAllUsesOfValueWith call
- // below causing later nodes that share frozen operands to fold again and no
- // longer being able to confirm other operands are not poison due to recursion
- // depth limits on isGuaranteedNotToBeUndefOrPoison.
- bool AllowMultipleMaybePoisonOperands =
- N0.getOpcode() == ISD::SELECT_CC || N0.getOpcode() == ISD::SETCC ||
- N0.getOpcode() == ISD::BUILD_VECTOR ||
- N0.getOpcode() == ISD::INSERT_SUBVECTOR ||
- N0.getOpcode() == ISD::BUILD_PAIR ||
- N0.getOpcode() == ISD::VECTOR_SHUFFLE ||
- N0.getOpcode() == ISD::CONCAT_VECTORS || N0.getOpcode() == ISD::FMUL;
-
// Avoid turning a BUILD_VECTOR that can be recognized as "all zeros", "all
// ones" or "constant" into something that depends on FrozenUndef. We can
// instead pick undef values to keep those properties, while at the same time
@@ -18592,16 +18573,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
if (DAG.isGuaranteedNotToBeUndefOrPoison(Op,
UndefPoisonKind::UndefOrPoison))
continue;
- bool HadMaybePoisonOperands = !MaybePoisonOperands.empty();
- bool IsNewMaybePoisonOperand = MaybePoisonOperands.insert(Op).second;
- if (IsNewMaybePoisonOperand)
+ if (MaybePoisonOperands.insert(Op).second)
MaybePoisonOperandNumbers.push_back(OpNo);
- if (!HadMaybePoisonOperands)
- continue;
- if (IsNewMaybePoisonOperand && !AllowMultipleMaybePoisonOperands) {
- // Multiple maybe-poison ops when not allowed - bail out.
- return SDValue();
- }
}
// NOTE: the whole op may be not guaranteed to not be undef or poison because
// it could create undef or poison due to it's poison-generating flags.
@@ -18638,7 +18611,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
if (N->getOpcode() == ISD::DELETED_NODE)
return SDValue(N, 0);
}
-
assert(N->getOpcode() != ISD::DELETED_NODE && "Node was deleted!");
// The whole node may have been updated, so the value we were holding
diff --git a/llvm/test/CodeGen/AArch64/div-i256.ll b/llvm/test/CodeGen/AArch64/div-i256.ll
index 5f8d362c85bb2..81558dc35cf8e 100644
--- a/llvm/test/CodeGen/AArch64/div-i256.ll
+++ b/llvm/test/CodeGen/AArch64/div-i256.ll
@@ -213,17 +213,17 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: sbcs x15, x9, x12
; CHECK-NEXT: eor x9, x3, x12
; CHECK-NEXT: clz x16, x14
-; CHECK-NEXT: sbcs x18, x8, x12
-; CHECK-NEXT: clz x17, x15
+; CHECK-NEXT: sbcs x17, x8, x12
+; CHECK-NEXT: clz x0, x15
; CHECK-NEXT: add x16, x16, #64
-; CHECK-NEXT: sbc x0, x9, x12
+; CHECK-NEXT: sbc x18, x9, x12
; CHECK-NEXT: subs x8, x10, x13
; CHECK-NEXT: eor x10, x6, x13
; CHECK-NEXT: sbcs x9, x11, x13
; CHECK-NEXT: eor x11, x7, x13
-; CHECK-NEXT: orr x1, x14, x18
+; CHECK-NEXT: orr x1, x14, x17
; CHECK-NEXT: sbcs x10, x10, x13
-; CHECK-NEXT: orr x4, x15, x0
+; CHECK-NEXT: orr x4, x15, x18
; CHECK-NEXT: clz x5, x8
; CHECK-NEXT: sbc x11, x11, x13
; CHECK-NEXT: orr x2, x8, x10
@@ -243,41 +243,41 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: cmp x11, #0
; CHECK-NEXT: csel x1, x1, x3, ne
; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: clz x3, x18
+; CHECK-NEXT: clz x3, x17
; CHECK-NEXT: csel x2, x2, x5, ne
; CHECK-NEXT: cmp x6, #0
; CHECK-NEXT: add x3, x3, #64
; CHECK-NEXT: add x2, x2, #128
-; CHECK-NEXT: clz x5, x0
+; CHECK-NEXT: clz x5, x18
; CHECK-NEXT: csel x1, x1, x2, ne
-; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: cmp x18, #0
; CHECK-NEXT: csel x2, x5, x3, ne
; CHECK-NEXT: cmp x15, #0
-; CHECK-NEXT: orr x3, x18, x0
-; CHECK-NEXT: csel x16, x17, x16, ne
+; CHECK-NEXT: orr x3, x17, x18
+; CHECK-NEXT: csel x16, x0, x16, ne
; CHECK-NEXT: cmp x3, #0
; CHECK-NEXT: mov w3, #255 // =0xff
; CHECK-NEXT: add x16, x16, #128
; CHECK-NEXT: csel x16, x2, x16, ne
; CHECK-NEXT: subs x2, x1, x16
; CHECK-NEXT: ngcs x16, xzr
-; CHECK-NEXT: ngcs x17, xzr
+; CHECK-NEXT: ngcs x0, xzr
; CHECK-NEXT: ngc x1, xzr
; CHECK-NEXT: cmp x3, x2
; CHECK-NEXT: ngcs xzr, x16
-; CHECK-NEXT: ngcs xzr, x17
+; CHECK-NEXT: ngcs xzr, x0
; CHECK-NEXT: ngcs xzr, x1
; CHECK-NEXT: csinc w5, w4, wzr, hs
; CHECK-NEXT: cmp w5, #0
-; CHECK-NEXT: csel x13, xzr, x0, ne
-; CHECK-NEXT: csel x4, xzr, x18, ne
+; CHECK-NEXT: csel x13, xzr, x18, ne
+; CHECK-NEXT: csel x4, xzr, x17, ne
; CHECK-NEXT: csel x7, xzr, x15, ne
; CHECK-NEXT: csel x3, xzr, x14, ne
; CHECK-NEXT: tbnz w5, #0, .LBB1_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
; CHECK-NEXT: eor x5, x2, #0xff
; CHECK-NEXT: orr x6, x16, x1
-; CHECK-NEXT: orr x5, x5, x17
+; CHECK-NEXT: orr x5, x5, x0
; CHECK-NEXT: orr x5, x5, x6
; CHECK-NEXT: cbz x5, .LBB1_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
@@ -299,11 +299,11 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: stp x14, x15, [sp, #96]
; CHECK-NEXT: and x19, x3, #0x3f
; CHECK-NEXT: adcs x16, x16, xzr
-; CHECK-NEXT: stp x18, x0, [sp, #112]
+; CHECK-NEXT: stp x17, x18, [sp, #112]
; CHECK-NEXT: mvn w20, w3
; CHECK-NEXT: eor x19, x19, #0x3f
; CHECK-NEXT: stp q0, q0, [sp, #64]
-; CHECK-NEXT: adcs x17, x17, xzr
+; CHECK-NEXT: adcs x0, x0, xzr
; CHECK-NEXT: ldp x2, x6, [x4, #8]
; CHECK-NEXT: ldr x7, [x4]
; CHECK-NEXT: ldr x5, [x4, #24]
@@ -332,31 +332,31 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: mov x20, xzr
; CHECK-NEXT: and x14, x21, #0x18
-; CHECK-NEXT: stp x18, x0, [sp, #16]
-; CHECK-NEXT: and x0, x13, #0x3f
+; CHECK-NEXT: stp x17, x18, [sp, #16]
+; CHECK-NEXT: and x18, x13, #0x3f
; CHECK-NEXT: add x14, x15, x14
; CHECK-NEXT: mvn w21, w13
-; CHECK-NEXT: eor x0, x0, #0x3f
-; CHECK-NEXT: ldp x15, x18, [x14, #16]
+; CHECK-NEXT: eor x18, x18, #0x3f
+; CHECK-NEXT: ldp x15, x17, [x14, #16]
; CHECK-NEXT: mov x7, xzr
; CHECK-NEXT: ldp x24, x22, [x14]
; CHECK-NEXT: lsl x14, x15, #1
-; CHECK-NEXT: lsl x23, x18, #1
+; CHECK-NEXT: lsl x23, x17, #1
; CHECK-NEXT: lsr x25, x15, x13
; CHECK-NEXT: lsl x15, x22, #1
; CHECK-NEXT: lsr x27, x22, x13
; CHECK-NEXT: lsr x28, x24, x13
; CHECK-NEXT: lsl x26, x14, x21
; CHECK-NEXT: subs x14, x8, #1
-; CHECK-NEXT: lsl x23, x23, x0
-; CHECK-NEXT: lsl x0, x15, x0
+; CHECK-NEXT: lsl x23, x23, x18
+; CHECK-NEXT: lsl x18, x15, x18
; CHECK-NEXT: sbcs x15, x9, xzr
-; CHECK-NEXT: lsr x22, x18, x13
-; CHECK-NEXT: sbcs x18, x10, xzr
+; CHECK-NEXT: lsr x22, x17, x13
+; CHECK-NEXT: sbcs x17, x10, xzr
; CHECK-NEXT: orr x21, x23, x25
; CHECK-NEXT: orr x24, x27, x26
-; CHECK-NEXT: orr x23, x0, x28
-; CHECK-NEXT: sbc x0, x11, xzr
+; CHECK-NEXT: orr x23, x18, x28
+; CHECK-NEXT: sbc x18, x11, xzr
; CHECK-NEXT: .LBB1_4: // %udiv-do-while
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: extr x25, x23, x5, #63
@@ -369,9 +369,9 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: sbcs xzr, x15, x26
; CHECK-NEXT: orr x3, x20, x3
; CHECK-NEXT: orr x5, x7, x5
-; CHECK-NEXT: sbcs xzr, x18, x27
+; CHECK-NEXT: sbcs xzr, x17, x27
; CHECK-NEXT: mov x7, xzr
-; CHECK-NEXT: sbc x21, x0, x22
+; CHECK-NEXT: sbc x21, x18, x22
; CHECK-NEXT: asr x28, x21, #63
; CHECK-NEXT: and x21, x28, x8
; CHECK-NEXT: subs x23, x25, x21
@@ -386,10 +386,10 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: sbcs x16, x16, xzr
; CHECK-NEXT: orr x1, x6, x1, lsl #1
; CHECK-NEXT: and x6, x28, #0x1
-; CHECK-NEXT: sbcs x17, x17, xzr
+; CHECK-NEXT: sbcs x0, x0, xzr
; CHECK-NEXT: orr x2, x19, x25
; CHECK-NEXT: sbc x4, x4, xzr
-; CHECK-NEXT: orr x20, x13, x17
+; CHECK-NEXT: orr x20, x13, x0
; CHECK-NEXT: orr x19, x16, x4
; CHECK-NEXT: orr x25, x20, x19
; CHECK-NEXT: mov x19, xzr
diff --git a/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll b/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll
index 8297fa2d4e3f9..78d23b4aed25f 100644
--- a/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll
+++ b/llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll
@@ -205,9 +205,8 @@ define i1 @test_disjoint3(i1 %0, i32 %1, i32 %2) {
; CHECK-LABEL: test_disjoint3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: tst w9, w8
+; CHECK-NEXT: tst w2, w8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
@@ -227,9 +226,8 @@ define i1 @test_disjoint4(i1 %0, i32 %1, i32 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: and w8, w9, w8
-; CHECK-NEXT: cmp w8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: tst w9, w8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -248,9 +246,8 @@ define i1 @test_disjoint_inverse_4(i1 %0, i32 %1, i32 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: bic w8, w9, w8
-; CHECK-NEXT: cmp w8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: bics wzr, w9, w8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -310,9 +307,8 @@ define i1 @test_disjoint3_inverse(i1 %0, i32 %1, i32 %2) {
; CHECK-LABEL: test_disjoint3_inverse:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr w9, w2, #0x800000
; CHECK-NEXT: lsl w8, w8, w1
-; CHECK-NEXT: bics wzr, w9, w8
+; CHECK-NEXT: bics wzr, w2, w8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
@@ -371,9 +367,8 @@ define i1 @test_disjoint3_64(i1 %0, i64 %1, i64 %2) {
; CHECK-LABEL: test_disjoint3_64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: tst x9, x8
+; CHECK-NEXT: tst x2, x8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
@@ -393,9 +388,8 @@ define i1 @test_disjoint4_64(i1 %0, i64 %1, i64 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: and x8, x9, x8
-; CHECK-NEXT: cmp x8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: tst x9, x8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -414,9 +408,8 @@ define i1 @test_disjoint_inverse_4_64(i1 %0, i64 %1, i64 %2) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: bic x8, x9, x8
-; CHECK-NEXT: cmp x8, #1
-; CHECK-NEXT: cset w8, lt
+; CHECK-NEXT: bics xzr, x9, x8
+; CHECK-NEXT: cset w8, le
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
@@ -476,9 +469,8 @@ define i1 @test_disjoint3_inverse_64(i1 %0, i64 %1, i64 %2) {
; CHECK-LABEL: test_disjoint3_inverse_64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: orr x9, x2, #0x80000000000000
; CHECK-NEXT: lsl x8, x8, x1
-; CHECK-NEXT: bics xzr, x9, x8
+; CHECK-NEXT: bics xzr, x2, x8
; CHECK-NEXT: cset w8, mi
; CHECK-NEXT: orr w8, w0, w8
; CHECK-NEXT: and w0, w8, #0x1
diff --git a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
index f5312828cfd78..844c1c85f2d82 100644
--- a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -2310,20 +2310,20 @@ define i32 @test_udot_v25i8(ptr nocapture readonly %a, ptr nocapture readonly %b
; CHECK-SD-LABEL: test_udot_v25i8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldp q3, q0, [x1]
-; CHECK-SD-NEXT: movi v5.2d, #0000000000000000
; CHECK-SD-NEXT: ldp q2, q1, [x0]
; CHECK-SD-NEXT: umull2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: umull v5.8h, v3.8b, v2.8b
; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b
-; CHECK-SD-NEXT: umull v1.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-SD-NEXT: umull2 v2.8h, v3.16b, v2.16b
; CHECK-SD-NEXT: ushll v3.4s, v4.4h, #0
-; CHECK-SD-NEXT: uaddl2 v4.4s, v1.8h, v0.8h
-; CHECK-SD-NEXT: uaddl v0.4s, v1.4h, v0.4h
-; CHECK-SD-NEXT: mov v5.s[0], v3.s[0]
-; CHECK-SD-NEXT: uaddw2 v1.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: uaddl2 v4.4s, v5.8h, v0.8h
+; CHECK-SD-NEXT: uaddl v0.4s, v5.4h, v0.4h
+; CHECK-SD-NEXT: mov v1.s[0], v3.s[0]
+; CHECK-SD-NEXT: uaddw2 v3.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: uaddw v1.4s, v1.4s, v2.4h
; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: uaddw v2.4s, v5.4s, v2.4h
-; CHECK-SD-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-SD-NEXT: addv s0, v0.4s
; CHECK-SD-NEXT: fmov w8, s0
; CHECK-SD-NEXT: add w0, w8, w2
@@ -2739,20 +2739,20 @@ define i32 @test_sdot_v25i8(ptr nocapture readonly %a, ptr nocapture readonly %b
; CHECK-SD-LABEL: test_sdot_v25i8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldp q3, q0, [x1]
-; CHECK-SD-NEXT: movi v5.2d, #0000000000000000
; CHECK-SD-NEXT: ldp q2, q1, [x0]
; CHECK-SD-NEXT: smull2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: smull v5.8h, v3.8b, v2.8b
; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
-; CHECK-SD-NEXT: smull v1.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-SD-NEXT: smull2 v2.8h, v3.16b, v2.16b
; CHECK-SD-NEXT: sshll v3.4s, v4.4h, #0
-; CHECK-SD-NEXT: saddl2 v4.4s, v1.8h, v0.8h
-; CHECK-SD-NEXT: saddl v0.4s, v1.4h, v0.4h
-; CHECK-SD-NEXT: mov v5.s[0], v3.s[0]
-; CHECK-SD-NEXT: saddw2 v1.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: saddl2 v4.4s, v5.8h, v0.8h
+; CHECK-SD-NEXT: saddl v0.4s, v5.4h, v0.4h
+; CHECK-SD-NEXT: mov v1.s[0], v3.s[0]
+; CHECK-SD-NEXT: saddw2 v3.4s, v4.4s, v2.8h
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v3.4s
+; CHECK-SD-NEXT: saddw v1.4s, v1.4s, v2.4h
; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: saddw v2.4s, v5.4s, v2.4h
-; CHECK-SD-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-SD-NEXT: addv s0, v0.4s
; CHECK-SD-NEXT: fmov w8, s0
; CHECK-SD-NEXT: add w0, w8, w2
@@ -3070,209 +3070,221 @@ define i32 @test_sdot_v25i8_double(<25 x i8> %a, <25 x i8> %b, <25 x i8> %c, <25
; CHECK-SD-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: .cfi_offset w29, -16
-; CHECK-SD-NEXT: ldr b0, [sp, #216]
-; CHECK-SD-NEXT: add x8, sp, #224
-; CHECK-SD-NEXT: ldr b1, [sp, #16]
-; CHECK-SD-NEXT: ldr b2, [sp, #280]
-; CHECK-SD-NEXT: add x9, sp, #240
-; CHECK-SD-NEXT: ldr b4, [sp, #80]
-; CHECK-SD-NEXT: ld1 { v0.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #24
-; CHECK-SD-NEXT: add x10, sp, #48
-; CHECK-SD-NEXT: ld1 { v1.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #232
-; CHECK-SD-NEXT: add x11, sp, #96
-; CHECK-SD-NEXT: ldr b5, [sp, #152]
-; CHECK-SD-NEXT: add x12, sp, #168
-; CHECK-SD-NEXT: ldr b6, [sp, #616]
+; CHECK-SD-NEXT: ldrb w9, [sp, #280]
+; CHECK-SD-NEXT: ldrb w8, [sp, #80]
+; CHECK-SD-NEXT: add x11, sp, #160
+; CHECK-SD-NEXT: ldr b0, [sp, #152]
+; CHECK-SD-NEXT: ldrb w10, [sp, #288]
+; CHECK-SD-NEXT: fmov s1, w0
+; CHECK-SD-NEXT: fmov s2, w9
+; CHECK-SD-NEXT: fmov s3, w8
+; CHECK-SD-NEXT: ldrb w9, [sp, #88]
+; CHECK-SD-NEXT: ld1 { v0.b }[1], [x11]
+; CHECK-SD-NEXT: add x8, sp, #168
+; CHECK-SD-NEXT: ldr b4, [sp, #216]
+; CHECK-SD-NEXT: ldr b5, [sp, #16]
+; CHECK-SD-NEXT: ldr b6, [sp, #552]
+; CHECK-SD-NEXT: ldrb w11, [sp, #136]
+; CHECK-SD-NEXT: mov v2.b[1], w10
+; CHECK-SD-NEXT: mov v3.b[1], w9
+; CHECK-SD-NEXT: ldrb w9, [sp, #96]
; CHECK-SD-NEXT: ld1 { v0.b }[2], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #296]
+; CHECK-SD-NEXT: ldrb w10, [sp, #104]
+; CHECK-SD-NEXT: ldr b7, [sp, #352]
+; CHECK-SD-NEXT: mov v1.b[1], w1
+; CHECK-SD-NEXT: ldrb w12, [sp, #496]
+; CHECK-SD-NEXT: ldr b19, [sp, #616]
+; CHECK-SD-NEXT: ldr b22, [sp, #416]
+; CHECK-SD-NEXT: movi v23.2d, #0000000000000000
+; CHECK-SD-NEXT: mov v2.b[2], w8
+; CHECK-SD-NEXT: add x8, sp, #176
+; CHECK-SD-NEXT: mov v3.b[2], w9
+; CHECK-SD-NEXT: ld1 { v0.b }[3], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #304]
+; CHECK-SD-NEXT: add x9, sp, #224
+; CHECK-SD-NEXT: ld1 { v4.b }[1], [x9]
+; CHECK-SD-NEXT: add x9, sp, #184
+; CHECK-SD-NEXT: mov v1.b[2], w2
+; CHECK-SD-NEXT: mov v2.b[3], w8
+; CHECK-SD-NEXT: ld1 { v0.b }[4], [x9]
+; CHECK-SD-NEXT: ldrb w8, [sp, #312]
+; CHECK-SD-NEXT: mov v3.b[3], w10
+; CHECK-SD-NEXT: add x9, sp, #24
+; CHECK-SD-NEXT: add x10, sp, #232
+; CHECK-SD-NEXT: ld1 { v5.b }[1], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #112]
+; CHECK-SD-NEXT: ld1 { v4.b }[2], [x10]
+; CHECK-SD-NEXT: add x10, sp, #192
+; CHECK-SD-NEXT: mov v1.b[3], w3
+; CHECK-SD-NEXT: mov v2.b[4], w8
; CHECK-SD-NEXT: add x8, sp, #32
-; CHECK-SD-NEXT: fmov s3, w0
-; CHECK-SD-NEXT: ld1 { v1.b }[2], [x8]
-; CHECK-SD-NEXT: add x8, sp, #288
-; CHECK-SD-NEXT: ldr b7, [sp, #416]
-; CHECK-SD-NEXT: ld1 { v2.b }[1], [x8]
+; CHECK-SD-NEXT: ld1 { v0.b }[5], [x10]
+; CHECK-SD-NEXT: ld1 { v5.b }[2], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #320]
+; CHECK-SD-NEXT: mov v3.b[4], w9
+; CHECK-SD-NEXT: add x9, sp, #240
+; CHECK-SD-NEXT: ldrb w10, [sp, #120]
+; CHECK-SD-NEXT: ld1 { v4.b }[3], [x9]
+; CHECK-SD-NEXT: add x9, sp, #200
+; CHECK-SD-NEXT: mov v1.b[4], w4
+; CHECK-SD-NEXT: mov v2.b[5], w8
; CHECK-SD-NEXT: add x8, sp, #40
-; CHECK-SD-NEXT: ldr b22, [sp, #744]
-; CHECK-SD-NEXT: ld1 { v0.b }[3], [x9]
+; CHECK-SD-NEXT: ld1 { v0.b }[6], [x9]
+; CHECK-SD-NEXT: ld1 { v5.b }[3], [x8]
; CHECK-SD-NEXT: add x9, sp, #248
-; CHECK-SD-NEXT: mov v3.b[1], w1
-; CHECK-SD-NEXT: ld1 { v1.b }[3], [x8]
-; CHECK-SD-NEXT: add x8, sp, #88
-; CHECK-SD-NEXT: ldr b23, [sp, #544]
-; CHECK-SD-NEXT: ld1 { v4.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #256
-; CHECK-SD-NEXT: ldr b19, [sp, #680]
-; CHECK-SD-NEXT: ld1 { v0.b }[4], [x9]
-; CHECK-SD-NEXT: add x9, sp, #296
-; CHECK-SD-NEXT: ldr b20, [sp, #480]
-; CHECK-SD-NEXT: ld1 { v1.b }[4], [x10]
-; CHECK-SD-NEXT: ld1 { v2.b }[2], [x9]
-; CHECK-SD-NEXT: add x10, sp, #160
-; CHECK-SD-NEXT: ld1 { v4.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #304
-; CHECK-SD-NEXT: ld1 { v5.b }[1], [x10]
-; CHECK-SD-NEXT: ld1 { v0.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #56
-; CHECK-SD-NEXT: add x10, sp, #264
-; CHECK-SD-NEXT: ld1 { v1.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #64
-; CHECK-SD-NEXT: ld1 { v2.b }[3], [x11]
-; CHECK-SD-NEXT: add x9, sp, #272
-; CHECK-SD-NEXT: ld1 { v5.b }[2], [x12]
-; CHECK-SD-NEXT: add x11, sp, #72
-; CHECK-SD-NEXT: ld1 { v0.b }[6], [x10]
-; CHECK-SD-NEXT: add x10, sp, #312
-; CHECK-SD-NEXT: mov v3.b[2], w2
-; CHECK-SD-NEXT: ld1 { v1.b }[6], [x8]
-; CHECK-SD-NEXT: add x8, sp, #104
-; CHECK-SD-NEXT: ld1 { v2.b }[4], [x10]
-; CHECK-SD-NEXT: ld1 { v4.b }[3], [x8]
-; CHECK-SD-NEXT: add x8, sp, #112
-; CHECK-SD-NEXT: add x10, sp, #128
+; CHECK-SD-NEXT: ldrb w8, [sp, #328]
+; CHECK-SD-NEXT: mov v3.b[5], w10
+; CHECK-SD-NEXT: ld1 { v4.b }[4], [x9]
+; CHECK-SD-NEXT: add x9, sp, #208
; CHECK-SD-NEXT: ld1 { v0.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #320
-; CHECK-SD-NEXT: ldr b21, [sp, #552]
-; CHECK-SD-NEXT: ld1 { v2.b }[5], [x9]
-; CHECK-SD-NEXT: add x9, sp, #176
-; CHECK-SD-NEXT: ld1 { v1.b }[7], [x11]
-; CHECK-SD-NEXT: ld1 { v4.b }[4], [x8]
-; CHECK-SD-NEXT: add x8, sp, #624
-; CHECK-SD-NEXT: ld1 { v5.b }[3], [x9]
-; CHECK-SD-NEXT: ld1 { v6.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #120
-; CHECK-SD-NEXT: add x9, sp, #328
-; CHECK-SD-NEXT: ld1 { v2.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #184
-; CHECK-SD-NEXT: add x11, sp, #192
-; CHECK-SD-NEXT: ld1 { v4.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #632
+; CHECK-SD-NEXT: add x9, sp, #48
+; CHECK-SD-NEXT: ldrb w10, [sp, #128]
+; CHECK-SD-NEXT: mov v2.b[6], w8
; CHECK-SD-NEXT: ld1 { v5.b }[4], [x9]
-; CHECK-SD-NEXT: ld1 { v6.b }[2], [x8]
-; CHECK-SD-NEXT: add x9, sp, #640
-; CHECK-SD-NEXT: add x8, sp, #336
-; CHECK-SD-NEXT: ld1 { v2.b }[7], [x8]
-; CHECK-SD-NEXT: add x8, sp, #656
-; CHECK-SD-NEXT: smull v23.8h, v23.8b, v22.8b
-; CHECK-SD-NEXT: ld1 { v5.b }[5], [x11]
-; CHECK-SD-NEXT: add x11, sp, #648
+; CHECK-SD-NEXT: add x9, sp, #256
+; CHECK-SD-NEXT: ld1 { v4.b }[5], [x9]
+; CHECK-SD-NEXT: add x9, sp, #56
+; CHECK-SD-NEXT: ldrb w8, [sp, #544]
+; CHECK-SD-NEXT: mov v3.b[6], w10
+; CHECK-SD-NEXT: ldrb w10, [sp, #336]
+; CHECK-SD-NEXT: mov v1.b[5], w5
+; CHECK-SD-NEXT: ld1 { v5.b }[5], [x9]
+; CHECK-SD-NEXT: add x9, sp, #560
+; CHECK-SD-NEXT: dup v16.8b, w8
+; CHECK-SD-NEXT: mov v2.b[7], w10
+; CHECK-SD-NEXT: add x10, sp, #264
+; CHECK-SD-NEXT: ld1 { v6.b }[1], [x9]
; CHECK-SD-NEXT: ld1 { v4.b }[6], [x10]
-; CHECK-SD-NEXT: ld1 { v6.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #200
-; CHECK-SD-NEXT: add x10, sp, #136
-; CHECK-SD-NEXT: ldr b22, [sp, #352]
-; CHECK-SD-NEXT: add x12, sp, #360
-; CHECK-SD-NEXT: mov v3.b[3], w3
-; CHECK-SD-NEXT: ld1 { v5.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #208
-; CHECK-SD-NEXT: ld1 { v4.b }[7], [x10]
-; CHECK-SD-NEXT: ld1 { v6.b }[4], [x11]
-; CHECK-SD-NEXT: add x11, sp, #424
-; CHECK-SD-NEXT: add x10, sp, #488
+; CHECK-SD-NEXT: add x10, sp, #64
+; CHECK-SD-NEXT: ldrb w9, [sp, #680]
+; CHECK-SD-NEXT: ld1 { v5.b }[6], [x10]
+; CHECK-SD-NEXT: add x10, sp, #568
+; CHECK-SD-NEXT: mov v3.b[7], w11
+; CHECK-SD-NEXT: ld1 { v6.b }[2], [x10]
+; CHECK-SD-NEXT: add x11, sp, #272
+; CHECK-SD-NEXT: add x10, sp, #72
+; CHECK-SD-NEXT: ld1 { v4.b }[7], [x11]
+; CHECK-SD-NEXT: add x11, sp, #360
+; CHECK-SD-NEXT: fmov s17, w9
+; CHECK-SD-NEXT: ld1 { v5.b }[7], [x10]
+; CHECK-SD-NEXT: add x10, sp, #576
; CHECK-SD-NEXT: ld1 { v7.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #560
-; CHECK-SD-NEXT: ld1 { v20.b }[1], [x10]
-; CHECK-SD-NEXT: ld1 { v5.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #440
-; CHECK-SD-NEXT: ld1 { v21.b }[1], [x11]
-; CHECK-SD-NEXT: ld1 { v6.b }[5], [x8]
-; CHECK-SD-NEXT: add x8, sp, #432
-; CHECK-SD-NEXT: ld1 { v22.b }[1], [x12]
-; CHECK-SD-NEXT: ld1 { v7.b }[2], [x8]
-; CHECK-SD-NEXT: add x11, sp, #496
-; CHECK-SD-NEXT: add x12, sp, #568
-; CHECK-SD-NEXT: add x13, sp, #368
-; CHECK-SD-NEXT: ld1 { v20.b }[2], [x11]
-; CHECK-SD-NEXT: ld1 { v21.b }[2], [x12]
-; CHECK-SD-NEXT: ld1 { v22.b }[2], [x13]
-; CHECK-SD-NEXT: add x10, sp, #448
-; CHECK-SD-NEXT: mov v3.b[4], w4
+; CHECK-SD-NEXT: ld1 { v6.b }[3], [x10]
+; CHECK-SD-NEXT: ldrb w10, [sp, #480]
+; CHECK-SD-NEXT: ldrb w11, [sp, #688]
+; CHECK-SD-NEXT: add x9, sp, #368
+; CHECK-SD-NEXT: mov v21.16b, v16.16b
+; CHECK-SD-NEXT: mov v20.16b, v16.16b
+; CHECK-SD-NEXT: fmov s18, w10
+; CHECK-SD-NEXT: ld1 { v7.b }[2], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #488]
+; CHECK-SD-NEXT: mov v17.b[1], w11
+; CHECK-SD-NEXT: ldrb w11, [sp, #696]
+; CHECK-SD-NEXT: ldrb w10, [sp, #344]
+; CHECK-SD-NEXT: mov v1.b[6], w6
+; CHECK-SD-NEXT: mov v18.b[1], w9
+; CHECK-SD-NEXT: add x9, sp, #584
+; CHECK-SD-NEXT: mov v20.b[0], w10
+; CHECK-SD-NEXT: ld1 { v6.b }[4], [x9]
+; CHECK-SD-NEXT: add x9, sp, #376
+; CHECK-SD-NEXT: ldrb w10, [sp, #504]
; CHECK-SD-NEXT: ld1 { v7.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #688
-; CHECK-SD-NEXT: add x11, sp, #576
-; CHECK-SD-NEXT: ld1 { v19.b }[1], [x9]
-; CHECK-SD-NEXT: add x9, sp, #696
-; CHECK-SD-NEXT: add x12, sp, #376
-; CHECK-SD-NEXT: ld1 { v21.b }[3], [x11]
-; CHECK-SD-NEXT: ld1 { v22.b }[3], [x12]
-; CHECK-SD-NEXT: add x11, sp, #512
-; CHECK-SD-NEXT: ld1 { v7.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #504
-; CHECK-SD-NEXT: add x12, sp, #584
-; CHECK-SD-NEXT: ld1 { v19.b }[2], [x9]
-; CHECK-SD-NEXT: add x9, sp, #704
-; CHECK-SD-NEXT: ld1 { v20.b }[3], [x10]
-; CHECK-SD-NEXT: add x13, sp, #384
-; CHECK-SD-NEXT: mov v3.b[5], w5
-; CHECK-SD-NEXT: ld1 { v21.b }[4], [x12]
-; CHECK-SD-NEXT: ld1 { v22.b }[4], [x13]
-; CHECK-SD-NEXT: add x10, sp, #456
-; CHECK-SD-NEXT: ldr b16, [sp, #344]
-; CHECK-SD-NEXT: ld1 { v19.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #712
-; CHECK-SD-NEXT: ld1 { v20.b }[4], [x11]
-; CHECK-SD-NEXT: ldr b17, [sp, #144]
+; CHECK-SD-NEXT: ldrb w9, [sp, #144]
+; CHECK-SD-NEXT: mov v17.b[2], w11
+; CHECK-SD-NEXT: ldrb w11, [sp, #704]
+; CHECK-SD-NEXT: mov v1.b[7], w7
+; CHECK-SD-NEXT: mov v18.b[2], w12
+; CHECK-SD-NEXT: mov v21.b[0], w9
+; CHECK-SD-NEXT: add x9, sp, #592
+; CHECK-SD-NEXT: ld1 { v6.b }[5], [x9]
+; CHECK-SD-NEXT: add x9, sp, #384
+; CHECK-SD-NEXT: ld1 { v7.b }[4], [x9]
+; CHECK-SD-NEXT: mov v17.b[3], w11
+; CHECK-SD-NEXT: add x11, sp, #624
+; CHECK-SD-NEXT: ld1 { v19.b }[1], [x11]
+; CHECK-SD-NEXT: ldrb w9, [sp, #712]
+; CHECK-SD-NEXT: add x11, sp, #600
+; CHECK-SD-NEXT: mov v18.b[3], w10
+; CHECK-SD-NEXT: add x10, sp, #424
+; CHECK-SD-NEXT: ld1 { v6.b }[6], [x11]
+; CHECK-SD-NEXT: ld1 { v22.b }[1], [x10]
+; CHECK-SD-NEXT: add x10, sp, #392
+; CHECK-SD-NEXT: ldrb w11, [sp, #512]
; CHECK-SD-NEXT: ld1 { v7.b }[5], [x10]
-; CHECK-SD-NEXT: add x10, sp, #520
-; CHECK-SD-NEXT: add x11, sp, #592
-; CHECK-SD-NEXT: add x12, sp, #392
-; CHECK-SD-NEXT: mov v3.b[6], w6
-; CHECK-SD-NEXT: ld1 { v19.b }[4], [x9]
-; CHECK-SD-NEXT: add x9, sp, #720
-; CHECK-SD-NEXT: ld1 { v20.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v21.b }[5], [x11]
-; CHECK-SD-NEXT: ld1 { v22.b }[5], [x12]
-; CHECK-SD-NEXT: smull v16.8h, v17.8b, v16.8b
-; CHECK-SD-NEXT: add x8, sp, #664
-; CHECK-SD-NEXT: add x10, sp, #464
-; CHECK-SD-NEXT: add x11, sp, #528
-; CHECK-SD-NEXT: ld1 { v19.b }[5], [x9]
-; CHECK-SD-NEXT: add x9, sp, #728
-; CHECK-SD-NEXT: add x12, sp, #600
-; CHECK-SD-NEXT: add x13, sp, #400
-; CHECK-SD-NEXT: ld1 { v6.b }[6], [x8]
-; CHECK-SD-NEXT: ld1 { v20.b }[6], [x11]
-; CHECK-SD-NEXT: ld1 { v21.b }[6], [x12]
-; CHECK-SD-NEXT: ld1 { v22.b }[6], [x13]
+; CHECK-SD-NEXT: add x10, sp, #632
+; CHECK-SD-NEXT: mov v17.b[4], w9
+; CHECK-SD-NEXT: ld1 { v19.b }[2], [x10]
+; CHECK-SD-NEXT: add x10, sp, #432
+; CHECK-SD-NEXT: ldrb w9, [sp, #720]
+; CHECK-SD-NEXT: ld1 { v22.b }[2], [x10]
+; CHECK-SD-NEXT: add x10, sp, #608
+; CHECK-SD-NEXT: mov v18.b[4], w11
+; CHECK-SD-NEXT: add x11, sp, #640
+; CHECK-SD-NEXT: ld1 { v6.b }[7], [x10]
+; CHECK-SD-NEXT: add x10, sp, #440
+; CHECK-SD-NEXT: ld1 { v19.b }[3], [x11]
+; CHECK-SD-NEXT: ldrb w11, [sp, #520]
+; CHECK-SD-NEXT: mov v17.b[5], w9
+; CHECK-SD-NEXT: ld1 { v22.b }[3], [x10]
+; CHECK-SD-NEXT: add x10, sp, #400
+; CHECK-SD-NEXT: add x9, sp, #648
+; CHECK-SD-NEXT: smull v20.8h, v21.8b, v20.8b
+; CHECK-SD-NEXT: mov v21.16b, v16.16b
; CHECK-SD-NEXT: ld1 { v7.b }[6], [x10]
+; CHECK-SD-NEXT: ldrb w10, [sp, #744]
+; CHECK-SD-NEXT: mov v18.b[5], w11
+; CHECK-SD-NEXT: add x11, sp, #448
+; CHECK-SD-NEXT: ld1 { v19.b }[4], [x9]
+; CHECK-SD-NEXT: ld1 { v22.b }[4], [x11]
+; CHECK-SD-NEXT: mov v16.b[0], w8
+; CHECK-SD-NEXT: mov v21.b[0], w10
+; CHECK-SD-NEXT: add x10, sp, #656
+; CHECK-SD-NEXT: ldrb w9, [sp, #528]
+; CHECK-SD-NEXT: ldrb w11, [sp, #728]
+; CHECK-SD-NEXT: add x8, sp, #408
+; CHECK-SD-NEXT: sshll v20.4s, v20.4h, #0
+; CHECK-SD-NEXT: ld1 { v19.b }[5], [x10]
+; CHECK-SD-NEXT: add x10, sp, #456
+; CHECK-SD-NEXT: mov v18.b[6], w9
+; CHECK-SD-NEXT: ld1 { v22.b }[5], [x10]
+; CHECK-SD-NEXT: mov v17.b[6], w11
+; CHECK-SD-NEXT: add x9, sp, #664
+; CHECK-SD-NEXT: smull v16.8h, v16.8b, v21.8b
+; CHECK-SD-NEXT: ld1 { v7.b }[7], [x8]
+; CHECK-SD-NEXT: ldrb w8, [sp, #736]
; CHECK-SD-NEXT: ld1 { v19.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #736
-; CHECK-SD-NEXT: mov v3.b[7], w7
-; CHECK-SD-NEXT: sshll v18.4s, v16.4h, #0
-; CHECK-SD-NEXT: movi v16.2d, #0000000000000000
-; CHECK-SD-NEXT: movi v17.2d, #0000000000000000
-; CHECK-SD-NEXT: add x8, sp, #672
-; CHECK-SD-NEXT: add x10, sp, #472
-; CHECK-SD-NEXT: add x11, sp, #608
-; CHECK-SD-NEXT: ld1 { v19.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #536
-; CHECK-SD-NEXT: add x12, sp, #408
-; CHECK-SD-NEXT: ld1 { v20.b }[7], [x9]
-; CHECK-SD-NEXT: ld1 { v21.b }[7], [x11]
-; CHECK-SD-NEXT: ld1 { v22.b }[7], [x12]
-; CHECK-SD-NEXT: ld1 { v6.b }[7], [x8]
-; CHECK-SD-NEXT: ld1 { v7.b }[7], [x10]
-; CHECK-SD-NEXT: sshll v23.4s, v23.4h, #0
+; CHECK-SD-NEXT: add x9, sp, #464
+; CHECK-SD-NEXT: movi v21.2d, #0000000000000000
+; CHECK-SD-NEXT: ld1 { v22.b }[6], [x9]
+; CHECK-SD-NEXT: ldrb w9, [sp, #536]
; CHECK-SD-NEXT: smull v0.8h, v1.8b, v0.8b
-; CHECK-SD-NEXT: smull v1.8h, v4.8b, v2.8b
-; CHECK-SD-NEXT: smull v2.8h, v3.8b, v5.8b
-; CHECK-SD-NEXT: smull v3.8h, v20.8b, v19.8b
-; CHECK-SD-NEXT: smull v4.8h, v22.8b, v21.8b
-; CHECK-SD-NEXT: mov v17.s[0], v18.s[0]
-; CHECK-SD-NEXT: smull v5.8h, v7.8b, v6.8b
-; CHECK-SD-NEXT: mov v16.s[0], v23.s[0]
-; CHECK-SD-NEXT: saddl2 v6.4s, v2.8h, v1.8h
-; CHECK-SD-NEXT: saddl v1.4s, v2.4h, v1.4h
-; CHECK-SD-NEXT: saddl2 v2.4s, v4.8h, v3.8h
-; CHECK-SD-NEXT: saddl v3.4s, v4.4h, v3.4h
-; CHECK-SD-NEXT: saddw v4.4s, v17.4s, v0.4h
-; CHECK-SD-NEXT: saddw v7.4s, v16.4s, v5.4h
-; CHECK-SD-NEXT: saddw2 v0.4s, v6.4s, v0.8h
+; CHECK-SD-NEXT: mov v17.b[7], w8
+; CHECK-SD-NEXT: add x8, sp, #672
+; CHECK-SD-NEXT: smull v1.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: mov v18.b[7], w9
+; CHECK-SD-NEXT: add x9, sp, #472
+; CHECK-SD-NEXT: ld1 { v19.b }[7], [x8]
+; CHECK-SD-NEXT: ld1 { v22.b }[7], [x9]
+; CHECK-SD-NEXT: sshll v16.4s, v16.4h, #0
+; CHECK-SD-NEXT: smull v2.8h, v5.8b, v4.8b
+; CHECK-SD-NEXT: mov v23.s[0], v20.s[0]
+; CHECK-SD-NEXT: smull v3.8h, v7.8b, v6.8b
+; CHECK-SD-NEXT: saddl v7.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: saddl2 v0.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: smull v4.8h, v18.8b, v17.8b
+; CHECK-SD-NEXT: smull v5.8h, v22.8b, v19.8b
+; CHECK-SD-NEXT: mov v21.s[0], v16.s[0]
+; CHECK-SD-NEXT: saddw v6.4s, v23.4s, v2.4h
+; CHECK-SD-NEXT: saddw2 v0.4s, v0.4s, v2.8h
+; CHECK-SD-NEXT: saddl v1.4s, v3.4h, v4.4h
+; CHECK-SD-NEXT: saddl2 v3.4s, v3.8h, v4.8h
+; CHECK-SD-NEXT: saddw v4.4s, v21.4s, v5.4h
+; CHECK-SD-NEXT: add v6.4s, v7.4s, v6.4s
; CHECK-SD-NEXT: add v1.4s, v1.4s, v4.4s
-; CHECK-SD-NEXT: saddw2 v2.4s, v2.4s, v5.8h
-; CHECK-SD-NEXT: add v3.4s, v3.4s, v7.4s
-; CHECK-SD-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-SD-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-SD-NEXT: saddw2 v2.4s, v3.4s, v5.8h
+; CHECK-SD-NEXT: add v0.4s, v6.4s, v0.4s
+; CHECK-SD-NEXT: add v1.4s, v1.4s, v2.4s
; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: addv s0, v0.4s
; CHECK-SD-NEXT: fmov w0, s0
@@ -5508,267 +5520,275 @@ define i32 @test_sdot_v33i8_double(<33 x i8> %a, <33 x i8> %b, <33 x i8> %c, <33
; CHECK-SD-NEXT: .cfi_offset w29, -16
; CHECK-SD-NEXT: ldr b0, [sp, #344]
; CHECK-SD-NEXT: add x8, sp, #352
+; CHECK-SD-NEXT: add x9, sp, #360
; CHECK-SD-NEXT: ldr b1, [sp, #80]
-; CHECK-SD-NEXT: ldr b2, [sp, #216]
-; CHECK-SD-NEXT: add x9, sp, #96
-; CHECK-SD-NEXT: add x10, sp, #104
+; CHECK-SD-NEXT: add x12, sp, #368
+; CHECK-SD-NEXT: ldr b3, [sp, #216]
; CHECK-SD-NEXT: ld1 { v0.b }[1], [x8]
; CHECK-SD-NEXT: add x8, sp, #88
-; CHECK-SD-NEXT: ldr b4, [sp, #408]
+; CHECK-SD-NEXT: add x11, sp, #96
; CHECK-SD-NEXT: ld1 { v1.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #360
-; CHECK-SD-NEXT: add x12, sp, #248
-; CHECK-SD-NEXT: add x13, sp, #432
-; CHECK-SD-NEXT: add x11, sp, #384
+; CHECK-SD-NEXT: add x13, sp, #104
+; CHECK-SD-NEXT: add x14, sp, #384
+; CHECK-SD-NEXT: add x16, sp, #240
+; CHECK-SD-NEXT: ldr b4, [sp, #408]
+; CHECK-SD-NEXT: add x15, sp, #392
+; CHECK-SD-NEXT: ld1 { v0.b }[2], [x9]
; CHECK-SD-NEXT: ldr b5, [sp, #144]
-; CHECK-SD-NEXT: ld1 { v0.b }[2], [x8]
-; CHECK-SD-NEXT: add x8, sp, #224
; CHECK-SD-NEXT: ldr b6, [sp, #280]
-; CHECK-SD-NEXT: ld1 { v2.b }[1], [x8]
-; CHECK-SD-NEXT: ld1 { v1.b }[2], [x9]
-; CHECK-SD-NEXT: add x8, sp, #368
-; CHECK-SD-NEXT: add x9, sp, #232
-; CHECK-SD-NEXT: ldr b16, [sp, #744]
-; CHECK-SD-NEXT: ldr b17, [sp, #480]
-; CHECK-SD-NEXT: ld1 { v0.b }[3], [x8]
-; CHECK-SD-NEXT: add x8, sp, #376
-; CHECK-SD-NEXT: ldr b18, [sp, #936]
-; CHECK-SD-NEXT: ld1 { v2.b }[2], [x9]
-; CHECK-SD-NEXT: ld1 { v1.b }[3], [x10]
-; CHECK-SD-NEXT: add x9, sp, #240
-; CHECK-SD-NEXT: add x10, sp, #392
-; CHECK-SD-NEXT: ldr b19, [sp, #672]
-; CHECK-SD-NEXT: ldr b7, [sp, #16]
-; CHECK-SD-NEXT: ld1 { v0.b }[4], [x8]
-; CHECK-SD-NEXT: add x8, sp, #112
-; CHECK-SD-NEXT: ldr b21, [sp, #1000]
-; CHECK-SD-NEXT: ld1 { v2.b }[3], [x9]
-; CHECK-SD-NEXT: ld1 { v1.b }[4], [x8]
-; CHECK-SD-NEXT: add x8, sp, #416
-; CHECK-SD-NEXT: ld1 { v4.b }[1], [x8]
-; CHECK-SD-NEXT: add x8, sp, #120
-; CHECK-SD-NEXT: add x9, sp, #400
-; CHECK-SD-NEXT: ld1 { v0.b }[5], [x11]
-; CHECK-SD-NEXT: add x11, sp, #128
-; CHECK-SD-NEXT: ldr b22, [sp, #736]
-; CHECK-SD-NEXT: ld1 { v2.b }[4], [x12]
-; CHECK-SD-NEXT: add x12, sp, #424
-; CHECK-SD-NEXT: ld1 { v1.b }[5], [x8]
-; CHECK-SD-NEXT: ld1 { v4.b }[2], [x12]
-; CHECK-SD-NEXT: add x12, sp, #152
-; CHECK-SD-NEXT: add x8, sp, #136
-; CHECK-SD-NEXT: ld1 { v5.b }[1], [x12]
-; CHECK-SD-NEXT: add x12, sp, #440
-; CHECK-SD-NEXT: ld1 { v0.b }[6], [x10]
-; CHECK-SD-NEXT: ld1 { v1.b }[6], [x11]
-; CHECK-SD-NEXT: add x11, sp, #288
-; CHECK-SD-NEXT: add x10, sp, #256
+; CHECK-SD-NEXT: ld1 { v1.b }[2], [x11]
+; CHECK-SD-NEXT: ldrb w8, [sp, #736]
+; CHECK-SD-NEXT: ldrb w10, [sp, #208]
+; CHECK-SD-NEXT: ldrb w11, [sp, #472]
+; CHECK-SD-NEXT: ldr b18, [sp, #744]
+; CHECK-SD-NEXT: ldr b19, [sp, #480]
+; CHECK-SD-NEXT: ld1 { v0.b }[3], [x12]
+; CHECK-SD-NEXT: add x12, sp, #224
+; CHECK-SD-NEXT: dup v16.8b, w8
+; CHECK-SD-NEXT: ld1 { v3.b }[1], [x12]
+; CHECK-SD-NEXT: add x12, sp, #376
+; CHECK-SD-NEXT: ld1 { v1.b }[3], [x13]
+; CHECK-SD-NEXT: add x13, sp, #400
+; CHECK-SD-NEXT: ldr b21, [sp, #936]
+; CHECK-SD-NEXT: ldr b22, [sp, #672]
+; CHECK-SD-NEXT: ld1 { v0.b }[4], [x12]
+; CHECK-SD-NEXT: add x12, sp, #232
+; CHECK-SD-NEXT: ldrb w9, [sp, #1000]
+; CHECK-SD-NEXT: ld1 { v3.b }[2], [x12]
+; CHECK-SD-NEXT: add x12, sp, #112
+; CHECK-SD-NEXT: mov v7.16b, v16.16b
+; CHECK-SD-NEXT: ld1 { v1.b }[4], [x12]
+; CHECK-SD-NEXT: add x12, sp, #120
+; CHECK-SD-NEXT: mov v17.16b, v16.16b
+; CHECK-SD-NEXT: ld1 { v0.b }[5], [x14]
+; CHECK-SD-NEXT: add x14, sp, #128
+; CHECK-SD-NEXT: mov v20.16b, v16.16b
+; CHECK-SD-NEXT: ld1 { v3.b }[3], [x16]
+; CHECK-SD-NEXT: add x16, sp, #416
+; CHECK-SD-NEXT: mov v7.b[0], w11
+; CHECK-SD-NEXT: ld1 { v4.b }[1], [x16]
+; CHECK-SD-NEXT: ld1 { v1.b }[5], [x12]
+; CHECK-SD-NEXT: add x16, sp, #248
+; CHECK-SD-NEXT: ld1 { v0.b }[6], [x15]
+; CHECK-SD-NEXT: add x15, sp, #424
+; CHECK-SD-NEXT: add x12, sp, #136
+; CHECK-SD-NEXT: ld1 { v3.b }[4], [x16]
+; CHECK-SD-NEXT: add x16, sp, #256
+; CHECK-SD-NEXT: mov v17.b[0], w10
+; CHECK-SD-NEXT: ld1 { v4.b }[2], [x15]
+; CHECK-SD-NEXT: add x15, sp, #152
+; CHECK-SD-NEXT: ld1 { v1.b }[6], [x14]
+; CHECK-SD-NEXT: ld1 { v5.b }[1], [x15]
+; CHECK-SD-NEXT: add x14, sp, #160
+; CHECK-SD-NEXT: ld1 { v0.b }[7], [x13]
+; CHECK-SD-NEXT: ld1 { v3.b }[5], [x16]
+; CHECK-SD-NEXT: add x13, sp, #432
+; CHECK-SD-NEXT: add x11, sp, #456
; CHECK-SD-NEXT: ld1 { v4.b }[3], [x13]
-; CHECK-SD-NEXT: ld1 { v6.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #296
-; CHECK-SD-NEXT: ld1 { v0.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #160
-; CHECK-SD-NEXT: ld1 { v2.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v5.b }[2], [x9]
-; CHECK-SD-NEXT: add x10, sp, #168
-; CHECK-SD-NEXT: ld1 { v1.b }[7], [x8]
+; CHECK-SD-NEXT: add x13, sp, #288
+; CHECK-SD-NEXT: ld1 { v1.b }[7], [x12]
+; CHECK-SD-NEXT: ld1 { v5.b }[2], [x14]
+; CHECK-SD-NEXT: add x12, sp, #264
+; CHECK-SD-NEXT: ld1 { v6.b }[1], [x13]
+; CHECK-SD-NEXT: add x13, sp, #168
+; CHECK-SD-NEXT: ld1 { v3.b }[6], [x12]
+; CHECK-SD-NEXT: add x12, sp, #440
; CHECK-SD-NEXT: ld1 { v4.b }[4], [x12]
+; CHECK-SD-NEXT: add x12, sp, #296
+; CHECK-SD-NEXT: add x14, sp, #680
+; CHECK-SD-NEXT: ld1 { v5.b }[3], [x13]
+; CHECK-SD-NEXT: ld1 { v6.b }[2], [x12]
+; CHECK-SD-NEXT: add x13, sp, #176
; CHECK-SD-NEXT: add x12, sp, #448
-; CHECK-SD-NEXT: ld1 { v6.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #304
-; CHECK-SD-NEXT: add x8, sp, #464
-; CHECK-SD-NEXT: add x13, sp, #768
-; CHECK-SD-NEXT: ld1 { v5.b }[3], [x10]
-; CHECK-SD-NEXT: add x10, sp, #176
-; CHECK-SD-NEXT: add x9, sp, #264
+; CHECK-SD-NEXT: ld1 { v22.b }[1], [x14]
+; CHECK-SD-NEXT: add x15, sp, #496
; CHECK-SD-NEXT: ld1 { v4.b }[5], [x12]
-; CHECK-SD-NEXT: add x12, sp, #456
-; CHECK-SD-NEXT: ld1 { v6.b }[3], [x11]
-; CHECK-SD-NEXT: add x11, sp, #760
-; CHECK-SD-NEXT: ld1 { v2.b }[6], [x9]
-; CHECK-SD-NEXT: add x9, sp, #272
-; CHECK-SD-NEXT: ld1 { v5.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #312
-; CHECK-SD-NEXT: fmov s3, w0
-; CHECK-SD-NEXT: ld1 { v4.b }[6], [x12]
-; CHECK-SD-NEXT: ld1 { v6.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #320
-; CHECK-SD-NEXT: add x12, sp, #680
-; CHECK-SD-NEXT: ld1 { v2.b }[7], [x9]
-; CHECK-SD-NEXT: add x9, sp, #184
+; CHECK-SD-NEXT: add x12, sp, #304
+; CHECK-SD-NEXT: smull v7.8h, v17.8b, v7.8b
+; CHECK-SD-NEXT: ld1 { v5.b }[4], [x13]
+; CHECK-SD-NEXT: ld1 { v6.b }[3], [x12]
+; CHECK-SD-NEXT: add x12, sp, #184
+; CHECK-SD-NEXT: add x13, sp, #944
+; CHECK-SD-NEXT: ldr b17, [sp, #16]
+; CHECK-SD-NEXT: add x14, sp, #504
+; CHECK-SD-NEXT: ld1 { v4.b }[6], [x11]
+; CHECK-SD-NEXT: add x11, sp, #312
+; CHECK-SD-NEXT: ld1 { v21.b }[1], [x13]
+; CHECK-SD-NEXT: ld1 { v5.b }[5], [x12]
+; CHECK-SD-NEXT: add x12, sp, #752
+; CHECK-SD-NEXT: ld1 { v6.b }[4], [x11]
+; CHECK-SD-NEXT: ld1 { v18.b }[1], [x12]
+; CHECK-SD-NEXT: add x12, sp, #488
+; CHECK-SD-NEXT: add x11, sp, #192
; CHECK-SD-NEXT: ld1 { v19.b }[1], [x12]
-; CHECK-SD-NEXT: add x12, sp, #776
-; CHECK-SD-NEXT: ld1 { v5.b }[5], [x9]
-; CHECK-SD-NEXT: ld1 { v4.b }[7], [x8]
-; CHECK-SD-NEXT: add x8, sp, #752
-; CHECK-SD-NEXT: ld1 { v6.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v16.b }[1], [x8]
-; CHECK-SD-NEXT: add x10, sp, #24
-; CHECK-SD-NEXT: smull v22.8h, v22.8b, v21.8b
-; CHECK-SD-NEXT: ld1 { v7.b }[1], [x10]
-; CHECK-SD-NEXT: add x10, sp, #496
-; CHECK-SD-NEXT: mov v3.b[1], w1
-; CHECK-SD-NEXT: add x9, sp, #192
-; CHECK-SD-NEXT: ldr b20, [sp, #472]
-; CHECK-SD-NEXT: ldr b23, [sp, #208]
-; CHECK-SD-NEXT: ld1 { v16.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #488
-; CHECK-SD-NEXT: ld1 { v5.b }[6], [x9]
+; CHECK-SD-NEXT: add x12, sp, #760
+; CHECK-SD-NEXT: add x13, sp, #688
+; CHECK-SD-NEXT: ld1 { v5.b }[6], [x11]
+; CHECK-SD-NEXT: add x11, sp, #320
+; CHECK-SD-NEXT: ld1 { v22.b }[2], [x13]
+; CHECK-SD-NEXT: ld1 { v18.b }[2], [x12]
+; CHECK-SD-NEXT: add x12, sp, #952
+; CHECK-SD-NEXT: ld1 { v6.b }[5], [x11]
+; CHECK-SD-NEXT: ld1 { v19.b }[2], [x15]
+; CHECK-SD-NEXT: add x11, sp, #24
+; CHECK-SD-NEXT: ld1 { v21.b }[2], [x12]
; CHECK-SD-NEXT: ld1 { v17.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #944
-; CHECK-SD-NEXT: add x9, sp, #328
-; CHECK-SD-NEXT: ld1 { v18.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #688
-; CHECK-SD-NEXT: ld1 { v6.b }[6], [x9]
-; CHECK-SD-NEXT: ld1 { v16.b }[3], [x13]
-; CHECK-SD-NEXT: ld1 { v19.b }[2], [x11]
-; CHECK-SD-NEXT: add x11, sp, #504
-; CHECK-SD-NEXT: ld1 { v17.b }[2], [x10]
-; CHECK-SD-NEXT: add x10, sp, #952
-; CHECK-SD-NEXT: add x13, sp, #784
-; CHECK-SD-NEXT: ld1 { v18.b }[2], [x10]
-; CHECK-SD-NEXT: add x10, sp, #32
-; CHECK-SD-NEXT: add x9, sp, #40
-; CHECK-SD-NEXT: ld1 { v16.b }[4], [x12]
-; CHECK-SD-NEXT: add x12, sp, #696
-; CHECK-SD-NEXT: ld1 { v7.b }[2], [x10]
-; CHECK-SD-NEXT: ld1 { v17.b }[3], [x11]
-; CHECK-SD-NEXT: add x11, sp, #960
-; CHECK-SD-NEXT: ld1 { v19.b }[3], [x12]
+; CHECK-SD-NEXT: add x11, sp, #768
+; CHECK-SD-NEXT: add x13, sp, #960
; CHECK-SD-NEXT: ld1 { v18.b }[3], [x11]
-; CHECK-SD-NEXT: add x10, sp, #512
-; CHECK-SD-NEXT: add x11, sp, #704
-; CHECK-SD-NEXT: ld1 { v16.b }[5], [x13]
-; CHECK-SD-NEXT: add x12, sp, #792
-; CHECK-SD-NEXT: sshll v24.4s, v22.4h, #0
-; CHECK-SD-NEXT: ld1 { v17.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #968
-; CHECK-SD-NEXT: ld1 { v19.b }[4], [x11]
-; CHECK-SD-NEXT: ld1 { v18.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #520
-; CHECK-SD-NEXT: add x11, sp, #976
-; CHECK-SD-NEXT: ld1 { v16.b }[6], [x12]
-; CHECK-SD-NEXT: add x12, sp, #712
-; CHECK-SD-NEXT: smull v20.8h, v23.8b, v20.8b
-; CHECK-SD-NEXT: ld1 { v17.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[5], [x12]
-; CHECK-SD-NEXT: add x12, sp, #720
+; CHECK-SD-NEXT: add x11, sp, #776
+; CHECK-SD-NEXT: add x15, sp, #512
+; CHECK-SD-NEXT: ld1 { v19.b }[3], [x14]
+; CHECK-SD-NEXT: add x14, sp, #696
+; CHECK-SD-NEXT: ld1 { v21.b }[3], [x13]
+; CHECK-SD-NEXT: ld1 { v22.b }[3], [x14]
+; CHECK-SD-NEXT: add x14, sp, #968
+; CHECK-SD-NEXT: add x13, sp, #520
+; CHECK-SD-NEXT: ld1 { v18.b }[4], [x11]
+; CHECK-SD-NEXT: add x11, sp, #784
+; CHECK-SD-NEXT: mov v20.b[0], w9
+; CHECK-SD-NEXT: ld1 { v19.b }[4], [x15]
+; CHECK-SD-NEXT: add x15, sp, #704
+; CHECK-SD-NEXT: ld1 { v21.b }[4], [x14]
+; CHECK-SD-NEXT: ld1 { v22.b }[4], [x15]
+; CHECK-SD-NEXT: mov v16.b[0], w8
+; CHECK-SD-NEXT: add x8, sp, #976
; CHECK-SD-NEXT: ld1 { v18.b }[5], [x11]
-; CHECK-SD-NEXT: add x11, sp, #528
-; CHECK-SD-NEXT: add x10, sp, #800
-; CHECK-SD-NEXT: ld1 { v16.b }[7], [x10]
-; CHECK-SD-NEXT: add x10, sp, #536
-; CHECK-SD-NEXT: ldr b22, [sp, #872]
-; CHECK-SD-NEXT: ld1 { v17.b }[6], [x11]
-; CHECK-SD-NEXT: add x11, sp, #984
-; CHECK-SD-NEXT: ld1 { v19.b }[6], [x12]
+; CHECK-SD-NEXT: add x9, sp, #712
+; CHECK-SD-NEXT: add x11, sp, #792
+; CHECK-SD-NEXT: ld1 { v19.b }[5], [x13]
+; CHECK-SD-NEXT: ld1 { v21.b }[5], [x8]
+; CHECK-SD-NEXT: add x8, sp, #800
+; CHECK-SD-NEXT: ld1 { v22.b }[5], [x9]
+; CHECK-SD-NEXT: add x9, sp, #528
+; CHECK-SD-NEXT: fmov s2, w0
; CHECK-SD-NEXT: ld1 { v18.b }[6], [x11]
-; CHECK-SD-NEXT: add x11, sp, #992
-; CHECK-SD-NEXT: add x12, sp, #728
+; CHECK-SD-NEXT: add x11, sp, #720
+; CHECK-SD-NEXT: smull v20.8h, v16.8b, v20.8b
+; CHECK-SD-NEXT: ld1 { v19.b }[6], [x9]
+; CHECK-SD-NEXT: add x9, sp, #984
+; CHECK-SD-NEXT: add x12, sp, #32
+; CHECK-SD-NEXT: ld1 { v21.b }[6], [x9]
+; CHECK-SD-NEXT: ld1 { v22.b }[6], [x11]
+; CHECK-SD-NEXT: add x9, sp, #992
+; CHECK-SD-NEXT: ld1 { v18.b }[7], [x8]
+; CHECK-SD-NEXT: add x8, sp, #536
+; CHECK-SD-NEXT: add x11, sp, #728
+; CHECK-SD-NEXT: movi v16.2d, #0000000000000000
+; CHECK-SD-NEXT: ld1 { v19.b }[7], [x8]
+; CHECK-SD-NEXT: ld1 { v17.b }[2], [x12]
+; CHECK-SD-NEXT: ld1 { v21.b }[7], [x9]
+; CHECK-SD-NEXT: ld1 { v22.b }[7], [x11]
+; CHECK-SD-NEXT: sshll v23.4s, v20.4h, #0
+; CHECK-SD-NEXT: mov v2.b[1], w1
+; CHECK-SD-NEXT: add x9, sp, #40
+; CHECK-SD-NEXT: add x8, sp, #328
+; CHECK-SD-NEXT: smull v18.8h, v19.8b, v18.8b
+; CHECK-SD-NEXT: ld1 { v17.b }[3], [x9]
+; CHECK-SD-NEXT: ldr b20, [sp, #872]
+; CHECK-SD-NEXT: smull v19.8h, v22.8b, v21.8b
+; CHECK-SD-NEXT: ldr b21, [sp, #808]
+; CHECK-SD-NEXT: ldr b22, [sp, #544]
+; CHECK-SD-NEXT: mov v16.s[0], v23.s[0]
; CHECK-SD-NEXT: ldr b23, [sp, #608]
-; CHECK-SD-NEXT: ld1 { v7.b }[3], [x9]
-; CHECK-SD-NEXT: add x9, sp, #880
-; CHECK-SD-NEXT: ld1 { v17.b }[7], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[7], [x12]
-; CHECK-SD-NEXT: add x10, sp, #816
-; CHECK-SD-NEXT: ld1 { v18.b }[7], [x11]
+; CHECK-SD-NEXT: add x9, sp, #816
; CHECK-SD-NEXT: add x11, sp, #552
+; CHECK-SD-NEXT: ld1 { v6.b }[6], [x8]
+; CHECK-SD-NEXT: add x8, sp, #880
; CHECK-SD-NEXT: add x12, sp, #616
-; CHECK-SD-NEXT: mov v3.b[2], w2
-; CHECK-SD-NEXT: ld1 { v22.b }[1], [x9]
+; CHECK-SD-NEXT: ld1 { v21.b }[1], [x9]
+; CHECK-SD-NEXT: ld1 { v22.b }[1], [x11]
+; CHECK-SD-NEXT: mov v2.b[2], w2
+; CHECK-SD-NEXT: ld1 { v20.b }[1], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[1], [x12]
-; CHECK-SD-NEXT: smull v16.8h, v17.8b, v16.8b
+; CHECK-SD-NEXT: add x11, sp, #824
; CHECK-SD-NEXT: add x12, sp, #560
-; CHECK-SD-NEXT: add x9, sp, #888
-; CHECK-SD-NEXT: smull v17.8h, v19.8b, v18.8b
-; CHECK-SD-NEXT: ldr b18, [sp, #808]
-; CHECK-SD-NEXT: ldr b19, [sp, #544]
+; CHECK-SD-NEXT: add x8, sp, #888
; CHECK-SD-NEXT: add x13, sp, #624
-; CHECK-SD-NEXT: ld1 { v22.b }[2], [x9]
-; CHECK-SD-NEXT: add x9, sp, #896
-; CHECK-SD-NEXT: ld1 { v18.b }[1], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[1], [x11]
-; CHECK-SD-NEXT: add x11, sp, #824
-; CHECK-SD-NEXT: add x10, sp, #48
+; CHECK-SD-NEXT: ld1 { v21.b }[2], [x11]
+; CHECK-SD-NEXT: ld1 { v22.b }[2], [x12]
+; CHECK-SD-NEXT: add x9, sp, #48
+; CHECK-SD-NEXT: ld1 { v20.b }[2], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[2], [x13]
-; CHECK-SD-NEXT: mov v3.b[3], w3
-; CHECK-SD-NEXT: ld1 { v7.b }[4], [x10]
-; CHECK-SD-NEXT: add x10, sp, #832
-; CHECK-SD-NEXT: ld1 { v22.b }[3], [x9]
-; CHECK-SD-NEXT: ld1 { v18.b }[2], [x11]
-; CHECK-SD-NEXT: ld1 { v19.b }[2], [x12]
+; CHECK-SD-NEXT: mov v2.b[3], w3
+; CHECK-SD-NEXT: ld1 { v17.b }[4], [x9]
+; CHECK-SD-NEXT: add x9, sp, #832
; CHECK-SD-NEXT: add x11, sp, #568
+; CHECK-SD-NEXT: add x8, sp, #896
; CHECK-SD-NEXT: add x12, sp, #632
-; CHECK-SD-NEXT: add x9, sp, #904
-; CHECK-SD-NEXT: add x13, sp, #640
+; CHECK-SD-NEXT: ld1 { v21.b }[3], [x9]
+; CHECK-SD-NEXT: ld1 { v22.b }[3], [x11]
+; CHECK-SD-NEXT: ld1 { v20.b }[3], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[3], [x12]
-; CHECK-SD-NEXT: add x12, sp, #576
-; CHECK-SD-NEXT: mov v3.b[4], w4
-; CHECK-SD-NEXT: ld1 { v18.b }[3], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[3], [x11]
; CHECK-SD-NEXT: add x11, sp, #840
-; CHECK-SD-NEXT: add x10, sp, #56
-; CHECK-SD-NEXT: ld1 { v22.b }[4], [x9]
-; CHECK-SD-NEXT: add x9, sp, #912
+; CHECK-SD-NEXT: add x12, sp, #576
+; CHECK-SD-NEXT: mov v2.b[4], w4
+; CHECK-SD-NEXT: add x8, sp, #904
+; CHECK-SD-NEXT: add x13, sp, #640
+; CHECK-SD-NEXT: ld1 { v21.b }[4], [x11]
+; CHECK-SD-NEXT: ld1 { v22.b }[4], [x12]
+; CHECK-SD-NEXT: add x9, sp, #56
+; CHECK-SD-NEXT: ld1 { v20.b }[4], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[4], [x13]
-; CHECK-SD-NEXT: ld1 { v7.b }[5], [x10]
-; CHECK-SD-NEXT: add x10, sp, #848
-; CHECK-SD-NEXT: ld1 { v18.b }[4], [x11]
-; CHECK-SD-NEXT: ld1 { v19.b }[4], [x12]
+; CHECK-SD-NEXT: ld1 { v17.b }[5], [x9]
+; CHECK-SD-NEXT: add x9, sp, #848
; CHECK-SD-NEXT: add x11, sp, #584
+; CHECK-SD-NEXT: add x8, sp, #912
; CHECK-SD-NEXT: add x12, sp, #648
-; CHECK-SD-NEXT: mov v3.b[5], w5
-; CHECK-SD-NEXT: ld1 { v22.b }[5], [x9]
+; CHECK-SD-NEXT: ld1 { v21.b }[5], [x9]
+; CHECK-SD-NEXT: ld1 { v22.b }[5], [x11]
+; CHECK-SD-NEXT: mov v2.b[5], w5
+; CHECK-SD-NEXT: ld1 { v20.b }[5], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[5], [x12]
-; CHECK-SD-NEXT: add x12, sp, #592
-; CHECK-SD-NEXT: movi v21.2d, #0000000000000000
-; CHECK-SD-NEXT: ld1 { v18.b }[5], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[5], [x11]
; CHECK-SD-NEXT: add x11, sp, #856
-; CHECK-SD-NEXT: add x9, sp, #920
+; CHECK-SD-NEXT: add x12, sp, #592
+; CHECK-SD-NEXT: add x8, sp, #920
; CHECK-SD-NEXT: add x13, sp, #656
-; CHECK-SD-NEXT: add x10, sp, #64
-; CHECK-SD-NEXT: ld1 { v22.b }[6], [x9]
+; CHECK-SD-NEXT: ld1 { v21.b }[6], [x11]
+; CHECK-SD-NEXT: ld1 { v22.b }[6], [x12]
+; CHECK-SD-NEXT: add x9, sp, #64
+; CHECK-SD-NEXT: ld1 { v20.b }[6], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[6], [x13]
-; CHECK-SD-NEXT: mov v3.b[6], w6
-; CHECK-SD-NEXT: ld1 { v18.b }[6], [x11]
-; CHECK-SD-NEXT: ld1 { v19.b }[6], [x12]
-; CHECK-SD-NEXT: ld1 { v7.b }[6], [x10]
-; CHECK-SD-NEXT: add x10, sp, #864
+; CHECK-SD-NEXT: mov v2.b[6], w6
+; CHECK-SD-NEXT: ld1 { v17.b }[6], [x9]
+; CHECK-SD-NEXT: add x9, sp, #864
; CHECK-SD-NEXT: add x11, sp, #600
-; CHECK-SD-NEXT: add x9, sp, #928
+; CHECK-SD-NEXT: add x8, sp, #928
; CHECK-SD-NEXT: add x12, sp, #664
-; CHECK-SD-NEXT: mov v21.s[0], v24.s[0]
-; CHECK-SD-NEXT: ld1 { v22.b }[7], [x9]
-; CHECK-SD-NEXT: ld1 { v18.b }[7], [x10]
-; CHECK-SD-NEXT: ld1 { v19.b }[7], [x11]
+; CHECK-SD-NEXT: ld1 { v21.b }[7], [x9]
+; CHECK-SD-NEXT: ld1 { v22.b }[7], [x11]
+; CHECK-SD-NEXT: add x10, sp, #272
+; CHECK-SD-NEXT: ld1 { v20.b }[7], [x8]
; CHECK-SD-NEXT: ld1 { v23.b }[7], [x12]
-; CHECK-SD-NEXT: add x8, sp, #200
-; CHECK-SD-NEXT: mov v3.b[7], w7
-; CHECK-SD-NEXT: add x10, sp, #336
-; CHECK-SD-NEXT: ld1 { v5.b }[7], [x8]
+; CHECK-SD-NEXT: ld1 { v3.b }[7], [x10]
+; CHECK-SD-NEXT: add x10, sp, #464
+; CHECK-SD-NEXT: mov v2.b[7], w7
+; CHECK-SD-NEXT: add x9, sp, #336
+; CHECK-SD-NEXT: ld1 { v4.b }[7], [x10]
+; CHECK-SD-NEXT: add x10, sp, #200
; CHECK-SD-NEXT: add x8, sp, #72
-; CHECK-SD-NEXT: ld1 { v6.b }[7], [x10]
-; CHECK-SD-NEXT: smull v18.8h, v19.8b, v18.8b
-; CHECK-SD-NEXT: movi v19.2d, #0000000000000000
-; CHECK-SD-NEXT: ld1 { v7.b }[7], [x8]
-; CHECK-SD-NEXT: smull v22.8h, v23.8b, v22.8b
-; CHECK-SD-NEXT: sshll v20.4s, v20.4h, #0
+; CHECK-SD-NEXT: smull v21.8h, v22.8b, v21.8b
+; CHECK-SD-NEXT: movi v22.2d, #0000000000000000
+; CHECK-SD-NEXT: ld1 { v5.b }[7], [x10]
+; CHECK-SD-NEXT: ld1 { v6.b }[7], [x9]
+; CHECK-SD-NEXT: ld1 { v17.b }[7], [x8]
+; CHECK-SD-NEXT: smull v20.8h, v23.8b, v20.8b
+; CHECK-SD-NEXT: sshll v7.4s, v7.4h, #0
; CHECK-SD-NEXT: smull v0.8h, v1.8b, v0.8b
-; CHECK-SD-NEXT: saddw v1.4s, v21.4s, v16.4h
-; CHECK-SD-NEXT: smull v2.8h, v3.8b, v2.8b
+; CHECK-SD-NEXT: saddw v1.4s, v16.4s, v18.4h
+; CHECK-SD-NEXT: smull v2.8h, v2.8b, v3.8b
; CHECK-SD-NEXT: smull v3.8h, v5.8b, v4.8b
-; CHECK-SD-NEXT: smull v4.8h, v7.8b, v6.8b
-; CHECK-SD-NEXT: mov v19.s[0], v20.s[0]
-; CHECK-SD-NEXT: saddl2 v5.4s, v18.8h, v17.8h
-; CHECK-SD-NEXT: saddl v7.4s, v18.4h, v17.4h
-; CHECK-SD-NEXT: saddl2 v6.4s, v16.8h, v22.8h
-; CHECK-SD-NEXT: saddw v1.4s, v1.4s, v22.4h
+; CHECK-SD-NEXT: smull v4.8h, v17.8b, v6.8b
+; CHECK-SD-NEXT: saddl2 v5.4s, v21.8h, v19.8h
+; CHECK-SD-NEXT: mov v22.s[0], v7.s[0]
+; CHECK-SD-NEXT: saddl2 v6.4s, v18.8h, v20.8h
+; CHECK-SD-NEXT: saddl v7.4s, v21.4h, v19.4h
+; CHECK-SD-NEXT: saddw v1.4s, v1.4s, v20.4h
; CHECK-SD-NEXT: saddl2 v17.4s, v2.8h, v0.8h
; CHECK-SD-NEXT: saddl2 v16.4s, v4.8h, v3.8h
-; CHECK-SD-NEXT: saddl v3.4s, v4.4h, v3.4h
-; CHECK-SD-NEXT: saddw v2.4s, v19.4s, v2.4h
; CHECK-SD-NEXT: add v5.4s, v6.4s, v5.4s
+; CHECK-SD-NEXT: saddl v3.4s, v4.4h, v3.4h
+; CHECK-SD-NEXT: saddw v2.4s, v22.4s, v2.4h
; CHECK-SD-NEXT: add v1.4s, v1.4s, v7.4s
; CHECK-SD-NEXT: add v6.4s, v17.4s, v16.4s
; CHECK-SD-NEXT: saddw v0.4s, v2.4s, v0.4h
diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
index d3fa414cfda69..865a24a541802 100644
--- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
@@ -4316,56 +4316,57 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-ISEL-NEXT: [[S_MUL_I32_19:%[0-9]+]]:sreg_32 = S_MUL_I32 [[COPY21]], [[COPY69]]
; GCN-ISEL-NEXT: [[S_USUBO:%[0-9]+]]:sreg_32, [[S_USUBO1:%[0-9]+]]:sreg_64_xexec = S_USUBO_PSEUDO [[COPY56]], killed [[S_MUL_I32_19]], implicit-def dead $scc
; GCN-ISEL-NEXT: [[S_SUB_C:%[0-9]+]]:sreg_32, [[S_SUB_C1:%[0-9]+]]:sreg_64_xexec = S_SUB_CO_PSEUDO killed [[S_SUB_I32_3]], [[COPY22]], [[S_USUBO1]], implicit-def dead $scc
-; GCN-ISEL-NEXT: [[S_USUBO2:%[0-9]+]]:sreg_32, [[S_USUBO3:%[0-9]+]]:sreg_64_xexec = S_USUBO_PSEUDO [[S_USUBO]], [[COPY21]], implicit-def dead $scc
+; GCN-ISEL-NEXT: [[COPY72:%[0-9]+]]:sreg_32 = COPY killed [[S_USUBO]]
+; GCN-ISEL-NEXT: [[S_USUBO2:%[0-9]+]]:sreg_32, [[S_USUBO3:%[0-9]+]]:sreg_64_xexec = S_USUBO_PSEUDO [[COPY72]], [[COPY21]], implicit-def dead $scc
; GCN-ISEL-NEXT: [[S_SUB_C2:%[0-9]+]]:sreg_32, [[S_SUB_C3:%[0-9]+]]:sreg_64_xexec = S_SUB_CO_PSEUDO killed [[S_SUB_C]], [[S_MOV_B32_10]], killed [[S_USUBO3]], implicit-def dead $scc
-; GCN-ISEL-NEXT: S_CMP_GE_U32 [[S_SUB_C2]], [[COPY22]], implicit-def $scc
+; GCN-ISEL-NEXT: [[COPY73:%[0-9]+]]:sreg_32 = COPY killed [[S_SUB_C2]]
+; GCN-ISEL-NEXT: S_CMP_GE_U32 [[COPY73]], [[COPY22]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_MOV_B32_11:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-ISEL-NEXT: [[S_CSELECT_B32_4:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
; GCN-ISEL-NEXT: S_CMP_GE_U32 killed [[S_USUBO2]], [[COPY21]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_5:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
-; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[S_SUB_C2]], [[COPY22]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[COPY73]], [[COPY22]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_6:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_5]], killed [[S_CSELECT_B32_4]], implicit $scc
-; GCN-ISEL-NEXT: [[COPY72:%[0-9]+]]:sreg_32 = COPY killed [[S_CSELECT_B32_6]]
; GCN-ISEL-NEXT: [[REG_SEQUENCE22:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY69]], %subreg.sub0, [[COPY68]], %subreg.sub1
; GCN-ISEL-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 1
; GCN-ISEL-NEXT: [[S_ADD_U6:%[0-9]+]]:sreg_64 = S_ADD_U64_PSEUDO [[REG_SEQUENCE22]], killed [[S_MOV_B64_2]], implicit-def dead $scc
-; GCN-ISEL-NEXT: [[COPY73:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub0
+; GCN-ISEL-NEXT: [[COPY74:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub0
; GCN-ISEL-NEXT: [[S_MOV_B64_3:%[0-9]+]]:sreg_64 = S_MOV_B64 2
; GCN-ISEL-NEXT: [[S_ADD_U7:%[0-9]+]]:sreg_64 = S_ADD_U64_PSEUDO [[REG_SEQUENCE22]], killed [[S_MOV_B64_3]], implicit-def dead $scc
-; GCN-ISEL-NEXT: [[COPY74:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub0
-; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[COPY72]], [[S_MOV_B32_10]], implicit-def $scc
-; GCN-ISEL-NEXT: [[S_CSELECT_B32_7:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY74]], killed [[COPY73]], implicit $scc
-; GCN-ISEL-NEXT: [[COPY75:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub1
-; GCN-ISEL-NEXT: [[COPY76:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub1
-; GCN-ISEL-NEXT: [[S_CSELECT_B32_8:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY76]], killed [[COPY75]], implicit $scc
+; GCN-ISEL-NEXT: [[COPY75:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub0
+; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[S_CSELECT_B32_6]], [[S_MOV_B32_10]], implicit-def $scc
+; GCN-ISEL-NEXT: [[S_CSELECT_B32_7:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY75]], killed [[COPY74]], implicit $scc
+; GCN-ISEL-NEXT: [[COPY76:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U6]].sub1
+; GCN-ISEL-NEXT: [[COPY77:%[0-9]+]]:sreg_32 = COPY [[S_ADD_U7]].sub1
+; GCN-ISEL-NEXT: [[S_CSELECT_B32_8:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[COPY77]], killed [[COPY76]], implicit $scc
; GCN-ISEL-NEXT: [[S_SUB_C4:%[0-9]+]]:sreg_32, [[S_SUB_C5:%[0-9]+]]:sreg_64_xexec = S_SUB_CO_PSEUDO [[COPY60]], [[S_ADD_I32_8]], [[S_USUBO1]], implicit-def dead $scc
-; GCN-ISEL-NEXT: S_CMP_GE_U32 [[S_SUB_C4]], [[COPY22]], implicit-def $scc
+; GCN-ISEL-NEXT: [[COPY78:%[0-9]+]]:sreg_32 = COPY killed [[S_SUB_C4]]
+; GCN-ISEL-NEXT: S_CMP_GE_U32 [[COPY78]], [[COPY22]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_9:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
-; GCN-ISEL-NEXT: S_CMP_GE_U32 [[S_USUBO]], [[COPY21]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_GE_U32 [[COPY72]], [[COPY21]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_10:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_MOV_B32_11]], [[S_MOV_B32_10]], implicit $scc
-; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[S_SUB_C4]], [[COPY22]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_EQ_U32 [[COPY78]], [[COPY22]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_11:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_10]], killed [[S_CSELECT_B32_9]], implicit $scc
-; GCN-ISEL-NEXT: [[COPY77:%[0-9]+]]:sreg_32 = COPY killed [[S_CSELECT_B32_11]]
-; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[COPY77]], [[S_MOV_B32_10]], implicit-def $scc
+; GCN-ISEL-NEXT: S_CMP_LG_U32 killed [[S_CSELECT_B32_11]], [[S_MOV_B32_10]], implicit-def $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_12:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_8]], [[COPY68]], implicit $scc
; GCN-ISEL-NEXT: [[S_CSELECT_B32_13:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_CSELECT_B32_7]], [[COPY69]], implicit $scc
; GCN-ISEL-NEXT: [[REG_SEQUENCE23:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_CSELECT_B32_13]], %subreg.sub0, killed [[S_CSELECT_B32_12]], %subreg.sub1
; GCN-ISEL-NEXT: [[S_MOV_B64_4:%[0-9]+]]:sreg_64 = S_MOV_B64 0
-; GCN-ISEL-NEXT: [[COPY78:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE23]]
+; GCN-ISEL-NEXT: [[COPY79:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE23]]
; GCN-ISEL-NEXT: S_BRANCH %bb.1
; GCN-ISEL-NEXT: {{ $}}
; GCN-ISEL-NEXT: bb.4..split:
; GCN-ISEL-NEXT: [[PHI2:%[0-9]+]]:sreg_64 = PHI [[PHI]], %bb.1, [[COPY20]], %bb.2
-; GCN-ISEL-NEXT: [[COPY79:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub1
-; GCN-ISEL-NEXT: [[COPY80:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub0
-; GCN-ISEL-NEXT: [[REG_SEQUENCE24:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[COPY80]], %subreg.sub0, killed [[COPY79]], %subreg.sub1
-; GCN-ISEL-NEXT: [[COPY81:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub1
-; GCN-ISEL-NEXT: [[COPY82:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub0
+; GCN-ISEL-NEXT: [[COPY80:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub1
+; GCN-ISEL-NEXT: [[COPY81:%[0-9]+]]:sreg_32 = COPY [[COPY7]].sub0
+; GCN-ISEL-NEXT: [[REG_SEQUENCE24:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[COPY81]], %subreg.sub0, killed [[COPY80]], %subreg.sub1
+; GCN-ISEL-NEXT: [[COPY82:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub1
+; GCN-ISEL-NEXT: [[COPY83:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE24]].sub0
; GCN-ISEL-NEXT: [[S_MOV_B32_12:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GCN-ISEL-NEXT: [[S_MOV_B32_13:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
-; GCN-ISEL-NEXT: [[REG_SEQUENCE25:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY82]], %subreg.sub0, killed [[COPY81]], %subreg.sub1, killed [[S_MOV_B32_13]], %subreg.sub2, killed [[S_MOV_B32_12]], %subreg.sub3
-; GCN-ISEL-NEXT: [[COPY83:%[0-9]+]]:vreg_64 = COPY [[PHI2]]
-; GCN-ISEL-NEXT: BUFFER_STORE_DWORDX2_OFFSET [[COPY83]], killed [[REG_SEQUENCE25]], 0, 0, 0, 0, implicit $exec :: (store (s64) into %ir.15, addrspace 1)
+; GCN-ISEL-NEXT: [[REG_SEQUENCE25:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY83]], %subreg.sub0, killed [[COPY82]], %subreg.sub1, killed [[S_MOV_B32_13]], %subreg.sub2, killed [[S_MOV_B32_12]], %subreg.sub3
+; GCN-ISEL-NEXT: [[COPY84:%[0-9]+]]:vreg_64 = COPY [[PHI2]]
+; GCN-ISEL-NEXT: BUFFER_STORE_DWORDX2_OFFSET [[COPY84]], killed [[REG_SEQUENCE25]], 0, 0, 0, 0, implicit $exec :: (store (s64) into %ir.15, addrspace 1)
; GCN-ISEL-NEXT: S_ENDPGM 0
%result = udiv i64 %x, %y
store i64 %result, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
index 3d88221af213b..98a0d57708288 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
@@ -14,12 +14,11 @@ define amdgpu_kernel void @uniform_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY2]], %subreg.sub0, killed [[COPY1]], %subreg.sub1, killed [[S_MOV_B32_1]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
+ ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LOAD_DWORD_IMM]]
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 16
- ; GCN-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
- ; GCN-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LSHR_B32_]]
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY3]], implicit-def dead $scc
- ; GCN-NEXT: S_CMP_EQ_U32 killed [[S_AND_B32_]], 1, implicit-def $scc
+ ; GCN-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], killed [[S_MOV_B32_2]], implicit-def dead $scc
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 65536, [[COPY3]], implicit-def dead $scc
+ ; GCN-NEXT: S_CMP_LG_U32 killed [[S_AND_B32_]], 0, implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $scc
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN-NEXT: S_CMP_LT_I32 killed [[S_LSHL_B32_]], killed [[S_MOV_B32_3]], implicit-def $scc
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-e5m3fnu.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-e5m3fnu.ll
index 88c1685cc01fc..c1fae3b386c4a 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-e5m3fnu.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-e5m3fnu.ll
@@ -115,28 +115,31 @@ define i8 @to_e5m3fnu_dynamic(float %x) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v0
+; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0
; CHECK-NEXT: s_mov_b32 s4, 0x7fffff
; CHECK-NEXT: v_sub_nc_u32_e32 v2, 7, v1
-; CHECK-NEXT: v_and_or_b32 v4, v3, s4, 0x800000
-; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v3
-; CHECK-NEXT: v_bfe_u32 v9, v3, 20, 3
-; CHECK-NEXT: v_lshrrev_b32_e32 v3, 19, v3
+; CHECK-NEXT: v_and_or_b32 v6, v4, s4, 0x800000
+; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v4
+; CHECK-NEXT: v_bfe_u32 v9, v4, 20, 3
+; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4
; CHECK-NEXT: v_min_u32_e32 v2, 31, v2
-; CHECK-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
-; CHECK-NEXT: v_lshrrev_b32_e32 v7, v2, v4
-; CHECK-NEXT: v_bfe_u32 v6, v4, 0, v5
-; CHECK-NEXT: v_lshrrev_b32_e32 v4, v5, v4
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_sub_nc_u32_e64 v3, v2, 1 clamp
+; CHECK-NEXT: v_lshrrev_b32_e32 v7, v2, v6
+; CHECK-NEXT: v_lshlrev_b32_e64 v5, v3, 1
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; CHECK-NEXT: v_and_b32_e32 v5, v6, v5
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; CHECK-NEXT: v_and_or_b32 v5, v7, 1, v6
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: v_and_b32_e32 v4, v4, v5
-; CHECK-NEXT: v_and_or_b32 v5, v9, 1, v6
-; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
; CHECK-NEXT: v_and_b32_e32 v3, v3, v5
+; CHECK-NEXT: v_and_or_b32 v5, v9, 1, v6
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_and_b32_e32 v2, v2, v3
+; CHECK-NEXT: v_and_b32_e32 v3, v4, v5
; CHECK-NEXT: v_add_nc_u32_e32 v2, v7, v2
; CHECK-NEXT: v_add_nc_u32_e32 v3, v9, v3
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
index b9ac9dce0696c..a35dd84b3d937 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
@@ -26,58 +26,57 @@ define i8 @to_fp8_f16(half %x) {
; GFX950-LABEL: to_fp8_f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v3, v0
-; GFX950-NEXT: v_sub_u16_e32 v4, 2, v3
; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
-; GFX950-NEXT: s_movk_i32 s0, 0x400
-; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
-; GFX950-NEXT: v_min_u16_e32 v4, 15, v4
-; GFX950-NEXT: v_bitop3_b16 v2, v1, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v7, v4, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v5, v4, v2
-; GFX950-NEXT: v_lshrrev_b16_e32 v2, v7, v2
-; GFX950-NEXT: v_lshlrev_b16_e64 v7, v7, 1
-; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v1
-; GFX950-NEXT: v_add_u16_e32 v7, -1, v7
-; GFX950-NEXT: v_bitop3_b16 v7, v8, v7, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
-; GFX950-NEXT: v_and_b32_e32 v6, 1, v5
-; GFX950-NEXT: s_movk_i32 s0, 0x80
-; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v2, v7, v6 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, 7, v8
-; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX950-NEXT: v_add_u16_e32 v2, v5, v2
+; GFX950-NEXT: v_and_b32_e32 v3, 0x3ff, v1
+; GFX950-NEXT: v_and_b32_e32 v6, 63, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, 7, v3
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v5, 1, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v6, v5 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v4, v2
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
-; GFX950-NEXT: v_and_b32_sdwa v5, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v5, v4
+; GFX950-NEXT: v_sub_u16_e32 v5, 2, v5
+; GFX950-NEXT: v_min_u16_e32 v5, 15, v5
+; GFX950-NEXT: v_sub_u16_e64 v8, v5, 1 clamp
+; GFX950-NEXT: v_add_u16_e32 v4, 6, v4
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v8, 1
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v5, v2, v4 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v4, 6, v1
-; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v1, v4, v1, v7 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v4
+; GFX950-NEXT: v_and_b32_sdwa v7, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v6 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v6, 0x3ff
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v9, s0 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v1, v1, s0, v6 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v5, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, v8, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_or_b32_e32 v3, v3, v6
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v3 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v1, v6, v1
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v3, v3, v4
-; GFX950-NEXT: v_add_u16_e32 v3, 6, v3
; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v4, 3, v3
-; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v4 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v7, v1, v3 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v4
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
@@ -218,112 +217,108 @@ define <2 x i8> @to_fp8_v2f16(<2 x half> %x) {
; GFX950-LABEL: to_fp8_v2f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v4, v0
-; GFX950-NEXT: v_sub_u16_e32 v5, 2, v4
; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
-; GFX950-NEXT: s_movk_i32 s0, 0x400
-; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_and_b32_e32 v3, 0x3ff, v1
+; GFX950-NEXT: v_and_b32_e32 v6, 63, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, 7, v3
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v5, 1, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v6, v5 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v4, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v5, v4
+; GFX950-NEXT: v_sub_u16_e32 v5, 2, v5
; GFX950-NEXT: v_min_u16_e32 v5, 15, v5
-; GFX950-NEXT: v_bitop3_b16 v3, v1, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v8, v5, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, v5, v3
-; GFX950-NEXT: v_lshrrev_b16_e32 v3, v8, v3
-; GFX950-NEXT: v_lshlrev_b16_e64 v8, v8, 1
-; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v1
-; GFX950-NEXT: v_add_u16_e32 v8, -1, v8
-; GFX950-NEXT: v_bitop3_b16 v8, v9, v8, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
-; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX950-NEXT: s_movk_i32 s1, 0x80
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v3, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_sub_u16_e64 v9, v5, 1 clamp
+; GFX950-NEXT: v_add_u16_e32 v4, 6, v4
+; GFX950-NEXT: v_lshlrev_b16_e64 v10, v9, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v4
+; GFX950-NEXT: v_and_b32_sdwa v7, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s1, 0x400
+; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
+; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v6 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v6, 0x3ff
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v10, s1 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v1, v1, s1, v6 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v5, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, v9, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, 7, v9
-; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX950-NEXT: v_add_u16_e32 v3, v6, v3
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: v_and_b32_sdwa v6, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v5 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v5, 6, v1
-; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v8 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v1, v7, v1
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX950-NEXT: v_and_b32_sdwa v10, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v4, v4, v5
-; GFX950-NEXT: v_add_u16_e32 v4, 6, v4
+; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v3 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v1, v8, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: s_movk_i32 s0, 0xff
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v5, 3, v4
-; GFX950-NEXT: v_bitop3_b16 v1, v6, v1, v5 bitop3:0xfe
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v7, v1, v3 bitop3:0xfe
; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v4
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_frexp_mant_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_e32 v5, 0x3ff, v3
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
-; GFX950-NEXT: v_bitop3_b16 v2, v4, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v4
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX950-NEXT: v_sub_u16_e32 v6, 2, v5
-; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
-; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v2
-; GFX950-NEXT: v_lshrrev_b16_e32 v2, v9, v2
-; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
-; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
-; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
+; GFX950-NEXT: v_and_b32_e32 v9, 63, v3
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 7, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, 6, v3
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: s_movk_i32 s0, 0xff
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_bitop3_b16 v3, v3, s1, v6 bitop3:0xec
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v2, v9, v8 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v10
-; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
-; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX950-NEXT: v_add_u16_e32 v2, v7, v2
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
-; GFX950-NEXT: v_lshrrev_b32_e32 v7, 31, v0
-; GFX950-NEXT: v_lshlrev_b16_e32 v7, 7, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v6 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v4
-; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v6, v4, v9 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v4, v8, v4
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
-; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v6, 2, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v8, v7
+; GFX950-NEXT: v_add_u16_e32 v7, 6, v7
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
-; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v6 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v7
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v9 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v11, v9, 1
+; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v11, s1 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v6, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v9, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_or_b32_e32 v5, v5, v8
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v5 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v3, v8, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v10, v3, v5 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX950-NEXT: v_mov_b32_e32 v4, 0
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v0, 8, v2
; GFX950-NEXT: v_bitop3_b16 v0, v1, v0, s0 bitop3:0xec
; GFX950-NEXT: v_and_b32_e32 v1, 0xff, v2
@@ -542,211 +537,205 @@ define <3 x i8> @to_fp8_v3f16(<3 x half> %x) {
; GFX950-LABEL: to_fp8_v3f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
-; GFX950-NEXT: v_sub_u16_e32 v6, 2, v5
; GFX950-NEXT: v_frexp_mant_f16_e32 v3, v0
-; GFX950-NEXT: s_movk_i32 s0, 0x400
-; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_and_b32_e32 v4, 0x3ff, v3
+; GFX950-NEXT: v_and_b32_e32 v7, 63, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 7, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v6, 1, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v7, v6 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v5, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v6, v5
+; GFX950-NEXT: v_sub_u16_e32 v6, 2, v6
; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
-; GFX950-NEXT: v_bitop3_b16 v4, v3, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v4
-; GFX950-NEXT: v_lshrrev_b16_e32 v4, v9, v4
-; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
-; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v3
-; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
-; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX950-NEXT: s_movk_i32 s1, 0x80
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_sub_u16_e64 v10, v6, 1 clamp
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v11, v10, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v5
+; GFX950-NEXT: v_and_b32_sdwa v8, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s1, 0x400
+; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_bitop3_b16 v7, v8, v2, v7 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v11, s1 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v3, v3, s1, v2 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v6, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v10, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v10
-; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
-; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: v_and_b32_sdwa v7, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_movk_i32 s2, 0xff
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v6 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v3
-; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v9 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v3, v8, v3
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_or_b32_e32 v4, v4, v9
+; GFX950-NEXT: v_and_b32_sdwa v11, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
-; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v4 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v3, v9, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: s_movk_i32 s2, 0xff
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
-; GFX950-NEXT: v_bitop3_b16 v3, v7, v3, v6 bitop3:0xfe
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v8, v3, v4 bitop3:0xfe
; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
; GFX950-NEXT: v_frexp_mant_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v6, v5, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX950-NEXT: v_and_b32_e32 v10, 63, v5
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
-; GFX950-NEXT: v_and_b32_e32 v12, 0x3ff, v5
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v7, vcc
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v8, 2, v7
-; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
-; GFX950-NEXT: v_sub_u16_e64 v11, v8, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, v11, v6
-; GFX950-NEXT: v_lshlrev_b16_e64 v11, v11, 1
-; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_and_b32_e32 v7, 0x3ff, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v8, vcc
; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; GFX950-NEXT: v_bitop3_b16 v11, v12, v11, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v7
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v6, v11, v10 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v12
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
-; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v9, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_bitop3_b16 v5, v5, s1, v2 bitop3:0xec
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v8, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v9, 31, v0
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 7, v9
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v9, v8
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v9
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v12, 1
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v13, s1 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v8 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v5
-; GFX950-NEXT: v_and_b32_e32 v5, 63, v5
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v11 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 3, v8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v12, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v7 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v5, v10, v5
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v7, v7, v8
-; GFX950-NEXT: v_add_u16_e32 v7, 6, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v7
-; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v8 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v7
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v8, v1
+; GFX950-NEXT: v_and_b32_sdwa v12, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v11, v5, v7 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX950-NEXT: v_mov_b32_e32 v6, 0
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v6 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v5, 8, v0
; GFX950-NEXT: v_bitop3_b16 v0, v4, v5, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v1
-; GFX950-NEXT: v_bitop3_b16 v7, v4, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
-; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
-; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v4
-; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
-; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v4
+; GFX950-NEXT: v_and_b32_e32 v11, 63, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v7, v9, v7
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
-; GFX950-NEXT: v_and_b32_sdwa v10, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v1
+; GFX950-NEXT: v_bitop3_b16 v4, v4, s1, v2 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v10, v9
+; GFX950-NEXT: v_sub_u16_e32 v10, 2, v10
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v13, 1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v14, s1 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v4
-; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v12 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v12, v7, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_or_b32_e32 v8, v8, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v13, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v8 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v4, v11, v4
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_and_b32_sdwa v13, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v9 bitop3:0xfe
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v12, v4, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
-; GFX950-NEXT: v_bitop3_b16 v2, v7, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v2
-; GFX950-NEXT: v_lshrrev_b16_e32 v2, v12, v2
-; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
-; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v7
-; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v7
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
-; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_and_b32_e32 v12, 63, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v9
; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v7
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v2, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v8, v10, v8
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v8
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v2, v7, s1, v2 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v11, v10
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_sub_u16_e32 v7, 2, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v10
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_bitop3_b16 v8, v13, v8, v12 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e64 v12, v7, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v12, 1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, s1 bitop3:0xc8
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX950-NEXT: v_add_u16_e32 v2, v10, v2
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
-; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v1
-; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v7
-; GFX950-NEXT: v_and_b32_e32 v7, 63, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v7, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v12, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v9, v7, v12 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v7, v11, v7
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v9 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v2, v11, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v13, v2, v7 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v6 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v13, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -1110,211 +1099,205 @@ define <4 x i8> @to_fp8_v4f16(<4 x half> %x) {
; GFX950-LABEL: to_fp8_v4f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
-; GFX950-NEXT: v_sub_u16_e32 v6, 2, v5
; GFX950-NEXT: v_frexp_mant_f16_e32 v3, v0
-; GFX950-NEXT: s_movk_i32 s0, 0x400
-; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_and_b32_e32 v4, 0x3ff, v3
+; GFX950-NEXT: v_and_b32_e32 v7, 63, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 7, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v6, 1, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v7, v6 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v5, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v6, v5
+; GFX950-NEXT: v_sub_u16_e32 v6, 2, v6
; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
-; GFX950-NEXT: v_bitop3_b16 v4, v3, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v4
-; GFX950-NEXT: v_lshrrev_b16_e32 v4, v9, v4
-; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
-; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v3
-; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
-; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX950-NEXT: s_movk_i32 s1, 0x80
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_sub_u16_e64 v10, v6, 1 clamp
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v11, v10, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v5
+; GFX950-NEXT: v_and_b32_sdwa v8, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s1, 0x400
+; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_bitop3_b16 v7, v8, v2, v7 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v11, s1 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v3, v3, s1, v2 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v6, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v10, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v10
-; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
-; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: v_and_b32_sdwa v7, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_movk_i32 s2, 0xff
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v6 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v3
-; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v9 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v3, v8, v3
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_or_b32_e32 v4, v4, v9
+; GFX950-NEXT: v_and_b32_sdwa v11, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
-; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v4 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v3, v9, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: s_movk_i32 s2, 0xff
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
-; GFX950-NEXT: v_bitop3_b16 v3, v7, v3, v6 bitop3:0xfe
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v8, v3, v4 bitop3:0xfe
; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
; GFX950-NEXT: v_frexp_mant_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v6, v5, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX950-NEXT: v_and_b32_e32 v10, 63, v5
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
-; GFX950-NEXT: v_and_b32_e32 v12, 0x3ff, v5
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v7, vcc
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v8, 2, v7
-; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
-; GFX950-NEXT: v_sub_u16_e64 v11, v8, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, v11, v6
-; GFX950-NEXT: v_lshlrev_b16_e64 v11, v11, 1
-; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_and_b32_e32 v7, 0x3ff, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v8, vcc
; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; GFX950-NEXT: v_bitop3_b16 v11, v12, v11, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v7
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v6, v11, v10 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v12
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
-; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v9, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_bitop3_b16 v5, v5, s1, v2 bitop3:0xec
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v8, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v9, 31, v0
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 7, v9
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v9, v8
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v9
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v12, 1
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v13, s1 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v8 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v5
-; GFX950-NEXT: v_and_b32_e32 v5, 63, v5
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v11 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 3, v8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v12, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v7 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v5, v10, v5
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v7, v7, v8
-; GFX950-NEXT: v_add_u16_e32 v7, 6, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v7
-; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v8 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v7
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v8, v1
+; GFX950-NEXT: v_and_b32_sdwa v12, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v11, v5, v7 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX950-NEXT: v_mov_b32_e32 v6, 0
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v6 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v5, 8, v0
; GFX950-NEXT: v_bitop3_b16 v0, v4, v5, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v1
-; GFX950-NEXT: v_bitop3_b16 v7, v4, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
-; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
-; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v4
-; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
-; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v4
+; GFX950-NEXT: v_and_b32_e32 v11, 63, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v7, v9, v7
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
-; GFX950-NEXT: v_and_b32_sdwa v10, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v1
+; GFX950-NEXT: v_bitop3_b16 v4, v4, s1, v2 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v10, v9
+; GFX950-NEXT: v_sub_u16_e32 v10, 2, v10
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v13, 1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v14, s1 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v4
-; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v12 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v12, v7, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_or_b32_e32 v8, v8, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v13, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v8 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v4, v11, v4
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_and_b32_sdwa v13, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v9 bitop3:0xfe
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v12, v4, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
-; GFX950-NEXT: v_bitop3_b16 v2, v7, s0, v2 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v2
-; GFX950-NEXT: v_lshrrev_b16_e32 v2, v12, v2
-; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
-; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v7
-; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v7
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
-; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_and_b32_e32 v12, 63, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v9
; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v7
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v2, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v8, v10, v8
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v8
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v2, v7, s1, v2 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v11, v10
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_sub_u16_e32 v7, 2, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v10
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_bitop3_b16 v8, v13, v8, v12 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e64 v12, v7, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v12, 1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, s1 bitop3:0xc8
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX950-NEXT: v_add_u16_e32 v2, v10, v2
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
-; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v1
-; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v7
-; GFX950-NEXT: v_and_b32_e32 v7, 63, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v7, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v12, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v9, v7, v12 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v7, v11, v7
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v9 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v2, v11, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v13, v2, v7 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v6 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v13, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll
index e97e1d2a8dd80..b74157892cd71 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll
@@ -11,27 +11,29 @@ define i8 @to_fp8_f32(float %x) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
-; GFX942-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX942-NEXT: v_sub_u32_e32 v4, 15, v3
-; GFX942-NEXT: v_and_b32_e32 v2, 0x7fffff, v1
; GFX942-NEXT: v_min_u32_e32 v4, 31, v4
-; GFX942-NEXT: v_or_b32_e32 v2, 0x800000, v2
+; GFX942-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX942-NEXT: v_sub_u32_e64 v6, v4, 1 clamp
-; GFX942-NEXT: v_bfe_u32 v7, v2, 0, v6
+; GFX942-NEXT: v_and_b32_e32 v2, 0x7fffff, v1
+; GFX942-NEXT: v_lshlrev_b32_e64 v7, v6, 1
+; GFX942-NEXT: v_or_b32_e32 v2, 0x800000, v2
+; GFX942-NEXT: v_add_u32_e32 v7, -1, v7
+; GFX942-NEXT: v_and_b32_e32 v7, v2, v7
; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX942-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; GFX942-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX942-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX942-NEXT: v_and_or_b32 v7, v5, 1, v7
-; GFX942-NEXT: v_and_b32_e32 v2, v2, v7
+; GFX942-NEXT: v_or_b32_e32 v7, v7, v5
; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX942-NEXT: v_and_b32_e32 v2, v2, v7
; GFX942-NEXT: s_movk_i32 s0, 0x80
-; GFX942-NEXT: v_bfe_u32 v6, v1, 20, 3
-; GFX942-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX942-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX942-NEXT: v_and_b32_e32 v2, v4, v2
; GFX942-NEXT: v_add_u32_e32 v2, v5, v2
; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
; GFX942-NEXT: v_and_b32_sdwa v5, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_bfe_u32 v6, v1, 20, 3
; GFX942-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX942-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
; GFX942-NEXT: v_or3_b32 v2, v5, v4, v2
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
index cc038e9cb65ea..420061d6d04f4 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
@@ -916,46 +916,49 @@ define i4 @to_fp4_f32(float %x) {
; GFX950-LABEL: to_fp4_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_sub_u32_e32 v2, 23, v1
-; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
-; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
-; GFX950-NEXT: v_or_b32_e32 v4, 0x800000, v4
-; GFX950-NEXT: v_sub_u32_e64 v6, v2, 1 clamp
-; GFX950-NEXT: v_lshrrev_b32_e32 v7, v6, v4
-; GFX950-NEXT: v_bfe_u32 v6, v4, 0, v6
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX950-NEXT: v_bfe_u32 v5, v4, v2, 1
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v5, v7, v6, v5 bitop3:0xe0
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
+; GFX950-NEXT: v_sub_u32_e32 v5, 23, v4
+; GFX950-NEXT: v_min_u32_e32 v5, 31, v5
+; GFX950-NEXT: v_sub_u32_e64 v7, v5, 1 clamp
+; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX950-NEXT: v_lshlrev_b32_e64 v8, v7, 1
+; GFX950-NEXT: v_and_b32_e32 v2, 0x7fffff, v1
+; GFX950-NEXT: s_mov_b32 s0, 0x800000
+; GFX950-NEXT: v_add_u32_e32 v8, -1, v8
+; GFX950-NEXT: v_or_b32_e32 v3, 0x800000, v2
+; GFX950-NEXT: v_bitop3_b32 v2, v2, v8, s0 bitop3:0xc8
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v4
-; GFX950-NEXT: v_and_b32_e32 v6, 0x1fffff, v3
-; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX950-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v6, v5, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v3, v7, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v2, v5, v3, v2 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v2, v6, v2
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 1, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v5, 28, v0
-; GFX950-NEXT: v_and_b32_e32 v5, 8, v5
+; GFX950-NEXT: v_and_b32_e32 v6, 0x1fffff, v1
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 2, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 2, vcc
+; GFX950-NEXT: v_and_b32_e32 v5, 8, v5
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX950-NEXT: v_or3_b32 v2, v5, v4, v2
-; GFX950-NEXT: v_lshrrev_b32_e32 v4, 21, v3
+; GFX950-NEXT: v_or3_b32 v2, v5, v3, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v3, 21, v1
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_bfe_u32 v3, v3, 22, 1
-; GFX950-NEXT: v_bitop3_b32 v4, v4, v6, v3 bitop3:0xe0
-; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 1, v3
+; GFX950-NEXT: v_bfe_u32 v1, v1, 22, 1
+; GFX950-NEXT: v_bitop3_b32 v3, v3, v6, v1 bitop3:0xe0
+; GFX950-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 1, v1
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX950-NEXT: v_lshlrev_b32_e32 v4, 1, v1
-; GFX950-NEXT: v_or3_b32 v3, v5, v4, v3
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX950-NEXT: v_lshlrev_b32_e32 v4, 1, v3
+; GFX950-NEXT: v_or3_b32 v1, v5, v4, v1
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc
@@ -969,57 +972,59 @@ define i4 @to_fp4_f32(float %x) {
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 23, v1
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
-; GFX1200-NEXT: v_bfe_u32 v8, v3, 22, 1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_and_or_b32 v6, v4, s0, 0x800000
+; GFX1200-NEXT: v_and_b32_e32 v7, 0x1fffff, v4
+; GFX1200-NEXT: v_bfe_u32 v8, v4, 22, 1
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 21, v4
; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
-; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, v2, v4
-; GFX1200-NEXT: v_bfe_u32 v6, v4, 0, v5
-; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_sub_nc_u32_e64 v3, v2, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, v2, v6
+; GFX1200-NEXT: v_lshlrev_b32_e64 v5, v3, 1
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, v3, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1200-NEXT: v_and_b32_e32 v5, v6, v5
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v6
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
-; GFX1200-NEXT: v_and_b32_e32 v7, 0x1fffff, v3
-; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 21, v3
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1200-NEXT: v_or_b32_e32 v5, v5, v9
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b32_e32 v3, v3, v5
; GFX1200-NEXT: v_or_b32_e32 v6, v7, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 28, v0
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_and_b32_e32 v4, v4, v6
+; GFX1200-NEXT: v_and_b32_e32 v2, v2, v3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_add_nc_u32_e32 v3, v8, v4
; GFX1200-NEXT: v_add_nc_u32_e32 v2, v9, v2
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_b32_e32 v4, 8, v4
-; GFX1200-NEXT: v_and_b32_e32 v3, v3, v6
-; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_add_nc_u32_e32 v3, v8, v3
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
-; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 28, v0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
-; GFX1200-NEXT: v_or3_b32 v2, v4, v5, v2
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
; GFX1200-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX1200-NEXT: v_and_b32_e32 v4, 8, v4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or3_b32 v2, v4, v5, v2
; GFX1200-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
@@ -1034,43 +1039,51 @@ define i4 @to_fp4_f32(float %x) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX1250-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX1250-NEXT: s_mov_b32 s0, 0x7fffff
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX1250-NEXT: v_dual_sub_nc_u32 v2, 23, v1 :: v_dual_lshrrev_b32 v6, 21, v3
-; GFX1250-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
-; GFX1250-NEXT: v_and_b32_e32 v8, 0x1fffff, v3
-; GFX1250-NEXT: v_bfe_u32 v3, v3, 22, 1
+; GFX1250-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_sub_nc_u32_e32 v2, 23, v1
+; GFX1250-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
+; GFX1250-NEXT: v_and_b32_e32 v8, 0x1fffff, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_min_u32_e32 v2, 31, v2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
-; GFX1250-NEXT: v_bfe_u32 v9, v4, v2, 1
-; GFX1250-NEXT: v_bfe_u32 v7, v4, 0, v5
-; GFX1250-NEXT: v_dual_lshrrev_b32 v5, v5, v4 :: v_dual_lshrrev_b32 v4, v2, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
-; GFX1250-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1250-NEXT: v_or_b32_e32 v7, 0x800000, v6
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_sub_nc_u32_e64 v3, v2, 1 clamp
+; GFX1250-NEXT: v_lshrrev_b32_e32 v9, v2, v7
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_lshlrev_b32_e64 v5, v3, 1
+; GFX1250-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_bitop3_b32 v5, v6, v5, 0x800000 bitop3:0xc8
+; GFX1250-NEXT: v_lshrrev_b32_e32 v6, 21, v4
+; GFX1250-NEXT: v_bfe_u32 v4, v4, 22, 1
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
+; GFX1250-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX1250-NEXT: v_bitop3_b32 v5, v5, v7, v9 bitop3:0xe0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_dual_lshrrev_b32 v3, v3, v7 :: v_dual_bitop2_b32 v5, v5, v9 bitop3:0x54
; GFX1250-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_bitop3_b32 v6, v6, v8, v3 bitop3:0xe0
-; GFX1250-NEXT: v_dual_cndmask_b32 v2, 0, v5 :: v_dual_add_nc_u32 v3, v3, v6
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_dual_add_nc_u32 v2, v4, v2 :: v_dual_lshrrev_b32 v4, 28, v0
+; GFX1250-NEXT: v_bitop3_b32 v6, v6, v8, v4 bitop3:0xe0
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_bitop3_b32 v2, v2, v3, v5 bitop3:0x80
+; GFX1250-NEXT: v_dual_add_nc_u32 v3, v4, v6 :: v_dual_lshrrev_b32 v4, 28, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_add_nc_u32_e32 v2, v9, v2
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_and_b32_e32 v4, 8, v4
; GFX1250-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
-; GFX1250-NEXT: v_and_b32_e32 v4, 8, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1250-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
-; GFX1250-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_or3_b32 v2, v4, v5, v2
+; GFX1250-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1250-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
@@ -1086,43 +1099,51 @@ define i4 @to_fp4_f32(float %x) {
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX1310-NEXT: s_mov_b32 s0, 0x7fffff
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_dual_sub_nc_u32 v2, 23, v1 :: v_dual_lshrrev_b32 v6, 21, v3
-; GFX1310-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
-; GFX1310-NEXT: v_and_b32_e32 v8, 0x1fffff, v3
-; GFX1310-NEXT: v_bfe_u32 v3, v3, 22, 1
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_sub_nc_u32_e32 v2, 23, v1
+; GFX1310-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
+; GFX1310-NEXT: v_and_b32_e32 v8, 0x1fffff, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_min_u32_e32 v2, 31, v2
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
-; GFX1310-NEXT: v_bfe_u32 v9, v4, v2, 1
-; GFX1310-NEXT: v_bfe_u32 v7, v4, 0, v5
-; GFX1310-NEXT: v_dual_lshrrev_b32 v5, v5, v4 :: v_dual_lshrrev_b32 v4, v2, v4
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
-; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: v_or_b32_e32 v7, 0x800000, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_sub_nc_u32_e64 v3, v2, 1 clamp
+; GFX1310-NEXT: v_lshrrev_b32_e32 v9, v2, v7
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_lshlrev_b32_e64 v5, v3, 1
+; GFX1310-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b32 v5, v6, v5, 0x800000 bitop3:0xc8
+; GFX1310-NEXT: v_lshrrev_b32_e32 v6, 21, v4
+; GFX1310-NEXT: v_bfe_u32 v4, v4, 22, 1
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX1310-NEXT: v_bitop3_b32 v5, v5, v7, v9 bitop3:0xe0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_dual_lshrrev_b32 v3, v3, v7 :: v_dual_bitop2_b32 v5, v5, v9 bitop3:0x54
; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1310-NEXT: v_bitop3_b32 v6, v6, v8, v3 bitop3:0xe0
-; GFX1310-NEXT: v_dual_cndmask_b32 v2, 0, v5 :: v_dual_add_nc_u32 v3, v3, v6
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_dual_add_nc_u32 v2, v4, v2 :: v_dual_lshrrev_b32 v4, 28, v0
+; GFX1310-NEXT: v_bitop3_b32 v6, v6, v8, v4 bitop3:0xe0
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b32 v2, v2, v3, v5 bitop3:0x80
+; GFX1310-NEXT: v_dual_add_nc_u32 v3, v4, v6 :: v_dual_lshrrev_b32 v4, 28, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_add_nc_u32_e32 v2, v9, v2
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_and_b32_e32 v4, 8, v4
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
-; GFX1310-NEXT: v_and_b32_e32 v4, 8, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
-; GFX1310-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_or3_b32 v2, v4, v5, v2
+; GFX1310-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1310-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
@@ -1533,60 +1554,59 @@ define i8 @to_fp8_bf16(bfloat %x) {
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v0
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
; GFX950-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX950-NEXT: v_xor_b32_e32 v6, -1, v5
; GFX950-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7f, v2
+; GFX950-NEXT: v_and_b32_e32 v7, 7, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 4, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, 3, v2
+; GFX950-NEXT: v_and_b32_e32 v6, 1, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v7, v6 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v5, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
; GFX950-NEXT: s_movk_i32 s0, 0x80
-; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v6, v5
+; GFX950-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
-; GFX950-NEXT: v_bitop3_b16 v4, v2, s0, v3 bitop3:0xec
; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v4
-; GFX950-NEXT: v_lshrrev_b16_e32 v4, v9, v4
-; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
-; GFX950-NEXT: v_and_b32_e32 v10, 0x7f, v2
-; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
-; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v10, v9, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v5
; GFX950-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
+; GFX950-NEXT: v_bitop3_b16 v3, v0, v3, v7 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v7, 0x7f
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v10, s0 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v2, v2, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v6, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v9, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, 4, v10
-; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, 3, v2
-; GFX950-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v6, v2, v8 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v2, v7, v2
+; GFX950-NEXT: v_or_b32_e32 v4, v4, v8
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v6, v2, v4 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v2, v8, v2
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
-; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
-; GFX950-NEXT: v_bitop3_b16 v2, v0, v2, v6 bitop3:0xfe
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v0, v2, v4 bitop3:0xfe
; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_bf16:
@@ -1624,60 +1644,63 @@ define i8 @to_fp8_bf16(bfloat %x) {
; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, -1
; GFX1200-NEXT: v_lshrrev_b16 v2.l, 4, v2.l
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b16 v2.h, v3.h, v2.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b16 v3.l, v2.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, v1.l, v3.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_b16 v3.l, v4.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, v1.l, v3.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
; GFX1200-NEXT: v_and_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v1.l, v1.h, v3.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_mov_b16_e32 v4.l, v8.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, v2.h
-; GFX1200-NEXT: v_or_b16 v3.l, v4.l, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
-; GFX1200-NEXT: v_and_b16 v1.l, v1.h, v3.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, s0
-; GFX1200-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
+; GFX1200-NEXT: v_or_b16 v1.h, v4.l, v3.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v7.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b16 v1.l, v1.l, v1.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v0.h, v4.h, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v1.l, v6.l, v3.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, vcc_lo
+; GFX1200-NEXT: v_and_b16 v1.l, v4.l, v1.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v0.h, v3.l, v1.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v0.h
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v6.l, v4.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u16 v1.l, v1.l, 6
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s0
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, 0, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_lshlrev_b16 v2.h, 3, v1.l
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, 0, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.l
+; GFX1200-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX1200-NEXT: v_or_b16 v1.h, v0.l, v1.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b16 v2.h, v0.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b16 v0.h, v1.h, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_or_b16 v1.l, v2.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b16 v0.h, v1.l, v0.h, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v5
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
@@ -1685,73 +1708,72 @@ define i8 @to_fp8_bf16(bfloat %x) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x80
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; GFX1250-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v6
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
+; GFX1250-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v7
; GFX1250-TRUE16-NEXT: v_and_b16 v0.l, 0x80, v0.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_xor_b16 v1.l, v7.l, -1
+; GFX1250-TRUE16-NEXT: v_xor_b16 v1.l, v8.l, -1
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_min_u16 v1.l, v1.l, 15
-; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, 0x7f, v2.l
; GFX1250-TRUE16-NEXT: v_and_b16 v3.l, v2.l, 7
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, 0x7f, v2.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v4.h, 3, v2.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v1.h, v1.l, 1 clamp
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v4.h, 4, v2.h
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v4.l, 4, v2.h
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.h, v1.h, 1
-; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_and_b16 v5.l, v4.l, 1
; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v3.h, -1
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v2.l, v4.l, 0x7f bitop3:0xec
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v2.l, 3, v2.l
-; GFX1250-TRUE16-NEXT: v_and_b16 v4.l, v4.h, 1
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x80
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.h, v2.h, v3.l, 0x80 bitop3:0xc8
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v3.l, v1.l, v3.h
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v2.l, v5.l, v4.l bitop3:0xe0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v2.l, v3.h, 0x7f bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v4.h, v6.l, v5.l bitop3:0xe0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
-; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, v3.l, 1
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v2.l, v4.h, v2.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.h, v1.h, v2.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v2.h, v4.l, v3.l
; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
-; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v1.h, v4.l, v2.h bitop3:0xe0
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0, s0
-; GFX1250-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v7.l, v4.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, v1.l, v2.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_or_b16 v3.l, v3.l, v1.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.l, v3.l, v1.l
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, 6
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v2.l, v1.h, v3.l bitop3:0x80
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v8.l, v4.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.l, v1.l, v1.h
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, 6
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.h, 0, vcc_lo
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v1.l
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.l, 3, v0.h
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, vcc_lo
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.h, 0, 8, vcc_lo
; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v0.h
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v0.l, v1.h, v2.l bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v0.l, v1.l, v2.h bitop3:0xfe
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.l, vcc_lo
-; GFX1250-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v6
+; GFX1250-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v7, v7
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, s0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, vcc_lo
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -1765,61 +1787,61 @@ define i8 @to_fp8_bf16(bfloat %x) {
; GFX1250-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0x80, v0
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX1250-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, v1
-; GFX1250-FAKE16-NEXT: v_min_u16 v3, v3, 15
+; GFX1250-FAKE16-NEXT: v_xor_b32_e32 v4, -1, v2
+; GFX1250-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v1
+; GFX1250-FAKE16-NEXT: v_min_u16 v4, v4, 15
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0
; GFX1250-FAKE16-NEXT: s_movk_i32 s0, 0x80
-; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v5, v3, 1 clamp
+; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v6, v4, 1 clamp
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 0x7f, v4
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v9, v4, s0, 0x7f bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v3
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v8, 7, v4
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, v5, 1
-; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v10, 4, v6
-; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v4, 3, v4
-; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v12, v3, v9
-; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8
-; GFX1250-FAKE16-NEXT: v_add_nc_u16 v7, v7, -1
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v11, 1, v10
-; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v5, v5, v9
-; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v6, v7, 0x80 bitop3:0xc8
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 1, v12
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, v8, v11 bitop3:0xe0
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
-; GFX1250-FAKE16-NEXT: v_add_nc_u16 v4, v10, v4
-; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v5, v6, v7 bitop3:0xe0
-; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, v5, s0
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0x7f, v3
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 7, v3
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v10, 3, v3
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v3, s0, 0x7f bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v9, v6, 1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v8, 4, v5
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v4
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v9, v9, -1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v11, 1, v8
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v5, v9, 0x80 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v9, v4, v3
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v10, v7, v11 bitop3:0xe0
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v3, v6, v3
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v7, v8, v7
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1250-FAKE16-NEXT: v_add_nc_u16 v3, v12, v3
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, v5
-; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v7
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v5, v5, v9
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v6, v7, 0, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v4, v3, v5 bitop3:0x80
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, v7
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v3, v9, v3
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, 6
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 3, v2
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 3, v2
; GFX1250-FAKE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v0, v6, v4 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v0, v3, v5 bitop3:0xfe
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
; GFX1250-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX1250-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f, v0, vcc_lo
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -1836,61 +1858,61 @@ define i8 @to_fp8_bf16(bfloat %x) {
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX1310-NEXT: v_and_b32_e32 v0, 0x80, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v4, v1
-; GFX1310-NEXT: v_min_u16 v3, v3, 15
+; GFX1310-NEXT: v_xor_b32_e32 v4, -1, v2
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v3, v1
+; GFX1310-NEXT: v_min_u16 v4, v4, 15
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0
+; GFX1310-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0
; GFX1310-NEXT: s_movk_i32 s0, 0x80
-; GFX1310-NEXT: v_sub_nc_u16 v5, v3, 1 clamp
+; GFX1310-NEXT: v_sub_nc_u16 v6, v4, 1 clamp
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1310-NEXT: v_and_b32_e32 v6, 0x7f, v4
-; GFX1310-NEXT: v_bitop3_b16 v9, v4, s0, 0x7f bitop3:0xec
-; GFX1310-NEXT: v_cmp_ne_u16_e64 s0, 0, v3
-; GFX1310-NEXT: v_and_b32_e32 v8, 7, v4
-; GFX1310-NEXT: v_lshlrev_b16 v7, v5, 1
-; GFX1310-NEXT: v_lshrrev_b16 v10, 4, v6
-; GFX1310-NEXT: v_lshrrev_b16 v4, 3, v4
-; GFX1310-NEXT: v_lshrrev_b16 v12, v3, v9
-; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8
-; GFX1310-NEXT: v_add_nc_u16 v7, v7, -1
-; GFX1310-NEXT: v_and_b32_e32 v11, 1, v10
-; GFX1310-NEXT: v_lshrrev_b16 v5, v5, v9
-; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_bitop3_b16 v6, v6, v7, 0x80 bitop3:0xc8
-; GFX1310-NEXT: v_and_b32_e32 v7, 1, v12
-; GFX1310-NEXT: v_bitop3_b16 v4, v4, v8, v11 bitop3:0xe0
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
-; GFX1310-NEXT: v_add_nc_u16 v4, v10, v4
-; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4
-; GFX1310-NEXT: v_bitop3_b16 v5, v5, v6, v7 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cndmask_b32_e64 v3, 0, v5, s0
+; GFX1310-NEXT: v_and_b32_e32 v5, 0x7f, v3
+; GFX1310-NEXT: v_and_b32_e32 v7, 7, v3
+; GFX1310-NEXT: v_lshrrev_b16 v10, 3, v3
+; GFX1310-NEXT: v_bitop3_b16 v3, v3, s0, 0x7f bitop3:0xec
+; GFX1310-NEXT: v_lshlrev_b16 v9, v6, 1
+; GFX1310-NEXT: v_lshrrev_b16 v8, 4, v5
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7
+; GFX1310-NEXT: v_cmp_ne_u16_e64 s0, 0, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_add_nc_u16 v9, v9, -1
+; GFX1310-NEXT: v_and_b32_e32 v11, 1, v8
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b16 v5, v5, v9, 0x80 bitop3:0xc8
+; GFX1310-NEXT: v_lshrrev_b16 v9, v4, v3
+; GFX1310-NEXT: v_bitop3_b16 v7, v10, v7, v11 bitop3:0xe0
+; GFX1310-NEXT: v_lshrrev_b16 v3, v6, v3
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_add_nc_u16 v7, v8, v7
; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1310-NEXT: v_add_nc_u16 v3, v12, v3
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_add_nc_u16 v2, v2, v5
-; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v7
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_or_b32_e32 v5, v5, v9
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, v7, 0, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: v_bitop3_b16 v3, v4, v3, v5 bitop3:0x80
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_add_nc_u16 v2, v2, v7
+; GFX1310-NEXT: v_add_nc_u16 v3, v9, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_add_nc_u16 v2, v2, 6
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_lshlrev_b16 v4, 3, v2
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
-; GFX1310-NEXT: v_lshlrev_b16 v6, 3, v2
; GFX1310-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b16 v4, v0, v6, v4 bitop3:0xfe
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_bitop3_b16 v3, v0, v3, v5 bitop3:0xfe
-; GFX1310-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v0, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.bf16(bfloat %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
@@ -1903,45 +1925,46 @@ define i8 @to_e5m3fnu_f32(float %x) {
; GFX950-LABEL: to_e5m3fnu_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_sub_u32_e32 v2, 7, v1
-; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX950-NEXT: v_and_b32_e32 v5, 0x7ffff, v1
+; GFX950-NEXT: v_and_b32_e32 v3, 0x7fffff, v1
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v2, 19, v1
+; GFX950-NEXT: v_bfe_u32 v4, v3, 20, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v2, v2, v5, v4 bitop3:0xe0
+; GFX950-NEXT: v_bfe_u32 v1, v1, 20, 3
+; GFX950-NEXT: v_add_u32_e32 v1, v1, v2
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v1
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
+; GFX950-NEXT: s_mov_b32 s0, 0x800000
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v2, vcc
+; GFX950-NEXT: v_sub_u32_e32 v2, 7, v2
; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
-; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
-; GFX950-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX950-NEXT: v_sub_u32_e64 v7, v2, 1 clamp
-; GFX950-NEXT: v_lshrrev_b32_e32 v8, v7, v5
-; GFX950-NEXT: v_bfe_u32 v7, v5, 0, v7
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX950-NEXT: v_bfe_u32 v6, v5, v2, 1
-; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 1
-; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v6, v8, v7, v6 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b32_e64 v8, v7, 1
+; GFX950-NEXT: v_add_u32_e32 v8, -1, v8
+; GFX950-NEXT: v_or_b32_e32 v5, 0x800000, v3
+; GFX950-NEXT: v_bitop3_b32 v3, v3, v8, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v6, v2, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, v7, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v5
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX950-NEXT: v_add_u32_e32 v2, v2, v6
+; GFX950-NEXT: v_or_b32_e32 v3, v3, v6
+; GFX950-NEXT: v_lshl_or_b32 v1, v4, 3, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v2, v2, v5, v3 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v2, v6, v2
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
-; GFX950-NEXT: v_and_b32_e32 v6, 0x7ffff, v3
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX950-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX950-NEXT: v_lshrrev_b32_e32 v5, 19, v3
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v4, v5, v6, v4 bitop3:0xe0
-; GFX950-NEXT: v_bfe_u32 v3, v3, 20, 3
-; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 14, v1, vcc
-; GFX950-NEXT: v_lshl_or_b32 v3, v1, 3, v3
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 8, vcc
+; GFX950-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX950-NEXT: v_mov_b32_e32 v2, 0xff
; GFX950-NEXT: s_nop 0
@@ -1959,61 +1982,66 @@ define i8 @to_e5m3fnu_f32(float %x) {
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 7, v1
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
-; GFX1200-NEXT: v_and_b32_e32 v8, 0x7ffff, v3
-; GFX1200-NEXT: v_bfe_u32 v9, v3, 20, 3
-; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 19, v3
+; GFX1200-NEXT: v_and_or_b32 v6, v4, s0, 0x800000
+; GFX1200-NEXT: v_and_b32_e32 v8, 0x7ffff, v4
+; GFX1200-NEXT: v_bfe_u32 v9, v4, 20, 3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 19, v4
; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
-; GFX1200-NEXT: v_lshrrev_b32_e32 v7, v2, v4
-; GFX1200-NEXT: v_bfe_u32 v6, v4, 0, v5
-; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
+; GFX1200-NEXT: v_sub_nc_u32_e64 v3, v2, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, v2, v6
+; GFX1200-NEXT: v_lshlrev_b32_e64 v5, v3, 1
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, v3, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1200-NEXT: v_and_b32_e32 v5, v6, v5
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX1200-NEXT: v_and_or_b32 v5, v7, 1, v6
+; GFX1200-NEXT: v_or_b32_e32 v5, v5, v7
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
+; GFX1200-NEXT: v_and_b32_e32 v3, v3, v5
; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_dual_cndmask_b32 v2, 0, v4 :: v_dual_and_b32 v3, v3, v5
-; GFX1200-NEXT: v_add_nc_u32_e32 v2, v7, v2
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b32_e32 v2, v2, v3
+; GFX1200-NEXT: v_and_b32_e32 v3, v4, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_add_nc_u32_e32 v2, v7, v2
; GFX1200-NEXT: v_add_nc_u32_e32 v3, v9, v3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshl_or_b32 v3, v1, 3, v3
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
@@ -2039,50 +2067,54 @@ define i8 @to_e5m3fnu_f32(float %x) {
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_dual_sub_nc_u32 v3, 7, v1 :: v_dual_lshrrev_b32 v10, 19, v2
-; GFX1310-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
-; GFX1310-NEXT: v_and_b32_e32 v9, 0x7ffff, v2
-; GFX1310-NEXT: v_bfe_u32 v2, v2, 20, 3
-; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_or_b32_e32 v5, 0x800000, v4
-; GFX1310-NEXT: v_bfe_u32 v4, v4, 20, 1
-; GFX1310-NEXT: v_sub_nc_u32_e64 v6, v3, 1 clamp
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_bfe_u32 v8, v5, v3, 1
-; GFX1310-NEXT: v_bfe_u32 v7, v5, 0, v6
-; GFX1310-NEXT: v_dual_lshrrev_b32 v6, v6, v5 :: v_dual_lshrrev_b32 v5, v3, v5
+; GFX1310-NEXT: v_dual_sub_nc_u32 v2, 7, v1 :: v_dual_lshrrev_b32 v8, 19, v4
+; GFX1310-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
+; GFX1310-NEXT: v_and_b32_e32 v9, 0x7ffff, v4
+; GFX1310-NEXT: v_bfe_u32 v4, v4, 20, 3
+; GFX1310-NEXT: v_min_u32_e32 v2, 31, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_or_b32_e32 v7, 0x800000, v6
+; GFX1310-NEXT: v_sub_nc_u32_e64 v3, v2, 1 clamp
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshrrev_b32_e32 v10, v2, v7
+; GFX1310-NEXT: v_lshlrev_b32_e64 v5, v3, 1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1310-NEXT: v_bitop3_b32 v5, v6, v5, 0x800000 bitop3:0xc8
+; GFX1310-NEXT: v_bfe_u32 v6, v6, 20, 1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
-; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
-; GFX1310-NEXT: v_bitop3_b32 v6, v6, v7, v8 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1310-NEXT: v_bitop3_b32 v4, v10, v7, v4 bitop3:0xe0
-; GFX1310-NEXT: v_dual_cndmask_b32 v3, 0, v6 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_add_nc_u32_e32 v3, v5, v3
-; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v2
+; GFX1310-NEXT: v_dual_lshrrev_b32 v3, v3, v7 :: v_dual_bitop2_b32 v5, v5, v10 bitop3:0x54
+; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_bitop3_b32 v6, v8, v9, v6 bitop3:0xe0
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1310-NEXT: v_bitop3_b32 v2, v2, v3, v5 bitop3:0x80
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_add_nc_u32_e32 v3, v4, v6
+; GFX1310-NEXT: v_add_nc_u32_e32 v2, v10, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
-; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v2
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
-; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
-; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX1310-NEXT: v_lshl_or_b32 v2, v1, 3, v2
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, 8, s0
+; GFX1310-NEXT: v_lshl_or_b32 v3, v1, 3, v3
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M3FNU", metadata !"round.tonearest", i1 false)
@@ -2093,95 +2125,99 @@ define <2 x i8> @to_e5m3fnu_v2f32(<2 x float> %x) {
; GFX950-LABEL: to_e5m3fnu_v2f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
-; GFX950-NEXT: v_sub_u32_e32 v3, 7, v2
-; GFX950-NEXT: v_frexp_mant_f32_e32 v4, v1
+; GFX950-NEXT: v_frexp_mant_f32_e32 v2, v1
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7ffff, v2
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b32_e32 v3, 19, v2
+; GFX950-NEXT: v_bfe_u32 v5, v4, 20, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v3, v3, v6, v5 bitop3:0xe0
+; GFX950-NEXT: v_bfe_u32 v2, v2, 20, 3
+; GFX950-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
+; GFX950-NEXT: s_mov_b32 s0, 0x800000
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v5, vcc, 14, v3, vcc
+; GFX950-NEXT: v_sub_u32_e32 v3, 7, v3
; GFX950-NEXT: v_min_u32_e32 v3, 31, v3
-; GFX950-NEXT: v_and_b32_e32 v5, 0x7fffff, v4
-; GFX950-NEXT: v_or_b32_e32 v6, 0x800000, v5
; GFX950-NEXT: v_sub_u32_e64 v8, v3, 1 clamp
-; GFX950-NEXT: v_lshrrev_b32_e32 v9, v8, v6
-; GFX950-NEXT: v_bfe_u32 v8, v6, 0, v8
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; GFX950-NEXT: v_bfe_u32 v7, v6, v3, 1
-; GFX950-NEXT: v_bfe_u32 v5, v5, 20, 1
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v7, v9, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b32_e64 v9, v8, 1
+; GFX950-NEXT: v_add_u32_e32 v9, -1, v9
+; GFX950-NEXT: v_or_b32_e32 v6, 0x800000, v4
+; GFX950-NEXT: v_bitop3_b32 v4, v4, v9, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-NEXT: v_lshrrev_b32_e32 v7, v3, v6
+; GFX950-NEXT: v_lshrrev_b32_e32 v6, v8, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX950-NEXT: v_lshrrev_b32_e32 v3, v3, v6
-; GFX950-NEXT: s_movk_i32 s0, 0xff
-; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX950-NEXT: v_add_u32_e32 v3, v3, v7
+; GFX950-NEXT: v_or_b32_e32 v4, v4, v7
+; GFX950-NEXT: v_lshl_or_b32 v2, v5, 3, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v3, v3, v6, v4 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v3, v7, v3
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
-; GFX950-NEXT: v_and_b32_e32 v7, 0x7ffff, v4
+; GFX950-NEXT: s_movk_i32 s1, 0xff
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX950-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX950-NEXT: v_lshrrev_b32_e32 v6, 19, v4
-; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v5, v6, v7, v5 bitop3:0xe0
-; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 3
-; GFX950-NEXT: v_add_u32_e32 v4, v4, v5
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
-; GFX950-NEXT: v_frexp_mant_f32_e32 v6, v0
-; GFX950-NEXT: v_and_b32_e32 v7, 0x7fffff, v6
-; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v2, vcc, 14, v2, vcc
-; GFX950-NEXT: v_lshl_or_b32 v4, v2, 3, v4
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v2
-; GFX950-NEXT: v_or_b32_e32 v8, 0x800000, v7
-; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 1
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
-; GFX950-NEXT: v_sub_u32_e32 v5, 7, v4
-; GFX950-NEXT: v_min_u32_e32 v5, 31, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX950-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX950-NEXT: v_and_b32_e32 v8, 0x7ffff, v4
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v1
-; GFX950-NEXT: v_sub_u32_e64 v10, v5, 1 clamp
; GFX950-NEXT: v_mov_b32_e32 v3, 0xff
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; GFX950-NEXT: v_lshrrev_b32_e32 v11, v10, v8
-; GFX950-NEXT: v_bfe_u32 v10, v8, 0, v10
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, 19, v4
+; GFX950-NEXT: v_bfe_u32 v7, v6, 20, 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX950-NEXT: v_bfe_u32 v9, v8, v5, 1
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 3
; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v1
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v9, v11, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v5, v5, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_add_u32_e32 v4, v4, v5
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
+; GFX950-NEXT: v_or_b32_e32 v8, 0x800000, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v7, vcc, 14, v5, vcc
+; GFX950-NEXT: v_sub_u32_e32 v5, 7, v5
+; GFX950-NEXT: v_min_u32_e32 v5, 31, v5
+; GFX950-NEXT: v_sub_u32_e64 v10, v5, 1 clamp
+; GFX950-NEXT: v_lshlrev_b32_e64 v11, v10, 1
+; GFX950-NEXT: v_add_u32_e32 v11, -1, v11
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v11, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b32_e32 v9, v5, v8
+; GFX950-NEXT: v_lshrrev_b32_e32 v8, v10, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; GFX950-NEXT: v_lshrrev_b32_e32 v5, v5, v8
-; GFX950-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX950-NEXT: v_add_u32_e32 v5, v5, v9
+; GFX950-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX950-NEXT: v_lshl_or_b32 v4, v7, 3, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v5, v5, v8, v6 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v5, v9, v5
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
-; GFX950-NEXT: v_and_b32_e32 v9, 0x7ffff, v6
+; GFX950-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; GFX950-NEXT: v_or_b32_e32 v5, v8, v5
-; GFX950-NEXT: v_lshrrev_b32_e32 v8, 19, v6
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v7, v8, v9, v7 bitop3:0xe0
-; GFX950-NEXT: v_bfe_u32 v6, v6, 20, 3
-; GFX950-NEXT: v_add_u32_e32 v6, v6, v7
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
-; GFX950-NEXT: v_lshl_or_b32 v6, v4, 3, v6
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX950-NEXT: v_bitop3_b16 v0, v0, v2, s0 bitop3:0xec
+; GFX950-NEXT: v_bitop3_b16 v0, v0, v2, s1 bitop3:0xec
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_e5m3fnu_v2f32:
@@ -2191,95 +2227,100 @@ define <2 x i8> @to_e5m3fnu_v2f32(<2 x float> %x) {
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
-; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v4, v1
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v7, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
-; GFX1200-NEXT: v_sub_nc_u32_e32 v7, 7, v3
-; GFX1200-NEXT: v_and_b32_e32 v8, 0x7ffff, v2
-; GFX1200-NEXT: v_sub_nc_u32_e32 v10, 7, v5
+; GFX1200-NEXT: v_sub_nc_u32_e32 v5, 7, v2
+; GFX1200-NEXT: v_sub_nc_u32_e32 v6, 7, v3
+; GFX1200-NEXT: v_and_b32_e32 v9, 0x7ffff, v4
+; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v7
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_and_or_b32 v6, v2, s0, 0x800000
-; GFX1200-NEXT: v_and_b32_e32 v12, 0x7ffff, v4
-; GFX1200-NEXT: v_min_u32_e32 v7, 31, v7
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX1200-NEXT: v_min_u32_e32 v10, 31, v10
-; GFX1200-NEXT: v_and_or_b32 v11, v4, s0, 0x800000
-; GFX1200-NEXT: v_bfe_u32 v9, v2, 20, 3
-; GFX1200-NEXT: v_sub_nc_u32_e64 v14, v7, 1 clamp
+; GFX1200-NEXT: v_and_or_b32 v8, v4, s0, 0x800000
+; GFX1200-NEXT: v_min_u32_e32 v5, 31, v5
+; GFX1200-NEXT: v_min_u32_e32 v6, 31, v6
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
+; GFX1200-NEXT: v_and_or_b32 v12, v7, s0, 0x800000
+; GFX1200-NEXT: v_bfe_u32 v10, v4, 20, 3
+; GFX1200-NEXT: v_sub_nc_u32_e64 v11, v5, 1 clamp
+; GFX1200-NEXT: v_sub_nc_u32_e64 v13, v6, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_sub_nc_u32_e64 v15, v10, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX1200-NEXT: v_lshrrev_b32_e32 v17, v7, v6
-; GFX1200-NEXT: v_bfe_u32 v16, v6, 0, v14
-; GFX1200-NEXT: v_lshrrev_b32_e32 v19, v10, v11
-; GFX1200-NEXT: v_bfe_u32 v18, v11, 0, v15
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
+; GFX1200-NEXT: v_lshrrev_b32_e32 v18, v5, v8
+; GFX1200-NEXT: v_lshlrev_b32_e64 v16, v11, 1
+; GFX1200-NEXT: v_lshlrev_b32_e64 v17, v13, 1
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 19, v4
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b32_e32 v2, 19, v2
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
+; GFX1200-NEXT: v_add_nc_u32_e32 v16, -1, v16
+; GFX1200-NEXT: v_add_nc_u32_e32 v17, -1, v17
+; GFX1200-NEXT: v_and_or_b32 v9, v10, 1, v9
+; GFX1200-NEXT: v_lshrrev_b32_e32 v19, v6, v12
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b32_e32 v16, v8, v16
+; GFX1200-NEXT: v_and_b32_e32 v17, v12, v17
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, v11, v8
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, v13, v12
+; GFX1200-NEXT: v_bfe_u32 v15, v7, 20, 3
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX1200-NEXT: v_and_or_b32 v8, v9, 1, v8
-; GFX1200-NEXT: v_lshrrev_b32_e32 v6, v14, v6
-; GFX1200-NEXT: v_lshrrev_b32_e32 v11, v15, v11
-; GFX1200-NEXT: v_bfe_u32 v13, v4, 20, 3
+; GFX1200-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 19, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_and_or_b32 v14, v15, 1, v14
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX1200-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 19, v4
-; GFX1200-NEXT: v_and_or_b32 v12, v13, 1, v12
-; GFX1200-NEXT: v_and_or_b32 v14, v17, 1, v16
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
-; GFX1200-NEXT: v_add_nc_u32_e32 v2, v9, v2
-; GFX1200-NEXT: v_and_b32_e32 v4, v4, v12
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_and_or_b32 v15, v19, 1, v18
-; GFX1200-NEXT: v_add_nc_u32_e32 v4, v13, v4
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_b32_e32 v8, v11, v15
-; GFX1200-NEXT: v_and_b32_e32 v6, v6, v14
-; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v4
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX1200-NEXT: v_add_nc_u32_e32 v4, v10, v4
+; GFX1200-NEXT: v_and_b32_e32 v7, v7, v14
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b32_e32 v12, v16, v18
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
-; GFX1200-NEXT: v_add_co_ci_u32_e64 v5, null, 14, v5, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
+; GFX1200-NEXT: v_add_nc_u32_e32 v7, v15, v7
+; GFX1200-NEXT: v_and_b32_e32 v8, v8, v12
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b32_e32 v13, v17, v19
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v7, 0, v8, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_lshl_or_b32 v4, v5, 3, v4
-; GFX1200-NEXT: v_add_nc_u32_e32 v7, v19, v7
-; GFX1200-NEXT: v_add_nc_u32_e32 v6, v17, v6
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v4
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v7
+; GFX1200-NEXT: v_and_b32_e32 v5, v5, v8
+; GFX1200-NEXT: v_and_b32_e32 v9, v11, v13
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
-; GFX1200-NEXT: v_add_co_ci_u32_e64 v3, null, 14, v3, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
-; GFX1200-NEXT: v_cmp_lt_i32_e64 s1, 7, v6
+; GFX1200-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v2, null, 14, v2, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_lshl_or_b32 v2, v3, 3, v2
+; GFX1200-NEXT: v_and_b32_e32 v6, v6, v9
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, v18, v5
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v3, null, 14, v3, s0
+; GFX1200-NEXT: v_add_nc_u32_e32 v6, v19, v6
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
+; GFX1200-NEXT: v_lshl_or_b32 v4, v2, 3, v4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_lshl_or_b32 v7, v3, 3, v7
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s1, 7, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, v6, 0, s1
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 8, s1
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX1200-NEXT: v_or_b32_e32 v7, v9, v7
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 8, s1
+; GFX1200-NEXT: v_or_b32_e32 v5, v8, v5
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b32_e32 v6, v9, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v5
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
@@ -2325,83 +2366,84 @@ define <2 x i8> @to_e5m3fnu_v2f32(<2 x float> %x) {
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
-; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v3, v1
-; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v5, v0
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_dual_sub_nc_u32 v6, 7, v2 :: v_dual_lshrrev_b32 v8, 19, v3
-; GFX1310-NEXT: v_and_b32_e32 v7, 0x7fffff, v3
-; GFX1310-NEXT: v_dual_sub_nc_u32 v10, 7, v4 :: v_dual_lshrrev_b32 v12, 19, v5
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_min_u32_e32 v6, 31, v6
-; GFX1310-NEXT: v_and_b32_e32 v11, 0x7fffff, v5
-; GFX1310-NEXT: v_or_b32_e32 v14, 0x800000, v7
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v1
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_dual_lshrrev_b32 v6, 19, v2 :: v_dual_sub_nc_u32 v9, 7, v3
+; GFX1310-NEXT: v_dual_lshrrev_b32 v10, 19, v4 :: v_dual_sub_nc_u32 v12, 7, v5
+; GFX1310-NEXT: v_and_b32_e32 v8, 0x7ffff, v2
+; GFX1310-NEXT: v_and_b32_e32 v7, 0x7fffff, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1310-NEXT: v_min_u32_e32 v10, 31, v10
-; GFX1310-NEXT: v_and_b32_e32 v9, 0x7ffff, v3
-; GFX1310-NEXT: v_sub_nc_u32_e64 v15, v6, 1 clamp
-; GFX1310-NEXT: v_or_b32_e32 v16, 0x800000, v11
-; GFX1310-NEXT: v_bfe_u32 v18, v14, v6, 1
-; GFX1310-NEXT: v_sub_nc_u32_e64 v17, v10, 1 clamp
-; GFX1310-NEXT: v_and_b32_e32 v13, 0x7ffff, v5
-; GFX1310-NEXT: v_bfe_u32 v19, v14, 0, v15
-; GFX1310-NEXT: v_lshrrev_b32_e32 v15, v15, v14
-; GFX1310-NEXT: v_bfe_u32 v7, v7, 20, 1
-; GFX1310-NEXT: v_bfe_u32 v21, v16, 0, v17
-; GFX1310-NEXT: v_lshrrev_b32_e32 v17, v17, v16
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v19
-; GFX1310-NEXT: v_bfe_u32 v20, v16, v10, 1
-; GFX1310-NEXT: v_bfe_u32 v3, v3, 20, 3
-; GFX1310-NEXT: v_bfe_u32 v11, v11, 20, 1
-; GFX1310-NEXT: v_bfe_u32 v5, v5, 20, 3
-; GFX1310-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_bitop3_b32 v15, v15, v19, v18 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
-; GFX1310-NEXT: v_bitop3_b32 v17, v17, v21, v20 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX1310-NEXT: v_lshrrev_b32_e32 v14, v6, v14
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_bitop3_b32 v7, v8, v9, v7 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e32 v6, 0, v15, vcc_lo
+; GFX1310-NEXT: v_min_u32_e32 v9, 31, v9
+; GFX1310-NEXT: v_and_b32_e32 v13, 0x7ffff, v4
+; GFX1310-NEXT: v_min_u32_e32 v12, 31, v12
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX1310-NEXT: v_and_b32_e32 v11, 0x7fffff, v4
+; GFX1310-NEXT: v_sub_nc_u32_e64 v15, v9, 1 clamp
+; GFX1310-NEXT: v_bfe_u32 v14, v7, 20, 1
+; GFX1310-NEXT: v_sub_nc_u32_e64 v17, v12, 1 clamp
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1310-NEXT: v_or_b32_e32 v16, 0x800000, v7
+; GFX1310-NEXT: v_lshlrev_b32_e64 v18, v15, 1
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
-; GFX1310-NEXT: v_dual_add_nc_u32 v3, v3, v7 :: v_dual_add_nc_u32 v6, v14, v6
+; GFX1310-NEXT: v_lshlrev_b32_e64 v20, v17, 1
+; GFX1310-NEXT: v_bfe_u32 v19, v11, 20, 1
+; GFX1310-NEXT: v_or_b32_e32 v21, 0x800000, v11
+; GFX1310-NEXT: v_add_nc_u32_e32 v18, -1, v18
; GFX1310-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
-; GFX1310-NEXT: v_lshrrev_b32_e32 v10, v10, v16
+; GFX1310-NEXT: v_bitop3_b32 v6, v6, v8, v14 bitop3:0xe0
+; GFX1310-NEXT: v_lshrrev_b32_e32 v8, v9, v16
+; GFX1310-NEXT: v_add_nc_u32_e32 v14, -1, v20
+; GFX1310-NEXT: v_bitop3_b32 v7, v7, v18, 0x800000 bitop3:0xc8
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
+; GFX1310-NEXT: v_bitop3_b32 v10, v10, v13, v19 bitop3:0xe0
+; GFX1310-NEXT: v_lshrrev_b32_e32 v13, v12, v21
+; GFX1310-NEXT: v_bitop3_b32 v11, v11, v14, 0x800000 bitop3:0xc8
+; GFX1310-NEXT: v_bfe_u32 v2, v2, 20, 3
+; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1310-NEXT: v_dual_lshrrev_b32 v14, v15, v16 :: v_dual_lshrrev_b32 v15, v17, v21
+; GFX1310-NEXT: v_bfe_u32 v4, v4, 20, 3
+; GFX1310-NEXT: v_add_nc_u32_e32 v2, v2, v6
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_dual_add_nc_u32 v4, v4, v10 :: v_dual_bitop2_b32 v7, v7, v8 bitop3:0x54
+; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v4
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v3
-; GFX1310-NEXT: v_bitop3_b32 v9, v12, v13, v11 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e32 v8, 0, v17, vcc_lo
-; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v6
+; GFX1310-NEXT: v_bitop3_b32 v7, v9, v14, v7 bitop3:0x80
+; GFX1310-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v5, null, 14, v5, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_bitop3_b32 v6, v12, v15, v11 bitop3:0x80
+; GFX1310-NEXT: v_add_nc_u32_e32 v7, v8, v7
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v3, null, 14, v3, vcc_lo
+; GFX1310-NEXT: v_add_nc_u32_e32 v6, v13, v6
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
-; GFX1310-NEXT: v_add_co_ci_u32_e64 v2, null, 14, v2, s0
-; GFX1310-NEXT: v_dual_add_nc_u32 v5, v5, v9 :: v_dual_add_nc_u32 v7, v10, v8
-; GFX1310-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
-; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s1, 7, v7
+; GFX1310-NEXT: v_lshl_or_b32 v4, v5, 3, v4
+; GFX1310-NEXT: v_lshl_or_b32 v2, v3, 3, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_lshl_or_b32 v3, v2, 3, v3
-; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v5
-; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
-; GFX1310-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v6
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, v7, 0, s1
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 8, s1
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc_lo
-; GFX1310-NEXT: v_add_co_ci_u32_e64 v4, null, 14, v4, s0
-; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
-; GFX1310-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1310-NEXT: v_lshl_or_b32 v5, v4, 3, v5
-; GFX1310-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX1310-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc_lo
-; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
+; GFX1310-NEXT: v_dual_cndmask_b32 v2, v2, v7, vcc_lo :: v_dual_bitop2_b32 v6, v9, v6 bitop3:0x54
+; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v5
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cndmask_b32_e32 v3, v4, v6, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
; GFX1310-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
@@ -2425,47 +2467,47 @@ define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX950-LABEL: to_e5m3fnu_v4f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
-; GFX950-NEXT: v_sub_u32_e32 v5, 7, v4
-; GFX950-NEXT: v_frexp_mant_f32_e32 v6, v1
+; GFX950-NEXT: v_frexp_mant_f32_e32 v4, v1
+; GFX950-NEXT: v_and_b32_e32 v8, 0x7ffff, v4
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, 19, v4
+; GFX950-NEXT: v_bfe_u32 v7, v6, 20, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v5, v5, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 3
+; GFX950-NEXT: v_add_u32_e32 v4, v4, v5
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
+; GFX950-NEXT: s_mov_b32 s0, 0x800000
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v7, vcc, 14, v5, vcc
+; GFX950-NEXT: v_sub_u32_e32 v5, 7, v5
; GFX950-NEXT: v_min_u32_e32 v5, 31, v5
-; GFX950-NEXT: v_and_b32_e32 v7, 0x7fffff, v6
-; GFX950-NEXT: v_or_b32_e32 v8, 0x800000, v7
; GFX950-NEXT: v_sub_u32_e64 v10, v5, 1 clamp
-; GFX950-NEXT: v_lshrrev_b32_e32 v11, v10, v8
-; GFX950-NEXT: v_bfe_u32 v10, v8, 0, v10
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX950-NEXT: v_bfe_u32 v9, v8, v5, 1
-; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 1
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v9, v11, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b32_e64 v11, v10, 1
+; GFX950-NEXT: v_add_u32_e32 v11, -1, v11
+; GFX950-NEXT: v_or_b32_e32 v8, 0x800000, v6
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v11, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b32_e32 v9, v5, v8
+; GFX950-NEXT: v_lshrrev_b32_e32 v8, v10, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; GFX950-NEXT: v_lshrrev_b32_e32 v5, v5, v8
-; GFX950-NEXT: s_movk_i32 s0, 0xff
-; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX950-NEXT: v_add_u32_e32 v5, v5, v9
+; GFX950-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX950-NEXT: v_lshl_or_b32 v4, v7, 3, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v5, v5, v8, v6 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v5, v9, v5
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
-; GFX950-NEXT: v_and_b32_e32 v9, 0x7ffff, v6
+; GFX950-NEXT: s_movk_i32 s1, 0xff
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; GFX950-NEXT: v_or_b32_e32 v5, v8, v5
-; GFX950-NEXT: v_lshrrev_b32_e32 v8, 19, v6
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v7, v8, v9, v7 bitop3:0xe0
-; GFX950-NEXT: v_bfe_u32 v6, v6, 20, 3
-; GFX950-NEXT: v_add_u32_e32 v6, v6, v7
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
-; GFX950-NEXT: v_frexp_mant_f32_e32 v7, v0
-; GFX950-NEXT: v_and_b32_e32 v8, 0x7fffff, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
-; GFX950-NEXT: v_lshl_or_b32 v6, v4, 3, v6
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
-; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v8
-; GFX950-NEXT: v_bfe_u32 v8, v8, 20, 1
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v1
; GFX950-NEXT: v_mov_b32_e32 v5, 0xff
; GFX950-NEXT: s_nop 0
@@ -2473,137 +2515,145 @@ define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
-; GFX950-NEXT: v_sub_u32_e32 v6, 7, v4
+; GFX950-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX950-NEXT: v_and_b32_e32 v9, 0x7ffff, v4
+; GFX950-NEXT: v_and_b32_e32 v7, 0x7fffff, v4
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v6, 19, v4
+; GFX950-NEXT: v_bfe_u32 v8, v7, 20, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 3
+; GFX950-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
+; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v8, vcc, 14, v6, vcc
+; GFX950-NEXT: v_sub_u32_e32 v6, 7, v6
; GFX950-NEXT: v_min_u32_e32 v6, 31, v6
; GFX950-NEXT: v_sub_u32_e64 v11, v6, 1 clamp
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, v11, v9
-; GFX950-NEXT: v_bfe_u32 v11, v9, 0, v11
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; GFX950-NEXT: v_bfe_u32 v10, v9, v6, 1
-; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v10, v12, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b32_e64 v12, v11, 1
+; GFX950-NEXT: v_add_u32_e32 v12, -1, v12
+; GFX950-NEXT: v_bitop3_b32 v7, v7, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v10, v6, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v9, v11, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v6, v6, v9
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; GFX950-NEXT: v_add_u32_e32 v6, v6, v10
+; GFX950-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX950-NEXT: v_lshl_or_b32 v4, v8, 3, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v9, v7 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v6, v10, v6
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
-; GFX950-NEXT: v_and_b32_e32 v10, 0x7ffff, v7
+; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX950-NEXT: v_or_b32_e32 v6, v9, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v9, 19, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v8, v9, v10, v8 bitop3:0xe0
-; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 3
-; GFX950-NEXT: v_add_u32_e32 v7, v7, v8
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v7
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
-; GFX950-NEXT: v_lshl_or_b32 v7, v4, 3, v7
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v8
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
-; GFX950-NEXT: v_frexp_mant_f32_e32 v7, v3
-; GFX950-NEXT: v_and_b32_e32 v8, 0x7fffff, v7
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v8
-; GFX950-NEXT: v_bfe_u32 v8, v8, 20, 1
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
-; GFX950-NEXT: v_sub_u32_e32 v6, 7, v4
+; GFX950-NEXT: v_frexp_mant_f32_e32 v4, v3
+; GFX950-NEXT: v_and_b32_e32 v9, 0x7ffff, v4
+; GFX950-NEXT: v_and_b32_e32 v7, 0x7fffff, v4
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v6, 19, v4
+; GFX950-NEXT: v_bfe_u32 v8, v7, 20, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 3
+; GFX950-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v6, v3
+; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v8, vcc, 14, v6, vcc
+; GFX950-NEXT: v_sub_u32_e32 v6, 7, v6
; GFX950-NEXT: v_min_u32_e32 v6, 31, v6
; GFX950-NEXT: v_sub_u32_e64 v11, v6, 1 clamp
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, v11, v9
-; GFX950-NEXT: v_bfe_u32 v11, v9, 0, v11
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; GFX950-NEXT: v_bfe_u32 v10, v9, v6, 1
-; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, s0 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v10, v12, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b32_e64 v12, v11, 1
+; GFX950-NEXT: v_add_u32_e32 v12, -1, v12
+; GFX950-NEXT: v_bitop3_b32 v7, v7, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v10, v6, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v9, v11, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v6, v6, v9
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; GFX950-NEXT: v_add_u32_e32 v6, v6, v10
+; GFX950-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX950-NEXT: v_lshl_or_b32 v4, v8, 3, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v9, v7 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v6, v10, v6
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
-; GFX950-NEXT: v_and_b32_e32 v10, 0x7ffff, v7
+; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, s1 bitop3:0xec
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX950-NEXT: v_or_b32_e32 v6, v9, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v9, 19, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v8, v9, v10, v8 bitop3:0xe0
-; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 3
-; GFX950-NEXT: v_add_u32_e32 v7, v7, v8
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v7
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
-; GFX950-NEXT: v_lshl_or_b32 v7, v4, 3, v7
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v8
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v3
-; GFX950-NEXT: v_frexp_mant_f32_e32 v7, v2
-; GFX950-NEXT: v_and_b32_e32 v8, 0x7fffff, v7
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v3, v3
-; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v8
-; GFX950-NEXT: v_bfe_u32 v8, v8, 20, 1
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v2
-; GFX950-NEXT: v_sub_u32_e32 v6, 7, v4
+; GFX950-NEXT: v_frexp_mant_f32_e32 v4, v2
+; GFX950-NEXT: v_and_b32_e32 v9, 0x7ffff, v4
+; GFX950-NEXT: v_and_b32_e32 v7, 0x7fffff, v4
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v6, 19, v4
+; GFX950-NEXT: v_bfe_u32 v8, v7, 20, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 3
+; GFX950-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
+; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v8, vcc, 14, v6, vcc
+; GFX950-NEXT: v_sub_u32_e32 v6, 7, v6
; GFX950-NEXT: v_min_u32_e32 v6, 31, v6
; GFX950-NEXT: v_sub_u32_e64 v11, v6, 1 clamp
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, v11, v9
-; GFX950-NEXT: v_bfe_u32 v11, v9, 0, v11
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; GFX950-NEXT: v_bfe_u32 v10, v9, v6, 1
-; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v10, v12, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b32_e64 v12, v11, 1
+; GFX950-NEXT: v_add_u32_e32 v12, -1, v12
+; GFX950-NEXT: v_bitop3_b32 v7, v7, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v10, v6, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v9, v11, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v6, v6, v9
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; GFX950-NEXT: v_add_u32_e32 v6, v6, v10
+; GFX950-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX950-NEXT: v_lshl_or_b32 v4, v8, 3, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v6, v6, v9, v7 bitop3:0x80
+; GFX950-NEXT: v_add_u32_e32 v6, v10, v6
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
-; GFX950-NEXT: v_and_b32_e32 v10, 0x7ffff, v7
+; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX950-NEXT: v_or_b32_e32 v6, v9, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v9, 19, v7
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b32 v8, v9, v10, v8 bitop3:0xe0
-; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 3
-; GFX950-NEXT: v_add_u32_e32 v7, v7, v8
-; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v7
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
-; GFX950-NEXT: v_lshl_or_b32 v7, v4, 3, v7
-; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v8
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v2
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v2, v2
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v2, v3, s0 bitop3:0xec
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v3, s1 bitop3:0xec
; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
@@ -2618,179 +2668,197 @@ define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v8, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v5, v1
-; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
; GFX1200-NEXT: s_mov_b32 s1, 0x7fffff
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v7, v0
-; GFX1200-NEXT: v_sub_nc_u32_e32 v8, 7, v4
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v6, v0
+; GFX1200-NEXT: v_sub_nc_u32_e32 v7, 7, v4
+; GFX1200-NEXT: v_sub_nc_u32_e32 v12, 7, v8
+; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v5
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v13, v5, s1, 0x800000
-; GFX1200-NEXT: v_sub_nc_u32_e32 v11, 7, v6
-; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v5
-; GFX1200-NEXT: v_and_or_b32 v17, v7, s1, 0x800000
-; GFX1200-NEXT: v_min_u32_e32 v8, 31, v8
-; GFX1200-NEXT: v_bfe_u32 v15, v5, 20, 3
-; GFX1200-NEXT: v_min_u32_e32 v11, 31, v11
+; GFX1200-NEXT: v_and_or_b32 v17, v6, s1, 0x800000
+; GFX1200-NEXT: v_min_u32_e32 v7, 31, v7
+; GFX1200-NEXT: v_min_u32_e32 v12, 31, v12
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
+; GFX1200-NEXT: v_bfe_u32 v15, v5, 20, 3
; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 19, v5
-; GFX1200-NEXT: v_sub_nc_u32_e64 v16, v8, 1 clamp
-; GFX1200-NEXT: v_lshrrev_b32_e32 v22, v8, v13
-; GFX1200-NEXT: v_sub_nc_u32_e64 v18, v11, 1 clamp
+; GFX1200-NEXT: v_sub_nc_u32_e64 v16, v7, 1 clamp
+; GFX1200-NEXT: v_sub_nc_u32_e64 v20, v12, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b32_e32 v23, v11, v17
-; GFX1200-NEXT: v_bfe_u32 v20, v13, 0, v16
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, v16, v13
-; GFX1200-NEXT: v_bfe_u32 v21, v17, 0, v18
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1200-NEXT: v_lshrrev_b32_e32 v25, v7, v13
+; GFX1200-NEXT: v_lshlrev_b32_e64 v19, v16, 1
+; GFX1200-NEXT: v_lshlrev_b32_e64 v24, v20, 1
; GFX1200-NEXT: v_and_or_b32 v14, v15, 1, v14
-; GFX1200-NEXT: v_lshrrev_b32_e32 v17, v18, v17
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v26, v12, v17
+; GFX1200-NEXT: v_add_nc_u32_e32 v19, -1, v19
+; GFX1200-NEXT: v_add_nc_u32_e32 v24, -1, v24
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v10, v3
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v9, v3
; GFX1200-NEXT: v_and_b32_e32 v5, v5, v14
-; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v12, v2
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
-; GFX1200-NEXT: v_sub_nc_u32_e32 v14, 7, v10
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, v20, v17
+; GFX1200-NEXT: v_and_b32_e32 v19, v13, v19
+; GFX1200-NEXT: v_and_b32_e32 v24, v17, v24
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, v16, v13
+; GFX1200-NEXT: v_sub_nc_u32_e32 v22, 7, v10
; GFX1200-NEXT: v_add_nc_u32_e32 v5, v15, v5
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_and_or_b32 v16, v22, 1, v20
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX1200-NEXT: v_min_u32_e32 v14, 31, v14
-; GFX1200-NEXT: v_and_or_b32 v20, v9, s1, 0x800000
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v19
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v9, v3
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v11, v2
+; GFX1200-NEXT: v_min_u32_e32 v22, 31, v22
+; GFX1200-NEXT: v_and_b32_e32 v18, 0x7ffff, v6
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
+; GFX1200-NEXT: v_and_or_b32 v21, v9, s1, 0x800000
+; GFX1200-NEXT: v_sub_nc_u32_e64 v24, v22, 1 clamp
+; GFX1200-NEXT: v_sub_nc_u32_e32 v23, 7, v11
+; GFX1200-NEXT: v_or_b32_e32 v16, v19, v25
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX1200-NEXT: v_min_u32_e32 v15, 31, v23
; GFX1200-NEXT: v_and_b32_e32 v13, v13, v16
-; GFX1200-NEXT: v_and_b32_e32 v19, 0x7ffff, v7
-; GFX1200-NEXT: v_and_or_b32 v18, v23, 1, v21
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b32_e32 v16, v19, v26
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v13, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX1200-NEXT: v_and_b32_e32 v16, v17, v18
-; GFX1200-NEXT: v_sub_nc_u32_e32 v13, 7, v12
-; GFX1200-NEXT: v_lshrrev_b32_e32 v18, v14, v20
-; GFX1200-NEXT: v_add_nc_u32_e32 v8, v22, v8
-; GFX1200-NEXT: v_bfe_u32 v22, v9, 20, 3
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v11, 0, v16, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
-; GFX1200-NEXT: v_sub_nc_u32_e64 v16, v14, 1 clamp
-; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
-; GFX1200-NEXT: v_min_u32_e32 v13, 31, v13
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v19, v2
+; GFX1200-NEXT: v_and_b32_e32 v7, v7, v13
+; GFX1200-NEXT: v_and_b32_e32 v14, v14, v16
+; GFX1200-NEXT: v_lshlrev_b32_e64 v13, v24, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v4, null, 14, v4, vcc_lo
+; GFX1200-NEXT: v_add_nc_u32_e32 v7, v25, v7
+; GFX1200-NEXT: v_and_b32_e32 v12, v12, v14
+; GFX1200-NEXT: v_lshrrev_b32_e32 v16, v22, v21
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_lshl_or_b32 v5, v4, 3, v5
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_add_nc_u32_e32 v12, v26, v12
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 8, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 8, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_lshl_or_b32 v5, v4, 3, v5
-; GFX1200-NEXT: v_or_b32_e32 v8, v15, v8
-; GFX1200-NEXT: v_add_nc_u32_e32 v11, v23, v11
-; GFX1200-NEXT: v_bfe_u32 v15, v20, 0, v16
-; GFX1200-NEXT: v_lshrrev_b32_e32 v16, v16, v20
-; GFX1200-NEXT: v_sub_nc_u32_e64 v20, v13, 1 clamp
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v11
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v17, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v12
+; GFX1200-NEXT: v_or_b32_e32 v7, v14, v7
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
-; GFX1200-NEXT: v_or_b32_e32 v11, v17, v11
+; GFX1200-NEXT: v_add_nc_u32_e32 v13, -1, v13
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b32_e32 v12, v14, v12
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v8, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v15, v2
-; GFX1200-NEXT: v_and_b32_e32 v21, 0x7ffff, v9
-; GFX1200-NEXT: v_bfe_u32 v17, v7, 20, 3
-; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 19, v7
+; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX1200-NEXT: v_and_b32_e32 v13, v21, v13
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, v24, v21
+; GFX1200-NEXT: v_and_or_b32 v21, v19, s1, 0x800000
+; GFX1200-NEXT: v_bfe_u32 v18, v6, 20, 3
+; GFX1200-NEXT: v_cmp_ne_u32_e64 s0, 0, v13
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
+; GFX1200-NEXT: v_and_b32_e32 v22, 0x7ffff, v9
+; GFX1200-NEXT: v_lshrrev_b32_e32 v6, 19, v6
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_and_or_b32 v14, v18, 1, v17
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b32_e32 v5, v13, v16
+; GFX1200-NEXT: v_sub_nc_u32_e64 v13, v15, 1 clamp
+; GFX1200-NEXT: v_and_b32_e32 v6, v6, v14
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b32_e32 v5, v7, v5
+; GFX1200-NEXT: v_lshlrev_b32_e64 v20, v13, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v19
-; GFX1200-NEXT: v_and_or_b32 v19, v15, s1, 0x800000
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
+; GFX1200-NEXT: v_lshrrev_b32_e32 v22, v15, v21
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, v13, v21
+; GFX1200-NEXT: v_add_nc_u32_e32 v20, -1, v20
+; GFX1200-NEXT: v_and_b32_e32 v5, v7, v5
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX1200-NEXT: v_add_nc_u32_e32 v6, v18, v6
+; GFX1200-NEXT: v_and_b32_e32 v7, v21, v20
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, v16, v5
+; GFX1200-NEXT: v_and_b32_e32 v16, 0x7ffff, v19
+; GFX1200-NEXT: v_bfe_u32 v20, v9, 20, 3
; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 19, v9
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_and_or_b32 v5, v18, 1, v5
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1200-NEXT: v_bfe_u32 v21, v19, 20, 3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_or_b32 v17, v20, 1, v17
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
-; GFX1200-NEXT: v_lshrrev_b32_e32 v23, v13, v19
-; GFX1200-NEXT: v_and_b32_e32 v5, v16, v5
-; GFX1200-NEXT: v_bfe_u32 v16, v19, 0, v20
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_or_b32 v8, v17, 1, v8
-; GFX1200-NEXT: v_lshrrev_b32_e32 v19, v20, v19
-; GFX1200-NEXT: v_bfe_u32 v20, v15, 20, 3
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX1200-NEXT: v_and_or_b32 v21, v22, 1, v21
-; GFX1200-NEXT: v_and_b32_e32 v7, v7, v8
+; GFX1200-NEXT: v_and_b32_e32 v9, v9, v17
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b32_e32 v7, v7, v22
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
-; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v15
-; GFX1200-NEXT: v_and_b32_e32 v9, v9, v21
-; GFX1200-NEXT: v_lshrrev_b32_e32 v15, 19, v15
-; GFX1200-NEXT: v_and_or_b32 v16, v23, 1, v16
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
-; GFX1200-NEXT: v_add_nc_u32_e32 v9, v22, v9
-; GFX1200-NEXT: v_add_nc_u32_e32 v7, v17, v7
-; GFX1200-NEXT: v_and_b32_e32 v8, v19, v16
-; GFX1200-NEXT: v_add_nc_u32_e32 v5, v18, v5
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_or_b32 v14, v20, 1, v14
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX1200-NEXT: v_add_nc_u32_e32 v9, v20, v9
+; GFX1200-NEXT: v_and_b32_e32 v7, v13, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_or_b32 v15, v21, 1, v16
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v16, 19, v19
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
-; GFX1200-NEXT: v_and_b32_e32 v13, v15, v14
+; GFX1200-NEXT: v_and_b32_e32 v7, v13, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_add_nc_u32_e32 v8, v23, v8
+; GFX1200-NEXT: v_and_b32_e32 v13, v16, v15
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v9
-; GFX1200-NEXT: v_add_nc_u32_e32 v13, v20, v13
-; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
+; GFX1200-NEXT: v_add_nc_u32_e32 v7, v22, v7
+; GFX1200-NEXT: v_add_nc_u32_e32 v13, v21, v13
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-NEXT: v_or_b32_e32 v5, v14, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v7
; GFX1200-NEXT: v_add_co_ci_u32_e64 v10, null, 14, v10, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v13
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 8, s0
; GFX1200-NEXT: v_lshl_or_b32 v9, v10, 3, v9
-; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v10
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v13, v13, 0, vcc_lo
-; GFX1200-NEXT: v_add_co_ci_u32_e64 v12, null, 14, v12, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
-; GFX1200-NEXT: v_or_b32_e32 v8, v15, v8
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v11, null, 14, v11, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v6
+; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v10
+; GFX1200-NEXT: v_or_b32_e32 v7, v15, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_lshl_or_b32 v13, v11, 3, v13
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v9, v5, s0
-; GFX1200-NEXT: v_lshl_or_b32 v13, v12, 3, v13
-; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v12
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
-; GFX1200-NEXT: v_add_co_ci_u32_e64 v6, null, 14, v6, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v11
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v8, null, 14, v8, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_lshl_or_b32 v7, v6, 3, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, v13, v7, s0
+; GFX1200-NEXT: v_lshl_or_b32 v6, v8, 3, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0xff, v5, vcc_lo
@@ -2798,11 +2866,11 @@ define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0xff, v8, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
+; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0xff, v7, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v8
; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v5.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v6, v7, v11, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v2.l
@@ -2867,185 +2935,188 @@ define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
; GFX1310-NEXT: v_frexp_mant_f32_e32 v5, v1
-; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v8, v0
-; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v9, v3
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_dual_sub_nc_u32 v7, 7, v4 :: v_dual_lshrrev_b32 v12, 19, v5
-; GFX1310-NEXT: v_and_b32_e32 v11, 0x7fffff, v5
-; GFX1310-NEXT: v_and_b32_e32 v13, 0x7ffff, v5
-; GFX1310-NEXT: v_dual_sub_nc_u32 v16, 7, v6 :: v_dual_sub_nc_u32 v18, 7, v9
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_min_u32_e32 v7, 31, v7
-; GFX1310-NEXT: v_or_b32_e32 v14, 0x800000, v11
-; GFX1310-NEXT: v_bfe_u32 v11, v11, 20, 1
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v6, v0
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v9, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_dual_sub_nc_u32 v8, 7, v4 :: v_dual_lshrrev_b32 v12, 19, v5
+; GFX1310-NEXT: v_and_b32_e32 v13, 0x7fffff, v5
+; GFX1310-NEXT: v_and_b32_e32 v14, 0x7ffff, v5
+; GFX1310-NEXT: v_and_b32_e32 v18, 0x7ffff, v6
+; GFX1310-NEXT: v_min_u32_e32 v8, 31, v8
+; GFX1310-NEXT: v_dual_lshrrev_b32 v15, 19, v6 :: v_dual_sub_nc_u32 v19, 7, v7
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
+; GFX1310-NEXT: v_or_b32_e32 v25, 0x800000, v13
+; GFX1310-NEXT: v_sub_nc_u32_e64 v16, v8, 1 clamp
+; GFX1310-NEXT: v_bfe_u32 v24, v13, 20, 1
+; GFX1310-NEXT: v_and_b32_e32 v17, 0x7fffff, v6
+; GFX1310-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX1310-NEXT: v_lshlrev_b32_e64 v20, v16, 1
+; GFX1310-NEXT: v_min_u32_e32 v19, 31, v19
+; GFX1310-NEXT: v_bfe_u32 v26, v17, 20, 1
; GFX1310-NEXT: v_bfe_u32 v5, v5, 20, 3
-; GFX1310-NEXT: v_and_b32_e32 v17, 0x7fffff, v8
-; GFX1310-NEXT: v_sub_nc_u32_e64 v15, v7, 1 clamp
-; GFX1310-NEXT: v_min_u32_e32 v16, 31, v16
-; GFX1310-NEXT: v_bfe_u32 v21, v14, v7, 1
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v10, v3
-; GFX1310-NEXT: v_or_b32_e32 v22, 0x800000, v17
-; GFX1310-NEXT: v_bfe_u32 v20, v14, 0, v15
-; GFX1310-NEXT: v_min_u32_e32 v18, 31, v18
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_and_b32_e32 v19, 0x7fffff, v10
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX1310-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; GFX1310-NEXT: v_dual_add_nc_u32 v20, -1, v20 :: v_dual_lshrrev_b32 v27, v8, v25
+; GFX1310-NEXT: v_bfe_u32 v6, v6, 20, 3
+; GFX1310-NEXT: v_bitop3_b32 v12, v12, v14, v24 bitop3:0xe0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_bitop3_b32 v14, v15, v18, v26 bitop3:0xe0
+; GFX1310-NEXT: v_bitop3_b32 v13, v13, v20, 0x800000 bitop3:0xc8
+; GFX1310-NEXT: v_or_b32_e32 v20, 0x800000, v17
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v10, v3
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v11, v2
+; GFX1310-NEXT: v_and_b32_e32 v21, 0x7fffff, v9
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
+; GFX1310-NEXT: v_dual_lshrrev_b32 v15, v19, v20 :: v_dual_add_nc_u32 v6, v6, v14
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_dual_sub_nc_u32 v22, 7, v10 :: v_dual_sub_nc_u32 v23, 7, v11
; GFX1310-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_bitop3_b32 v11, v12, v13, v11 bitop3:0xe0
-; GFX1310-NEXT: v_lshrrev_b32_e32 v15, v15, v14
-; GFX1310-NEXT: v_bfe_u32 v13, v22, v16, 1
-; GFX1310-NEXT: v_add_nc_u32_e32 v5, v5, v11
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_bitop3_b32 v15, v15, v20, v21 bitop3:0xe0
-; GFX1310-NEXT: v_sub_nc_u32_e64 v20, v16, 1 clamp
-; GFX1310-NEXT: v_dual_cndmask_b32 v7, 0, v15 :: v_dual_lshrrev_b32 v14, v7, v14
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_bfe_u32 v12, v22, 0, v20
-; GFX1310-NEXT: v_lshrrev_b32_e32 v11, v20, v22
-; GFX1310-NEXT: v_sub_nc_u32_e64 v15, v18, 1 clamp
-; GFX1310-NEXT: v_add_nc_u32_e32 v7, v14, v7
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v7
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX1310-NEXT: v_lshrrev_b32_e32 v16, v16, v25
+; GFX1310-NEXT: v_min_u32_e32 v22, 31, v22
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_or_b32_e32 v13, v13, v27
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v19
+; GFX1310-NEXT: v_bitop3_b32 v8, v8, v16, v13 bitop3:0x80
+; GFX1310-NEXT: v_sub_nc_u32_e64 v13, v19, 1 clamp
+; GFX1310-NEXT: v_sub_nc_u32_e64 v16, v22, 1 clamp
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_add_nc_u32_e32 v8, v27, v8
+; GFX1310-NEXT: v_lshlrev_b32_e64 v14, v13, 1
+; GFX1310-NEXT: v_add_nc_u32_e32 v5, v5, v12
; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1310-NEXT: v_lshlrev_b32_e64 v19, v16, 1
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
+; GFX1310-NEXT: v_add_nc_u32_e32 v14, -1, v14
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
-; GFX1310-NEXT: v_bitop3_b32 v11, v11, v12, v13 bitop3:0xe0
+; GFX1310-NEXT: v_lshrrev_b32_e32 v13, v13, v20
+; GFX1310-NEXT: v_bfe_u32 v20, v21, 20, 1
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v18, 0, 8, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1310-NEXT: v_add_co_ci_u32_e64 v4, null, 14, v4, vcc_lo
-; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 8, s0
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX1310-NEXT: v_lshrrev_b32_e32 v14, v16, v22
-; GFX1310-NEXT: v_or_b32_e32 v13, 0x800000, v19
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_or_b32_e32 v8, v18, v8
+; GFX1310-NEXT: v_bitop3_b32 v14, v17, v14, 0x800000 bitop3:0xc8
; GFX1310-NEXT: v_lshl_or_b32 v5, v4, 3, v5
-; GFX1310-NEXT: v_or_b32_e32 v7, v12, v7
-; GFX1310-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
-; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
-; GFX1310-NEXT: v_cmp_neq_f32_e64 s0, 0, v1
-; GFX1310-NEXT: v_bfe_u32 v12, v13, v18, 1
-; GFX1310-NEXT: v_bfe_u32 v19, v19, 20, 1
-; GFX1310-NEXT: v_dual_add_nc_u32 v11, v14, v11 :: v_dual_lshrrev_b32 v14, v15, v13
-; GFX1310-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX1310-NEXT: v_bfe_u32 v5, v13, 0, v15
-; GFX1310-NEXT: v_lshrrev_b32_e32 v13, v18, v13
-; GFX1310-NEXT: v_frexp_mant_f32_e32 v15, v2
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, v4, s0
-; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v11
-; GFX1310-NEXT: v_cndmask_b32_e64 v7, v11, 0, vcc_lo
-; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
-; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_gt_i32_e64 s0, 1, v4
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX1310-NEXT: v_and_b32_e32 v17, 0x7ffff, v9
+; GFX1310-NEXT: v_min_u32_e32 v18, 31, v23
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, v5, v8, s0
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v5, null, 14, v7, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
+; GFX1310-NEXT: v_dual_add_nc_u32 v8, -1, v19 :: v_dual_lshrrev_b32 v14, 19, v9
+; GFX1310-NEXT: v_bfe_u32 v9, v9, 20, 3
+; GFX1310-NEXT: v_lshl_or_b32 v6, v5, 3, v6
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
+; GFX1310-NEXT: v_bitop3_b32 v8, v21, v8, 0x800000 bitop3:0xc8
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_dual_cndmask_b32 v4, 0, v4, vcc_lo :: v_dual_bitop2_b32 v7, v7, v15 bitop3:0x54
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1310-NEXT: v_bitop3_b32 v5, v14, v5, v12 bitop3:0xe0
-; GFX1310-NEXT: v_and_b32_e32 v12, 0x7ffff, v8
-; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v14, v2
+; GFX1310-NEXT: v_bitop3_b32 v7, v12, v13, v7 bitop3:0x80
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0xff, v4, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX1310-NEXT: v_or_b32_e32 v4, v11, v7
-; GFX1310-NEXT: v_bfe_u32 v11, v17, 20, 1
-; GFX1310-NEXT: v_and_b32_e32 v17, 0x7ffff, v10
-; GFX1310-NEXT: v_dual_lshrrev_b32 v7, 19, v8 :: v_dual_cndmask_b32 v5, 0, v5, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX1310-NEXT: v_sub_nc_u32_e32 v16, 7, v14
-; GFX1310-NEXT: v_lshrrev_b32_e32 v18, 19, v10
-; GFX1310-NEXT: v_bfe_u32 v10, v10, 20, 3
-; GFX1310-NEXT: v_bfe_u32 v8, v8, 20, 3
-; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX1310-NEXT: v_or_b32_e32 v4, 0x800000, v21
+; GFX1310-NEXT: v_sub_nc_u32_e64 v21, v18, 1 clamp
+; GFX1310-NEXT: v_add_nc_u32_e32 v7, v15, v7
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX1310-NEXT: v_min_u32_e32 v16, 31, v16
-; GFX1310-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_bitop3_b32 v7, v7, v12, v11 bitop3:0xe0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshlrev_b32_e64 v23, v21, 1
; GFX1310-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; GFX1310-NEXT: v_sub_nc_u32_e64 v21, v16, 1 clamp
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_bitop3_b32 v12, v18, v17, v19 bitop3:0xe0
-; GFX1310-NEXT: v_add_nc_u32_e32 v5, v13, v5
-; GFX1310-NEXT: v_and_b32_e32 v13, 0x7fffff, v15
-; GFX1310-NEXT: v_add_nc_u32_e32 v10, v10, v12
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
+; GFX1310-NEXT: v_bitop3_b32 v14, v14, v17, v20 bitop3:0xe0
+; GFX1310-NEXT: v_dual_lshrrev_b32 v19, v22, v4 :: v_dual_lshrrev_b32 v4, v16, v4
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v16, v2
+; GFX1310-NEXT: v_add_nc_u32_e32 v20, -1, v23
+; GFX1310-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_dual_add_nc_u32 v9, v9, v14 :: v_dual_bitop2_b32 v8, v8, v19 bitop3:0x54
+; GFX1310-NEXT: v_and_b32_e32 v17, 0x7fffff, v16
+; GFX1310-NEXT: v_and_b32_e32 v13, 0x7ffff, v16
+; GFX1310-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_bitop3_b32 v4, v22, v4, v8 bitop3:0x80
+; GFX1310-NEXT: v_bitop3_b32 v12, v17, v20, 0x800000 bitop3:0xc8
+; GFX1310-NEXT: v_or_b32_e32 v8, 0x800000, v17
+; GFX1310-NEXT: v_bfe_u32 v17, v17, 20, 1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
-; GFX1310-NEXT: v_or_b32_e32 v20, 0x800000, v13
-; GFX1310-NEXT: v_lshrrev_b32_e32 v12, 19, v15
-; GFX1310-NEXT: v_bfe_u32 v13, v13, 20, 1
-; GFX1310-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1310-NEXT: v_bfe_u32 v11, v20, 0, v21
-; GFX1310-NEXT: v_lshrrev_b32_e32 v18, v21, v20
-; GFX1310-NEXT: v_and_b32_e32 v21, 0x7ffff, v15
-; GFX1310-NEXT: v_bfe_u32 v17, v20, v16, 1
-; GFX1310-NEXT: v_cndmask_b32_e64 v19, 0, 8, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e64 s0, 0, v11
-; GFX1310-NEXT: v_add_nc_u32_e32 v7, v8, v7
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX1310-NEXT: v_dual_lshrrev_b32 v14, v18, v8 :: v_dual_lshrrev_b32 v8, v21, v8
+; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
+; GFX1310-NEXT: v_add_nc_u32_e32 v4, v19, v4
+; GFX1310-NEXT: v_lshrrev_b32_e32 v19, 19, v16
+; GFX1310-NEXT: v_bfe_u32 v16, v16, 20, 3
+; GFX1310-NEXT: v_or_b32_e32 v12, v12, v14
+; GFX1310-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_bitop3_b32 v13, v19, v13, v17 bitop3:0xe0
+; GFX1310-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v9
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_bitop3_b32 v8, v18, v8, v12 bitop3:0x80
+; GFX1310-NEXT: v_add_nc_u32_e32 v12, v16, v13
+; GFX1310-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc_lo
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v10, null, 14, v10, vcc_lo
+; GFX1310-NEXT: v_add_nc_u32_e32 v8, v14, v8
+; GFX1310-NEXT: v_cndmask_b32_e64 v13, 0, 8, s0
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v12
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_or_b32_e32 v5, v19, v5
-; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_bitop3_b32 v11, v18, v11, v17 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX1310-NEXT: v_lshrrev_b32_e32 v16, v16, v20
-; GFX1310-NEXT: v_bitop3_b32 v12, v12, v17, v13 bitop3:0xe0
-; GFX1310-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
-; GFX1310-NEXT: v_bfe_u32 v13, v15, 20, 3
-; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v10
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_dual_add_nc_u32 v11, v16, v11 :: v_dual_add_nc_u32 v12, v13, v12
-; GFX1310-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc_lo
-; GFX1310-NEXT: v_add_co_ci_u32_e64 v9, null, 14, v9, vcc_lo
-; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v11
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v12
-; GFX1310-NEXT: v_lshl_or_b32 v8, v9, 3, v10
-; GFX1310-NEXT: v_cndmask_b32_e64 v10, v11, 0, vcc_lo
-; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc_lo
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1310-NEXT: v_cndmask_b32_e64 v12, v12, 0, s0
-; GFX1310-NEXT: v_add_co_ci_u32_e64 v13, null, 14, v14, s0
+; GFX1310-NEXT: v_lshl_or_b32 v9, v10, 3, v9
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_or_b32_e32 v4, v13, v4
+; GFX1310-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc_lo
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v11, null, 14, v11, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v13, 0, 8, s0
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
-; GFX1310-NEXT: v_cmp_gt_i32_e64 s0, 1, v9
-; GFX1310-NEXT: v_lshl_or_b32 v9, v13, 3, v12
+; GFX1310-NEXT: v_cmp_gt_i32_e64 s0, 1, v10
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_or_b32_e32 v8, v13, v8
; GFX1310-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1310-NEXT: v_dual_cndmask_b32 v5, v8, v5, s0 :: v_dual_bitop2_b32 v8, v11, v10 bitop3:0x54
-; GFX1310-NEXT: v_add_co_ci_u32_e64 v6, null, 14, v6, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, v9, v4, s0
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v3
-; GFX1310-NEXT: v_lshl_or_b32 v7, v6, 3, v7
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX1310-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
-; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v13
+; GFX1310-NEXT: v_lshl_or_b32 v9, v11, 3, v12
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_dual_cndmask_b32 v4, 0, v4, vcc_lo :: v_dual_bitop2_b32 v7, v10, v7 bitop3:0x54
+; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v11
; GFX1310-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v3
-; GFX1310-NEXT: v_cndmask_b32_e32 v3, 0xff, v5, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cndmask_b32_e32 v3, 0xff, v4, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v2
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1310-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc_lo
-; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
-; GFX1310-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc_lo
+; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v5
+; GFX1310-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v2, 0xff, v4, vcc_lo
; GFX1310-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX1310-NEXT: v_cndmask_b32_e32 v2, 0xff, v5, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b16 v2, v2, v3, 0xff bitop3:0xec
-; GFX1310-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e32 v4, 0, v5, vcc_lo
; GFX1310-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_lshl_or_b32 v3, v2, 16, v3
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0xff, v4, vcc_lo
; GFX1310-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b16 v0, v0, v1, 0xff bitop3:0xec
-; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_dual_lshrrev_b32 v1, 8, v3 :: v_dual_lshrrev_b32 v3, 24, v4
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E5M3FNU", metadata !"round.tonearest", i1 false)
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
index fa961455f3900..dce4d0fa83df1 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
@@ -285,312 +285,303 @@ define <5 x i8> @to_fp8_v5f16(<5 x half> %x) {
; GFX950-LABEL: to_fp8_v5f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v2
-; GFX950-NEXT: v_sub_u16_e32 v7, 2, v6
; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v2
+; GFX950-NEXT: v_and_b32_e32 v5, 0x3ff, v4
+; GFX950-NEXT: v_and_b32_e32 v8, 63, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 7, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v6, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v7, v2
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v7, v6
+; GFX950-NEXT: v_sub_u16_e32 v7, 2, v7
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_sub_u16_e64 v11, v7, 1 clamp
+; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v11, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v6
+; GFX950-NEXT: v_and_b32_sdwa v9, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_bitop3_b16 v8, v9, v3, v8 bitop3:0xfe
; GFX950-NEXT: v_mov_b32_e32 v3, 0x3ff
-; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
-; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v10, v7, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, v7, v5
-; GFX950-NEXT: v_lshrrev_b16_e32 v5, v10, v5
-; GFX950-NEXT: v_lshlrev_b16_e64 v10, v10, 1
-; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v4
-; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
-; GFX950-NEXT: v_bitop3_b16 v10, v11, v10, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
-; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
-; GFX950-NEXT: s_movk_i32 s1, 0x80
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v5, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v4, v4, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v7, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v11, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v11
-; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
-; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v8, v5
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; GFX950-NEXT: v_and_b32_sdwa v8, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_or_b32_e32 v5, v5, v10
+; GFX950-NEXT: v_and_b32_sdwa v12, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v5 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v4, v10, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
; GFX950-NEXT: s_movk_i32 s2, 0xff
-; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v7 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v4
-; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
; GFX950-NEXT: s_mov_b32 s3, 0x7f7f0000
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v10 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v4, v9, v4
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v6, v7
-; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v6
-; GFX950-NEXT: v_bitop3_b16 v4, v8, v4, v7 bitop3:0xfe
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v5 bitop3:0xfe
; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v7, v6, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v6
; GFX950-NEXT: v_mov_b32_e32 v5, 0x7f
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
-; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
-; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
-; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v6
+; GFX950-NEXT: v_and_b32_e32 v11, 63, v6
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v2, v2
-; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v6
; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_bitop3_b16 v6, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v7, v9, v7
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
-; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v2
-; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v10, v9
+; GFX950-NEXT: v_sub_u16_e32 v10, 2, v10
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v13, 1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v14, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v6
-; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v12 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v12, v7, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_or_b32_e32 v8, v8, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v10, v6, v8 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_and_b32_sdwa v13, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_bitop3_b16 v6, v10, v6, v9 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
; GFX950-NEXT: v_mov_b32_e32 v8, 0
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v9, v1
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v2, v8 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v2, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v10, 2, v9
-; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX950-NEXT: v_bitop3_b16 v4, v4, v2, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v2, v1
-; GFX950-NEXT: v_bitop3_b16 v6, v2, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
-; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
-; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v2
-; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
-; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_or_b32_sdwa v7, v4, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v6, v13, v12 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v14
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
-; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v2
+; GFX950-NEXT: v_and_b32_e32 v12, 63, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v2
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v10, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
-; GFX950-NEXT: v_and_b32_sdwa v11, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v11, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v2, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v11, v10
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v11
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v15, v14, 1
+; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v15, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v10 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, 6, v2
-; GFX950-NEXT: v_and_b32_e32 v2, 63, v2
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v13 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v10
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_bitop3_b16 v6, v13, v6, v12 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_or_b32_e32 v9, v9, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v14, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v9 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v2, v12, v2
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v9, v9, v10
-; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_and_b32_sdwa v14, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_or_b32_sdwa v7, v4, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v10, 3, v9
-; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v10 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v13, v2, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v9, v6, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc
-; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
-; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
-; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v6
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v6
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v13, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_and_b32_e32 v13, 63, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v10
; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v6
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v9, v11, v9
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v1
-; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v6, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v11, v12, v11
+; GFX950-NEXT: v_sub_u16_e32 v12, 2, v12
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v15, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_add_u16_e32 v11, 6, v11
+; GFX950-NEXT: v_bitop3_b16 v10, v10, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v6
-; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v14 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v11
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v14, v9, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v15, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v10 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v6, v13, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
-; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
-; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v11 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v0
-; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v14, v6, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v11
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v8 src0_sel:WORD_1 src1_sel:DWORD
-; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
-; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
-; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_and_b32_sdwa v14, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX950-NEXT: v_bitop3_b16 v2, v2, v1, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
-; GFX950-NEXT: v_bitop3_b16 v9, v1, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v1
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
-; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v1
+; GFX950-NEXT: v_and_b32_e32 v13, 63, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v10
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v9, v11, v9
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
-; GFX950-NEXT: v_and_b32_sdwa v12, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: v_lshrrev_b64 v[6:7], 24, v[6:7]
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v12, v0
+; GFX950-NEXT: v_bitop3_b16 v1, v1, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v11, v12, v11
+; GFX950-NEXT: v_sub_u16_e32 v12, 2, v12
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v15, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_add_u16_e32 v11, 6, v11
+; GFX950-NEXT: v_bitop3_b16 v10, v10, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v1
-; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v1, v11, v1, v14 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v11
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v14, v9, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, v15, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v12, v1, v10 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v1, v13, v1
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
-; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_and_b32_sdwa v15, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v1, v12, v1, v11 bitop3:0xfe
-; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX950-NEXT: v_frexp_mant_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v14, v1, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v11
+; GFX950-NEXT: v_lshrrev_b64 v[6:7], 24, v[6:7]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
-; GFX950-NEXT: v_bitop3_b16 v3, v9, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v3
-; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v9
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v14, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_and_b32_e32 v14, 63, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v11
; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 6, v9
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v3, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v10, v10, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v10, v12, v10
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v3, v9, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v12, v13, v12
+; GFX950-NEXT: v_add_u16_e32 v12, 6, v12
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v14, 3, v12
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_bitop3_b16 v10, v15, v10, v14 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e64 v14, v9, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v14, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_bitop3_b16 v11, v11, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v0
-; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v11 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v9
-; GFX950-NEXT: v_and_b32_e32 v9, 63, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v9, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v11, v9, v14 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v9, v13, v9
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: v_bitop3_b16 v3, v9, v3, v11 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v3, v13, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
-; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
-; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
-; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v15, v3, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
@@ -614,363 +605,372 @@ define <5 x i8> @to_fp8_v5f16(<5 x half> %x) {
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v2.h
; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
-; GFX1200-NEXT: v_and_b16 v6.h, 0x3ff, v3.h
; GFX1200-NEXT: v_and_b16 v7.l, v3.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v5.h
+; GFX1200-NEXT: v_and_b16 v6.h, 0x3ff, v3.h
; GFX1200-NEXT: v_and_b16 v9.l, v4.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v5.h
; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
-; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v6.h
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, 7, v6.h
+; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v6.h
; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_min_u16 v8.l, v8.l, 15
-; GFX1200-NEXT: v_and_b16 v11.l, v6.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v10.l, v9.h, 1
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v8.h, 1
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, v8.l, 1 clamp
+; GFX1200-NEXT: v_min_u16 v8.l, v8.l, 15
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, v8.h, 1
; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v10.l
-; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v7.h
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v11.l, v8.l, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v5.l, v6.h
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.l
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_and_b16 v7.l, v6.h, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v8.h, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v9.h, v3.h
; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
-; GFX1200-NEXT: v_and_b16 v10.h, v10.l, v10.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, v8.h, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, v11.l, 1
; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v6.h, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v8.l, v7.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v9.l, 1
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v1.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v5.l, v11.h, 1
-; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
-; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v6.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v8.l, v10.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
+; GFX1200-NEXT: v_and_b16 v7.l, v10.h, v7.l
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_and_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v13.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_and_b16 v6.h, v10.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
-; GFX1200-NEXT: v_and_b16 v10.l, v7.l, v10.h
-; GFX1200-NEXT: v_and_b16 v10.h, v7.h, 1
-; GFX1200-NEXT: v_or_b16 v5.l, v11.l, v5.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, v9.l, v7.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v10.l
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
-; GFX1200-NEXT: v_and_b16 v5.l, v8.h, v5.l
-; GFX1200-NEXT: v_and_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s1
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, vcc_lo
-; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v14.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.l, v6.h
; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v11.h, v5.l
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v10.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v8.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v3.l
+; GFX1200-NEXT: v_or_b16 v7.l, v8.l, v8.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v11.l, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v7.l
+; GFX1200-NEXT: v_or_b16 v7.l, v9.l, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s0
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v15.l
+; GFX1200-NEXT: v_or_b16 v8.h, v4.l, v8.h
; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v8.h
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_and_b16 v7.l, v8.l, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s0
+; GFX1200-NEXT: v_or_b16 v7.h, v4.l, v9.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v3.l, 2, v6.l
+; GFX1200-NEXT: v_or_b16 v3.h, v8.h, v3.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.h
+; GFX1200-NEXT: v_and_b16 v7.l, v9.l, v7.l
+; GFX1200-NEXT: v_or_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 24, v2
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, s1
-; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
-; GFX1200-NEXT: v_or_b16 v7.h, v4.l, v7.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v2
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v6.h, v7.l
-; GFX1200-NEXT: v_min_u16 v6.h, v9.h, 15
-; GFX1200-NEXT: v_or_b16 v5.l, v7.h, v5.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 7, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.l, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.h, v7.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v1.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v6.h, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v6.h, vcc_lo
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v3.l, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v8.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
+; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s1
+; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s1
+; GFX1200-NEXT: v_and_b16 v8.l, v9.l, v8.l
+; GFX1200-NEXT: v_or_b16 v8.h, v9.h, v8.h
+; GFX1200-NEXT: v_or_b16 v4.l, v9.h, v4.l
; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, 6
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v7.l, 1
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s2
-; GFX1200-NEXT: v_or_b16 v7.h, v8.l, v7.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v5.l
-; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, s1
-; GFX1200-NEXT: v_or_b16 v3.l, v7.h, v3.l
-; GFX1200-NEXT: v_or_b16 v9.h, v8.l, v9.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.l
-; GFX1200-NEXT: v_and_b16 v2.l, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
-; GFX1200-NEXT: v_or_b16 v4.l, v9.h, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, v6.h, v10.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v3.h, vcc_lo
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, 63
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
-; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 1
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_or_b16 v2.l, v8.h, v5.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v4.l, v4.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v3.l, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v8.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v2.h, v2.h
-; GFX1200-NEXT: v_or_b16 v3.h, v5.l, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v10.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v1.h
-; GFX1200-NEXT: v_and_b16 v5.l, v7.h, 1
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v7.l, v9.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.h
+; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, s0
-; GFX1200-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX1200-NEXT: v_and_b16 v3.h, v4.l, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v7.l
-; GFX1200-NEXT: v_or_b16 v5.l, v9.l, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v3.l, 8, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v4.l, v2.l, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, 7, v7.h
+; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, v6.h, 63
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
-; GFX1200-NEXT: v_min_u16 v2.h, v4.l, 15
-; GFX1200-NEXT: v_and_b16 v4.l, v5.h, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v1.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v4.h, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v2.h, 1 clamp
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.h, v4.l
-; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, v5.h, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
-; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, -1
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v9.h, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_and_b16 v4.l, v5.h, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.l, v1.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
+; GFX1200-NEXT: v_and_b16 v5.h, v3.l, 1
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.h, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, v2.h, v7.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_and_b16 v6.h, v7.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v9.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v11.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v5.l
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v2.h, v1.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
-; GFX1200-NEXT: v_and_b16 v6.h, v4.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_min_u16 v7.l, v7.h, 15
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_and_b16 v9.l, v2.h, 63
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: v_or_b16 v5.h, v8.l, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, v7.l, 1 clamp
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v5.h, v6.h, v5.h
+; GFX1200-NEXT: v_and_b16 v6.h, 0x3ff, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v4.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
-; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v6.h
-; GFX1200-NEXT: v_or_b16 v7.h, v8.h, v8.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v6.l
; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
-; GFX1200-NEXT: v_or_b16 v3.h, v7.h, v3.h
-; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v10.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v4.h, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v8.l
-; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v6.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v9.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
-; GFX1200-NEXT: v_or_b16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s0
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v5.h
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v6.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, 6, v2.h
+; GFX1200-NEXT: v_and_b16 v7.h, v8.l, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v5.h, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v7.l, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.h
+; GFX1200-NEXT: v_and_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_and_b16 v5.h, 0x80, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v4.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v7.h, v9.l, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: v_and_b16 v2.h, v2.h, v7.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v6.l
+; GFX1200-NEXT: v_or_b16 v8.h, v5.h, v8.h
+; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v6.h, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v4.l, v3.h, s0
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.h, v5.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v6.h, v5.h, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, 2, v7.h
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v9.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
+; GFX1200-NEXT: v_min_u16 v7.l, v7.l, 15
+; GFX1200-NEXT: v_or_b16 v3.l, v6.h, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v0.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.h, v8.l, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v0.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v7.l, 1 clamp
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.h, v4.h
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 24, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v8.h, 1
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v6.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v10.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v1
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_and_b16 v10.l, 0x80, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, 6
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v8.h, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.l, v9.l
-; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v5.h
; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s1
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v5.l
+; GFX1200-NEXT: v_and_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v9.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s0
-; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v6.l
-; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.l, v9.h
-; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b16 v4.l, v10.l, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v0.h
-; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
-; GFX1200-NEXT: v_and_b16 v4.l, v10.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v11.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v5.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
+; GFX1200-NEXT: v_min_u16 v1.l, v5.h, 15
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v0.h
+; GFX1200-NEXT: v_or_b16 v4.h, v5.l, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v8.h, v9.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.h
-; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v7.h
-; GFX1200-NEXT: v_or_b16 v4.l, v6.l, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v9.h
+; GFX1200-NEXT: v_and_b16 v8.h, v6.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v1.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v2.h, v10.l, vcc_lo
-; GFX1200-NEXT: v_min_u16 v2.h, v4.h, 15
-; GFX1200-NEXT: v_and_b16 v4.h, v5.h, 63
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v0.h
-; GFX1200-NEXT: v_and_b16 v4.l, v6.l, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, v2.h, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v7.l
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, v6.l, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_and_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v10.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_and_b16 v9.h, v5.h, 63
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v7.l, 1
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v8.h, v5.l, 1
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v8.h
+; GFX1200-NEXT: v_and_b16 v9.l, v10.l, v9.l
+; GFX1200-NEXT: v_and_b16 v9.h, v6.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_and_b16 v7.l, v9.h, v7.l
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
-; GFX1200-NEXT: v_and_b16 v9.l, v4.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v11.l, v2.h, v9.h
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v8.h
-; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v9.h
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, v1.l, v10.l
+; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v9.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.h, v1.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v4.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v4.l, v5.l, v7.l
-; GFX1200-NEXT: v_and_b16 v8.h, v11.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.h, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.h, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v2.h
-; GFX1200-NEXT: v_or_b16 v5.h, v9.l, v8.h
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
-; GFX1200-NEXT: v_and_b16 v4.h, v6.l, v5.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v1.h
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v4.l, v4.h
+; GFX1200-NEXT: v_and_b16 v4.h, v5.h, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.l, v6.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v7.l, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v6.l, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.l
+; GFX1200-NEXT: v_or_b16 v5.l, v11.l, v8.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s3
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s4
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v4.h, s2
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 8, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v11.l, v2.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v8.l, v6.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v7.h, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v4.h, v5.h, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s3
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s2
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v9.l
; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
-; GFX1200-NEXT: v_and_b16 v4.h, 0x80, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s1
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v8.l, v7.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 24, v0
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v4.h
+; GFX1200-NEXT: v_or_b16 v6.l, v5.l, v6.l
; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x80, v8.l
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, s2
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v5.h
-; GFX1200-NEXT: v_or_b16 v6.l, v4.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s2
; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s2
-; GFX1200-NEXT: v_or_b16 v7.h, v8.l, v7.h
-; GFX1200-NEXT: v_or_b16 v7.l, v4.h, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s3
; GFX1200-NEXT: v_or_b16 v1.h, v6.l, v1.h
+; GFX1200-NEXT: v_or_b16 v7.h, v8.l, v7.h
+; GFX1200-NEXT: v_or_b16 v4.l, v7.l, v4.l
; GFX1200-NEXT: v_or_b16 v8.h, v8.l, v8.h
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
-; GFX1200-NEXT: v_or_b16 v2.h, v7.h, v2.h
-; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v5.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v5.h
; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.h
-; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v5.l, v1.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v4.h, v7.h, v4.h
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_or_b16 v1.l, v8.h, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s2
-; GFX1200-NEXT: v_or_b16 v4.l, v2.l, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s1
+; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.h, 8, v2.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v4.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, vcc_lo
; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v2.h, v8.l, s0
-; GFX1200-NEXT: v_or_b16 v2.h, v3.h, v1.l
+; GFX1200-NEXT: v_or_b16 v4.l, v3.h, v2.l
+; GFX1200-NEXT: v_or_b16 v2.h, v3.l, v2.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.l, v8.l, s0
; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.h, v0.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v1.h, vcc_lo
@@ -1062,312 +1062,302 @@ define <6 x i8> @to_fp8_v6f16(<6 x half> %x) {
; GFX950-LABEL: to_fp8_v6f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v2
-; GFX950-NEXT: v_sub_u16_e32 v7, 2, v6
; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v2
+; GFX950-NEXT: v_and_b32_e32 v5, 0x3ff, v4
+; GFX950-NEXT: v_and_b32_e32 v8, 63, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 7, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v6, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v7, v2
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v7, v6
+; GFX950-NEXT: v_sub_u16_e32 v7, 2, v7
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_sub_u16_e64 v11, v7, 1 clamp
+; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v11, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v6
+; GFX950-NEXT: v_and_b32_sdwa v9, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_bitop3_b16 v8, v9, v3, v8 bitop3:0xfe
; GFX950-NEXT: v_mov_b32_e32 v3, 0x3ff
-; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
-; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v10, v7, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, v7, v5
-; GFX950-NEXT: v_lshrrev_b16_e32 v5, v10, v5
-; GFX950-NEXT: v_lshlrev_b16_e64 v10, v10, 1
-; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v4
-; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
-; GFX950-NEXT: v_bitop3_b16 v10, v11, v10, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
-; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
-; GFX950-NEXT: s_movk_i32 s1, 0x80
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v5, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v4, v4, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v7, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v11, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v11
-; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
-; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v8, v5
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; GFX950-NEXT: v_and_b32_sdwa v8, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_or_b32_e32 v5, v5, v10
+; GFX950-NEXT: v_and_b32_sdwa v12, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v5 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v4, v10, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
; GFX950-NEXT: s_movk_i32 s2, 0xff
-; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v7 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v4
-; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
; GFX950-NEXT: s_mov_b32 s3, 0x7f7f0000
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v10 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v4, v9, v4
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v6, v7
-; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v6
-; GFX950-NEXT: v_bitop3_b16 v4, v8, v4, v7 bitop3:0xfe
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v5 bitop3:0xfe
; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v7, v6, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v6
; GFX950-NEXT: v_mov_b32_e32 v5, 0x7f
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
-; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
-; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
-; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v6
+; GFX950-NEXT: v_and_b32_e32 v11, 63, v6
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v2, v2
-; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v6
; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_bitop3_b16 v6, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v7, v9, v7
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
-; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v2
-; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v10, v9
+; GFX950-NEXT: v_sub_u16_e32 v10, 2, v10
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v13, 1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v14, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v6
-; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v12 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v12, v7, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_or_b32_e32 v8, v8, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v10, v6, v8 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_and_b32_sdwa v13, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_bitop3_b16 v6, v10, v6, v9 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
; GFX950-NEXT: v_mov_b32_e32 v8, 0
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v9, v1
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v2, v8 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v2, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v10, 2, v9
-; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX950-NEXT: v_bitop3_b16 v4, v4, v2, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v2, v1
-; GFX950-NEXT: v_bitop3_b16 v6, v2, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
-; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
-; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v2
-; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
-; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
-; GFX950-NEXT: v_or_b32_sdwa v7, v4, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v6, v13, v12 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v14
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
-; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v2
+; GFX950-NEXT: v_and_b32_e32 v12, 63, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v2
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v10, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
-; GFX950-NEXT: v_and_b32_sdwa v11, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v11, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v2, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v11, v10
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v11
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v15, v14, 1
+; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v15, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v10 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, 6, v2
-; GFX950-NEXT: v_and_b32_e32 v2, 63, v2
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v13 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v10
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_bitop3_b16 v6, v13, v6, v12 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_or_b32_e32 v9, v9, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v14, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v9 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v2, v12, v2
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v9, v9, v10
-; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_and_b32_sdwa v14, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_or_b32_sdwa v7, v4, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v10, 3, v9
-; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v10 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v13, v2, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v9, v6, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc
-; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
-; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
-; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v6
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v6
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v13, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_and_b32_e32 v13, 63, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v10
; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v6
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v9, v11, v9
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v1
-; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v6, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v11, v12, v11
+; GFX950-NEXT: v_sub_u16_e32 v12, 2, v12
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v15, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_add_u16_e32 v11, 6, v11
+; GFX950-NEXT: v_bitop3_b16 v10, v10, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v6
-; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v14 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v11
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v14, v9, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v15, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v10 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v6, v13, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
-; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
-; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v11 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v0
-; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v14, v6, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v11
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v8 src0_sel:WORD_1 src1_sel:DWORD
-; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
-; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
-; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
-; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_and_b32_sdwa v14, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX950-NEXT: v_bitop3_b16 v2, v2, v1, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
-; GFX950-NEXT: v_bitop3_b16 v9, v1, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v1
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
-; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v1
+; GFX950-NEXT: v_and_b32_e32 v13, 63, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v10
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v9, v11, v9
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
-; GFX950-NEXT: v_and_b32_sdwa v12, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v12, v0
+; GFX950-NEXT: v_bitop3_b16 v1, v1, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v11, v12, v11
+; GFX950-NEXT: v_sub_u16_e32 v12, 2, v12
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v15, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_add_u16_e32 v11, 6, v11
+; GFX950-NEXT: v_bitop3_b16 v10, v10, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v1
-; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v1, v11, v1, v14 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v11
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v14, v9, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, v15, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v12, v1, v10 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v1, v13, v1
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
-; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_and_b32_sdwa v15, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v1, v12, v1, v11 bitop3:0xfe
-; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX950-NEXT: v_frexp_mant_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v14, v1, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v11
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
-; GFX950-NEXT: v_bitop3_b16 v3, v9, s0, v3 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v3
-; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v9
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v14, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_and_b32_e32 v14, 63, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v11
; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 6, v9
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v3, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v10, v10, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v10, v12, v10
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v13, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v3, v9, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v12, v13, v12
+; GFX950-NEXT: v_add_u16_e32 v12, 6, v12
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v14, 3, v12
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_bitop3_b16 v10, v15, v10, v14 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e64 v14, v9, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v14, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_bitop3_b16 v11, v11, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v0
-; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v11 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v9
-; GFX950-NEXT: v_and_b32_e32 v9, 63, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v9, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v9, v11, v9, v14 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v9, v13, v9
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: v_bitop3_b16 v3, v9, v3, v11 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v3, v13, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
-; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
-; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
-; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v15, v3, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
@@ -1393,363 +1383,372 @@ define <6 x i8> @to_fp8_v6f16(<6 x half> %x) {
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v2.h
; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
-; GFX1200-NEXT: v_and_b16 v6.h, 0x3ff, v3.h
; GFX1200-NEXT: v_and_b16 v7.l, v3.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v5.h
+; GFX1200-NEXT: v_and_b16 v6.h, 0x3ff, v3.h
; GFX1200-NEXT: v_and_b16 v9.l, v4.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v5.h
; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
-; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v6.h
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, 7, v6.h
+; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v6.h
; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_min_u16 v8.l, v8.l, 15
-; GFX1200-NEXT: v_and_b16 v11.l, v6.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v10.l, v9.h, 1
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v8.h, 1
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, v8.l, 1 clamp
+; GFX1200-NEXT: v_min_u16 v8.l, v8.l, 15
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, v8.h, 1
; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v10.l
-; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v7.h
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v11.l, v8.l, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v5.l, v6.h
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.l
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_and_b16 v7.l, v6.h, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v8.h, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v9.h, v3.h
; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
-; GFX1200-NEXT: v_and_b16 v10.h, v10.l, v10.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, v8.h, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, v11.l, 1
; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v6.h, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v8.l, v7.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v9.l, 1
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v1.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v5.l, v11.h, 1
-; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
-; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v6.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v8.l, v10.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
+; GFX1200-NEXT: v_and_b16 v7.l, v10.h, v7.l
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_and_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v13.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_and_b16 v6.h, v10.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
-; GFX1200-NEXT: v_and_b16 v10.l, v7.l, v10.h
-; GFX1200-NEXT: v_and_b16 v10.h, v7.h, 1
-; GFX1200-NEXT: v_or_b16 v5.l, v11.l, v5.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, v9.l, v7.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v10.l
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
-; GFX1200-NEXT: v_and_b16 v5.l, v8.h, v5.l
-; GFX1200-NEXT: v_and_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s1
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, vcc_lo
-; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v14.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.l, v6.h
; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v11.h, v5.l
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v10.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v8.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v3.l
+; GFX1200-NEXT: v_or_b16 v7.l, v8.l, v8.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v11.l, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v7.l
+; GFX1200-NEXT: v_or_b16 v7.l, v9.l, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s0
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v15.l
+; GFX1200-NEXT: v_or_b16 v8.h, v4.l, v8.h
; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v8.h
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_and_b16 v7.l, v8.l, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s0
+; GFX1200-NEXT: v_or_b16 v7.h, v4.l, v9.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v3.l, 2, v6.l
+; GFX1200-NEXT: v_or_b16 v3.h, v8.h, v3.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.h
+; GFX1200-NEXT: v_and_b16 v7.l, v9.l, v7.l
+; GFX1200-NEXT: v_or_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 24, v2
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, s1
-; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
-; GFX1200-NEXT: v_or_b16 v7.h, v4.l, v7.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v2
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v6.h, v7.l
-; GFX1200-NEXT: v_min_u16 v6.h, v9.h, 15
-; GFX1200-NEXT: v_or_b16 v5.l, v7.h, v5.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 7, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.l, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.h, v7.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v1.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v6.h, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v6.h, vcc_lo
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v3.l, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v8.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
+; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s1
+; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s1
+; GFX1200-NEXT: v_and_b16 v8.l, v9.l, v8.l
+; GFX1200-NEXT: v_or_b16 v8.h, v9.h, v8.h
+; GFX1200-NEXT: v_or_b16 v4.l, v9.h, v4.l
; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, 6
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v7.l, 1
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s2
-; GFX1200-NEXT: v_or_b16 v7.h, v8.l, v7.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v5.l
-; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, s1
-; GFX1200-NEXT: v_or_b16 v3.l, v7.h, v3.l
-; GFX1200-NEXT: v_or_b16 v9.h, v8.l, v9.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.l
-; GFX1200-NEXT: v_and_b16 v2.l, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
-; GFX1200-NEXT: v_or_b16 v4.l, v9.h, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, v6.h, v10.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v3.h, vcc_lo
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, 63
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
-; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 1
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_or_b16 v2.l, v8.h, v5.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v4.l, v4.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v3.l, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v8.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v2.h, v2.h
-; GFX1200-NEXT: v_or_b16 v3.h, v5.l, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v10.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v1.h
-; GFX1200-NEXT: v_and_b16 v5.l, v7.h, 1
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v7.l, v9.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.h
+; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, s0
-; GFX1200-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX1200-NEXT: v_and_b16 v3.h, v4.l, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v7.l
-; GFX1200-NEXT: v_or_b16 v5.l, v9.l, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v3.l, 8, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v4.l, v2.l, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, 7, v7.h
+; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, v6.h, 63
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
-; GFX1200-NEXT: v_min_u16 v2.h, v4.l, 15
-; GFX1200-NEXT: v_and_b16 v4.l, v5.h, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v1.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v4.h, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v2.h, 1 clamp
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.h, v4.l
-; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, v5.h, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
-; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, -1
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v9.h, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_and_b16 v4.l, v5.h, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.l, v1.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
+; GFX1200-NEXT: v_and_b16 v5.h, v3.l, 1
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.h, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, v2.h, v7.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_and_b16 v6.h, v7.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v9.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v11.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v5.l
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v2.h, v1.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
-; GFX1200-NEXT: v_and_b16 v6.h, v4.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_min_u16 v7.l, v7.h, 15
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_and_b16 v9.l, v2.h, 63
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: v_or_b16 v5.h, v8.l, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, v7.l, 1 clamp
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v5.h, v6.h, v5.h
+; GFX1200-NEXT: v_and_b16 v6.h, 0x3ff, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v4.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
-; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v6.h
-; GFX1200-NEXT: v_or_b16 v7.h, v8.h, v8.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v6.l
; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
-; GFX1200-NEXT: v_or_b16 v3.h, v7.h, v3.h
-; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v10.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v4.h, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v8.l
-; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v6.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v9.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
-; GFX1200-NEXT: v_or_b16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s0
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v5.h
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v6.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, 6, v2.h
+; GFX1200-NEXT: v_and_b16 v7.h, v8.l, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v5.h, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v7.l, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.h
+; GFX1200-NEXT: v_and_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_and_b16 v5.h, 0x80, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v4.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v7.h, v9.l, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: v_and_b16 v2.h, v2.h, v7.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v6.l
+; GFX1200-NEXT: v_or_b16 v8.h, v5.h, v8.h
+; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v6.h, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v4.l, v3.h, s0
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.h, v5.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v6.h, v5.h, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, 2, v7.h
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v9.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
+; GFX1200-NEXT: v_min_u16 v7.l, v7.l, 15
+; GFX1200-NEXT: v_or_b16 v3.l, v6.h, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v0.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.h, v8.l, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v0.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v7.l, 1 clamp
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.h, v4.h
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 24, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v8.h, 1
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v6.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v10.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v1
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_and_b16 v10.l, 0x80, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, 6
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v8.h, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.l, v9.l
-; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v5.h
; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s1
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v5.l
+; GFX1200-NEXT: v_and_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v9.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s0
-; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v6.l
-; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.l, v9.h
-; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b16 v4.l, v10.l, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v0.h
-; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
-; GFX1200-NEXT: v_and_b16 v4.l, v10.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v11.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v5.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
+; GFX1200-NEXT: v_min_u16 v1.l, v5.h, 15
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v0.h
+; GFX1200-NEXT: v_or_b16 v4.h, v5.l, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v8.h, v9.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.h
-; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v7.h
-; GFX1200-NEXT: v_or_b16 v4.l, v6.l, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v9.h
+; GFX1200-NEXT: v_and_b16 v8.h, v6.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v1.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v2.h, v10.l, vcc_lo
-; GFX1200-NEXT: v_min_u16 v2.h, v4.h, 15
-; GFX1200-NEXT: v_and_b16 v4.h, v5.h, 63
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v0.h
-; GFX1200-NEXT: v_and_b16 v4.l, v6.l, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, v2.h, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v7.l
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, v6.l, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_and_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v10.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_and_b16 v9.h, v5.h, 63
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v7.l, 1
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v8.h, v5.l, 1
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v8.h
+; GFX1200-NEXT: v_and_b16 v9.l, v10.l, v9.l
+; GFX1200-NEXT: v_and_b16 v9.h, v6.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_and_b16 v7.l, v9.h, v7.l
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
-; GFX1200-NEXT: v_and_b16 v9.l, v4.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v11.l, v2.h, v9.h
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v8.h
-; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v9.h
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, v1.l, v10.l
+; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v9.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.h, v1.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v4.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v4.l, v5.l, v7.l
-; GFX1200-NEXT: v_and_b16 v8.h, v11.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.h, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.h, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v2.h
-; GFX1200-NEXT: v_or_b16 v5.h, v9.l, v8.h
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
-; GFX1200-NEXT: v_and_b16 v4.h, v6.l, v5.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v1.h
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v4.l, v4.h
+; GFX1200-NEXT: v_and_b16 v4.h, v5.h, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.l, v6.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v7.l, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v6.l, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.l
+; GFX1200-NEXT: v_or_b16 v5.l, v11.l, v8.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s3
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s4
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v4.h, s2
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 8, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v11.l, v2.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v8.l, v6.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v7.h, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v4.h, v5.h, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s3
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s2
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v9.l
; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
-; GFX1200-NEXT: v_and_b16 v4.h, 0x80, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s1
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v8.l, v7.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 24, v0
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v4.h
+; GFX1200-NEXT: v_or_b16 v6.l, v5.l, v6.l
; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x80, v8.l
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, s2
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v5.h
-; GFX1200-NEXT: v_or_b16 v6.l, v4.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s2
; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s2
-; GFX1200-NEXT: v_or_b16 v7.h, v8.l, v7.h
-; GFX1200-NEXT: v_or_b16 v7.l, v4.h, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s3
; GFX1200-NEXT: v_or_b16 v1.h, v6.l, v1.h
+; GFX1200-NEXT: v_or_b16 v7.h, v8.l, v7.h
+; GFX1200-NEXT: v_or_b16 v4.l, v7.l, v4.l
; GFX1200-NEXT: v_or_b16 v8.h, v8.l, v8.h
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
-; GFX1200-NEXT: v_or_b16 v2.h, v7.h, v2.h
-; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v5.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v5.h
; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.h
-; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v5.l, v1.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v4.h, v7.h, v4.h
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_or_b16 v1.l, v8.h, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s2
-; GFX1200-NEXT: v_or_b16 v4.l, v2.l, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s1
+; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.h, 8, v2.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v4.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, vcc_lo
; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v2.h, v8.l, s0
-; GFX1200-NEXT: v_or_b16 v2.h, v3.h, v1.l
+; GFX1200-NEXT: v_or_b16 v4.l, v3.h, v2.l
+; GFX1200-NEXT: v_or_b16 v2.h, v3.l, v2.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.l, v8.l, s0
; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.h, v0.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v1.h, vcc_lo
@@ -1763,10 +1762,10 @@ define <6 x i8> @to_fp8_v6f16(<6 x half> %x) {
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
; GFX1200-NEXT: v_lshrrev_b64 v[7:8], 24, v[5:6]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v7.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
@@ -1845,421 +1844,404 @@ define <7 x i8> @to_fp8_v7f16(<7 x half> %x) {
; GFX950-LABEL: to_fp8_v7f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v3
-; GFX950-NEXT: v_sub_u16_e32 v8, 2, v6
; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v3
+; GFX950-NEXT: v_and_b32_e32 v6, 0x3ff, v4
+; GFX950-NEXT: v_and_b32_e32 v9, 63, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 7, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v5, v7, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v8, v3
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v8, v7
+; GFX950-NEXT: v_sub_u16_e32 v8, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
+; GFX950-NEXT: v_sub_u16_e64 v12, v8, 1 clamp
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v7
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v12, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v9
+; GFX950-NEXT: v_and_b32_sdwa v10, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_bitop3_b16 v5, v10, v5, v7 bitop3:0xfe
; GFX950-NEXT: v_mov_b32_e32 v7, 0x3ff
-; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
-; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v11, v8, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v5
-; GFX950-NEXT: v_lshrrev_b16_e32 v5, v11, v5
-; GFX950-NEXT: v_lshlrev_b16_e64 v11, v11, 1
-; GFX950-NEXT: v_and_b32_e32 v12, 0x3ff, v4
-; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
-; GFX950-NEXT: v_bitop3_b16 v11, v12, v11, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
-; GFX950-NEXT: s_movk_i32 s1, 0x80
-; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v5, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v13, s0 bitop3:0xc8
+; GFX950-NEXT: v_bitop3_b16 v4, v4, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v8, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v12, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
-; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v12
-; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
-; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v9, v5
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; GFX950-NEXT: v_and_b32_sdwa v9, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_movk_i32 s2, 0xff
-; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v8 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v4
-; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v8, v4, v11 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v4, v10, v4
+; GFX950-NEXT: v_or_b32_e32 v6, v6, v11
+; GFX950-NEXT: v_and_b32_sdwa v13, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v8, v4, v6 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v4, v11, v4
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: v_mov_b32_e32 v10, 0x7f
+; GFX950-NEXT: s_movk_i32 s2, 0xff
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v6, v8
-; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v6
-; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v8 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v6 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3
; GFX950-NEXT: v_frexp_mant_f16_sdwa v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v6, v5, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
-; GFX950-NEXT: v_sub_u16_e64 v13, v9, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, v9, v6
-; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
-; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
-; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v5
-; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v5
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX950-NEXT: v_mov_b32_e32 v10, 0x7f
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v3, v3
-; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_and_b32_e32 v12, 63, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v8
; GFX950-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v6, v13, v12 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v5
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v9, v6
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
-; GFX950-NEXT: v_lshrrev_b32_e32 v11, 31, v3
-; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v11
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v5, v5, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v11, v9
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v11
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v15, v14, 1
+; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v15, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v5
-; GFX950-NEXT: v_and_b32_e32 v5, 63, v5
-; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v14
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v11
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v13 bitop3:0xe0
-; GFX950-NEXT: v_add_u16_e32 v5, v11, v5
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_bitop3_b16 v6, v13, v6, v12 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_or_b32_e32 v8, v8, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v14, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v11, v5, v8 bitop3:0x80
+; GFX950-NEXT: v_add_u16_e32 v5, v12, v5
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
; GFX950-NEXT: v_mov_b32_e32 v11, 0
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_bitop3_b16 v5, v12, v5, v9 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v13, v5, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v3, v11 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v3, v3 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_and_b32_sdwa v13, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v2
; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX950-NEXT: v_sub_u16_e32 v8, 2, v5
; GFX950-NEXT: v_bitop3_b16 v6, v4, v3, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v3, v2
-; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
-; GFX950-NEXT: v_bitop3_b16 v4, v3, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v13, v8, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v4
-; GFX950-NEXT: v_lshrrev_b16_e32 v4, v13, v4
-; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
-; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v3
-; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
-; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
-; GFX950-NEXT: v_and_b32_e32 v12, 1, v9
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v4, v13, v12 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v14
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
-; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX950-NEXT: v_add_u16_e32 v4, v9, v4
+; GFX950-NEXT: v_and_b32_e32 v5, 0x3ff, v3
+; GFX950-NEXT: v_and_b32_e32 v12, 63, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v12, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v8, v4
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
-; GFX950-NEXT: v_and_b32_sdwa v9, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v9, v2
+; GFX950-NEXT: v_bitop3_b16 v3, v3, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v9, v8
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v9
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_sub_u16_e64 v14, v9, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v15, v14, 1
+; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v15, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v8 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v3
-; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v8, v3, v13 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_bitop3_b16 v4, v13, v4, v12 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v9, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_or_b32_e32 v5, v5, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v9, v3, v5 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v5, v8
-; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v5
-; GFX950-NEXT: v_bitop3_b16 v3, v9, v3, v8 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_sdwa v14, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v13, v3, v5 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
; GFX950-NEXT: v_frexp_mant_f16_sdwa v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
-; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
-; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
-; GFX950-NEXT: v_sub_u16_e64 v14, v9, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v9, v5
-; GFX950-NEXT: v_lshrrev_b16_e32 v5, v14, v5
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v4
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v4
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v2, v2
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_and_b32_e32 v13, 63, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v8
; GFX950-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v5, v14, v13 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v12, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v5, v9, v5
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v2
-; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v12, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v4, v4, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_sub_u16_e32 v12, 2, v12
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v15, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v12, v5, v9 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v4
-; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v14 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_bitop3_b16 v5, v14, v5, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_or_b32_e32 v8, v8, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v15, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v12, v4, v8 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v4, v13, v4
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
-; GFX950-NEXT: v_bitop3_b16 v4, v12, v4, v9 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v14, v4, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v2, v11 src0_sel:WORD_1 src1_sel:DWORD
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v1
-; GFX950-NEXT: v_sub_u16_e32 v8, 2, v5
-; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v2, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
-; GFX950-NEXT: v_sub_u16_e64 v14, v8, 1 clamp
+; GFX950-NEXT: v_and_b32_sdwa v14, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX950-NEXT: v_bitop3_b16 v4, v3, v2, s2 bitop3:0xec
; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; GFX950-NEXT: v_or_b32_sdwa v9, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX950-NEXT: v_frexp_mant_f16_e32 v2, v1
-; GFX950-NEXT: v_bitop3_b16 v3, v2, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, v8, v3
-; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
-; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
-; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v2
-; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
-; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
-; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v3, v14, v13 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
-; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
+; GFX950-NEXT: v_and_b32_e32 v5, 0x3ff, v2
+; GFX950-NEXT: v_and_b32_e32 v13, 63, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, 6, v2
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v8, v3
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: v_and_b32_sdwa v12, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v12, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v2, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v12, v8
+; GFX950-NEXT: v_sub_u16_e32 v12, 2, v12
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v15, 1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v16, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v8 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v2
-; GFX950-NEXT: v_and_b32_e32 v2, 63, v2
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v2, v8, v2, v14 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v14, v3, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_or_b32_e32 v5, v5, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v15, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v12, v2, v5 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v2, v13, v2
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v5, v8
-; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
-; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v5
-; GFX950-NEXT: v_bitop3_b16 v2, v12, v2, v8 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_sdwa v15, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v14, v2, v5 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
; GFX950-NEXT: v_frexp_mant_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v5, v3, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
-; GFX950-NEXT: v_sub_u16_e32 v12, 2, v8
-; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
-; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v5
-; GFX950-NEXT: v_lshrrev_b16_e32 v5, v15, v5
-; GFX950-NEXT: v_lshlrev_b16_e64 v15, v15, 1
-; GFX950-NEXT: v_and_b32_e32 v16, 0x3ff, v3
-; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v3
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
-; GFX950-NEXT: v_bitop3_b16 v15, v16, v15, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_and_b32_e32 v14, 63, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v8
; GFX950-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v15
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v5, v15, v14 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
-; GFX950-NEXT: v_lshrrev_b16_e32 v14, 7, v16
-; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
-; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
-; GFX950-NEXT: v_add_u16_e32 v5, v13, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v5, v12, v5
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; GFX950-NEXT: v_lshrrev_b32_e32 v13, 31, v1
-; GFX950-NEXT: v_lshlrev_b16_e32 v13, 7, v13
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v3, v3, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v12, v13, v12
+; GFX950-NEXT: v_sub_u16_e32 v13, 2, v13
+; GFX950-NEXT: v_min_u16_e32 v13, 15, v13
+; GFX950-NEXT: v_sub_u16_e64 v16, v13, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v17, v16, 1
+; GFX950-NEXT: v_add_u16_e32 v17, -1, v17
+; GFX950-NEXT: v_add_u16_e32 v12, 6, v12
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v17, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v5, v13, v5, v12 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v12, 6, v3
-; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v15 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v14, 3, v12
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_bitop3_b16 v5, v15, v5, v14 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, v13, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_or_b32_e32 v8, v8, v14
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v16, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v13, v3, v8 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v3, v14, v3
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v8, v8, v12
-; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
-; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v8
-; GFX950-NEXT: v_bitop3_b16 v3, v13, v3, v12 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v12, v0
+; GFX950-NEXT: v_and_b32_sdwa v16, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v15, v3, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v11 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: v_lshrrev_b32_e32 v5, 8, v9
; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX950-NEXT: v_sub_u16_e32 v13, 2, v12
-; GFX950-NEXT: v_min_u16_e32 v13, 15, v13
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX950-NEXT: v_bitop3_b16 v2, v2, v1, s2 bitop3:0xec
; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
-; GFX950-NEXT: v_bitop3_b16 v3, v1, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v16, v13, 1 clamp
-; GFX950-NEXT: v_lshrrev_b16_e32 v14, v13, v3
-; GFX950-NEXT: v_lshrrev_b16_e32 v3, v16, v3
-; GFX950-NEXT: v_lshlrev_b16_e64 v16, v16, 1
-; GFX950-NEXT: v_and_b32_e32 v17, 0x3ff, v1
-; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
-; GFX950-NEXT: v_bitop3_b16 v16, v17, v16, s0 bitop3:0xc8
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v16
-; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
-; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX950-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v3, v16, v15 bitop3:0xe0
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
-; GFX950-NEXT: v_lshrrev_b16_e32 v15, 7, v17
-; GFX950-NEXT: v_and_b32_e32 v16, 1, v15
-; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX950-NEXT: v_add_u16_e32 v3, v14, v3
+; GFX950-NEXT: v_and_b32_e32 v12, 0x3ff, v1
+; GFX950-NEXT: v_and_b32_e32 v15, 63, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v12
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v15
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v15, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v13, v3
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
-; GFX950-NEXT: v_and_b32_sdwa v14, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX950-NEXT: v_lshrrev_b64 v[8:9], 24, v[8:9]
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v14, v0
+; GFX950-NEXT: v_bitop3_b16 v1, v1, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v13, v14, v13
+; GFX950-NEXT: v_sub_u16_e32 v14, 2, v14
+; GFX950-NEXT: v_min_u16_e32 v14, 15, v14
+; GFX950-NEXT: v_sub_u16_e64 v17, v14, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v18, v17, 1
+; GFX950-NEXT: v_add_u16_e32 v18, -1, v18
+; GFX950-NEXT: v_add_u16_e32 v13, 6, v13
+; GFX950-NEXT: v_bitop3_b16 v12, v12, v18, s0 bitop3:0xc8
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v14, v3, v13 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 6, v1
-; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v1, v13, v1, v16 bitop3:0xe0
+; GFX950-NEXT: v_lshlrev_b16_e32 v15, 3, v13
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_bitop3_b16 v3, v16, v3, v15 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v15, v14, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: v_or_b32_e32 v12, v12, v15
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, v17, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v14, v1, v12 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v1, v15, v1
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v12, v12, v13
-; GFX950-NEXT: v_add_u16_e32 v12, 6, v12
+; GFX950-NEXT: v_and_b32_sdwa v17, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v12
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
-; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v12, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_bitop3_b16 v1, v14, v1, v13 bitop3:0xfe
-; GFX950-NEXT: v_sub_u16_e32 v13, 2, v12
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX950-NEXT: v_frexp_mant_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX950-NEXT: v_min_u16_e32 v13, 15, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v16, v1, v12 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v13
+; GFX950-NEXT: v_lshrrev_b64 v[8:9], 24, v[8:9]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
-; GFX950-NEXT: v_bitop3_b16 v7, v3, s0, v7 bitop3:0xec
-; GFX950-NEXT: v_sub_u16_e64 v16, v13, 1 clamp
-; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v14, vcc
-; GFX950-NEXT: v_lshrrev_b16_e32 v14, v13, v7
-; GFX950-NEXT: v_lshrrev_b16_e32 v7, v16, v7
-; GFX950-NEXT: v_lshlrev_b16_e64 v16, v16, 1
-; GFX950-NEXT: v_and_b32_e32 v17, 0x3ff, v3
-; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v3
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v16, vcc
; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; GFX950-NEXT: v_bitop3_b16 v16, v17, v16, s0 bitop3:0xc8
-; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
+; GFX950-NEXT: v_and_b32_e32 v16, 63, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, 7, v13
; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v16
-; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
; GFX950-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v7, v16, v15 bitop3:0xe0
+; GFX950-NEXT: v_bitop3_b16 v12, v12, v16, v15 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v12, v14, v12
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v12
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v3, v3, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v14, v15, v14
+; GFX950-NEXT: v_add_u16_e32 v14, 6, v14
+; GFX950-NEXT: v_sub_u16_e32 v7, 2, v15
+; GFX950-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v16, 3, v14
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_bitop3_b16 v12, v17, v12, v16 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e64 v16, v7, 1 clamp
+; GFX950-NEXT: v_lshlrev_b16_e64 v18, v16, 1
+; GFX950-NEXT: v_add_u16_e32 v18, -1, v18
+; GFX950-NEXT: v_bitop3_b16 v13, v13, v18, s0 bitop3:0xc8
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
-; GFX950-NEXT: v_lshrrev_b16_e32 v15, 7, v17
-; GFX950-NEXT: v_and_b32_e32 v16, 1, v15
-; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
-; GFX950-NEXT: v_add_u16_e32 v7, v14, v7
-; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
-; GFX950-NEXT: v_lshrrev_b32_e32 v14, 31, v0
-; GFX950-NEXT: v_lshlrev_b16_e32 v14, 7, v14
-; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 8, vcc
-; GFX950-NEXT: v_bitop3_b16 v7, v14, v7, v13 bitop3:0xfe
-; GFX950-NEXT: v_lshrrev_b16_e32 v13, 6, v3
-; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
-; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX950-NEXT: v_bitop3_b16 v3, v13, v3, v16 bitop3:0xe0
+; GFX950-NEXT: v_lshrrev_b16_e32 v15, v7, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v16, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v7, v3, v13 bitop3:0x80
; GFX950-NEXT: v_add_u16_e32 v3, v15, v3
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GFX950-NEXT: v_add_u16_e32 v12, v12, v13
-; GFX950-NEXT: v_add_u16_e32 v12, 6, v12
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
-; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v12
-; GFX950-NEXT: v_bitop3_b16 v3, v14, v3, v13 bitop3:0xfe
-; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v17, v3, v7 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v14
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc
; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v11 src0_sel:WORD_1 src1_sel:DWORD
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v14, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v10, v3, vcc
@@ -2279,492 +2261,504 @@ define <7 x i8> @to_fp8_v7f16(<7 x half> %x) {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v3.l
; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v3.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v3.h
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v3.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v3.h
; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v3.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, 2, v4.l
-; GFX1200-NEXT: v_and_b16 v8.l, v4.h, 63
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, 2, v6.h
-; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 63
-; GFX1200-NEXT: v_min_u16 v6.l, v6.l, 15
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
-; GFX1200-NEXT: v_min_u16 v9.l, v9.l, 15
-; GFX1200-NEXT: v_sub_nc_u16 v9.h, v6.l, 1 clamp
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v4.l
+; GFX1200-NEXT: v_and_b16 v7.h, v4.h, 63
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v4.h
+; GFX1200-NEXT: v_and_b16 v9.h, v6.l, 63
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, 2, v6.h
+; GFX1200-NEXT: v_min_u16 v5.h, v5.h, 15
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, v5.h, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v7.h, 1
-; GFX1200-NEXT: v_sub_nc_u16 v12.h, v9.l, 1 clamp
-; GFX1200-NEXT: v_lshlrev_b16 v11.l, v9.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.h
+; GFX1200-NEXT: v_and_b16 v11.l, v7.l, 1
+; GFX1200-NEXT: v_min_u16 v8.h, v8.h, 15
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v9.l, 1
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v6.l, v10.h
-; GFX1200-NEXT: v_add_nc_u16 v11.l, v11.l, -1
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
-; GFX1200-NEXT: v_or_b16 v6.l, v12.l, v10.l
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, v12.h, 1
-; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v8.h
-; GFX1200-NEXT: v_and_b16 v11.l, v10.h, v11.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v10.l, v10.l, -1
-; GFX1200-NEXT: v_and_b16 v6.l, v11.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v11.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v9.h, v10.h
-; GFX1200-NEXT: v_and_b16 v9.h, v8.l, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v11.l, v9.l, v8.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
-; GFX1200-NEXT: v_and_b16 v13.l, v8.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0
-; GFX1200-NEXT: v_and_b16 v9.h, v11.l, 1
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
-; GFX1200-NEXT: v_or_b16 v6.l, v12.l, v6.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v2.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v5.h, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, v8.h, 1 clamp
+; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: v_and_b16 v10.h, v10.l, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v11.h, v5.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
+; GFX1200-NEXT: v_or_b16 v10.h, v12.l, v11.l
+; GFX1200-NEXT: v_and_b16 v12.l, v8.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v11.l, v8.h, v7.h
; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
-; GFX1200-NEXT: v_and_b16 v6.l, v7.h, v6.l
-; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v13.l
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v11.h, -1
+; GFX1200-NEXT: v_or_b16 v11.h, v14.l, v12.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v10.l, v13.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v15.l
+; GFX1200-NEXT: v_and_b16 v10.h, v7.h, v10.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v11.h
+; GFX1200-NEXT: v_and_b16 v9.l, v9.l, v10.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.l, v6.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v9.h, v7.l
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v9.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v12.h, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v10.l
-; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v9.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v11.h, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v8.h, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v13.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, s0
; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
-; GFX1200-NEXT: v_and_b16 v7.h, v7.h, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, 2, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v7.l, v7.l, 0, s0
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v9.l
+; GFX1200-NEXT: v_and_b16 v5.h, v8.l, v5.h
+; GFX1200-NEXT: v_or_b16 v7.h, v5.l, v7.h
; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, v7.h, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s1
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s2
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
-; GFX1200-NEXT: v_or_b16 v8.h, v5.l, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v11.l, v7.h
-; GFX1200-NEXT: v_or_b16 v8.l, v5.l, v8.l
; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.l
-; GFX1200-NEXT: v_min_u16 v4.l, v9.l, 15
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v10.l
-; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
-; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v7.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v3
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.l, v2.l
-; GFX1200-NEXT: v_sub_nc_u16 v8.h, v4.l, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 24, v3
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.l, v5.h
+; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
+; GFX1200-NEXT: v_or_b16 v8.l, v5.l, v8.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.h, v2.l
; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, 6
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.h
+; GFX1200-NEXT: v_and_b16 v7.h, 0x80, v9.l
+; GFX1200-NEXT: v_or_b16 v4.h, v8.l, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v8.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.l, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s0
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 7, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, 0x3ff, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v8.h, 1
-; GFX1200-NEXT: v_lshlrev_b16 v11.l, 3, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v7.h, v7.h, 0, s0
-; GFX1200-NEXT: v_or_b16 v9.l, v9.h, v9.l
-; GFX1200-NEXT: v_or_b16 v11.h, 0x400, v10.l
-; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s2
-; GFX1200-NEXT: v_or_b16 v11.l, v9.h, v11.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s0
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v6.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, v6.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, v7.l, vcc_lo
+; GFX1200-NEXT: v_min_u16 v4.l, v4.l, 15
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s0
+; GFX1200-NEXT: v_and_b16 v10.l, 0x3ff, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
+; GFX1200-NEXT: v_or_b16 v9.h, v7.h, v9.h
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, v4.l, 1 clamp
+; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: v_and_b16 v6.l, v11.h, v10.h
-; GFX1200-NEXT: v_or_b16 v7.h, v9.l, v7.h
-; GFX1200-NEXT: v_or_b16 v5.h, v11.l, v5.h
; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.h
+; GFX1200-NEXT: v_or_b16 v6.l, v9.h, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v9.l, 1
+; GFX1200-NEXT: v_or_b16 v5.h, v7.l, v5.h
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, v5.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v4.l, v11.h
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.h, v7.h, s0
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v6.l, v5.h, s0
; GFX1200-NEXT: v_and_b16 v5.h, v8.l, 63
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
-; GFX1200-NEXT: v_and_b16 v6.l, v6.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v9.h, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v4.l, v7.l
+; GFX1200-NEXT: v_and_b16 v6.h, v7.l, v10.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v9.l, v7.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v2.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v3.h, v3.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_or_b16 v5.h, v9.l, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v8.h, v11.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v3.l, v3.l
-; GFX1200-NEXT: v_and_b16 v3.l, v7.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v10.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v2.l
-; GFX1200-NEXT: v_and_b16 v5.h, v6.l, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v8.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v4.h, s0
-; GFX1200-NEXT: v_or_b16 v3.l, v9.l, v3.l
-; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v5.h, vcc_lo
-; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0x7f, v5.l, s1
-; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
-; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v6.h, v5.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v2.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v2.l, v2.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v7.h, v3.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v4.h, 1 clamp
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.l
-; GFX1200-NEXT: v_and_b16 v10.h, v6.l, 63
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v6.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v10.l, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v5.l, v7.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.l, v6.h, 1
+; GFX1200-NEXT: v_or_b16 v5.h, v10.l, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v4.h, v9.h
-; GFX1200-NEXT: v_and_b16 v8.l, v9.h, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v9.h
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
-; GFX1200-NEXT: v_and_b16 v10.h, v9.l, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
-; GFX1200-NEXT: v_and_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_or_b16 v10.l, v8.h, v10.l
-; GFX1200-NEXT: v_lshlrev_b16 v11.h, 3, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0x7f, v4.h, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v4.l, v11.l, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v8.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; GFX1200-NEXT: v_or_b16 v8.l, v11.l, v8.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.h, v1.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
-; GFX1200-NEXT: v_or_b16 v5.h, v10.l, v5.h
-; GFX1200-NEXT: v_or_b16 v10.h, v12.l, v10.h
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_or_b16 v8.l, v8.h, v11.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v7.l
-; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v10.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v6.l
-; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, 2, v9.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v2
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.h, v3.h
+; GFX1200-NEXT: v_and_b16 v3.h, v7.l, v5.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v2.h
+; GFX1200-NEXT: v_and_b16 v4.l, v5.l, v4.l
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.h, 0xff, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v6.h, v4.l
+; GFX1200-NEXT: v_and_b16 v3.h, v7.l, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v3.l, 8, v3.l
+; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v6.l, v3.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v2.h
+; GFX1200-NEXT: v_and_b16 v7.l, 0x80, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.l, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v6.h, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 63
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v6.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v5.h, s0
-; GFX1200-NEXT: v_min_u16 v5.h, v6.l, 15
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v9.l, v6.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v5.h, 1 clamp
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v8.h, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v7.l
-; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.l
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
-; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v7.l
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s0
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.h, v8.l
+; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s0
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s0
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 3, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v9.l
-; GFX1200-NEXT: v_and_b16 v8.l, v9.l, v8.l
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, s1
-; GFX1200-NEXT: v_or_b16 v2.l, v10.l, v2.l
-; GFX1200-NEXT: v_lshlrev_b16 v5.l, 8, v5.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
-; GFX1200-NEXT: v_and_b16 v8.l, v10.h, 1
-; GFX1200-NEXT: v_or_b16 v6.l, v8.h, v6.l
-; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v4.h
-; GFX1200-NEXT: v_and_b16 v4.h, v6.h, 63
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, 6
+; GFX1200-NEXT: v_or_b16 v9.h, v7.l, v9.h
+; GFX1200-NEXT: v_and_b16 v9.l, v8.h, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.l, v8.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, 3, v8.l
+; GFX1200-NEXT: v_or_b16 v3.h, v9.h, v3.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v9.l, v7.h, 1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.h, v1.l
+; GFX1200-NEXT: v_or_b16 v10.l, v7.l, v10.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_or_b16 v4.l, v10.l, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, 2, v9.h
+; GFX1200-NEXT: v_or_b16 v10.l, v12.l, v10.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.h, v9.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
-; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v8.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v1.h
-; GFX1200-NEXT: v_and_b16 v7.h, v4.l, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v8.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v7.h, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.h, v10.l
+; GFX1200-NEXT: v_min_u16 v6.h, v8.h, 15
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v1.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v4.l, v3.h, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v6.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v6.l, v8.l, v6.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_and_b16 v4.h, v7.l, v4.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.h
-; GFX1200-NEXT: v_min_u16 v5.h, v5.h, 15
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.h, v6.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 24, v2
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, vcc_lo
-; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v7.h
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.h, v2.h
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v7.l, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
+; GFX1200-NEXT: v_and_b16 v10.l, 0x80, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.h, v4.l
+; GFX1200-NEXT: v_or_b16 v5.h, 0x400, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v10.h, v4.h
-; GFX1200-NEXT: v_and_b16 v6.l, v6.h, v6.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.h
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, 8, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
+; GFX1200-NEXT: v_and_b16 v7.l, v5.h, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v6.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v2.h, 0x3ff, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v6.l, v7.l, 1
-; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.l
-; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v2.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, -1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v10.l
-; GFX1200-NEXT: v_lshrrev_b16 v2.h, 7, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, 3, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v9.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.l
+; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v10.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v6.h, v5.h
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
+; GFX1200-NEXT: v_or_b16 v2.l, v7.l, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, v7.h, 63
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v8.h, v5.h
+; GFX1200-NEXT: v_or_b16 v4.l, v11.l, v10.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v7.h
-; GFX1200-NEXT: v_and_b16 v6.l, v7.h, v6.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.l, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s0
-; GFX1200-NEXT: v_and_b16 v9.l, 0x80, v9.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v9.h, v11.l
-; GFX1200-NEXT: v_and_b16 v9.h, v2.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
-; GFX1200-NEXT: v_and_b16 v11.l, v10.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s2
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
-; GFX1200-NEXT: v_or_b16 v9.h, v10.l, v9.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
-; GFX1200-NEXT: v_or_b16 v7.h, v9.l, v8.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v6.l
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v9.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.h, v0.l
-; GFX1200-NEXT: v_or_b16 v10.l, v12.l, v11.l
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s1
-; GFX1200-NEXT: v_or_b16 v5.h, v9.l, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, v6.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, 2, v9.h
-; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v10.l
-; GFX1200-NEXT: v_or_b16 v4.h, v7.h, v4.h
-; GFX1200-NEXT: v_or_b16 v4.l, v5.h, v4.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.l
-; GFX1200-NEXT: v_min_u16 v6.h, v6.h, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v6.l
-; GFX1200-NEXT: v_sub_nc_u16 v8.h, v6.h, 1 clamp
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, v7.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v4.h, s1
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v1.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v1.h
+; GFX1200-NEXT: v_or_b16 v5.l, v9.l, v5.l
+; GFX1200-NEXT: v_and_b16 v4.l, v5.h, v4.l
; GFX1200-NEXT: v_mov_b16_e32 v7.l, v11.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 31, v1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, s1
-; GFX1200-NEXT: v_cndmask_b16 v10.l, 0, 8, s2
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.l, v7.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v5.h, v6.h, 1
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, 2, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s0
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 6, v7.h
+; GFX1200-NEXT: v_or_b16 v5.l, v8.l, v5.h
+; GFX1200-NEXT: v_min_u16 v5.h, v8.h, 15
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v1.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v10.h, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.l, v7.l, v5.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, v5.h, 1 clamp
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v7.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v8.h, 1
-; GFX1200-NEXT: v_lshlrev_b16 v11.l, 7, v11.l
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s2
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v7.l
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.l, v1.l
-; GFX1200-NEXT: v_lshlrev_b16 v4.h, 3, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v6.h, v10.h
-; GFX1200-NEXT: v_and_b16 v8.l, v10.h, v8.l
-; GFX1200-NEXT: v_or_b16 v5.h, v10.l, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
-; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.h, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v8.l, 1
+; GFX1200-NEXT: v_and_b16 v10.h, v7.h, 63
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.l, 0x7f, v4.l, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.h
-; GFX1200-NEXT: v_and_b16 v9.l, v7.l, 1
-; GFX1200-NEXT: v_or_b16 v2.h, v4.h, v2.h
-; GFX1200-NEXT: v_and_b16 v4.h, v11.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v10.l, 0, 8, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_and_b16 v8.h, v9.l, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 6, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v0.h
-; GFX1200-NEXT: v_and_b16 v4.l, 0xff, v4.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v12.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.h, s0
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v8.l
-; GFX1200-NEXT: v_or_b16 v4.h, v6.l, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v8.h, v10.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 8, v1.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v9.h, v11.l
+; GFX1200-NEXT: v_and_b16 v9.h, v7.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v2.h, v11.l, s0
-; GFX1200-NEXT: v_min_u16 v2.h, v5.h, 15
-; GFX1200-NEXT: v_and_b16 v5.h, v7.h, 63
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.h
-; GFX1200-NEXT: v_and_b16 v4.h, v6.l, v4.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v0.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v2.h, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 6, v7.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v2.h
-; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 63
-; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, 6
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
+; GFX1200-NEXT: v_and_b16 v6.h, 0x80, v6.h
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v8.l, v9.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v0.l
+; GFX1200-NEXT: v_and_b16 v5.h, v7.h, v9.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v8.h
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v10.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v10.l
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v5.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v5.h
+; GFX1200-NEXT: v_or_b16 v7.l, v6.h, v7.h
+; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v11.l
; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v9.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
+; GFX1200-NEXT: v_or_b16 v10.l, v6.h, v10.l
+; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v5.l
+; GFX1200-NEXT: v_and_b16 v8.l, v11.l, v8.l
+; GFX1200-NEXT: v_min_u16 v7.h, v7.h, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v4.l, v10.l, v4.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v9.h, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v10.h, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v10.l, v7.h, 1 clamp
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v8.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 24, v1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v10.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v9.h
+; GFX1200-NEXT: v_and_b16 v11.h, 0x80, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v10.h, 0, 8, s1
; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_or_b16 v11.l, 0x400, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v5.l, v4.l, s0
+; GFX1200-NEXT: v_cndmask_b16 v7.l, v7.l, 0, s1
+; GFX1200-NEXT: v_or_b16 v10.h, v11.h, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v5.l, 3, v6.l
+; GFX1200-NEXT: v_and_b16 v8.h, v11.l, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_or_b16 v7.l, v10.h, v7.l
+; GFX1200-NEXT: v_or_b16 v5.l, v11.h, v5.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v2.h, v2.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v2.h, v0.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v6.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v5.l, v5.l, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v10.h
-; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v9.l
-; GFX1200-NEXT: v_and_b16 v8.h, v10.h, v8.h
-; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
-; GFX1200-NEXT: v_lshrrev_b16 v12.l, v2.h, v10.h
-; GFX1200-NEXT: v_and_b16 v7.h, v7.h, v9.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v10.l
-; GFX1200-NEXT: v_and_b16 v9.l, v12.l, 1
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v7.h, v11.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v10.l, v11.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s2
-; GFX1200-NEXT: v_cmp_o_f16_e64 s2, v1.h, v1.h
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v4.h, s0
-; GFX1200-NEXT: v_and_b16 v4.h, v6.l, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.l, v7.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, 2, v2.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v6.l, v6.l, v5.h
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.h
+; GFX1200-NEXT: v_min_u16 v1.l, v7.l, 15
+; GFX1200-NEXT: v_and_b16 v8.h, v9.h, 63
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.h, v6.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v0.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v11.h, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v1.l, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_and_b16 v6.l, v7.l, v6.l
+; GFX1200-NEXT: v_and_b16 v10.h, v6.h, 63
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, v7.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
+; GFX1200-NEXT: v_and_b16 v8.h, v7.l, 1
+; GFX1200-NEXT: v_or_b16 v11.l, 0x400, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v10.l, v10.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_and_b16 v10.l, v11.l, v10.l
+; GFX1200-NEXT: v_and_b16 v10.h, v8.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, 6, v9.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v1.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v10.l, v12.l, v10.h
+; GFX1200-NEXT: v_and_b16 v8.h, v9.h, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v1.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v1.h
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v5.h, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.h, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v8.h
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.h, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s2
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v11.h, v1.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.h, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.l
-; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v1.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 7, v4.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s2
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v8.l, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v5.h
+; GFX1200-NEXT: v_or_b16 v6.h, v12.l, v9.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_and_b16 v5.h, v6.h, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s0
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s4
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s5
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s2
+; GFX1200-NEXT: v_and_b16 v6.l, v7.l, v6.h
; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v5.h, s3
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v0.l
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s5
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v11.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, v7.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v12.l, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s4
-; GFX1200-NEXT: v_and_b16 v5.h, 0x80, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v8.l, v9.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, 6
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v2.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v0
-; GFX1200-NEXT: v_or_b16 v7.l, v5.h, v7.l
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 8, v0.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s4
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v9.l, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s3
+; GFX1200-NEXT: v_and_b16 v6.l, v7.l, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s3
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
+; GFX1200-NEXT: v_and_b16 v6.h, 0x80, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s2
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v9.h, v6.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 24, v0
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.h, 6
+; GFX1200-NEXT: v_or_b16 v7.h, v6.h, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v6.l
+; GFX1200-NEXT: v_and_b16 v9.l, 0x80, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, 6
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s4
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s3
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s3
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v7.h
-; GFX1200-NEXT: v_or_b16 v8.l, v5.h, v8.l
-; GFX1200-NEXT: v_or_b16 v1.h, v7.l, v1.h
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s3
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v2.h
+; GFX1200-NEXT: v_or_b16 v8.l, v6.h, v8.l
+; GFX1200-NEXT: v_or_b16 v1.h, v7.h, v1.h
; GFX1200-NEXT: v_or_b16 v8.h, v9.l, v8.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v7.l
; GFX1200-NEXT: v_or_b16 v9.h, v9.l, v9.h
-; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v7.h
-; GFX1200-NEXT: v_or_b16 v2.h, v8.h, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, v3.h, v5.l
-; GFX1200-NEXT: v_or_b16 v4.h, v9.h, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v6.l, v1.h, s0
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.h, v2.h, s3
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v5.h, s0
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v2.h, v9.l, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v0.h, v0.h
+; GFX1200-NEXT: v_or_b16 v5.h, v8.l, v5.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v2.h
+; GFX1200-NEXT: v_or_b16 v6.l, v8.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v4.l, s0
+; GFX1200-NEXT: v_or_b16 v1.l, v9.h, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v2.l, vcc_lo
-; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v1.l
-; GFX1200-NEXT: v_and_b16 v1.l, 0xff, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, 0x7f, v5.l, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v1.h, s0
-; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s1
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s2
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.l, s3
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 8, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v6.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.l, v9.l, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.h, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v2.l, s1
+; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v4.l
+; GFX1200-NEXT: v_and_b16 v1.l, 0xff, v3.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v1.h, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
; GFX1200-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX1200-NEXT: v_mov_b16_e32 v4.l, v2.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v2.h
+; GFX1200-NEXT: v_or_b16 v6.h, v4.h, v3.l
; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b16 v6.l, v1.l, v0.h
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_or_b16 v0.l, v1.h, v2.l
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
index abbecb8005493..9bb6ea3b8e11b 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
@@ -427,21 +427,24 @@ define <2 x i8> @to_f8e4m3fn_v2f32(<2 x float> %x) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
-; CHECK-NEXT: v_frexp_mant_f32_e32 v2, v1
; CHECK-NEXT: v_sub_u32_e32 v5, 15, v4
-; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffff, v2
; CHECK-NEXT: v_min_u32_e32 v5, 31, v5
-; CHECK-NEXT: v_or_b32_e32 v3, 0x800000, v3
+; CHECK-NEXT: v_frexp_mant_f32_e32 v2, v1
; CHECK-NEXT: v_sub_u32_e64 v7, v5, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v8, v3, 0, v7
+; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffff, v2
+; CHECK-NEXT: v_lshlrev_b32_e64 v8, v7, 1
+; CHECK-NEXT: v_or_b32_e32 v3, 0x800000, v3
+; CHECK-NEXT: v_add_u32_e32 v8, -1, v8
+; CHECK-NEXT: v_and_b32_e32 v8, v3, v8
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CHECK-NEXT: v_lshrrev_b32_e32 v6, v5, v3
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v8, v6, 1, v8
+; CHECK-NEXT: v_or_b32_e32 v8, v8, v6
; CHECK-NEXT: v_lshrrev_b32_e32 v3, v7, v3
-; CHECK-NEXT: v_and_b32_e32 v3, v3, v8
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; CHECK-NEXT: v_and_b32_e32 v3, v3, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v3, v5, v3
; CHECK-NEXT: v_add_u32_e32 v3, v6, v3
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
; CHECK-NEXT: s_movk_i32 s4, 0x80
@@ -467,24 +470,27 @@ define <2 x i8> @to_f8e4m3fn_v2f32(<2 x float> %x) {
; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
-; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0
; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6
-; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4
; CHECK-NEXT: v_min_u32_e32 v7, 31, v7
-; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5
+; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0
; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp
+; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4
+; CHECK-NEXT: v_lshlrev_b32_e64 v10, v9, 1
+; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5
+; CHECK-NEXT: v_add_u32_e32 v10, -1, v10
; CHECK-NEXT: v_mov_b32_e32 v3, 0x7f
; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9
+; CHECK-NEXT: v_and_b32_e32 v10, v5, v10
; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10
+; CHECK-NEXT: v_or_b32_e32 v10, v10, v8
; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5
-; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v7, v5
; CHECK-NEXT: v_add_u32_e32 v5, v8, v5
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
@@ -524,21 +530,24 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
-; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v0
; CHECK-NEXT: v_sub_u32_e32 v6, 15, v5
-; CHECK-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
; CHECK-NEXT: v_min_u32_e32 v6, 31, v6
-; CHECK-NEXT: v_or_b32_e32 v4, 0x800000, v4
+; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v0
; CHECK-NEXT: v_sub_u32_e64 v8, v6, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v9, v4, 0, v8
+; CHECK-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
+; CHECK-NEXT: v_lshlrev_b32_e64 v9, v8, 1
+; CHECK-NEXT: v_or_b32_e32 v4, 0x800000, v4
+; CHECK-NEXT: v_add_u32_e32 v9, -1, v9
+; CHECK-NEXT: v_and_b32_e32 v9, v4, v9
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CHECK-NEXT: v_lshrrev_b32_e32 v7, v6, v4
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v9, v7, 1, v9
+; CHECK-NEXT: v_or_b32_e32 v9, v9, v7
; CHECK-NEXT: v_lshrrev_b32_e32 v4, v8, v4
-; CHECK-NEXT: v_and_b32_e32 v4, v4, v9
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; CHECK-NEXT: v_and_b32_e32 v4, v4, v9
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v4, v6, v4
; CHECK-NEXT: v_add_u32_e32 v4, v7, v4
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
; CHECK-NEXT: s_movk_i32 s4, 0x80
@@ -562,26 +571,29 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6
; CHECK-NEXT: v_mov_b32_e32 v4, 0x7f
; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
+; CHECK-NEXT: v_min_u32_e32 v7, 31, v7
; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v1
-; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6
+; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp
; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v3
-; CHECK-NEXT: v_min_u32_e32 v7, 31, v7
+; CHECK-NEXT: v_lshlrev_b32_e64 v10, v9, 1
; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5
-; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9
+; CHECK-NEXT: v_add_u32_e32 v10, -1, v10
+; CHECK-NEXT: v_and_b32_e32 v10, v5, v10
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10
+; CHECK-NEXT: v_or_b32_e32 v10, v10, v8
; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5
-; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v7, v5
; CHECK-NEXT: v_add_u32_e32 v5, v8, v5
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
@@ -602,27 +614,30 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: v_lshlrev_b32_e32 v7, 3, v6
; CHECK-NEXT: v_or3_b32 v3, v8, v7, v3
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6
+; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1
+; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6
; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
+; CHECK-NEXT: v_min_u32_e32 v7, 31, v7
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; CHECK-NEXT: v_frexp_mant_f32_e32 v3, v2
-; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6
+; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp
; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v3
-; CHECK-NEXT: v_min_u32_e32 v7, 31, v7
+; CHECK-NEXT: v_lshlrev_b32_e64 v10, v9, 1
; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5
-; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9
+; CHECK-NEXT: v_add_u32_e32 v10, -1, v10
+; CHECK-NEXT: v_and_b32_e32 v10, v5, v10
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10
+; CHECK-NEXT: v_or_b32_e32 v10, v10, v8
; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5
-; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v7, v5
; CHECK-NEXT: v_add_u32_e32 v5, v8, v5
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
@@ -659,21 +674,24 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
-; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v1
; CHECK-NEXT: v_sub_u32_e32 v7, 15, v6
-; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4
; CHECK-NEXT: v_min_u32_e32 v7, 31, v7
-; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5
+; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v1
; CHECK-NEXT: v_sub_u32_e64 v9, v7, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v10, v5, 0, v9
+; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffff, v4
+; CHECK-NEXT: v_lshlrev_b32_e64 v10, v9, 1
+; CHECK-NEXT: v_or_b32_e32 v5, 0x800000, v5
+; CHECK-NEXT: v_add_u32_e32 v10, -1, v10
+; CHECK-NEXT: v_and_b32_e32 v10, v5, v10
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CHECK-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v10, v8, 1, v10
+; CHECK-NEXT: v_or_b32_e32 v10, v10, v8
; CHECK-NEXT: v_lshrrev_b32_e32 v5, v9, v5
-; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v7, v5
; CHECK-NEXT: v_add_u32_e32 v5, v8, v5
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
; CHECK-NEXT: s_movk_i32 s4, 0x80
@@ -697,134 +715,143 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; CHECK-NEXT: v_mov_b32_e32 v5, 0x7f
-; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
-; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v0
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v4, v8, vcc
; CHECK-NEXT: v_sub_u32_e32 v8, 15, v7
-; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, 0x7f
+; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; CHECK-NEXT: v_min_u32_e32 v8, 31, v8
-; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; CHECK-NEXT: v_frexp_mant_f32_e32 v5, v0
; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10
+; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v5
+; CHECK-NEXT: v_lshlrev_b32_e64 v11, v10, 1
+; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6
+; CHECK-NEXT: v_add_u32_e32 v11, -1, v11
+; CHECK-NEXT: v_and_b32_e32 v11, v6, v11
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11
+; CHECK-NEXT: v_or_b32_e32 v11, v11, v9
; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6
-; CHECK-NEXT: v_and_b32_e32 v6, v6, v11
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; CHECK-NEXT: v_and_b32_e32 v6, v6, v11
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v6, v8, v6
; CHECK-NEXT: v_add_u32_e32 v6, v9, v6
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
; CHECK-NEXT: v_and_b32_sdwa v9, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6
-; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v4
+; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v5
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT: v_bfe_u32 v10, v4, 20, 3
+; CHECK-NEXT: v_bfe_u32 v10, v5, 20, 3
; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8
-; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4
-; CHECK-NEXT: v_and_b32_e32 v4, v4, v8
-; CHECK-NEXT: v_add_u32_e32 v4, v10, v4
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; CHECK-NEXT: v_lshrrev_b32_e32 v5, 19, v5
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v8
+; CHECK-NEXT: v_add_u32_e32 v5, v10, v5
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
+; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 6, v7, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v8, 3, v7
-; CHECK-NEXT: v_or3_b32 v4, v9, v8, v4
+; CHECK-NEXT: v_or3_b32 v5, v9, v8, v5
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
-; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v3
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; CHECK-NEXT: v_sub_u32_e32 v8, 15, v7
-; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; CHECK-NEXT: v_min_u32_e32 v8, 31, v8
-; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; CHECK-NEXT: v_frexp_mant_f32_e32 v5, v3
; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10
+; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v5
+; CHECK-NEXT: v_lshlrev_b32_e64 v11, v10, 1
+; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6
+; CHECK-NEXT: v_add_u32_e32 v11, -1, v11
+; CHECK-NEXT: v_and_b32_e32 v11, v6, v11
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11
+; CHECK-NEXT: v_or_b32_e32 v11, v11, v9
; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6
-; CHECK-NEXT: v_and_b32_e32 v6, v6, v11
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; CHECK-NEXT: v_and_b32_e32 v6, v6, v11
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v6, v8, v6
; CHECK-NEXT: v_add_u32_e32 v6, v9, v6
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
; CHECK-NEXT: v_and_b32_sdwa v9, v3, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6
-; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v4
+; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v5
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT: v_bfe_u32 v10, v4, 20, 3
+; CHECK-NEXT: v_bfe_u32 v10, v5, 20, 3
; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8
-; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4
-; CHECK-NEXT: v_and_b32_e32 v4, v4, v8
-; CHECK-NEXT: v_add_u32_e32 v4, v10, v4
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; CHECK-NEXT: v_lshrrev_b32_e32 v5, 19, v5
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v8
+; CHECK-NEXT: v_add_u32_e32 v5, v10, v5
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
+; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 6, v7, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v8, 3, v7
-; CHECK-NEXT: v_or3_b32 v4, v9, v8, v4
+; CHECK-NEXT: v_or3_b32 v5, v9, v8, v5
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
-; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v3, v3
; CHECK-NEXT: v_frexp_exp_i32_f32_e32 v7, v2
-; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
-; CHECK-NEXT: v_frexp_mant_f32_e32 v4, v2
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3
; CHECK-NEXT: v_sub_u32_e32 v8, 15, v7
-; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v4
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v3, v3
; CHECK-NEXT: v_min_u32_e32 v8, 31, v8
-; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6
+; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; CHECK-NEXT: v_frexp_mant_f32_e32 v5, v2
; CHECK-NEXT: v_sub_u32_e64 v10, v8, 1 clamp
-; CHECK-NEXT: v_bfe_u32 v11, v6, 0, v10
+; CHECK-NEXT: v_and_b32_e32 v6, 0x7fffff, v5
+; CHECK-NEXT: v_lshlrev_b32_e64 v11, v10, 1
+; CHECK-NEXT: v_or_b32_e32 v6, 0x800000, v6
+; CHECK-NEXT: v_add_u32_e32 v11, -1, v11
+; CHECK-NEXT: v_and_b32_e32 v11, v6, v11
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; CHECK-NEXT: v_lshrrev_b32_e32 v9, v8, v6
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT: v_and_or_b32 v11, v9, 1, v11
+; CHECK-NEXT: v_or_b32_e32 v11, v11, v9
; CHECK-NEXT: v_lshrrev_b32_e32 v6, v10, v6
-; CHECK-NEXT: v_and_b32_e32 v6, v6, v11
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
-; CHECK-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; CHECK-NEXT: v_and_b32_e32 v6, v6, v11
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v6, v8, v6
; CHECK-NEXT: v_add_u32_e32 v6, v9, v6
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
; CHECK-NEXT: v_and_b32_sdwa v9, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; CHECK-NEXT: v_or3_b32 v6, v9, v8, v6
-; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v4
+; CHECK-NEXT: v_and_b32_e32 v8, 0x7ffff, v5
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT: v_bfe_u32 v10, v4, 20, 3
+; CHECK-NEXT: v_bfe_u32 v10, v5, 20, 3
; CHECK-NEXT: v_and_or_b32 v8, v10, 1, v8
-; CHECK-NEXT: v_lshrrev_b32_e32 v4, 19, v4
-; CHECK-NEXT: v_and_b32_e32 v4, v4, v8
-; CHECK-NEXT: v_add_u32_e32 v4, v10, v4
-; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; CHECK-NEXT: v_lshrrev_b32_e32 v5, 19, v5
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v8
+; CHECK-NEXT: v_add_u32_e32 v5, v10, v5
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
+; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; CHECK-NEXT: v_addc_co_u32_e32 v7, vcc, 6, v7, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v8, 3, v7
-; CHECK-NEXT: v_or3_b32 v4, v9, v8, v4
+; CHECK-NEXT: v_or3_b32 v5, v9, v8, v5
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
-; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v2, v2
; CHECK-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; CHECK-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
; CHECK-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; CHECK-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; CHECK-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -1067,21 +1094,21 @@ define <2 x i8> @to_f8e4m3fn_v2f16(<2 x half> %x) {
; CHECK-NEXT: v_sub_u16_e32 v5, 2, v4
; CHECK-NEXT: v_min_u16_e32 v5, 15, v5
; CHECK-NEXT: v_frexp_mant_f16_e32 v1, v0
-; CHECK-NEXT: v_sub_u16_e64 v8, v5, 1 clamp
+; CHECK-NEXT: v_sub_u16_e64 v7, v5, 1 clamp
; CHECK-NEXT: v_and_b32_e32 v2, 0x3ff, v1
-; CHECK-NEXT: v_lshlrev_b16_e64 v9, v8, 1
+; CHECK-NEXT: v_lshlrev_b16_e64 v8, v7, 1
; CHECK-NEXT: v_or_b32_e32 v3, 0x400, v2
-; CHECK-NEXT: v_add_u16_e32 v9, -1, v9
-; CHECK-NEXT: v_and_b32_e32 v9, v3, v9
+; CHECK-NEXT: v_add_u16_e32 v8, -1, v8
+; CHECK-NEXT: v_and_b32_e32 v8, v3, v8
+; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
; CHECK-NEXT: v_lshrrev_b16_e32 v6, v5, v3
-; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
-; CHECK-NEXT: v_and_b32_e32 v7, 1, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT: v_or_b32_e32 v7, v9, v7
-; CHECK-NEXT: v_lshrrev_b16_e32 v3, v8, v3
-; CHECK-NEXT: v_and_b32_e32 v3, v3, v7
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_or_b32_e32 v8, v8, v6
+; CHECK-NEXT: v_lshrrev_b16_e32 v3, v7, v3
; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
-; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; CHECK-NEXT: v_and_b32_e32 v3, v3, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v3, v5, v3
; CHECK-NEXT: v_add_u16_e32 v3, v6, v3
; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
; CHECK-NEXT: s_movk_i32 s4, 0x80
@@ -1115,29 +1142,28 @@ define <2 x i8> @to_f8e4m3fn_v2f16(<2 x half> %x) {
; CHECK-NEXT: v_sub_u16_e32 v7, 2, v6
; CHECK-NEXT: v_min_u16_e32 v7, 15, v7
; CHECK-NEXT: v_frexp_mant_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; CHECK-NEXT: v_sub_u16_e64 v10, v7, 1 clamp
+; CHECK-NEXT: v_sub_u16_e64 v9, v7, 1 clamp
; CHECK-NEXT: v_and_b32_e32 v4, 0x3ff, v3
-; CHECK-NEXT: v_lshlrev_b16_e64 v11, v10, 1
+; CHECK-NEXT: v_lshlrev_b16_e64 v10, v9, 1
; CHECK-NEXT: v_or_b32_e32 v5, 0x400, v4
-; CHECK-NEXT: v_add_u16_e32 v11, -1, v11
+; CHECK-NEXT: v_add_u16_e32 v10, -1, v10
; CHECK-NEXT: v_mov_b32_e32 v2, 0x7f
; CHECK-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; CHECK-NEXT: v_and_b32_e32 v11, v5, v11
+; CHECK-NEXT: v_and_b32_e32 v10, v5, v10
; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
; CHECK-NEXT: v_lshrrev_b16_e32 v8, v7, v5
-; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
-; CHECK-NEXT: v_and_b32_e32 v9, 1, v8
-; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT: v_or_b32_e32 v9, v11, v9
-; CHECK-NEXT: v_lshrrev_b16_e32 v5, v10, v5
-; CHECK-NEXT: v_and_b32_e32 v5, v5, v9
+; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; CHECK-NEXT: v_or_b32_e32 v10, v10, v8
+; CHECK-NEXT: v_lshrrev_b16_e32 v5, v9, v5
; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
-; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v5, v10
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT: v_and_b32_e32 v5, v7, v5
; CHECK-NEXT: v_add_u16_e32 v5, v8, v5
; CHECK-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
-; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v0
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
-; CHECK-NEXT: v_lshlrev_b16_e32 v8, 7, v8
+; CHECK-NEXT: v_and_b32_sdwa v8, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; CHECK-NEXT: v_and_b32_e32 v9, 63, v3
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; CHECK-NEXT: v_or_b32_e32 v7, v8, v7
diff --git a/llvm/test/CodeGen/AMDGPU/sad.ll b/llvm/test/CodeGen/AMDGPU/sad.ll
index c73e60022b623..89acb92a09432 100644
--- a/llvm/test/CodeGen/AMDGPU/sad.ll
+++ b/llvm/test/CodeGen/AMDGPU/sad.ll
@@ -1218,7 +1218,6 @@ define amdgpu_kernel void @v_sad_u32_i16_pat1(ptr addrspace(1) %out, i16 %a, i16
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_lshr_b32 s4, s2, 16
; GFX12-5-SDAG-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX12-5-SDAG-NEXT: s_and_b32 s4, s4, 0xffff
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_min_u32 s5, s2, s4
; GFX12-5-SDAG-NEXT: s_max_u32 s2, s2, s4
@@ -1425,12 +1424,11 @@ define amdgpu_kernel void @v_sad_u32_i8_pat1(ptr addrspace(1) %out, i8 %a, i8 %b
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-5-SDAG-NEXT: s_lshr_b32 s3, s2, 8
-; GFX12-5-SDAG-NEXT: s_and_b32 s4, s2, 0xff
-; GFX12-5-SDAG-NEXT: s_and_b32 s3, s3, 0xff
+; GFX12-5-SDAG-NEXT: s_and_b32 s3, s2, 0xff
+; GFX12-5-SDAG-NEXT: s_bfe_u32 s4, s2, 0x80008
; GFX12-5-SDAG-NEXT: s_lshr_b32 s2, s2, 16
-; GFX12-5-SDAG-NEXT: s_min_u32 s5, s4, s3
-; GFX12-5-SDAG-NEXT: s_max_u32 s3, s4, s3
+; GFX12-5-SDAG-NEXT: s_min_u32 s5, s3, s4
+; GFX12-5-SDAG-NEXT: s_max_u32 s3, s3, s4
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s3, s5
; GFX12-5-SDAG-NEXT: s_add_co_i32 s2, s3, s2
@@ -1635,12 +1633,11 @@ define amdgpu_kernel void @s_sad_u32_i8_pat2(ptr addrspace(1) %out, i8 zeroext %
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-5-SDAG-NEXT: s_lshr_b32 s3, s2, 8
-; GFX12-5-SDAG-NEXT: s_and_b32 s4, s2, 0xff
-; GFX12-5-SDAG-NEXT: s_and_b32 s3, s3, 0xff
+; GFX12-5-SDAG-NEXT: s_and_b32 s3, s2, 0xff
+; GFX12-5-SDAG-NEXT: s_bfe_u32 s4, s2, 0x80008
; GFX12-5-SDAG-NEXT: s_lshr_b32 s2, s2, 16
-; GFX12-5-SDAG-NEXT: s_min_u32 s5, s4, s3
-; GFX12-5-SDAG-NEXT: s_max_u32 s3, s4, s3
+; GFX12-5-SDAG-NEXT: s_min_u32 s5, s3, s4
+; GFX12-5-SDAG-NEXT: s_max_u32 s3, s3, s4
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s3, s5
; GFX12-5-SDAG-NEXT: s_add_co_i32 s2, s3, s2
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index d9ec0d00e2aa7..975ea6993ee37 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -1133,9 +1133,9 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: s_ashr_i64 s[0:1], s[10:11], 31
; GCN-NEXT: s_ashr_i64 s[4:5], s[2:3], 31
; GCN-NEXT: s_ashr_i32 s2, s3, 31
-; GCN-NEXT: s_ashr_i32 s3, s5, 31
; GCN-NEXT: s_add_u32 s4, s4, s2
-; GCN-NEXT: s_addc_u32 s5, s5, s3
+; GCN-NEXT: s_mov_b32 s3, s5
+; GCN-NEXT: s_addc_u32 s5, s5, s5
; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5
@@ -1162,18 +1162,18 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: v_mul_hi_u32 v3, v0, s15
; GCN-NEXT: s_add_i32 s13, s13, s14
; GCN-NEXT: v_mul_hi_u32 v0, v0, s13
-; GCN-NEXT: v_mul_hi_u32 v4, v1, s15
-; GCN-NEXT: v_readfirstlane_b32 s14, v3
; GCN-NEXT: s_mul_i32 s16, s12, s13
+; GCN-NEXT: v_readfirstlane_b32 s14, v3
; GCN-NEXT: s_add_u32 s14, s14, s16
; GCN-NEXT: v_readfirstlane_b32 s16, v0
-; GCN-NEXT: v_mul_hi_u32 v0, v1, s13
+; GCN-NEXT: v_mul_hi_u32 v0, v1, s15
+; GCN-NEXT: v_mul_hi_u32 v1, v1, s13
; GCN-NEXT: s_addc_u32 s16, 0, s16
; GCN-NEXT: s_mul_i32 s15, s10, s15
-; GCN-NEXT: v_readfirstlane_b32 s17, v4
+; GCN-NEXT: v_readfirstlane_b32 s17, v0
; GCN-NEXT: s_add_u32 s14, s14, s15
; GCN-NEXT: s_addc_u32 s14, s16, s17
-; GCN-NEXT: v_readfirstlane_b32 s15, v0
+; GCN-NEXT: v_readfirstlane_b32 s15, v1
; GCN-NEXT: s_addc_u32 s15, s15, 0
; GCN-NEXT: s_mul_i32 s13, s10, s13
; GCN-NEXT: s_add_u32 s13, s14, s13
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 659882d67d6c8..a6a97ba4997e5 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -3770,8 +3770,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3874,8 +3874,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3982,8 +3982,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -4090,8 +4090,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4194,8 +4194,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4309,8 +4309,8 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 09f08d332793e..1ac4c2703ba95 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -3769,8 +3769,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3873,8 +3873,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3981,8 +3981,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -4089,8 +4089,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4193,8 +4193,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4308,8 +4308,8 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 2a587008515e5..1d2140d23dd18 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -3646,8 +3646,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3750,8 +3750,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3858,8 +3858,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -3966,8 +3966,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -4070,8 +4070,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -4185,8 +4185,8 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 77ea7b6d8df87..3e4bab5ab157c 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -3419,8 +3419,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3523,8 +3523,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -3631,8 +3631,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[4:5]
; GFX9-SDAG-NEXT: s_nop 1
-; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX9-SDAG-NEXT: s_nop 1
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -3739,8 +3739,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s4
; GFX10-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
@@ -3843,8 +3843,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX11-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
@@ -3958,8 +3958,8 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
diff --git a/llvm/test/CodeGen/NVPTX/float-to-arbitrary-fp.ll b/llvm/test/CodeGen/NVPTX/float-to-arbitrary-fp.ll
index 16ac8c8634db5..cc2df0405d66c 100644
--- a/llvm/test/CodeGen/NVPTX/float-to-arbitrary-fp.ll
+++ b/llvm/test/CodeGen/NVPTX/float-to-arbitrary-fp.ll
@@ -209,18 +209,18 @@ define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r21, 23, %r20;
; CHECK-NEXT: min.u32 %r22, %r21, 31;
; CHECK-NEXT: shr.u32 %r23, %r13, %r22;
-; CHECK-NEXT: and.b32 %r24, %r23, 1;
-; CHECK-NEXT: max.u32 %r25, %r22, 1;
-; CHECK-NEXT: add.s32 %r26, %r25, -1;
-; CHECK-NEXT: mov.b32 %r27, 1;
-; CHECK-NEXT: shl.b32 %r28, %r27, %r26;
-; CHECK-NEXT: add.s32 %r29, %r28, -1;
-; CHECK-NEXT: and.b32 %r30, %r13, %r29;
-; CHECK-NEXT: setp.ne.b32 %p3, %r30, 0;
-; CHECK-NEXT: selp.b32 %r31, 1, 0, %p3;
-; CHECK-NEXT: or.b32 %r32, %r31, %r24;
-; CHECK-NEXT: shr.u32 %r33, %r13, %r26;
-; CHECK-NEXT: and.b32 %r34, %r33, %r32;
+; CHECK-NEXT: max.u32 %r24, %r22, 1;
+; CHECK-NEXT: add.s32 %r25, %r24, -1;
+; CHECK-NEXT: mov.b32 %r26, 1;
+; CHECK-NEXT: shl.b32 %r27, %r26, %r25;
+; CHECK-NEXT: add.s32 %r28, %r27, -1;
+; CHECK-NEXT: and.b32 %r29, %r13, %r28;
+; CHECK-NEXT: setp.ne.b32 %p3, %r29, 0;
+; CHECK-NEXT: selp.b32 %r30, 1, 0, %p3;
+; CHECK-NEXT: or.b32 %r31, %r30, %r23;
+; CHECK-NEXT: shr.u32 %r32, %r13, %r25;
+; CHECK-NEXT: and.b32 %r33, %r32, %r31;
+; CHECK-NEXT: and.b32 %r34, %r33, 1;
; CHECK-NEXT: setp.ne.b32 %p4, %r22, 0;
; CHECK-NEXT: selp.b32 %r35, %r34, 0, %p4;
; CHECK-NEXT: add.s32 %r36, %r23, %r35;
@@ -271,17 +271,17 @@ define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r74, 23, %r73;
; CHECK-NEXT: min.u32 %r75, %r74, 31;
; CHECK-NEXT: shr.u32 %r76, %r66, %r75;
-; CHECK-NEXT: and.b32 %r77, %r76, 1;
-; CHECK-NEXT: max.u32 %r78, %r75, 1;
-; CHECK-NEXT: add.s32 %r79, %r78, -1;
-; CHECK-NEXT: shl.b32 %r80, %r27, %r79;
-; CHECK-NEXT: add.s32 %r81, %r80, -1;
-; CHECK-NEXT: and.b32 %r82, %r66, %r81;
-; CHECK-NEXT: setp.ne.b32 %p12, %r82, 0;
-; CHECK-NEXT: selp.b32 %r83, 1, 0, %p12;
-; CHECK-NEXT: or.b32 %r84, %r83, %r77;
-; CHECK-NEXT: shr.u32 %r85, %r66, %r79;
-; CHECK-NEXT: and.b32 %r86, %r85, %r84;
+; CHECK-NEXT: max.u32 %r77, %r75, 1;
+; CHECK-NEXT: add.s32 %r78, %r77, -1;
+; CHECK-NEXT: shl.b32 %r79, %r26, %r78;
+; CHECK-NEXT: add.s32 %r80, %r79, -1;
+; CHECK-NEXT: and.b32 %r81, %r66, %r80;
+; CHECK-NEXT: setp.ne.b32 %p12, %r81, 0;
+; CHECK-NEXT: selp.b32 %r82, 1, 0, %p12;
+; CHECK-NEXT: or.b32 %r83, %r82, %r76;
+; CHECK-NEXT: shr.u32 %r84, %r66, %r78;
+; CHECK-NEXT: and.b32 %r85, %r84, %r83;
+; CHECK-NEXT: and.b32 %r86, %r85, 1;
; CHECK-NEXT: setp.ne.b32 %p13, %r75, 0;
; CHECK-NEXT: selp.b32 %r87, %r86, 0, %p13;
; CHECK-NEXT: add.s32 %r88, %r76, %r87;
@@ -333,17 +333,17 @@ define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r127, 23, %r126;
; CHECK-NEXT: min.u32 %r128, %r127, 31;
; CHECK-NEXT: shr.u32 %r129, %r119, %r128;
-; CHECK-NEXT: and.b32 %r130, %r129, 1;
-; CHECK-NEXT: max.u32 %r131, %r128, 1;
-; CHECK-NEXT: add.s32 %r132, %r131, -1;
-; CHECK-NEXT: shl.b32 %r133, %r27, %r132;
-; CHECK-NEXT: add.s32 %r134, %r133, -1;
-; CHECK-NEXT: and.b32 %r135, %r119, %r134;
-; CHECK-NEXT: setp.ne.b32 %p21, %r135, 0;
-; CHECK-NEXT: selp.b32 %r136, 1, 0, %p21;
-; CHECK-NEXT: or.b32 %r137, %r136, %r130;
-; CHECK-NEXT: shr.u32 %r138, %r119, %r132;
-; CHECK-NEXT: and.b32 %r139, %r138, %r137;
+; CHECK-NEXT: max.u32 %r130, %r128, 1;
+; CHECK-NEXT: add.s32 %r131, %r130, -1;
+; CHECK-NEXT: shl.b32 %r132, %r26, %r131;
+; CHECK-NEXT: add.s32 %r133, %r132, -1;
+; CHECK-NEXT: and.b32 %r134, %r119, %r133;
+; CHECK-NEXT: setp.ne.b32 %p21, %r134, 0;
+; CHECK-NEXT: selp.b32 %r135, 1, 0, %p21;
+; CHECK-NEXT: or.b32 %r136, %r135, %r129;
+; CHECK-NEXT: shr.u32 %r137, %r119, %r131;
+; CHECK-NEXT: and.b32 %r138, %r137, %r136;
+; CHECK-NEXT: and.b32 %r139, %r138, 1;
; CHECK-NEXT: setp.ne.b32 %p22, %r128, 0;
; CHECK-NEXT: selp.b32 %r140, %r139, 0, %p22;
; CHECK-NEXT: add.s32 %r141, %r129, %r140;
@@ -394,17 +394,17 @@ define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r179, 23, %r178;
; CHECK-NEXT: min.u32 %r180, %r179, 31;
; CHECK-NEXT: shr.u32 %r181, %r171, %r180;
-; CHECK-NEXT: and.b32 %r182, %r181, 1;
-; CHECK-NEXT: max.u32 %r183, %r180, 1;
-; CHECK-NEXT: add.s32 %r184, %r183, -1;
-; CHECK-NEXT: shl.b32 %r185, %r27, %r184;
-; CHECK-NEXT: add.s32 %r186, %r185, -1;
-; CHECK-NEXT: and.b32 %r187, %r171, %r186;
-; CHECK-NEXT: setp.ne.b32 %p30, %r187, 0;
-; CHECK-NEXT: selp.b32 %r188, 1, 0, %p30;
-; CHECK-NEXT: or.b32 %r189, %r188, %r182;
-; CHECK-NEXT: shr.u32 %r190, %r171, %r184;
-; CHECK-NEXT: and.b32 %r191, %r190, %r189;
+; CHECK-NEXT: max.u32 %r182, %r180, 1;
+; CHECK-NEXT: add.s32 %r183, %r182, -1;
+; CHECK-NEXT: shl.b32 %r184, %r26, %r183;
+; CHECK-NEXT: add.s32 %r185, %r184, -1;
+; CHECK-NEXT: and.b32 %r186, %r171, %r185;
+; CHECK-NEXT: setp.ne.b32 %p30, %r186, 0;
+; CHECK-NEXT: selp.b32 %r187, 1, 0, %p30;
+; CHECK-NEXT: or.b32 %r188, %r187, %r181;
+; CHECK-NEXT: shr.u32 %r189, %r171, %r183;
+; CHECK-NEXT: and.b32 %r190, %r189, %r188;
+; CHECK-NEXT: and.b32 %r191, %r190, 1;
; CHECK-NEXT: setp.ne.b32 %p31, %r180, 0;
; CHECK-NEXT: selp.b32 %r192, %r191, 0, %p31;
; CHECK-NEXT: add.s32 %r193, %r181, %r192;
@@ -644,18 +644,18 @@ define <2 x i8> @to_f8e4m3fn_v2f32(<2 x float> %x) {
; CHECK-NEXT: sub.s32 %r19, 15, %r18;
; CHECK-NEXT: min.u32 %r20, %r19, 31;
; CHECK-NEXT: shr.u32 %r21, %r11, %r20;
-; CHECK-NEXT: and.b32 %r22, %r21, 1;
-; CHECK-NEXT: max.u32 %r23, %r20, 1;
-; CHECK-NEXT: add.s32 %r24, %r23, -1;
-; CHECK-NEXT: mov.b32 %r25, 1;
-; CHECK-NEXT: shl.b32 %r26, %r25, %r24;
-; CHECK-NEXT: add.s32 %r27, %r26, -1;
-; CHECK-NEXT: and.b32 %r28, %r11, %r27;
-; CHECK-NEXT: setp.ne.b32 %p3, %r28, 0;
-; CHECK-NEXT: selp.b32 %r29, 1, 0, %p3;
-; CHECK-NEXT: or.b32 %r30, %r29, %r22;
-; CHECK-NEXT: shr.u32 %r31, %r11, %r24;
-; CHECK-NEXT: and.b32 %r32, %r31, %r30;
+; CHECK-NEXT: max.u32 %r22, %r20, 1;
+; CHECK-NEXT: add.s32 %r23, %r22, -1;
+; CHECK-NEXT: mov.b32 %r24, 1;
+; CHECK-NEXT: shl.b32 %r25, %r24, %r23;
+; CHECK-NEXT: add.s32 %r26, %r25, -1;
+; CHECK-NEXT: and.b32 %r27, %r11, %r26;
+; CHECK-NEXT: setp.ne.b32 %p3, %r27, 0;
+; CHECK-NEXT: selp.b32 %r28, 1, 0, %p3;
+; CHECK-NEXT: or.b32 %r29, %r28, %r21;
+; CHECK-NEXT: shr.u32 %r30, %r11, %r23;
+; CHECK-NEXT: and.b32 %r31, %r30, %r29;
+; CHECK-NEXT: and.b32 %r32, %r31, 1;
; CHECK-NEXT: setp.ne.b32 %p4, %r20, 0;
; CHECK-NEXT: selp.b32 %r33, %r32, 0, %p4;
; CHECK-NEXT: add.s32 %r34, %r21, %r33;
@@ -711,17 +711,17 @@ define <2 x i8> @to_f8e4m3fn_v2f32(<2 x float> %x) {
; CHECK-NEXT: sub.s32 %r75, 15, %r74;
; CHECK-NEXT: min.u32 %r76, %r75, 31;
; CHECK-NEXT: shr.u32 %r77, %r67, %r76;
-; CHECK-NEXT: and.b32 %r78, %r77, 1;
-; CHECK-NEXT: max.u32 %r79, %r76, 1;
-; CHECK-NEXT: add.s32 %r80, %r79, -1;
-; CHECK-NEXT: shl.b32 %r81, %r25, %r80;
-; CHECK-NEXT: add.s32 %r82, %r81, -1;
-; CHECK-NEXT: and.b32 %r83, %r67, %r82;
-; CHECK-NEXT: setp.ne.b32 %p13, %r83, 0;
-; CHECK-NEXT: selp.b32 %r84, 1, 0, %p13;
-; CHECK-NEXT: or.b32 %r85, %r84, %r78;
-; CHECK-NEXT: shr.u32 %r86, %r67, %r80;
-; CHECK-NEXT: and.b32 %r87, %r86, %r85;
+; CHECK-NEXT: max.u32 %r78, %r76, 1;
+; CHECK-NEXT: add.s32 %r79, %r78, -1;
+; CHECK-NEXT: shl.b32 %r80, %r24, %r79;
+; CHECK-NEXT: add.s32 %r81, %r80, -1;
+; CHECK-NEXT: and.b32 %r82, %r67, %r81;
+; CHECK-NEXT: setp.ne.b32 %p13, %r82, 0;
+; CHECK-NEXT: selp.b32 %r83, 1, 0, %p13;
+; CHECK-NEXT: or.b32 %r84, %r83, %r77;
+; CHECK-NEXT: shr.u32 %r85, %r67, %r79;
+; CHECK-NEXT: and.b32 %r86, %r85, %r84;
+; CHECK-NEXT: and.b32 %r87, %r86, 1;
; CHECK-NEXT: setp.ne.b32 %p14, %r76, 0;
; CHECK-NEXT: selp.b32 %r88, %r87, 0, %p14;
; CHECK-NEXT: add.s32 %r89, %r77, %r88;
@@ -793,18 +793,18 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: sub.s32 %r20, 15, %r19;
; CHECK-NEXT: min.u32 %r21, %r20, 31;
; CHECK-NEXT: shr.u32 %r22, %r12, %r21;
-; CHECK-NEXT: and.b32 %r23, %r22, 1;
-; CHECK-NEXT: max.u32 %r24, %r21, 1;
-; CHECK-NEXT: add.s32 %r25, %r24, -1;
-; CHECK-NEXT: mov.b32 %r26, 1;
-; CHECK-NEXT: shl.b32 %r27, %r26, %r25;
-; CHECK-NEXT: add.s32 %r28, %r27, -1;
-; CHECK-NEXT: and.b32 %r29, %r12, %r28;
-; CHECK-NEXT: setp.ne.b32 %p3, %r29, 0;
-; CHECK-NEXT: selp.b32 %r30, 1, 0, %p3;
-; CHECK-NEXT: or.b32 %r31, %r30, %r23;
-; CHECK-NEXT: shr.u32 %r32, %r12, %r25;
-; CHECK-NEXT: and.b32 %r33, %r32, %r31;
+; CHECK-NEXT: max.u32 %r23, %r21, 1;
+; CHECK-NEXT: add.s32 %r24, %r23, -1;
+; CHECK-NEXT: mov.b32 %r25, 1;
+; CHECK-NEXT: shl.b32 %r26, %r25, %r24;
+; CHECK-NEXT: add.s32 %r27, %r26, -1;
+; CHECK-NEXT: and.b32 %r28, %r12, %r27;
+; CHECK-NEXT: setp.ne.b32 %p3, %r28, 0;
+; CHECK-NEXT: selp.b32 %r29, 1, 0, %p3;
+; CHECK-NEXT: or.b32 %r30, %r29, %r22;
+; CHECK-NEXT: shr.u32 %r31, %r12, %r24;
+; CHECK-NEXT: and.b32 %r32, %r31, %r30;
+; CHECK-NEXT: and.b32 %r33, %r32, 1;
; CHECK-NEXT: setp.ne.b32 %p4, %r21, 0;
; CHECK-NEXT: selp.b32 %r34, %r33, 0, %p4;
; CHECK-NEXT: add.s32 %r35, %r22, %r34;
@@ -859,17 +859,17 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: sub.s32 %r76, 15, %r75;
; CHECK-NEXT: min.u32 %r77, %r76, 31;
; CHECK-NEXT: shr.u32 %r78, %r68, %r77;
-; CHECK-NEXT: and.b32 %r79, %r78, 1;
-; CHECK-NEXT: max.u32 %r80, %r77, 1;
-; CHECK-NEXT: add.s32 %r81, %r80, -1;
-; CHECK-NEXT: shl.b32 %r82, %r26, %r81;
-; CHECK-NEXT: add.s32 %r83, %r82, -1;
-; CHECK-NEXT: and.b32 %r84, %r68, %r83;
-; CHECK-NEXT: setp.ne.b32 %p13, %r84, 0;
-; CHECK-NEXT: selp.b32 %r85, 1, 0, %p13;
-; CHECK-NEXT: or.b32 %r86, %r85, %r79;
-; CHECK-NEXT: shr.u32 %r87, %r68, %r81;
-; CHECK-NEXT: and.b32 %r88, %r87, %r86;
+; CHECK-NEXT: max.u32 %r79, %r77, 1;
+; CHECK-NEXT: add.s32 %r80, %r79, -1;
+; CHECK-NEXT: shl.b32 %r81, %r25, %r80;
+; CHECK-NEXT: add.s32 %r82, %r81, -1;
+; CHECK-NEXT: and.b32 %r83, %r68, %r82;
+; CHECK-NEXT: setp.ne.b32 %p13, %r83, 0;
+; CHECK-NEXT: selp.b32 %r84, 1, 0, %p13;
+; CHECK-NEXT: or.b32 %r85, %r84, %r78;
+; CHECK-NEXT: shr.u32 %r86, %r68, %r80;
+; CHECK-NEXT: and.b32 %r87, %r86, %r85;
+; CHECK-NEXT: and.b32 %r88, %r87, 1;
; CHECK-NEXT: setp.ne.b32 %p14, %r77, 0;
; CHECK-NEXT: selp.b32 %r89, %r88, 0, %p14;
; CHECK-NEXT: add.s32 %r90, %r78, %r89;
@@ -924,17 +924,17 @@ define <3 x i8> @to_f8e4m3fn_v3f32(<3 x float> %x) {
; CHECK-NEXT: sub.s32 %r131, 15, %r130;
; CHECK-NEXT: min.u32 %r132, %r131, 31;
; CHECK-NEXT: shr.u32 %r133, %r123, %r132;
-; CHECK-NEXT: and.b32 %r134, %r133, 1;
-; CHECK-NEXT: max.u32 %r135, %r132, 1;
-; CHECK-NEXT: add.s32 %r136, %r135, -1;
-; CHECK-NEXT: shl.b32 %r137, %r26, %r136;
-; CHECK-NEXT: add.s32 %r138, %r137, -1;
-; CHECK-NEXT: and.b32 %r139, %r123, %r138;
-; CHECK-NEXT: setp.ne.b32 %p23, %r139, 0;
-; CHECK-NEXT: selp.b32 %r140, 1, 0, %p23;
-; CHECK-NEXT: or.b32 %r141, %r140, %r134;
-; CHECK-NEXT: shr.u32 %r142, %r123, %r136;
-; CHECK-NEXT: and.b32 %r143, %r142, %r141;
+; CHECK-NEXT: max.u32 %r134, %r132, 1;
+; CHECK-NEXT: add.s32 %r135, %r134, -1;
+; CHECK-NEXT: shl.b32 %r136, %r25, %r135;
+; CHECK-NEXT: add.s32 %r137, %r136, -1;
+; CHECK-NEXT: and.b32 %r138, %r123, %r137;
+; CHECK-NEXT: setp.ne.b32 %p23, %r138, 0;
+; CHECK-NEXT: selp.b32 %r139, 1, 0, %p23;
+; CHECK-NEXT: or.b32 %r140, %r139, %r133;
+; CHECK-NEXT: shr.u32 %r141, %r123, %r135;
+; CHECK-NEXT: and.b32 %r142, %r141, %r140;
+; CHECK-NEXT: and.b32 %r143, %r142, 1;
; CHECK-NEXT: setp.ne.b32 %p24, %r132, 0;
; CHECK-NEXT: selp.b32 %r144, %r143, 0, %p24;
; CHECK-NEXT: add.s32 %r145, %r133, %r144;
@@ -1007,18 +1007,18 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r21, 15, %r20;
; CHECK-NEXT: min.u32 %r22, %r21, 31;
; CHECK-NEXT: shr.u32 %r23, %r13, %r22;
-; CHECK-NEXT: and.b32 %r24, %r23, 1;
-; CHECK-NEXT: max.u32 %r25, %r22, 1;
-; CHECK-NEXT: add.s32 %r26, %r25, -1;
-; CHECK-NEXT: mov.b32 %r27, 1;
-; CHECK-NEXT: shl.b32 %r28, %r27, %r26;
-; CHECK-NEXT: add.s32 %r29, %r28, -1;
-; CHECK-NEXT: and.b32 %r30, %r13, %r29;
-; CHECK-NEXT: setp.ne.b32 %p3, %r30, 0;
-; CHECK-NEXT: selp.b32 %r31, 1, 0, %p3;
-; CHECK-NEXT: or.b32 %r32, %r31, %r24;
-; CHECK-NEXT: shr.u32 %r33, %r13, %r26;
-; CHECK-NEXT: and.b32 %r34, %r33, %r32;
+; CHECK-NEXT: max.u32 %r24, %r22, 1;
+; CHECK-NEXT: add.s32 %r25, %r24, -1;
+; CHECK-NEXT: mov.b32 %r26, 1;
+; CHECK-NEXT: shl.b32 %r27, %r26, %r25;
+; CHECK-NEXT: add.s32 %r28, %r27, -1;
+; CHECK-NEXT: and.b32 %r29, %r13, %r28;
+; CHECK-NEXT: setp.ne.b32 %p3, %r29, 0;
+; CHECK-NEXT: selp.b32 %r30, 1, 0, %p3;
+; CHECK-NEXT: or.b32 %r31, %r30, %r23;
+; CHECK-NEXT: shr.u32 %r32, %r13, %r25;
+; CHECK-NEXT: and.b32 %r33, %r32, %r31;
+; CHECK-NEXT: and.b32 %r34, %r33, 1;
; CHECK-NEXT: setp.ne.b32 %p4, %r22, 0;
; CHECK-NEXT: selp.b32 %r35, %r34, 0, %p4;
; CHECK-NEXT: add.s32 %r36, %r23, %r35;
@@ -1073,17 +1073,17 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r77, 15, %r76;
; CHECK-NEXT: min.u32 %r78, %r77, 31;
; CHECK-NEXT: shr.u32 %r79, %r69, %r78;
-; CHECK-NEXT: and.b32 %r80, %r79, 1;
-; CHECK-NEXT: max.u32 %r81, %r78, 1;
-; CHECK-NEXT: add.s32 %r82, %r81, -1;
-; CHECK-NEXT: shl.b32 %r83, %r27, %r82;
-; CHECK-NEXT: add.s32 %r84, %r83, -1;
-; CHECK-NEXT: and.b32 %r85, %r69, %r84;
-; CHECK-NEXT: setp.ne.b32 %p13, %r85, 0;
-; CHECK-NEXT: selp.b32 %r86, 1, 0, %p13;
-; CHECK-NEXT: or.b32 %r87, %r86, %r80;
-; CHECK-NEXT: shr.u32 %r88, %r69, %r82;
-; CHECK-NEXT: and.b32 %r89, %r88, %r87;
+; CHECK-NEXT: max.u32 %r80, %r78, 1;
+; CHECK-NEXT: add.s32 %r81, %r80, -1;
+; CHECK-NEXT: shl.b32 %r82, %r26, %r81;
+; CHECK-NEXT: add.s32 %r83, %r82, -1;
+; CHECK-NEXT: and.b32 %r84, %r69, %r83;
+; CHECK-NEXT: setp.ne.b32 %p13, %r84, 0;
+; CHECK-NEXT: selp.b32 %r85, 1, 0, %p13;
+; CHECK-NEXT: or.b32 %r86, %r85, %r79;
+; CHECK-NEXT: shr.u32 %r87, %r69, %r81;
+; CHECK-NEXT: and.b32 %r88, %r87, %r86;
+; CHECK-NEXT: and.b32 %r89, %r88, 1;
; CHECK-NEXT: setp.ne.b32 %p14, %r78, 0;
; CHECK-NEXT: selp.b32 %r90, %r89, 0, %p14;
; CHECK-NEXT: add.s32 %r91, %r79, %r90;
@@ -1139,17 +1139,17 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r133, 15, %r132;
; CHECK-NEXT: min.u32 %r134, %r133, 31;
; CHECK-NEXT: shr.u32 %r135, %r125, %r134;
-; CHECK-NEXT: and.b32 %r136, %r135, 1;
-; CHECK-NEXT: max.u32 %r137, %r134, 1;
-; CHECK-NEXT: add.s32 %r138, %r137, -1;
-; CHECK-NEXT: shl.b32 %r139, %r27, %r138;
-; CHECK-NEXT: add.s32 %r140, %r139, -1;
-; CHECK-NEXT: and.b32 %r141, %r125, %r140;
-; CHECK-NEXT: setp.ne.b32 %p23, %r141, 0;
-; CHECK-NEXT: selp.b32 %r142, 1, 0, %p23;
-; CHECK-NEXT: or.b32 %r143, %r142, %r136;
-; CHECK-NEXT: shr.u32 %r144, %r125, %r138;
-; CHECK-NEXT: and.b32 %r145, %r144, %r143;
+; CHECK-NEXT: max.u32 %r136, %r134, 1;
+; CHECK-NEXT: add.s32 %r137, %r136, -1;
+; CHECK-NEXT: shl.b32 %r138, %r26, %r137;
+; CHECK-NEXT: add.s32 %r139, %r138, -1;
+; CHECK-NEXT: and.b32 %r140, %r125, %r139;
+; CHECK-NEXT: setp.ne.b32 %p23, %r140, 0;
+; CHECK-NEXT: selp.b32 %r141, 1, 0, %p23;
+; CHECK-NEXT: or.b32 %r142, %r141, %r135;
+; CHECK-NEXT: shr.u32 %r143, %r125, %r137;
+; CHECK-NEXT: and.b32 %r144, %r143, %r142;
+; CHECK-NEXT: and.b32 %r145, %r144, 1;
; CHECK-NEXT: setp.ne.b32 %p24, %r134, 0;
; CHECK-NEXT: selp.b32 %r146, %r145, 0, %p24;
; CHECK-NEXT: add.s32 %r147, %r135, %r146;
@@ -1204,17 +1204,17 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: sub.s32 %r188, 15, %r187;
; CHECK-NEXT: min.u32 %r189, %r188, 31;
; CHECK-NEXT: shr.u32 %r190, %r180, %r189;
-; CHECK-NEXT: and.b32 %r191, %r190, 1;
-; CHECK-NEXT: max.u32 %r192, %r189, 1;
-; CHECK-NEXT: add.s32 %r193, %r192, -1;
-; CHECK-NEXT: shl.b32 %r194, %r27, %r193;
-; CHECK-NEXT: add.s32 %r195, %r194, -1;
-; CHECK-NEXT: and.b32 %r196, %r180, %r195;
-; CHECK-NEXT: setp.ne.b32 %p33, %r196, 0;
-; CHECK-NEXT: selp.b32 %r197, 1, 0, %p33;
-; CHECK-NEXT: or.b32 %r198, %r197, %r191;
-; CHECK-NEXT: shr.u32 %r199, %r180, %r193;
-; CHECK-NEXT: and.b32 %r200, %r199, %r198;
+; CHECK-NEXT: max.u32 %r191, %r189, 1;
+; CHECK-NEXT: add.s32 %r192, %r191, -1;
+; CHECK-NEXT: shl.b32 %r193, %r26, %r192;
+; CHECK-NEXT: add.s32 %r194, %r193, -1;
+; CHECK-NEXT: and.b32 %r195, %r180, %r194;
+; CHECK-NEXT: setp.ne.b32 %p33, %r195, 0;
+; CHECK-NEXT: selp.b32 %r196, 1, 0, %p33;
+; CHECK-NEXT: or.b32 %r197, %r196, %r190;
+; CHECK-NEXT: shr.u32 %r198, %r180, %r192;
+; CHECK-NEXT: and.b32 %r199, %r198, %r197;
+; CHECK-NEXT: and.b32 %r200, %r199, 1;
; CHECK-NEXT: setp.ne.b32 %p34, %r189, 0;
; CHECK-NEXT: selp.b32 %r201, %r200, 0, %p34;
; CHECK-NEXT: add.s32 %r202, %r190, %r201;
diff --git a/llvm/test/CodeGen/NVPTX/i1-select.ll b/llvm/test/CodeGen/NVPTX/i1-select.ll
index c13e494c3077a..705580df5308b 100644
--- a/llvm/test/CodeGen/NVPTX/i1-select.ll
+++ b/llvm/test/CodeGen/NVPTX/i1-select.ll
@@ -8,24 +8,23 @@ define i32 @test_select_i1_trunc(i32 %a, i32 %b, i32 %c, i32 %true, i32 %false)
; CHECK-LABEL: test_select_i1_trunc(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<6>;
-; CHECK-NEXT: .reg .b64 %rd<7>;
+; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [test_select_i1_trunc_param_0];
-; CHECK-NEXT: and.b32 %r2, %r1, 1;
-; CHECK-NEXT: setp.ne.b32 %p1, %r2, 0;
-; CHECK-NEXT: mov.b64 %rd1, test_select_i1_trunc_param_2;
-; CHECK-NEXT: mov.b64 %rd2, test_select_i1_trunc_param_1;
-; CHECK-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [%rd3];
-; CHECK-NEXT: and.b32 %r4, %r3, 1;
-; CHECK-NEXT: setp.ne.b32 %p2, %r4, 0;
-; CHECK-NEXT: mov.b64 %rd4, test_select_i1_trunc_param_4;
-; CHECK-NEXT: mov.b64 %rd5, test_select_i1_trunc_param_3;
-; CHECK-NEXT: selp.b64 %rd6, %rd5, %rd4, %p2;
-; CHECK-NEXT: ld.param.b32 %r5, [%rd6];
-; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-NEXT: ld.param.b32 %r2, [test_select_i1_trunc_param_1];
+; CHECK-NEXT: and.b32 %r3, %r1, 1;
+; CHECK-NEXT: setp.ne.b32 %p1, %r3, 0;
+; CHECK-NEXT: ld.param.b32 %r4, [test_select_i1_trunc_param_2];
+; CHECK-NEXT: selp.b32 %r5, %r2, %r4, %p1;
+; CHECK-NEXT: and.b32 %r6, %r5, 1;
+; CHECK-NEXT: setp.ne.b32 %p2, %r6, 0;
+; CHECK-NEXT: mov.b64 %rd1, test_select_i1_trunc_param_4;
+; CHECK-NEXT: mov.b64 %rd2, test_select_i1_trunc_param_3;
+; CHECK-NEXT: selp.b64 %rd3, %rd2, %rd1, %p2;
+; CHECK-NEXT: ld.param.b32 %r7, [%rd3];
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NEXT: ret;
%a_trunc = trunc i32 %a to i1
%b_trunc = trunc i32 %b to i1
@@ -39,24 +38,23 @@ define i32 @test_select_i1_trunc_2(i64 %a, i16 %b, i32 %c, i32 %true, i32 %false
; CHECK-LABEL: test_select_i1_trunc_2(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b16 %rs<5>;
; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<9>;
+; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [test_select_i1_trunc_2_param_0];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_select_i1_trunc_2_param_1];
; CHECK-NEXT: and.b64 %rd2, %rd1, 1;
; CHECK-NEXT: setp.ne.b64 %p1, %rd2, 0;
-; CHECK-NEXT: mov.b64 %rd3, test_select_i1_trunc_2_param_2;
-; CHECK-NEXT: mov.b64 %rd4, test_select_i1_trunc_2_param_1;
-; CHECK-NEXT: selp.b64 %rd5, %rd4, %rd3, %p1;
-; CHECK-NEXT: ld.param.b16 %rs1, [%rd5];
-; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-NEXT: setp.ne.b16 %p2, %rs2, 0;
-; CHECK-NEXT: mov.b64 %rd6, test_select_i1_trunc_2_param_4;
-; CHECK-NEXT: mov.b64 %rd7, test_select_i1_trunc_2_param_3;
-; CHECK-NEXT: selp.b64 %rd8, %rd7, %rd6, %p2;
-; CHECK-NEXT: ld.param.b32 %r1, [%rd8];
+; CHECK-NEXT: ld.param.b16 %rs2, [test_select_i1_trunc_2_param_2];
+; CHECK-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
+; CHECK-NEXT: and.b16 %rs4, %rs3, 1;
+; CHECK-NEXT: setp.ne.b16 %p2, %rs4, 0;
+; CHECK-NEXT: mov.b64 %rd3, test_select_i1_trunc_2_param_4;
+; CHECK-NEXT: mov.b64 %rd4, test_select_i1_trunc_2_param_3;
+; CHECK-NEXT: selp.b64 %rd5, %rd4, %rd3, %p2;
+; CHECK-NEXT: ld.param.b32 %r1, [%rd5];
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%a_trunc = trunc i64 %a to i1
@@ -70,9 +68,9 @@ define i32 @test_select_i1_trunc_2(i64 %a, i16 %b, i32 %c, i32 %true, i32 %false
define i32 @test_select_i1_basic(i32 %v1, i32 %v2, i32 %v3, i32 %true, i32 %false) {
; CHECK-LABEL: test_select_i1_basic(
; CHECK: {
-; CHECK-NEXT: .reg .pred %p<6>;
+; CHECK-NEXT: .reg .pred %p<4>;
; CHECK-NEXT: .reg .b32 %r<6>;
-; CHECK-NEXT: .reg .b64 %rd<4>;
+; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [test_select_i1_basic_param_0];
@@ -81,13 +79,13 @@ define i32 @test_select_i1_basic(i32 %v1, i32 %v2, i32 %v3, i32 %true, i32 %fals
; CHECK-NEXT: setp.ne.b32 %p1, %r1, 0;
; CHECK-NEXT: ld.param.b32 %r4, [test_select_i1_basic_param_2];
; CHECK-NEXT: setp.eq.b32 %p2, %r4, 0;
-; CHECK-NEXT: and.pred %p3, %p1, %p2;
-; CHECK-NEXT: setp.eq.b32 %p4, %r3, 0;
-; CHECK-NEXT: or.pred %p5, %p4, %p3;
+; CHECK-NEXT: setp.eq.b32 %p3, %r3, 0;
; CHECK-NEXT: mov.b64 %rd1, test_select_i1_basic_param_4;
; CHECK-NEXT: mov.b64 %rd2, test_select_i1_basic_param_3;
-; CHECK-NEXT: selp.b64 %rd3, %rd2, %rd1, %p5;
-; CHECK-NEXT: ld.param.b32 %r5, [%rd3];
+; CHECK-NEXT: selp.b64 %rd3, %rd2, %rd1, %p2;
+; CHECK-NEXT: selp.b64 %rd4, %rd3, %rd1, %p1;
+; CHECK-NEXT: selp.b64 %rd5, %rd2, %rd4, %p3;
+; CHECK-NEXT: ld.param.b32 %r5, [%rd5];
; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NEXT: ret;
%b1 = icmp eq i32 %v1, 0
diff --git a/llvm/test/CodeGen/NVPTX/i128.ll b/llvm/test/CodeGen/NVPTX/i128.ll
index df1214c3f5e00..faf22112d56b4 100644
--- a/llvm/test/CodeGen/NVPTX/i128.ll
+++ b/llvm/test/CodeGen/NVPTX/i128.ll
@@ -149,75 +149,75 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: .reg .b64 %rd<66>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %_udiv-special-cases
-; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [urem_i128_param_0];
+; CHECK-NEXT: ld.param.v2.b64 {%rd7, %rd8}, [urem_i128_param_0];
; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [urem_i128_param_1];
-; CHECK-NEXT: or.b64 %rd7, %rd1, %rd2;
-; CHECK-NEXT: setp.eq.b64 %p1, %rd7, 0;
-; CHECK-NEXT: or.b64 %rd8, %rd5, %rd6;
-; CHECK-NEXT: setp.eq.b64 %p2, %rd8, 0;
+; CHECK-NEXT: or.b64 %rd9, %rd1, %rd2;
+; CHECK-NEXT: setp.eq.b64 %p1, %rd9, 0;
+; CHECK-NEXT: or.b64 %rd10, %rd7, %rd8;
+; CHECK-NEXT: setp.eq.b64 %p2, %rd10, 0;
; CHECK-NEXT: or.pred %p3, %p1, %p2;
; CHECK-NEXT: setp.ne.b64 %p4, %rd2, 0;
; CHECK-NEXT: clz.b64 %r1, %rd2;
-; CHECK-NEXT: cvt.u64.u32 %rd9, %r1;
+; CHECK-NEXT: cvt.u64.u32 %rd11, %r1;
; CHECK-NEXT: clz.b64 %r2, %rd1;
-; CHECK-NEXT: cvt.u64.u32 %rd10, %r2;
-; CHECK-NEXT: add.s64 %rd11, %rd10, 64;
-; CHECK-NEXT: selp.b64 %rd12, %rd9, %rd11, %p4;
-; CHECK-NEXT: setp.ne.b64 %p5, %rd6, 0;
-; CHECK-NEXT: clz.b64 %r3, %rd6;
-; CHECK-NEXT: cvt.u64.u32 %rd13, %r3;
-; CHECK-NEXT: clz.b64 %r4, %rd5;
-; CHECK-NEXT: cvt.u64.u32 %rd14, %r4;
-; CHECK-NEXT: add.s64 %rd15, %rd14, 64;
-; CHECK-NEXT: selp.b64 %rd16, %rd13, %rd15, %p5;
-; CHECK-NEXT: mov.b64 %rd17, 0;
-; CHECK-NEXT: sub.cc.s64 %rd18, %rd12, %rd16;
-; CHECK-NEXT: subc.cc.s64 %rd19, %rd17, 0;
-; CHECK-NEXT: setp.gt.u64 %p6, %rd18, 127;
-; CHECK-NEXT: setp.eq.b64 %p7, %rd19, 0;
+; CHECK-NEXT: cvt.u64.u32 %rd12, %r2;
+; CHECK-NEXT: add.s64 %rd13, %rd12, 64;
+; CHECK-NEXT: selp.b64 %rd14, %rd11, %rd13, %p4;
+; CHECK-NEXT: setp.ne.b64 %p5, %rd8, 0;
+; CHECK-NEXT: clz.b64 %r3, %rd8;
+; CHECK-NEXT: cvt.u64.u32 %rd15, %r3;
+; CHECK-NEXT: clz.b64 %r4, %rd7;
+; CHECK-NEXT: cvt.u64.u32 %rd16, %r4;
+; CHECK-NEXT: add.s64 %rd17, %rd16, 64;
+; CHECK-NEXT: selp.b64 %rd18, %rd15, %rd17, %p5;
+; CHECK-NEXT: mov.b64 %rd19, 0;
+; CHECK-NEXT: sub.cc.s64 %rd3, %rd14, %rd18;
+; CHECK-NEXT: subc.cc.s64 %rd4, %rd19, 0;
+; CHECK-NEXT: setp.gt.u64 %p6, %rd3, 127;
+; CHECK-NEXT: setp.eq.b64 %p7, %rd4, 0;
; CHECK-NEXT: and.pred %p8, %p7, %p6;
-; CHECK-NEXT: setp.ne.b64 %p9, %rd19, 0;
+; CHECK-NEXT: setp.ne.b64 %p9, %rd4, 0;
; CHECK-NEXT: or.pred %p10, %p8, %p9;
; CHECK-NEXT: or.pred %p11, %p3, %p10;
-; CHECK-NEXT: xor.b64 %rd20, %rd18, 127;
-; CHECK-NEXT: or.b64 %rd21, %rd20, %rd19;
+; CHECK-NEXT: xor.b64 %rd20, %rd3, 127;
+; CHECK-NEXT: or.b64 %rd21, %rd20, %rd4;
; CHECK-NEXT: setp.eq.b64 %p12, %rd21, 0;
-; CHECK-NEXT: selp.b64 %rd65, 0, %rd6, %p11;
-; CHECK-NEXT: selp.b64 %rd64, 0, %rd5, %p11;
+; CHECK-NEXT: selp.b64 %rd65, 0, %rd8, %p11;
+; CHECK-NEXT: selp.b64 %rd64, 0, %rd7, %p11;
; CHECK-NEXT: or.pred %p13, %p11, %p12;
; CHECK-NEXT: @%p13 bra $L__BB1_5;
; CHECK-NEXT: // %bb.1: // %udiv-bb1
-; CHECK-NEXT: add.cc.s64 %rd58, %rd18, 1;
-; CHECK-NEXT: addc.cc.s64 %rd59, %rd19, 0;
+; CHECK-NEXT: add.cc.s64 %rd58, %rd3, 1;
+; CHECK-NEXT: addc.cc.s64 %rd59, %rd4, 0;
; CHECK-NEXT: or.b64 %rd22, %rd58, %rd59;
; CHECK-NEXT: setp.eq.b64 %p14, %rd22, 0;
-; CHECK-NEXT: cvt.u32.u64 %r5, %rd18;
+; CHECK-NEXT: cvt.u32.u64 %r5, %rd3;
; CHECK-NEXT: sub.s32 %r6, 127, %r5;
-; CHECK-NEXT: shl.b64 %rd23, %rd6, %r6;
+; CHECK-NEXT: shl.b64 %rd23, %rd8, %r6;
; CHECK-NEXT: sub.s32 %r7, 64, %r6;
-; CHECK-NEXT: shr.u64 %rd24, %rd5, %r7;
+; CHECK-NEXT: shr.u64 %rd24, %rd7, %r7;
; CHECK-NEXT: or.b64 %rd25, %rd23, %rd24;
; CHECK-NEXT: sub.s32 %r8, 63, %r5;
-; CHECK-NEXT: shl.b64 %rd26, %rd5, %r8;
+; CHECK-NEXT: shl.b64 %rd26, %rd7, %r8;
; CHECK-NEXT: setp.gt.s32 %p15, %r6, 63;
; CHECK-NEXT: selp.b64 %rd63, %rd26, %rd25, %p15;
-; CHECK-NEXT: shl.b64 %rd62, %rd5, %r6;
+; CHECK-NEXT: shl.b64 %rd62, %rd7, %r6;
; CHECK-NEXT: mov.b64 %rd57, 0;
; CHECK-NEXT: mov.b64 %rd56, %rd57;
; CHECK-NEXT: @%p14 bra $L__BB1_4;
; CHECK-NEXT: // %bb.2: // %udiv-preheader
; CHECK-NEXT: cvt.u32.u64 %r9, %rd58;
-; CHECK-NEXT: shr.u64 %rd27, %rd5, %r9;
+; CHECK-NEXT: shr.u64 %rd27, %rd7, %r9;
; CHECK-NEXT: sub.s32 %r10, 64, %r9;
-; CHECK-NEXT: shl.b64 %rd28, %rd6, %r10;
+; CHECK-NEXT: shl.b64 %rd28, %rd8, %r10;
; CHECK-NEXT: or.b64 %rd29, %rd27, %rd28;
; CHECK-NEXT: add.s32 %r11, %r9, -64;
-; CHECK-NEXT: shr.u64 %rd30, %rd6, %r11;
+; CHECK-NEXT: shr.u64 %rd30, %rd8, %r11;
; CHECK-NEXT: setp.gt.s32 %p16, %r9, 63;
; CHECK-NEXT: selp.b64 %rd60, %rd30, %rd29, %p16;
-; CHECK-NEXT: shr.u64 %rd61, %rd6, %r9;
-; CHECK-NEXT: add.cc.s64 %rd3, %rd1, -1;
-; CHECK-NEXT: addc.cc.s64 %rd4, %rd2, -1;
+; CHECK-NEXT: shr.u64 %rd61, %rd8, %r9;
+; CHECK-NEXT: add.cc.s64 %rd5, %rd1, -1;
+; CHECK-NEXT: addc.cc.s64 %rd6, %rd2, -1;
; CHECK-NEXT: mov.b64 %rd56, %rd57;
; CHECK-NEXT: $L__BB1_3: // %udiv-do-while
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
@@ -233,8 +233,8 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: shl.b64 %rd40, %rd62, 1;
; CHECK-NEXT: or.b64 %rd62, %rd56, %rd40;
; CHECK-NEXT: or.b64 %rd63, %rd57, %rd39;
-; CHECK-NEXT: sub.cc.s64 %rd41, %rd3, %rd36;
-; CHECK-NEXT: subc.cc.s64 %rd42, %rd4, %rd33;
+; CHECK-NEXT: sub.cc.s64 %rd41, %rd5, %rd36;
+; CHECK-NEXT: subc.cc.s64 %rd42, %rd6, %rd33;
; CHECK-NEXT: shr.s64 %rd43, %rd42, 63;
; CHECK-NEXT: and.b64 %rd56, %rd43, 1;
; CHECK-NEXT: and.b64 %rd44, %rd43, %rd1;
@@ -257,8 +257,8 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: mad.lo.s64 %rd51, %rd1, %rd65, %rd50;
; CHECK-NEXT: mad.lo.s64 %rd52, %rd2, %rd64, %rd51;
; CHECK-NEXT: mul.lo.s64 %rd53, %rd1, %rd64;
-; CHECK-NEXT: sub.cc.s64 %rd54, %rd5, %rd53;
-; CHECK-NEXT: subc.cc.s64 %rd55, %rd6, %rd52;
+; CHECK-NEXT: sub.cc.s64 %rd54, %rd7, %rd53;
+; CHECK-NEXT: subc.cc.s64 %rd55, %rd8, %rd52;
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd54, %rd55};
; CHECK-NEXT: ret;
%div = urem i128 %lhs, %rhs
@@ -441,75 +441,75 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: .reg .b64 %rd<60>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %_udiv-special-cases
-; CHECK-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [udiv_i128_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [udiv_i128_param_1];
-; CHECK-NEXT: or.b64 %rd7, %rd5, %rd6;
-; CHECK-NEXT: setp.eq.b64 %p1, %rd7, 0;
-; CHECK-NEXT: or.b64 %rd8, %rd3, %rd4;
-; CHECK-NEXT: setp.eq.b64 %p2, %rd8, 0;
+; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [udiv_i128_param_0];
+; CHECK-NEXT: ld.param.v2.b64 {%rd7, %rd8}, [udiv_i128_param_1];
+; CHECK-NEXT: or.b64 %rd9, %rd7, %rd8;
+; CHECK-NEXT: setp.eq.b64 %p1, %rd9, 0;
+; CHECK-NEXT: or.b64 %rd10, %rd5, %rd6;
+; CHECK-NEXT: setp.eq.b64 %p2, %rd10, 0;
; CHECK-NEXT: or.pred %p3, %p1, %p2;
-; CHECK-NEXT: setp.ne.b64 %p4, %rd6, 0;
-; CHECK-NEXT: clz.b64 %r1, %rd6;
-; CHECK-NEXT: cvt.u64.u32 %rd9, %r1;
-; CHECK-NEXT: clz.b64 %r2, %rd5;
-; CHECK-NEXT: cvt.u64.u32 %rd10, %r2;
-; CHECK-NEXT: add.s64 %rd11, %rd10, 64;
-; CHECK-NEXT: selp.b64 %rd12, %rd9, %rd11, %p4;
-; CHECK-NEXT: setp.ne.b64 %p5, %rd4, 0;
-; CHECK-NEXT: clz.b64 %r3, %rd4;
-; CHECK-NEXT: cvt.u64.u32 %rd13, %r3;
-; CHECK-NEXT: clz.b64 %r4, %rd3;
-; CHECK-NEXT: cvt.u64.u32 %rd14, %r4;
-; CHECK-NEXT: add.s64 %rd15, %rd14, 64;
-; CHECK-NEXT: selp.b64 %rd16, %rd13, %rd15, %p5;
-; CHECK-NEXT: mov.b64 %rd17, 0;
-; CHECK-NEXT: sub.cc.s64 %rd18, %rd12, %rd16;
-; CHECK-NEXT: subc.cc.s64 %rd19, %rd17, 0;
-; CHECK-NEXT: setp.gt.u64 %p6, %rd18, 127;
-; CHECK-NEXT: setp.eq.b64 %p7, %rd19, 0;
+; CHECK-NEXT: setp.ne.b64 %p4, %rd8, 0;
+; CHECK-NEXT: clz.b64 %r1, %rd8;
+; CHECK-NEXT: cvt.u64.u32 %rd11, %r1;
+; CHECK-NEXT: clz.b64 %r2, %rd7;
+; CHECK-NEXT: cvt.u64.u32 %rd12, %r2;
+; CHECK-NEXT: add.s64 %rd13, %rd12, 64;
+; CHECK-NEXT: selp.b64 %rd14, %rd11, %rd13, %p4;
+; CHECK-NEXT: setp.ne.b64 %p5, %rd6, 0;
+; CHECK-NEXT: clz.b64 %r3, %rd6;
+; CHECK-NEXT: cvt.u64.u32 %rd15, %r3;
+; CHECK-NEXT: clz.b64 %r4, %rd5;
+; CHECK-NEXT: cvt.u64.u32 %rd16, %r4;
+; CHECK-NEXT: add.s64 %rd17, %rd16, 64;
+; CHECK-NEXT: selp.b64 %rd18, %rd15, %rd17, %p5;
+; CHECK-NEXT: mov.b64 %rd19, 0;
+; CHECK-NEXT: sub.cc.s64 %rd1, %rd14, %rd18;
+; CHECK-NEXT: subc.cc.s64 %rd2, %rd19, 0;
+; CHECK-NEXT: setp.gt.u64 %p6, %rd1, 127;
+; CHECK-NEXT: setp.eq.b64 %p7, %rd2, 0;
; CHECK-NEXT: and.pred %p8, %p7, %p6;
-; CHECK-NEXT: setp.ne.b64 %p9, %rd19, 0;
+; CHECK-NEXT: setp.ne.b64 %p9, %rd2, 0;
; CHECK-NEXT: or.pred %p10, %p8, %p9;
; CHECK-NEXT: or.pred %p11, %p3, %p10;
-; CHECK-NEXT: xor.b64 %rd20, %rd18, 127;
-; CHECK-NEXT: or.b64 %rd21, %rd20, %rd19;
+; CHECK-NEXT: xor.b64 %rd20, %rd1, 127;
+; CHECK-NEXT: or.b64 %rd21, %rd20, %rd2;
; CHECK-NEXT: setp.eq.b64 %p12, %rd21, 0;
-; CHECK-NEXT: selp.b64 %rd59, 0, %rd4, %p11;
-; CHECK-NEXT: selp.b64 %rd58, 0, %rd3, %p11;
+; CHECK-NEXT: selp.b64 %rd59, 0, %rd6, %p11;
+; CHECK-NEXT: selp.b64 %rd58, 0, %rd5, %p11;
; CHECK-NEXT: or.pred %p13, %p11, %p12;
; CHECK-NEXT: @%p13 bra $L__BB5_5;
; CHECK-NEXT: // %bb.1: // %udiv-bb1
-; CHECK-NEXT: add.cc.s64 %rd52, %rd18, 1;
-; CHECK-NEXT: addc.cc.s64 %rd53, %rd19, 0;
+; CHECK-NEXT: add.cc.s64 %rd52, %rd1, 1;
+; CHECK-NEXT: addc.cc.s64 %rd53, %rd2, 0;
; CHECK-NEXT: or.b64 %rd22, %rd52, %rd53;
; CHECK-NEXT: setp.eq.b64 %p14, %rd22, 0;
-; CHECK-NEXT: cvt.u32.u64 %r5, %rd18;
+; CHECK-NEXT: cvt.u32.u64 %r5, %rd1;
; CHECK-NEXT: sub.s32 %r6, 127, %r5;
-; CHECK-NEXT: shl.b64 %rd23, %rd4, %r6;
+; CHECK-NEXT: shl.b64 %rd23, %rd6, %r6;
; CHECK-NEXT: sub.s32 %r7, 64, %r6;
-; CHECK-NEXT: shr.u64 %rd24, %rd3, %r7;
+; CHECK-NEXT: shr.u64 %rd24, %rd5, %r7;
; CHECK-NEXT: or.b64 %rd25, %rd23, %rd24;
; CHECK-NEXT: sub.s32 %r8, 63, %r5;
-; CHECK-NEXT: shl.b64 %rd26, %rd3, %r8;
+; CHECK-NEXT: shl.b64 %rd26, %rd5, %r8;
; CHECK-NEXT: setp.gt.s32 %p15, %r6, 63;
; CHECK-NEXT: selp.b64 %rd57, %rd26, %rd25, %p15;
-; CHECK-NEXT: shl.b64 %rd56, %rd3, %r6;
+; CHECK-NEXT: shl.b64 %rd56, %rd5, %r6;
; CHECK-NEXT: mov.b64 %rd51, 0;
; CHECK-NEXT: mov.b64 %rd50, %rd51;
; CHECK-NEXT: @%p14 bra $L__BB5_4;
; CHECK-NEXT: // %bb.2: // %udiv-preheader
; CHECK-NEXT: cvt.u32.u64 %r9, %rd52;
-; CHECK-NEXT: shr.u64 %rd27, %rd3, %r9;
+; CHECK-NEXT: shr.u64 %rd27, %rd5, %r9;
; CHECK-NEXT: sub.s32 %r10, 64, %r9;
-; CHECK-NEXT: shl.b64 %rd28, %rd4, %r10;
+; CHECK-NEXT: shl.b64 %rd28, %rd6, %r10;
; CHECK-NEXT: or.b64 %rd29, %rd27, %rd28;
; CHECK-NEXT: add.s32 %r11, %r9, -64;
-; CHECK-NEXT: shr.u64 %rd30, %rd4, %r11;
+; CHECK-NEXT: shr.u64 %rd30, %rd6, %r11;
; CHECK-NEXT: setp.gt.s32 %p16, %r9, 63;
; CHECK-NEXT: selp.b64 %rd54, %rd30, %rd29, %p16;
-; CHECK-NEXT: shr.u64 %rd55, %rd4, %r9;
-; CHECK-NEXT: add.cc.s64 %rd1, %rd5, -1;
-; CHECK-NEXT: addc.cc.s64 %rd2, %rd6, -1;
+; CHECK-NEXT: shr.u64 %rd55, %rd6, %r9;
+; CHECK-NEXT: add.cc.s64 %rd3, %rd7, -1;
+; CHECK-NEXT: addc.cc.s64 %rd4, %rd8, -1;
; CHECK-NEXT: mov.b64 %rd50, %rd51;
; CHECK-NEXT: $L__BB5_3: // %udiv-do-while
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
@@ -525,12 +525,12 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) {
; CHECK-NEXT: shl.b64 %rd40, %rd56, 1;
; CHECK-NEXT: or.b64 %rd56, %rd50, %rd40;
; CHECK-NEXT: or.b64 %rd57, %rd51, %rd39;
-; CHECK-NEXT: sub.cc.s64 %rd41, %rd1, %rd36;
-; CHECK-NEXT: subc.cc.s64 %rd42, %rd2, %rd33;
+; CHECK-NEXT: sub.cc.s64 %rd41, %rd3, %rd36;
+; CHECK-NEXT: subc.cc.s64 %rd42, %rd4, %rd33;
; CHECK-NEXT: shr.s64 %rd43, %rd42, 63;
; CHECK-NEXT: and.b64 %rd50, %rd43, 1;
-; CHECK-NEXT: and.b64 %rd44, %rd43, %rd5;
-; CHECK-NEXT: and.b64 %rd45, %rd43, %rd6;
+; CHECK-NEXT: and.b64 %rd44, %rd43, %rd7;
+; CHECK-NEXT: and.b64 %rd45, %rd43, %rd8;
; CHECK-NEXT: sub.cc.s64 %rd54, %rd36, %rd44;
; CHECK-NEXT: subc.cc.s64 %rd55, %rd33, %rd45;
; CHECK-NEXT: add.cc.s64 %rd52, %rd52, -1;
diff --git a/llvm/test/CodeGen/RISCV/abds-neg.ll b/llvm/test/CodeGen/RISCV/abds-neg.ll
index 23e5d62a45c77..6c827bce1fbc5 100644
--- a/llvm/test/CodeGen/RISCV/abds-neg.ll
+++ b/llvm/test/CodeGen/RISCV/abds-neg.ll
@@ -2370,26 +2370,26 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a5, 8(a1)
-; RV32I-NEXT: lw t1, 12(a1)
+; RV32I-NEXT: lw t0, 12(a1)
; RV32I-NEXT: lw a7, 8(a2)
; RV32I-NEXT: lw a4, 0(a2)
-; RV32I-NEXT: lw t2, 12(a2)
+; RV32I-NEXT: lw t1, 12(a2)
; RV32I-NEXT: lw a6, 4(a2)
-; RV32I-NEXT: lw t0, 4(a1)
-; RV32I-NEXT: sltu a1, a5, a7
-; RV32I-NEXT: sub t1, t1, t2
+; RV32I-NEXT: lw a1, 4(a1)
+; RV32I-NEXT: sltu t2, a5, a7
+; RV32I-NEXT: sub t0, t0, t1
; RV32I-NEXT: sltu a2, a3, a4
-; RV32I-NEXT: sub a1, t1, a1
+; RV32I-NEXT: sub t0, t0, t2
; RV32I-NEXT: mv t1, a2
-; RV32I-NEXT: beq t0, a6, .LBB31_2
+; RV32I-NEXT: beq a1, a6, .LBB31_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, t0, a6
+; RV32I-NEXT: sltu t1, a1, a6
; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: sub a5, a5, a7
-; RV32I-NEXT: sub a6, t0, a6
-; RV32I-NEXT: sltu a7, a5, t1
+; RV32I-NEXT: sub a6, a1, a6
+; RV32I-NEXT: sltu a1, a5, t1
; RV32I-NEXT: sub a4, a3, a4
-; RV32I-NEXT: sub a7, a1, a7
+; RV32I-NEXT: sub a7, t0, a1
; RV32I-NEXT: sub a3, a5, t1
; RV32I-NEXT: srai a1, a7, 31
; RV32I-NEXT: sub t0, a6, a2
@@ -2438,26 +2438,26 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lw a3, 0(a1)
; RV32ZBB-NEXT: lw a5, 8(a1)
-; RV32ZBB-NEXT: lw t1, 12(a1)
+; RV32ZBB-NEXT: lw t0, 12(a1)
; RV32ZBB-NEXT: lw a7, 8(a2)
; RV32ZBB-NEXT: lw a4, 0(a2)
-; RV32ZBB-NEXT: lw t2, 12(a2)
+; RV32ZBB-NEXT: lw t1, 12(a2)
; RV32ZBB-NEXT: lw a6, 4(a2)
-; RV32ZBB-NEXT: lw t0, 4(a1)
-; RV32ZBB-NEXT: sltu a1, a5, a7
-; RV32ZBB-NEXT: sub t1, t1, t2
+; RV32ZBB-NEXT: lw a1, 4(a1)
+; RV32ZBB-NEXT: sltu t2, a5, a7
+; RV32ZBB-NEXT: sub t0, t0, t1
; RV32ZBB-NEXT: sltu a2, a3, a4
-; RV32ZBB-NEXT: sub a1, t1, a1
+; RV32ZBB-NEXT: sub t0, t0, t2
; RV32ZBB-NEXT: mv t1, a2
-; RV32ZBB-NEXT: beq t0, a6, .LBB31_2
+; RV32ZBB-NEXT: beq a1, a6, .LBB31_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, t0, a6
+; RV32ZBB-NEXT: sltu t1, a1, a6
; RV32ZBB-NEXT: .LBB31_2:
; RV32ZBB-NEXT: sub a5, a5, a7
-; RV32ZBB-NEXT: sub a6, t0, a6
-; RV32ZBB-NEXT: sltu a7, a5, t1
+; RV32ZBB-NEXT: sub a6, a1, a6
+; RV32ZBB-NEXT: sltu a1, a5, t1
; RV32ZBB-NEXT: sub a4, a3, a4
-; RV32ZBB-NEXT: sub a7, a1, a7
+; RV32ZBB-NEXT: sub a7, t0, a1
; RV32ZBB-NEXT: sub a3, a5, t1
; RV32ZBB-NEXT: srai a1, a7, 31
; RV32ZBB-NEXT: sub t0, a6, a2
@@ -2512,26 +2512,26 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a5, 8(a1)
-; RV32I-NEXT: lw t1, 12(a1)
+; RV32I-NEXT: lw t0, 12(a1)
; RV32I-NEXT: lw a7, 8(a2)
; RV32I-NEXT: lw a4, 0(a2)
-; RV32I-NEXT: lw t2, 12(a2)
+; RV32I-NEXT: lw t1, 12(a2)
; RV32I-NEXT: lw a6, 4(a2)
-; RV32I-NEXT: lw t0, 4(a1)
-; RV32I-NEXT: sltu a1, a5, a7
-; RV32I-NEXT: sub t1, t1, t2
+; RV32I-NEXT: lw a1, 4(a1)
+; RV32I-NEXT: sltu t2, a5, a7
+; RV32I-NEXT: sub t0, t0, t1
; RV32I-NEXT: sltu a2, a3, a4
-; RV32I-NEXT: sub a1, t1, a1
+; RV32I-NEXT: sub t0, t0, t2
; RV32I-NEXT: mv t1, a2
-; RV32I-NEXT: beq t0, a6, .LBB32_2
+; RV32I-NEXT: beq a1, a6, .LBB32_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, t0, a6
+; RV32I-NEXT: sltu t1, a1, a6
; RV32I-NEXT: .LBB32_2:
; RV32I-NEXT: sub a5, a5, a7
-; RV32I-NEXT: sub a6, t0, a6
-; RV32I-NEXT: sltu a7, a5, t1
+; RV32I-NEXT: sub a6, a1, a6
+; RV32I-NEXT: sltu a1, a5, t1
; RV32I-NEXT: sub a4, a3, a4
-; RV32I-NEXT: sub a7, a1, a7
+; RV32I-NEXT: sub a7, t0, a1
; RV32I-NEXT: sub a3, a5, t1
; RV32I-NEXT: srai a1, a7, 31
; RV32I-NEXT: sub t0, a6, a2
@@ -2580,26 +2580,26 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lw a3, 0(a1)
; RV32ZBB-NEXT: lw a5, 8(a1)
-; RV32ZBB-NEXT: lw t1, 12(a1)
+; RV32ZBB-NEXT: lw t0, 12(a1)
; RV32ZBB-NEXT: lw a7, 8(a2)
; RV32ZBB-NEXT: lw a4, 0(a2)
-; RV32ZBB-NEXT: lw t2, 12(a2)
+; RV32ZBB-NEXT: lw t1, 12(a2)
; RV32ZBB-NEXT: lw a6, 4(a2)
-; RV32ZBB-NEXT: lw t0, 4(a1)
-; RV32ZBB-NEXT: sltu a1, a5, a7
-; RV32ZBB-NEXT: sub t1, t1, t2
+; RV32ZBB-NEXT: lw a1, 4(a1)
+; RV32ZBB-NEXT: sltu t2, a5, a7
+; RV32ZBB-NEXT: sub t0, t0, t1
; RV32ZBB-NEXT: sltu a2, a3, a4
-; RV32ZBB-NEXT: sub a1, t1, a1
+; RV32ZBB-NEXT: sub t0, t0, t2
; RV32ZBB-NEXT: mv t1, a2
-; RV32ZBB-NEXT: beq t0, a6, .LBB32_2
+; RV32ZBB-NEXT: beq a1, a6, .LBB32_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, t0, a6
+; RV32ZBB-NEXT: sltu t1, a1, a6
; RV32ZBB-NEXT: .LBB32_2:
; RV32ZBB-NEXT: sub a5, a5, a7
-; RV32ZBB-NEXT: sub a6, t0, a6
-; RV32ZBB-NEXT: sltu a7, a5, t1
+; RV32ZBB-NEXT: sub a6, a1, a6
+; RV32ZBB-NEXT: sltu a1, a5, t1
; RV32ZBB-NEXT: sub a4, a3, a4
-; RV32ZBB-NEXT: sub a7, a1, a7
+; RV32ZBB-NEXT: sub a7, t0, a1
; RV32ZBB-NEXT: sub a3, a5, t1
; RV32ZBB-NEXT: srai a1, a7, 31
; RV32ZBB-NEXT: sub t0, a6, a2
diff --git a/llvm/test/CodeGen/RISCV/abds.ll b/llvm/test/CodeGen/RISCV/abds.ll
index 7d04e06ec7e7e..5ada36b8abeb3 100644
--- a/llvm/test/CodeGen/RISCV/abds.ll
+++ b/llvm/test/CodeGen/RISCV/abds.ll
@@ -2045,11 +2045,11 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sltu a4, a5, a6
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a4
-; RV32I-NEXT: snez a7, a3
; RV32I-NEXT: sub a4, a5, a6
-; RV32I-NEXT: add a2, a2, a7
-; RV32I-NEXT: neg a2, a2
+; RV32I-NEXT: snez a5, a3
; RV32I-NEXT: neg a3, a3
+; RV32I-NEXT: add a2, a2, a5
+; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: .LBB31_4:
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: sw a2, 4(a0)
@@ -2108,11 +2108,11 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sltu a4, a5, a6
; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: sub a1, a1, a4
-; RV32ZBB-NEXT: snez a7, a3
; RV32ZBB-NEXT: sub a4, a5, a6
-; RV32ZBB-NEXT: add a2, a2, a7
-; RV32ZBB-NEXT: neg a2, a2
+; RV32ZBB-NEXT: snez a5, a3
; RV32ZBB-NEXT: neg a3, a3
+; RV32ZBB-NEXT: add a2, a2, a5
+; RV32ZBB-NEXT: neg a2, a2
; RV32ZBB-NEXT: .LBB31_4:
; RV32ZBB-NEXT: sw a3, 0(a0)
; RV32ZBB-NEXT: sw a2, 4(a0)
@@ -2176,11 +2176,11 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sltu a4, a5, a6
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a4
-; RV32I-NEXT: snez a7, a3
; RV32I-NEXT: sub a4, a5, a6
-; RV32I-NEXT: add a2, a2, a7
-; RV32I-NEXT: neg a2, a2
+; RV32I-NEXT: snez a5, a3
; RV32I-NEXT: neg a3, a3
+; RV32I-NEXT: add a2, a2, a5
+; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: .LBB32_4:
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: sw a2, 4(a0)
@@ -2239,11 +2239,11 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sltu a4, a5, a6
; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: sub a1, a1, a4
-; RV32ZBB-NEXT: snez a7, a3
; RV32ZBB-NEXT: sub a4, a5, a6
-; RV32ZBB-NEXT: add a2, a2, a7
-; RV32ZBB-NEXT: neg a2, a2
+; RV32ZBB-NEXT: snez a5, a3
; RV32ZBB-NEXT: neg a3, a3
+; RV32ZBB-NEXT: add a2, a2, a5
+; RV32ZBB-NEXT: neg a2, a2
; RV32ZBB-NEXT: .LBB32_4:
; RV32ZBB-NEXT: sw a3, 0(a0)
; RV32ZBB-NEXT: sw a2, 4(a0)
diff --git a/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll b/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
index 068eb0cb14bfc..649b1cf976ee0 100644
--- a/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
+++ b/llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
@@ -38,69 +38,69 @@ define void @test_bitint_200_add(ptr %a, ptr %b, ptr %out) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a3, 0(a1)
-; RV32-NEXT: lw a7, 4(a1)
-; RV32-NEXT: lw t2, 4(a0)
-; RV32-NEXT: lw t1, 8(a0)
-; RV32-NEXT: lw t0, 12(a0)
+; RV32-NEXT: lw t0, 4(a1)
+; RV32-NEXT: lw a7, 4(a0)
+; RV32-NEXT: lw t2, 8(a0)
+; RV32-NEXT: lw t1, 12(a0)
; RV32-NEXT: lw a5, 8(a1)
; RV32-NEXT: lw a6, 12(a1)
; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add t3, t2, a7
-; RV32-NEXT: sltu a7, a3, a4
-; RV32-NEXT: add a4, t3, a7
-; RV32-NEXT: beq a4, t2, .LBB0_2
+; RV32-NEXT: add t3, a7, t0
+; RV32-NEXT: sltu t0, a3, a4
+; RV32-NEXT: add a4, t3, t0
+; RV32-NEXT: beq a4, a7, .LBB0_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: sltu a7, a4, t2
+; RV32-NEXT: sltu t0, a4, a7
; RV32-NEXT: .LBB0_2:
-; RV32-NEXT: add t2, t1, a5
-; RV32-NEXT: add a5, t2, a7
-; RV32-NEXT: add a6, t0, a6
-; RV32-NEXT: sltu t3, t2, t1
-; RV32-NEXT: sltu t2, a5, t2
+; RV32-NEXT: add t3, t2, a5
+; RV32-NEXT: lw a7, 20(a0)
+; RV32-NEXT: add a5, t3, t0
+; RV32-NEXT: add a6, t1, a6
+; RV32-NEXT: sltu t4, t3, t2
+; RV32-NEXT: sltu t3, a5, t3
+; RV32-NEXT: add a6, a6, t4
; RV32-NEXT: add a6, a6, t3
-; RV32-NEXT: add a6, a6, t2
-; RV32-NEXT: beq a6, t0, .LBB0_4
+; RV32-NEXT: beq a6, t1, .LBB0_4
; RV32-NEXT: # %bb.3:
-; RV32-NEXT: sltu t4, a6, t0
+; RV32-NEXT: sltu t4, a6, t1
; RV32-NEXT: j .LBB0_5
; RV32-NEXT: .LBB0_4:
-; RV32-NEXT: sltu t4, a5, t1
+; RV32-NEXT: sltu t4, a5, t2
; RV32-NEXT: .LBB0_5:
; RV32-NEXT: lw t3, 16(a0)
-; RV32-NEXT: lw t2, 20(a0)
; RV32-NEXT: lw t6, 16(a1)
; RV32-NEXT: lw t5, 20(a1)
-; RV32-NEXT: xor t1, a5, t1
-; RV32-NEXT: xor t0, a6, t0
-; RV32-NEXT: or t0, t1, t0
-; RV32-NEXT: beqz t0, .LBB0_7
+; RV32-NEXT: xor t2, a5, t2
+; RV32-NEXT: xor t1, a6, t1
+; RV32-NEXT: or t1, t2, t1
+; RV32-NEXT: beqz t1, .LBB0_7
; RV32-NEXT: # %bb.6:
-; RV32-NEXT: mv a7, t4
+; RV32-NEXT: mv t0, t4
; RV32-NEXT: .LBB0_7:
; RV32-NEXT: lbu a0, 24(a0)
; RV32-NEXT: add t6, t3, t6
-; RV32-NEXT: lbu a1, 24(a1)
-; RV32-NEXT: add a7, t6, a7
-; RV32-NEXT: add t4, t2, t5
-; RV32-NEXT: sltu t1, t6, t3
-; RV32-NEXT: sltu t3, a7, t6
-; RV32-NEXT: add t4, t4, t1
-; RV32-NEXT: add t0, t4, t3
-; RV32-NEXT: sltu t5, t0, t4
+; RV32-NEXT: lbu t1, 24(a1)
+; RV32-NEXT: add t0, t6, t0
+; RV32-NEXT: add t4, a7, t5
+; RV32-NEXT: sltu t2, t6, t3
+; RV32-NEXT: sltu t3, t0, t6
+; RV32-NEXT: add t4, t4, t2
+; RV32-NEXT: add a1, t4, t3
+; RV32-NEXT: sltu t5, a1, t4
; RV32-NEXT: and t3, t3, t5
-; RV32-NEXT: beq t4, t2, .LBB0_9
+; RV32-NEXT: beq t4, a7, .LBB0_9
; RV32-NEXT: # %bb.8:
-; RV32-NEXT: sltu t1, t4, t2
+; RV32-NEXT: sltu t2, t4, a7
; RV32-NEXT: .LBB0_9:
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add t1, t1, t3
; RV32-NEXT: add a0, a0, t1
+; RV32-NEXT: add t2, t2, t3
+; RV32-NEXT: add a0, a0, t2
; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: sw a5, 8(a2)
; RV32-NEXT: sw a6, 12(a2)
-; RV32-NEXT: sw a7, 16(a2)
-; RV32-NEXT: sw t0, 20(a2)
+; RV32-NEXT: sw t0, 16(a2)
+; RV32-NEXT: sw a1, 20(a2)
; RV32-NEXT: sb a0, 24(a2)
; RV32-NEXT: ret
%1 = load i200, ptr %a, align 8
diff --git a/llvm/test/CodeGen/RISCV/clmul.ll b/llvm/test/CodeGen/RISCV/clmul.ll
index 1a7dbdaadf1a8..b0a61880a44d6 100644
--- a/llvm/test/CodeGen/RISCV/clmul.ll
+++ b/llvm/test/CodeGen/RISCV/clmul.ll
@@ -4136,12 +4136,12 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sw s9, 196(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s10, 192(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 188(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s3, a3
+; RV32I-NEXT: mv s4, a3
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: srli a5, a3, 8
; RV32I-NEXT: addi a4, a0, -256
-; RV32I-NEXT: lui s4, 16
+; RV32I-NEXT: lui s5, 16
; RV32I-NEXT: and a5, a5, a4
; RV32I-NEXT: srli a6, a3, 24
; RV32I-NEXT: and a7, a3, a4
@@ -4164,254 +4164,254 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: and a7, a7, a6
; RV32I-NEXT: and t0, t0, a6
; RV32I-NEXT: slli a7, a7, 2
-; RV32I-NEXT: or t1, t0, a7
-; RV32I-NEXT: srli t2, t1, 1
+; RV32I-NEXT: or t2, t0, a7
+; RV32I-NEXT: srli t1, t2, 1
; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi t0, a7, 1365
; RV32I-NEXT: srli t3, a2, 8
-; RV32I-NEXT: and t2, t2, t0
+; RV32I-NEXT: and t4, t1, t0
; RV32I-NEXT: and t3, t3, a4
-; RV32I-NEXT: srli t4, a2, 24
-; RV32I-NEXT: and t5, a2, a4
-; RV32I-NEXT: slli t5, t5, 8
-; RV32I-NEXT: slli t6, a2, 24
-; RV32I-NEXT: or t3, t3, t4
-; RV32I-NEXT: or t4, t6, t5
-; RV32I-NEXT: and t1, t1, t0
-; RV32I-NEXT: or t3, t4, t3
-; RV32I-NEXT: srli t4, t3, 4
+; RV32I-NEXT: srli t5, a2, 24
+; RV32I-NEXT: and t6, a2, a4
+; RV32I-NEXT: slli t6, t6, 8
+; RV32I-NEXT: slli s0, a2, 24
+; RV32I-NEXT: or t3, t3, t5
+; RV32I-NEXT: or t5, s0, t6
+; RV32I-NEXT: and t2, t2, t0
+; RV32I-NEXT: or t3, t5, t3
+; RV32I-NEXT: srli t5, t3, 4
; RV32I-NEXT: and t3, t3, a5
-; RV32I-NEXT: and t4, t4, a5
+; RV32I-NEXT: and t5, t5, a5
; RV32I-NEXT: slli t3, t3, 4
-; RV32I-NEXT: slli t1, t1, 1
-; RV32I-NEXT: or t3, t4, t3
-; RV32I-NEXT: srli t4, t3, 2
+; RV32I-NEXT: slli t2, t2, 1
+; RV32I-NEXT: or t3, t5, t3
+; RV32I-NEXT: srli t5, t3, 2
; RV32I-NEXT: and t3, t3, a6
-; RV32I-NEXT: and t4, t4, a6
+; RV32I-NEXT: and t5, t5, a6
; RV32I-NEXT: slli t3, t3, 2
-; RV32I-NEXT: or t1, t2, t1
-; RV32I-NEXT: or t2, t4, t3
-; RV32I-NEXT: srli t3, t2, 1
-; RV32I-NEXT: and t2, t2, t0
+; RV32I-NEXT: or t2, t4, t2
+; RV32I-NEXT: or t3, t5, t3
+; RV32I-NEXT: srli t4, t3, 1
; RV32I-NEXT: and t3, t3, t0
-; RV32I-NEXT: slli t2, t2, 1
-; RV32I-NEXT: slli t4, t1, 1
-; RV32I-NEXT: or t3, t3, t2
-; RV32I-NEXT: andi t5, t3, 2
-; RV32I-NEXT: andi t6, t3, 1
-; RV32I-NEXT: seqz t5, t5
+; RV32I-NEXT: and t4, t4, t0
+; RV32I-NEXT: slli t3, t3, 1
+; RV32I-NEXT: slli t5, t2, 1
+; RV32I-NEXT: or t4, t4, t3
+; RV32I-NEXT: andi t6, t4, 2
+; RV32I-NEXT: andi s0, t4, 1
; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and t4, t5, t4
-; RV32I-NEXT: and t5, t6, t1
-; RV32I-NEXT: slli t6, t1, 2
-; RV32I-NEXT: andi s0, t3, 4
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: andi s1, t3, 8
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and t5, t6, t5
+; RV32I-NEXT: and t6, s0, t2
+; RV32I-NEXT: slli s0, t2, 2
+; RV32I-NEXT: andi s1, t4, 4
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: slli s2, t1, 3
+; RV32I-NEXT: andi s2, t4, 8
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: and t6, s0, t6
-; RV32I-NEXT: and s0, s1, s2
-; RV32I-NEXT: xor t4, t5, t4
-; RV32I-NEXT: xor t5, t6, s0
-; RV32I-NEXT: xor t4, t4, t5
-; RV32I-NEXT: andi t5, t3, 16
-; RV32I-NEXT: slli t6, t1, 4
-; RV32I-NEXT: seqz t5, t5
-; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: andi s0, t3, 32
-; RV32I-NEXT: and t5, t5, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: slli s0, t1, 5
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and t6, t6, s0
-; RV32I-NEXT: andi s0, t3, 64
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: slli s0, t1, 6
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and t6, t6, s0
-; RV32I-NEXT: andi s0, t3, 128
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: slli s0, t1, 7
+; RV32I-NEXT: seqz s2, s2
+; RV32I-NEXT: slli s3, t2, 3
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: and s0, s1, s0
+; RV32I-NEXT: and s1, s2, s3
+; RV32I-NEXT: xor t5, t6, t5
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: xor t5, t5, s0
+; RV32I-NEXT: andi t6, t4, 16
+; RV32I-NEXT: slli s0, t2, 4
+; RV32I-NEXT: seqz t6, t6
; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: andi s1, t4, 32
; RV32I-NEXT: and t6, t6, s0
-; RV32I-NEXT: andi s0, t3, 256
-; RV32I-NEXT: slli s1, t1, 8
-; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: slli s1, t2, 5
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: andi s2, t3, 512
; RV32I-NEXT: and s0, s0, s1
-; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: slli s2, t1, 9
-; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: andi s1, t4, 64
; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: and s0, s1, s2
-; RV32I-NEXT: xor t4, t4, t5
-; RV32I-NEXT: xor t5, t6, s0
-; RV32I-NEXT: slli t6, t1, 10
-; RV32I-NEXT: andi s0, t3, 1024
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: li s1, 1
+; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: slli s1, t2, 6
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli s5, s1, 11
-; RV32I-NEXT: and t6, s0, t6
-; RV32I-NEXT: and s0, t3, s5
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: slli s0, t1, 11
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and t6, t6, s0
-; RV32I-NEXT: lui s6, 1
-; RV32I-NEXT: slli s0, t1, 12
-; RV32I-NEXT: and s1, t3, s6
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: lui s7, 2
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: and s2, t3, s7
-; RV32I-NEXT: and s0, s1, s0
-; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: slli s2, t1, 13
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: and s0, s1, s2
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: andi s1, t4, 128
; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: lui s8, 4
-; RV32I-NEXT: slli s0, t1, 14
-; RV32I-NEXT: and s1, t3, s8
+; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: slli s1, t2, 7
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: andi s1, t4, 256
+; RV32I-NEXT: slli s2, t2, 8
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: and s2, t3, a0
-; RV32I-NEXT: and s0, s1, s0
-; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: slli s2, t1, 15
+; RV32I-NEXT: andi s3, t4, 512
+; RV32I-NEXT: and s1, s1, s2
+; RV32I-NEXT: seqz s2, s3
+; RV32I-NEXT: slli s3, t2, 9
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: and s1, s2, s3
+; RV32I-NEXT: xor t5, t5, t6
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: slli t6, t2, 10
+; RV32I-NEXT: andi s1, t4, 1024
+; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: li s2, 1
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: and s0, s1, s2
-; RV32I-NEXT: xor t4, t4, t5
-; RV32I-NEXT: xor t5, t6, s0
-; RV32I-NEXT: xor t4, t4, t5
-; RV32I-NEXT: slli t5, t1, 16
-; RV32I-NEXT: and t6, t3, s4
-; RV32I-NEXT: lui s2, 32
-; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: and s0, t3, s2
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli s1, t1, 17
+; RV32I-NEXT: slli s6, s2, 11
+; RV32I-NEXT: and t6, s1, t6
+; RV32I-NEXT: and s1, t4, s6
+; RV32I-NEXT: xor t6, s0, t6
+; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: slli s1, t2, 11
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and t5, t6, t5
; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: lui s7, 1
+; RV32I-NEXT: slli s1, t2, 12
+; RV32I-NEXT: and s2, t4, s7
+; RV32I-NEXT: seqz s2, s2
+; RV32I-NEXT: lui s8, 2
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: and s3, t4, s8
+; RV32I-NEXT: and s1, s2, s1
+; RV32I-NEXT: seqz s2, s3
+; RV32I-NEXT: slli s3, t2, 13
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: and s1, s2, s3
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: lui a0, 4
+; RV32I-NEXT: slli s1, t2, 14
+; RV32I-NEXT: and s2, t4, a0
+; RV32I-NEXT: seqz s2, s2
+; RV32I-NEXT: lui a0, 8
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: and s3, t4, a0
+; RV32I-NEXT: and s1, s2, s1
+; RV32I-NEXT: seqz s2, s3
+; RV32I-NEXT: slli s3, t2, 15
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: and s1, s2, s3
+; RV32I-NEXT: xor t5, t5, t6
+; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: xor t5, t5, s0
-; RV32I-NEXT: lui a0, 64
-; RV32I-NEXT: slli t6, t1, 18
-; RV32I-NEXT: and s0, t3, a0
+; RV32I-NEXT: and t6, t4, s5
+; RV32I-NEXT: slli s0, t2, 16
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: lui s3, 32
+; RV32I-NEXT: and t6, t6, s0
+; RV32I-NEXT: and s0, t4, s3
+; RV32I-NEXT: slli s1, t2, 17
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: lui a0, 128
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and s1, t3, a0
-; RV32I-NEXT: and t6, s0, t6
+; RV32I-NEXT: lui a0, 64
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: and s1, t4, a0
+; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: slli s1, t1, 19
+; RV32I-NEXT: slli s1, t2, 18
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: and s0, s0, s1
-; RV32I-NEXT: xor t5, t5, s0
-; RV32I-NEXT: lui a0, 256
-; RV32I-NEXT: slli t6, t1, 20
-; RV32I-NEXT: and s0, t3, a0
+; RV32I-NEXT: lui s1, 128
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: and s0, t4, s1
+; RV32I-NEXT: slli s1, t2, 19
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: lui s1, 512
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and s1, t3, s1
-; RV32I-NEXT: and t6, s0, t6
+; RV32I-NEXT: lui a0, 256
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: and s1, t4, a0
+; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: seqz s0, s1
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli s1, t1, 21
-; RV32I-NEXT: xor t5, t5, t6
+; RV32I-NEXT: lui a0, 512
+; RV32I-NEXT: slli s1, t2, 20
+; RV32I-NEXT: and s2, t4, a0
; RV32I-NEXT: and s0, s0, s1
-; RV32I-NEXT: xor t5, t5, s0
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: slli s2, t2, 21
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: and s0, s1, s2
+; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: lui a0, 1024
-; RV32I-NEXT: xor t4, t4, t5
-; RV32I-NEXT: and t5, t3, a0
-; RV32I-NEXT: seqz t5, t5
-; RV32I-NEXT: lui a0, 2048
-; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: and t6, t3, a0
+; RV32I-NEXT: xor t5, t5, t6
+; RV32I-NEXT: and t6, t4, a0
; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: slli s0, t1, 22
-; RV32I-NEXT: and t5, t5, s0
+; RV32I-NEXT: lui a0, 2048
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: slli s0, t1, 23
+; RV32I-NEXT: and s0, t4, a0
+; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: slli s1, t2, 22
+; RV32I-NEXT: and t6, t6, s1
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: slli s1, t2, 23
; RV32I-NEXT: lui a0, 4096
-; RV32I-NEXT: and t6, t6, s0
-; RV32I-NEXT: and s0, t3, a0
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: lui s1, 8192
-; RV32I-NEXT: slli s0, t1, 24
-; RV32I-NEXT: and s1, t3, s1
-; RV32I-NEXT: lui s9, 8192
-; RV32I-NEXT: and t6, t6, s0
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: and s1, t4, a0
+; RV32I-NEXT: lui s10, 4096
+; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli t6, t1, 25
-; RV32I-NEXT: lui s1, 16384
-; RV32I-NEXT: and t6, s0, t6
-; RV32I-NEXT: and s0, t3, s1
-; RV32I-NEXT: lui s10, 16384
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: lui s1, 32768
-; RV32I-NEXT: slli s0, t1, 26
-; RV32I-NEXT: and s1, t3, s1
-; RV32I-NEXT: lui s11, 32768
-; RV32I-NEXT: and t6, t6, s0
+; RV32I-NEXT: lui s2, 8192
+; RV32I-NEXT: slli s1, t2, 24
+; RV32I-NEXT: and s2, t4, s2
+; RV32I-NEXT: lui s11, 8192
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: slli s0, t2, 25
+; RV32I-NEXT: lui a0, 16384
+; RV32I-NEXT: and s0, s1, s0
+; RV32I-NEXT: and s1, t4, a0
+; RV32I-NEXT: lui ra, 16384
+; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli t6, t1, 27
-; RV32I-NEXT: lui s1, 65536
-; RV32I-NEXT: and t6, s0, t6
-; RV32I-NEXT: and s0, t3, s1
-; RV32I-NEXT: lui s4, 65536
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: slli s0, t1, 28
-; RV32I-NEXT: and t6, t6, s0
-; RV32I-NEXT: lui s0, 131072
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: and t6, t3, s0
-; RV32I-NEXT: lui s1, 131072
-; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: lui s0, 262144
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and t3, t3, s0
-; RV32I-NEXT: lui ra, 262144
+; RV32I-NEXT: lui a0, 32768
+; RV32I-NEXT: slli s1, t2, 26
+; RV32I-NEXT: and s2, t4, a0
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: slli s0, t2, 27
+; RV32I-NEXT: lui a0, 65536
+; RV32I-NEXT: and s0, s1, s0
+; RV32I-NEXT: and s1, t4, a0
+; RV32I-NEXT: lui s9, 65536
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: lui a0, 131072
+; RV32I-NEXT: slli s1, t2, 28
+; RV32I-NEXT: and s2, t4, a0
+; RV32I-NEXT: lui s5, 131072
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: slli s0, t2, 29
+; RV32I-NEXT: lui a0, 262144
+; RV32I-NEXT: and s0, s1, s0
+; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: lui s1, 262144
+; RV32I-NEXT: slli t2, t2, 30
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: srli t3, t3, 31
+; RV32I-NEXT: and t2, t4, t2
; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: slli s0, t1, 29
-; RV32I-NEXT: and t6, t6, s0
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: srli t2, t2, 31
-; RV32I-NEXT: slli s0, t1, 30
-; RV32I-NEXT: and t3, t3, s0
-; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: slli t1, t1, 31
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: xor t3, t6, t3
-; RV32I-NEXT: and t1, t2, t1
-; RV32I-NEXT: xor t2, t4, t5
-; RV32I-NEXT: xor t1, t3, t1
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: xor t2, s0, t2
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor t3, t5, t6
; RV32I-NEXT: xor t1, t2, t1
+; RV32I-NEXT: xor t1, t3, t1
; RV32I-NEXT: srli t2, t1, 8
; RV32I-NEXT: and t2, t2, a4
; RV32I-NEXT: and a4, t1, a4
@@ -4441,183 +4441,184 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: andi a4, a2, 2
; RV32I-NEXT: slli a5, a1, 1
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a4, -1
+; RV32I-NEXT: sw a0, 176(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a4, a2, 1
-; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 172(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a4, -1
+; RV32I-NEXT: sw a0, 172(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a4, a2, 4
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a6, a6, a1
+; RV32I-NEXT: and a6, a0, a1
; RV32I-NEXT: xor a5, a6, a5
-; RV32I-NEXT: addi a7, a4, -1
-; RV32I-NEXT: sw a7, 168(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a4, -1
+; RV32I-NEXT: sw a0, 168(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a4, a1, 2
; RV32I-NEXT: andi a6, a2, 8
-; RV32I-NEXT: and a4, a7, a4
+; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 164(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 3
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: andi a7, a2, 16
; RV32I-NEXT: xor a4, a4, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 160(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 160(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 4
; RV32I-NEXT: andi a6, a2, 32
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 156(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 156(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 5
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: andi a7, a2, 64
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 152(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 6
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: andi a7, a2, 128
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 148(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 148(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 7
; RV32I-NEXT: andi a6, a2, 256
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 144(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 144(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 8
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: andi a7, a2, 512
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 140(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 9
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: andi a7, a2, 1024
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 136(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 10
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, a2, s5
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a7, a2, s6
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 132(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 132(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 11
-; RV32I-NEXT: and a6, a2, s6
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a6, a2, s7
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 128(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 12
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, a2, s7
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a7, a2, s8
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 124(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 13
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, a2, s8
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: lui t0, 4
+; RV32I-NEXT: and a7, a2, t0
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 120(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 14
-; RV32I-NEXT: lui t0, 8
-; RV32I-NEXT: and a6, a2, t0
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: lui t1, 8
+; RV32I-NEXT: and a6, a2, t1
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 116(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 116(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 15
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: lui t6, 16
; RV32I-NEXT: and a7, a2, t6
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 112(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 16
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, a2, s2
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a7, a2, s3
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 108(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 17
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: lui t1, 64
-; RV32I-NEXT: and a7, a2, t1
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: lui t3, 64
+; RV32I-NEXT: and a7, a2, t3
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 104(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 18
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: lui t2, 128
; RV32I-NEXT: and a7, a2, t2
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 100(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 19
-; RV32I-NEXT: lui t3, 256
-; RV32I-NEXT: and a6, a2, t3
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: lui t4, 256
+; RV32I-NEXT: and a6, a2, t4
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 96(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 20
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: lui t4, 512
-; RV32I-NEXT: and a7, a2, t4
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: lui t5, 512
+; RV32I-NEXT: and a7, a2, t5
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 21
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: lui t5, 1024
-; RV32I-NEXT: and a7, a2, t5
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: lui a0, 1024
+; RV32I-NEXT: and a7, a2, a0
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 88(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 22
-; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: lui s0, 2048
; RV32I-NEXT: and a7, a2, s0
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 23
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, a2, a0
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a7, a2, s10
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 80(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a6, -1
+; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a1, 24
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, a2, s9
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a7, a2, s11
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: xor a4, a4, a5
@@ -4625,35 +4626,36 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: addi a6, a6, -1
; RV32I-NEXT: sw a6, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a4, a1, 25
-; RV32I-NEXT: and a5, a2, s10
+; RV32I-NEXT: and a5, a2, ra
; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a0, a5, -1
+; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 26
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: and a6, a2, s11
+; RV32I-NEXT: and a5, a0, a5
+; RV32I-NEXT: lui a0, 32768
+; RV32I-NEXT: and a6, a2, a0
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a6, a5, -1
; RV32I-NEXT: sw a6, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 27
; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: and a6, a2, s4
+; RV32I-NEXT: and a6, a2, s9
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a6, a5, -1
; RV32I-NEXT: sw a6, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 28
; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: and a6, a2, s1
+; RV32I-NEXT: and a6, a2, s5
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a6, a5, -1
; RV32I-NEXT: sw a6, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a1, 29
; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: and a6, a2, ra
+; RV32I-NEXT: and a6, a2, s1
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a6, a5, -1
@@ -4667,9 +4669,9 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: sw a2, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a2, a1
-; RV32I-NEXT: andi a2, s3, 2
+; RV32I-NEXT: andi a2, s4, 2
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: andi a5, s3, 1
+; RV32I-NEXT: andi a5, s4, 1
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
@@ -4680,8 +4682,8 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: xor a1, a4, a1
; RV32I-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a5, a2
-; RV32I-NEXT: andi a1, s3, 4
-; RV32I-NEXT: andi a4, s3, 8
+; RV32I-NEXT: andi a1, s4, 4
+; RV32I-NEXT: andi a4, s4, 8
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a1, a1, -1
@@ -4693,11 +4695,11 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: andi a4, s3, 16
+; RV32I-NEXT: andi a4, s4, 16
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a4
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: andi a4, s3, 32
+; RV32I-NEXT: andi a4, s4, 32
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: slli a5, a3, 4
; RV32I-NEXT: sw a5, 28(sp) # 4-byte Folded Spill
@@ -4705,7 +4707,7 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli a6, a3, 5
; RV32I-NEXT: sw a6, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a5, s3, 64
+; RV32I-NEXT: andi a5, s4, 64
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
@@ -4714,11 +4716,11 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: and a4, a5, a6
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: andi a4, s3, 128
+; RV32I-NEXT: andi a4, s4, 128
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a4
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: andi a4, s3, 256
+; RV32I-NEXT: andi a4, s4, 256
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: slli a5, a3, 7
; RV32I-NEXT: sw a5, 16(sp) # 4-byte Folded Spill
@@ -4726,14 +4728,14 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli a6, a3, 8
; RV32I-NEXT: sw a6, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a5, s3, 512
+; RV32I-NEXT: andi a5, s4, 512
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: slli a6, a3, 9
; RV32I-NEXT: sw a6, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, s3, 1024
+; RV32I-NEXT: andi a4, s4, 1024
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
@@ -4742,16 +4744,16 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: and a4, s3, s5
+; RV32I-NEXT: and a4, s4, s6
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a4
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a4, s3, s6
+; RV32I-NEXT: and a4, s4, s7
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: slli s11, a3, 11
; RV32I-NEXT: and a2, a2, s11
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a5, s3, s7
+; RV32I-NEXT: and a5, s4, s8
; RV32I-NEXT: slli s10, a3, 12
; RV32I-NEXT: and a4, a4, s10
; RV32I-NEXT: seqz a5, a5
@@ -4760,64 +4762,66 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: and a4, a5, s9
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: and a4, s3, s8
+; RV32I-NEXT: and a4, s4, t0
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a4
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a4, s3, t0
+; RV32I-NEXT: and a4, s4, t1
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: slli s8, a3, 14
; RV32I-NEXT: and a2, a2, s8
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a5, s3, t6
+; RV32I-NEXT: and a5, s4, t6
; RV32I-NEXT: slli s7, a3, 15
; RV32I-NEXT: and a4, a4, s7
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a4, s3, s2
+; RV32I-NEXT: and a4, s4, s3
; RV32I-NEXT: slli s6, a3, 16
; RV32I-NEXT: and a5, a5, s6
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a5, s3, t1
-; RV32I-NEXT: slli s5, a3, 17
-; RV32I-NEXT: and a4, a4, s5
+; RV32I-NEXT: and a5, s4, t3
+; RV32I-NEXT: slli s3, a3, 17
+; RV32I-NEXT: and a4, a4, s3
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: slli s1, a3, 18
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: and a4, a5, s1
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: and a4, s3, t2
+; RV32I-NEXT: and a4, s4, t2
; RV32I-NEXT: xor s2, a1, a2
; RV32I-NEXT: seqz a1, a4
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a2, s3, t3
+; RV32I-NEXT: and a2, s4, t4
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: slli s4, a3, 19
-; RV32I-NEXT: and a1, a1, s4
+; RV32I-NEXT: slli s5, a3, 19
+; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a4, s3, t4
+; RV32I-NEXT: and a4, s4, t5
; RV32I-NEXT: slli t6, a3, 20
; RV32I-NEXT: and a2, a2, t6
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a2, s3, t5
+; RV32I-NEXT: lui a2, 1024
+; RV32I-NEXT: and a2, s4, a2
; RV32I-NEXT: slli t5, a3, 21
; RV32I-NEXT: and a4, a4, t5
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: xor a1, a1, a4
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a4, s3, s0
+; RV32I-NEXT: and a4, s4, s0
; RV32I-NEXT: slli t4, a3, 22
; RV32I-NEXT: and a2, a2, t4
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a2, s3, a0
+; RV32I-NEXT: lui a2, 4096
+; RV32I-NEXT: and a2, s4, a2
; RV32I-NEXT: slli t3, a3, 23
; RV32I-NEXT: and a4, a4, t3
; RV32I-NEXT: seqz a2, a2
@@ -4825,53 +4829,52 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: lw s0, 180(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a2, s0
-; RV32I-NEXT: lui a0, 8192
-; RV32I-NEXT: and a2, s3, a0
+; RV32I-NEXT: lui a2, 8192
+; RV32I-NEXT: and a2, s4, a2
; RV32I-NEXT: xor a7, a1, a5
; RV32I-NEXT: seqz a1, a2
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: lui a0, 16384
-; RV32I-NEXT: and a2, s3, a0
+; RV32I-NEXT: lui a2, 16384
+; RV32I-NEXT: and a2, s4, a2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: slli t2, a3, 25
; RV32I-NEXT: and a1, a1, t2
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: lui a0, 32768
-; RV32I-NEXT: and a4, s3, a0
+; RV32I-NEXT: and a4, s4, a0
; RV32I-NEXT: slli t1, a3, 26
; RV32I-NEXT: and a2, a2, t1
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: lui a0, 65536
-; RV32I-NEXT: and a2, s3, a0
+; RV32I-NEXT: and a2, s4, a0
; RV32I-NEXT: slli t0, a3, 27
; RV32I-NEXT: and a4, a4, t0
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: xor a1, a1, a4
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: lui a0, 131072
-; RV32I-NEXT: and a0, s3, a0
+; RV32I-NEXT: and a0, s4, a0
; RV32I-NEXT: slli a6, a3, 28
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: xor a2, a1, a2
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: lui a0, 262144
-; RV32I-NEXT: and a0, s3, a0
+; RV32I-NEXT: and a0, s4, a0
; RV32I-NEXT: slli a5, a3, 29
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: xor a2, a2, a1
; RV32I-NEXT: addi a1, a0, -1
-; RV32I-NEXT: srli s3, s3, 31
+; RV32I-NEXT: srli s4, s4, 31
; RV32I-NEXT: slli a4, a3, 30
; RV32I-NEXT: and a0, a1, a4
-; RV32I-NEXT: seqz a1, s3
-; RV32I-NEXT: addi s3, a1, -1
+; RV32I-NEXT: seqz a1, s4
+; RV32I-NEXT: addi s4, a1, -1
; RV32I-NEXT: slli a1, a3, 31
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: and a2, s3, a1
+; RV32I-NEXT: and a2, s4, a1
; RV32I-NEXT: xor a7, s2, a7
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: lw a2, 48(sp) # 4-byte Folded Reload
@@ -4884,67 +4887,67 @@ define i64 @clmul_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: lw a7, 172(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a7, a3
; RV32I-NEXT: lw a7, 168(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, a7, s3
-; RV32I-NEXT: lw s3, 164(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, a7, s4
+; RV32I-NEXT: lw s4, 164(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, ra
+; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a0, a3, a0
-; RV32I-NEXT: xor a3, a7, s3
+; RV32I-NEXT: xor a3, a7, s4
; RV32I-NEXT: lw a7, 160(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, a7, s3
-; RV32I-NEXT: lw s3, 156(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, a7, s4
+; RV32I-NEXT: lw s4, 156(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, ra
-; RV32I-NEXT: xor a7, a7, s3
-; RV32I-NEXT: lw s3, 152(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, ra
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 152(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, ra
+; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a0, a0, a3
-; RV32I-NEXT: xor a3, a7, s3
+; RV32I-NEXT: xor a3, a7, s4
; RV32I-NEXT: lw a7, 148(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, a7, s3
-; RV32I-NEXT: lw s3, 144(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, a7, s4
+; RV32I-NEXT: lw s4, 144(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, ra
-; RV32I-NEXT: xor a7, a7, s3
-; RV32I-NEXT: lw s3, 140(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, ra
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 140(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, ra
-; RV32I-NEXT: xor a7, a7, s3
-; RV32I-NEXT: lw s3, 136(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, ra
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, ra
+; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a0, a0, a3
-; RV32I-NEXT: xor a3, a7, s3
+; RV32I-NEXT: xor a3, a7, s4
; RV32I-NEXT: lw a7, 132(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a7, a7, s11
-; RV32I-NEXT: lw s3, 128(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, s10
-; RV32I-NEXT: xor a7, a7, s3
-; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, s9
+; RV32I-NEXT: lw s4, 128(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s10
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s9
; RV32I-NEXT: xor a0, a0, a3
-; RV32I-NEXT: xor a3, a7, s3
+; RV32I-NEXT: xor a3, a7, s4
; RV32I-NEXT: lw a7, 120(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a7, a7, s8
-; RV32I-NEXT: lw s3, 116(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, s7
-; RV32I-NEXT: xor a7, a7, s3
-; RV32I-NEXT: lw s3, 112(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, s6
-; RV32I-NEXT: xor a7, a7, s3
-; RV32I-NEXT: lw s3, 108(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: lw s4, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s7
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s3, s4, s3
; RV32I-NEXT: xor a7, a7, s3
; RV32I-NEXT: lw s3, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s1, s3, s1
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: xor a3, a7, s1
; RV32I-NEXT: lw a7, 100(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, a7, s4
+; RV32I-NEXT: and a7, a7, s5
; RV32I-NEXT: lw s1, 96(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t6, s1, t6
; RV32I-NEXT: xor a7, a7, t6
@@ -6558,286 +6561,287 @@ define i64 @clmul_i64_zext(i32 %x, i32 %y) {
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: .cfi_offset s10, -48
; RV32I-NEXT: .cfi_offset s11, -52
-; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: mv t2, a0
+; RV32I-NEXT: mv a4, a1
+; RV32I-NEXT: mv t0, a0
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: srli a0, a0, 8
-; RV32I-NEXT: addi t1, a1, -256
-; RV32I-NEXT: lui s3, 16
-; RV32I-NEXT: and a0, a0, t1
-; RV32I-NEXT: srli a2, t2, 24
-; RV32I-NEXT: and a4, t2, t1
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: slli a1, t2, 24
-; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a0, a0, a2
-; RV32I-NEXT: or a2, a1, a4
-; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: lui a2, 61681
-; RV32I-NEXT: srli a4, a0, 4
-; RV32I-NEXT: addi a6, a2, -241
-; RV32I-NEXT: and a2, a4, a6
+; RV32I-NEXT: addi t4, a1, -256
+; RV32I-NEXT: lui t1, 16
+; RV32I-NEXT: and a0, a0, t4
+; RV32I-NEXT: srli a1, t0, 24
+; RV32I-NEXT: and a3, t0, t4
+; RV32I-NEXT: slli a3, a3, 8
+; RV32I-NEXT: slli a2, t0, 24
+; RV32I-NEXT: sw a2, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: or a1, a2, a3
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: lui a1, 61681
+; RV32I-NEXT: srli a3, a0, 4
+; RV32I-NEXT: addi a6, a1, -241
+; RV32I-NEXT: and a1, a3, a6
; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: lui a4, 209715
-; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: addi a7, a4, 819
-; RV32I-NEXT: srli a2, a0, 2
+; RV32I-NEXT: lui a3, 209715
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: addi a7, a3, 819
+; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a7
-; RV32I-NEXT: and a2, a2, a7
+; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a2, a0, 1
-; RV32I-NEXT: lui t0, 349525
-; RV32I-NEXT: addi t0, t0, 1365
-; RV32I-NEXT: srli a5, a3, 8
-; RV32I-NEXT: and a2, a2, t0
-; RV32I-NEXT: mv a1, t1
-; RV32I-NEXT: sw t1, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, t1
-; RV32I-NEXT: srli t1, a3, 24
-; RV32I-NEXT: and t3, a3, a1
+; RV32I-NEXT: sw a2, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t2, 349525
+; RV32I-NEXT: addi t2, t2, 1365
+; RV32I-NEXT: srli a1, a4, 8
+; RV32I-NEXT: and a3, a2, t2
+; RV32I-NEXT: and a1, a1, t4
+; RV32I-NEXT: srli a5, a4, 24
+; RV32I-NEXT: and t3, a4, t4
; RV32I-NEXT: slli t3, t3, 8
-; RV32I-NEXT: slli t4, a3, 24
-; RV32I-NEXT: or a5, a5, t1
-; RV32I-NEXT: or t1, t4, t3
-; RV32I-NEXT: and a0, a0, t0
-; RV32I-NEXT: or a5, t1, a5
-; RV32I-NEXT: srli t1, a5, 4
+; RV32I-NEXT: slli t5, a4, 24
+; RV32I-NEXT: or a1, a1, a5
+; RV32I-NEXT: or a5, t5, t3
+; RV32I-NEXT: and a0, a0, t2
+; RV32I-NEXT: or a1, a5, a1
+; RV32I-NEXT: srli a5, a1, 4
+; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: and t1, t1, a6
-; RV32I-NEXT: slli a5, a5, 4
+; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: or a5, t1, a5
-; RV32I-NEXT: srli t1, a5, 2
+; RV32I-NEXT: or a1, a5, a1
+; RV32I-NEXT: srli a5, a1, 2
+; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: and t1, t1, a7
-; RV32I-NEXT: slli a5, a5, 2
-; RV32I-NEXT: or s10, a2, a0
-; RV32I-NEXT: or a0, t1, a5
-; RV32I-NEXT: srli a2, a0, 1
-; RV32I-NEXT: and a0, a0, t0
-; RV32I-NEXT: and a2, a2, t0
-; RV32I-NEXT: slli a5, a0, 1
-; RV32I-NEXT: slli t1, s10, 1
-; RV32I-NEXT: or a0, a2, a5
-; RV32I-NEXT: andi a2, a0, 2
-; RV32I-NEXT: andi t3, a0, 1
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and a2, a2, t1
-; RV32I-NEXT: and t1, t3, s10
-; RV32I-NEXT: slli t3, s10, 2
-; RV32I-NEXT: andi t4, a0, 4
-; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: andi t5, a0, 8
-; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: slli t3, a1, 2
+; RV32I-NEXT: or a1, a3, a0
+; RV32I-NEXT: or a0, a5, t3
+; RV32I-NEXT: srli a3, a0, 1
+; RV32I-NEXT: and a0, a0, t2
+; RV32I-NEXT: and a3, a3, t2
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, a1, 1
+; RV32I-NEXT: or a0, a3, a0
+; RV32I-NEXT: andi a3, a0, 2
+; RV32I-NEXT: andi t5, a0, 1
+; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz t5, t5
-; RV32I-NEXT: slli t6, s10, 3
+; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: and t4, t5, t6
-; RV32I-NEXT: xor a2, t1, a2
-; RV32I-NEXT: xor t1, t3, t4
-; RV32I-NEXT: xor a2, a2, t1
-; RV32I-NEXT: andi t1, a0, 16
-; RV32I-NEXT: slli t3, s10, 4
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: andi t4, a0, 32
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, s10, 5
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: andi t4, a0, 64
-; RV32I-NEXT: xor t1, t1, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, s10, 6
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: andi t4, a0, 128
-; RV32I-NEXT: xor t1, t1, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, s10, 7
+; RV32I-NEXT: and a3, a3, t3
+; RV32I-NEXT: and t3, t5, a1
+; RV32I-NEXT: slli t5, a1, 2
+; RV32I-NEXT: andi t6, a0, 4
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: andi s0, a0, 8
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: slli s1, a1, 3
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and t5, t6, t5
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: xor a3, t3, a3
+; RV32I-NEXT: xor t3, t5, s0
+; RV32I-NEXT: xor a3, a3, t3
+; RV32I-NEXT: andi t3, a0, 16
+; RV32I-NEXT: slli t5, a1, 4
+; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: andi t4, a0, 256
-; RV32I-NEXT: slli t5, s10, 8
-; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: andi t6, a0, 512
-; RV32I-NEXT: and t4, t4, t5
+; RV32I-NEXT: andi t6, a0, 32
+; RV32I-NEXT: and t3, t3, t5
; RV32I-NEXT: seqz t5, t6
-; RV32I-NEXT: slli t6, s10, 9
+; RV32I-NEXT: slli t6, a1, 5
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: and t4, t5, t6
-; RV32I-NEXT: xor a2, a2, t1
-; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: slli t4, s10, 10
-; RV32I-NEXT: andi t1, a0, 1024
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: li t5, 1
-; RV32I-NEXT: addi t6, t1, -1
-; RV32I-NEXT: slli t1, t5, 11
-; RV32I-NEXT: and t4, t6, t4
-; RV32I-NEXT: and t5, a0, t1
-; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: seqz t4, t5
-; RV32I-NEXT: slli t5, s10, 11
-; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: and t4, t4, t5
-; RV32I-NEXT: lui a1, 1
-; RV32I-NEXT: slli t5, s10, 12
-; RV32I-NEXT: and t6, a0, a1
+; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: andi t6, a0, 64
+; RV32I-NEXT: xor t3, t3, t5
+; RV32I-NEXT: seqz t5, t6
+; RV32I-NEXT: slli t6, a1, 6
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: andi t6, a0, 128
+; RV32I-NEXT: xor t3, t3, t5
+; RV32I-NEXT: seqz t5, t6
+; RV32I-NEXT: slli t6, a1, 7
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: andi t6, a0, 256
+; RV32I-NEXT: slli s0, a1, 8
; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: lui s0, 2
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and s0, a0, s0
-; RV32I-NEXT: and t5, t6, t5
+; RV32I-NEXT: andi s1, a0, 512
+; RV32I-NEXT: and t6, t6, s0
+; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: slli s1, a1, 9
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: xor t5, t5, t6
+; RV32I-NEXT: and s0, s0, s1
+; RV32I-NEXT: xor a3, a3, t3
+; RV32I-NEXT: xor t5, t5, s0
+; RV32I-NEXT: slli t6, a1, 10
+; RV32I-NEXT: andi t3, a0, 1024
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: li s0, 1
+; RV32I-NEXT: addi s1, t3, -1
+; RV32I-NEXT: slli t3, s0, 11
+; RV32I-NEXT: and t6, s1, t6
+; RV32I-NEXT: and s0, a0, t3
+; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: slli s0, s10, 13
+; RV32I-NEXT: slli s0, a1, 11
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: xor t4, t4, t5
-; RV32I-NEXT: and t5, t6, s0
-; RV32I-NEXT: xor t6, t4, t5
-; RV32I-NEXT: lui a1, 4
-; RV32I-NEXT: slli s0, s10, 14
-; RV32I-NEXT: and t5, a0, a1
-; RV32I-NEXT: seqz s1, t5
-; RV32I-NEXT: lui t5, 8
+; RV32I-NEXT: and t6, t6, s0
+; RV32I-NEXT: lui s1, 1
+; RV32I-NEXT: slli s0, a1, 12
+; RV32I-NEXT: and s1, a0, s1
+; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: lui a2, 2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: and s2, a0, t5
+; RV32I-NEXT: and s2, a0, a2
; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: slli s2, s10, 15
+; RV32I-NEXT: slli s2, a1, 13
; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: and s0, s1, s2
-; RV32I-NEXT: xor a2, a2, t3
-; RV32I-NEXT: xor t3, t6, s0
-; RV32I-NEXT: xor a2, a2, t3
-; RV32I-NEXT: slli t3, s10, 16
-; RV32I-NEXT: and s0, a0, s3
-; RV32I-NEXT: lui t6, 32
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: and s1, a0, t6
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: xor s0, t6, s0
+; RV32I-NEXT: lui a2, 4
+; RV32I-NEXT: slli s1, a1, 14
+; RV32I-NEXT: and t6, a0, a2
+; RV32I-NEXT: seqz s2, t6
+; RV32I-NEXT: lui t6, 8
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: and s3, a0, t6
+; RV32I-NEXT: and s1, s2, s1
+; RV32I-NEXT: seqz s2, s3
+; RV32I-NEXT: slli s3, a1, 15
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: and s1, s2, s3
+; RV32I-NEXT: xor a3, a3, t5
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: xor a3, a3, s0
+; RV32I-NEXT: slli t5, a1, 16
+; RV32I-NEXT: and s1, a0, t1
+; RV32I-NEXT: lui s0, 32
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: slli s2, s10, 17
+; RV32I-NEXT: and s2, a0, s0
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: and t3, s0, t3
-; RV32I-NEXT: and s0, s1, s2
-; RV32I-NEXT: xor t3, t3, s0
-; RV32I-NEXT: lui s1, 64
-; RV32I-NEXT: slli s2, s10, 18
-; RV32I-NEXT: and s0, a0, s1
-; RV32I-NEXT: seqz s3, s0
-; RV32I-NEXT: lui s0, 128
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s4, a0, s0
-; RV32I-NEXT: and s2, s3, s2
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, s10, 19
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: xor t3, t3, s2
-; RV32I-NEXT: and s2, s3, s4
-; RV32I-NEXT: xor t3, t3, s2
-; RV32I-NEXT: lui s2, 256
-; RV32I-NEXT: slli s4, s10, 20
-; RV32I-NEXT: and s3, a0, s2
-; RV32I-NEXT: seqz s5, s3
-; RV32I-NEXT: lui s3, 512
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: and s6, a0, s3
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: slli s6, s10, 21
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: xor t3, t3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor t3, t3, s4
-; RV32I-NEXT: lui s4, 1024
-; RV32I-NEXT: xor a4, a2, t3
-; RV32I-NEXT: and t3, a0, s4
-; RV32I-NEXT: slli s6, s10, 22
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: seqz s2, s2
+; RV32I-NEXT: slli s3, a1, 17
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: and t5, s1, t5
+; RV32I-NEXT: and s1, s2, s3
+; RV32I-NEXT: xor t5, t5, s1
+; RV32I-NEXT: lui s2, 64
+; RV32I-NEXT: slli s3, a1, 18
+; RV32I-NEXT: and s1, a0, s2
+; RV32I-NEXT: seqz s4, s1
+; RV32I-NEXT: lui s1, 128
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and s5, a0, s1
+; RV32I-NEXT: and s3, s4, s3
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, a1, 19
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: xor t5, t5, s3
+; RV32I-NEXT: and s3, s4, s5
+; RV32I-NEXT: xor t5, t5, s3
+; RV32I-NEXT: lui s3, 256
+; RV32I-NEXT: slli s5, a1, 20
+; RV32I-NEXT: and s4, a0, s3
+; RV32I-NEXT: seqz s6, s4
+; RV32I-NEXT: lui s4, 512
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: and s7, a0, s4
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: slli s7, a1, 21
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: xor t5, t5, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor t5, t5, s5
+; RV32I-NEXT: lui s6, 1024
+; RV32I-NEXT: xor t1, a3, t5
+; RV32I-NEXT: and t5, a0, s6
+; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: lui s5, 2048
-; RV32I-NEXT: and t3, t3, s6
-; RV32I-NEXT: and s6, a0, s5
-; RV32I-NEXT: slli s7, s10, 23
-; RV32I-NEXT: seqz s6, s6
-; RV32I-NEXT: addi s8, s6, -1
-; RV32I-NEXT: lui s6, 4096
-; RV32I-NEXT: and s7, s8, s7
-; RV32I-NEXT: and s8, a0, s6
-; RV32I-NEXT: xor t3, t3, s7
-; RV32I-NEXT: seqz s7, s8
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: and s7, a0, s5
+; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: slli s8, a1, 22
+; RV32I-NEXT: and t5, t5, s8
; RV32I-NEXT: addi s8, s7, -1
-; RV32I-NEXT: lui s7, 8192
-; RV32I-NEXT: slli s9, s10, 24
-; RV32I-NEXT: and a1, a0, s7
+; RV32I-NEXT: slli s9, a1, 23
+; RV32I-NEXT: lui s7, 4096
; RV32I-NEXT: and s8, s8, s9
-; RV32I-NEXT: seqz s9, a1
-; RV32I-NEXT: xor t3, t3, s8
-; RV32I-NEXT: addi s9, s9, -1
-; RV32I-NEXT: slli a1, s10, 25
-; RV32I-NEXT: lui s8, 16384
-; RV32I-NEXT: and s9, s9, a1
-; RV32I-NEXT: and a1, a0, s8
-; RV32I-NEXT: xor t3, t3, s9
-; RV32I-NEXT: seqz s9, a1
-; RV32I-NEXT: addi a2, s9, -1
-; RV32I-NEXT: lui s9, 32768
-; RV32I-NEXT: slli ra, s10, 26
-; RV32I-NEXT: and a1, a0, s9
+; RV32I-NEXT: and s9, a0, s7
+; RV32I-NEXT: xor t5, t5, s8
+; RV32I-NEXT: seqz s8, s9
+; RV32I-NEXT: addi s9, s8, -1
+; RV32I-NEXT: lui s8, 8192
+; RV32I-NEXT: slli s10, a1, 24
+; RV32I-NEXT: and s11, a0, s8
+; RV32I-NEXT: and s9, s9, s10
+; RV32I-NEXT: seqz s10, s11
+; RV32I-NEXT: xor t5, t5, s9
+; RV32I-NEXT: addi s10, s10, -1
+; RV32I-NEXT: slli s11, a1, 25
+; RV32I-NEXT: lui s9, 16384
+; RV32I-NEXT: and s10, s10, s11
+; RV32I-NEXT: and s11, a0, s9
+; RV32I-NEXT: xor t5, t5, s10
+; RV32I-NEXT: seqz s10, s11
+; RV32I-NEXT: addi s11, s10, -1
+; RV32I-NEXT: lui s10, 32768
+; RV32I-NEXT: slli ra, a1, 26
+; RV32I-NEXT: and a2, a0, s10
+; RV32I-NEXT: and s11, s11, ra
+; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: xor t5, t5, s11
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: slli ra, a1, 27
+; RV32I-NEXT: lui s11, 65536
; RV32I-NEXT: and a2, a2, ra
-; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: xor t3, t3, a2
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli ra, s10, 27
-; RV32I-NEXT: lui t4, 65536
-; RV32I-NEXT: and a1, a1, ra
-; RV32I-NEXT: and ra, a0, t4
-; RV32I-NEXT: xor a1, t3, a1
-; RV32I-NEXT: seqz t3, ra
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: slli ra, s10, 28
-; RV32I-NEXT: and ra, t3, ra
-; RV32I-NEXT: lui t3, 131072
-; RV32I-NEXT: xor a2, a1, ra
-; RV32I-NEXT: and ra, a0, t3
-; RV32I-NEXT: seqz a1, ra
-; RV32I-NEXT: lui ra, 262144
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a0, a0, ra
+; RV32I-NEXT: and ra, a0, s11
+; RV32I-NEXT: xor a5, t5, a2
+; RV32I-NEXT: seqz t5, ra
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: lui ra, 131072
+; RV32I-NEXT: slli a2, a1, 28
+; RV32I-NEXT: and a3, a0, ra
+; RV32I-NEXT: and a2, t5, a2
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: xor a2, a5, a2
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: slli a5, a1, 29
+; RV32I-NEXT: lui t5, 262144
+; RV32I-NEXT: and a3, a3, a5
+; RV32I-NEXT: and a0, a0, t5
+; RV32I-NEXT: slli a1, a1, 30
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: slli s11, s10, 29
-; RV32I-NEXT: and a1, a1, s11
; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: lw a5, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a5, a5, 31
-; RV32I-NEXT: slli s11, s10, 30
-; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli s10, s10, 31
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: and a1, a5, s10
-; RV32I-NEXT: xor a2, a4, a2
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: seqz a1, a5
+; RV32I-NEXT: lw a5, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli a5, a5, 31
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: xor a0, a3, a0
+; RV32I-NEXT: and a1, a1, a5
+; RV32I-NEXT: xor a2, t1, a2
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a0, a2, a0
; RV32I-NEXT: srli a1, a0, 8
-; RV32I-NEXT: lw a2, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: srli a4, a0, 24
+; RV32I-NEXT: and a1, a1, t4
+; RV32I-NEXT: and a2, a0, t4
+; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: slli a2, a2, 8
-; RV32I-NEXT: or a1, a1, a4
+; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
@@ -6854,204 +6858,204 @@ define i64 @clmul_i64_zext(i32 %x, i32 %y) {
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1364
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: andi a2, a3, 2
+; RV32I-NEXT: andi a2, a4, 2
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: andi a4, a3, 1
+; RV32I-NEXT: andi a3, a4, 1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: slli a5, t2, 1
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: slli a5, t0, 1
; RV32I-NEXT: and a2, a2, a5
-; RV32I-NEXT: and a4, a4, t2
-; RV32I-NEXT: and a1, a1, t0
-; RV32I-NEXT: xor a2, a4, a2
-; RV32I-NEXT: andi a4, a3, 4
-; RV32I-NEXT: andi a5, a3, 8
-; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: and a3, a3, t0
+; RV32I-NEXT: and a1, a1, t2
+; RV32I-NEXT: xor a2, a3, a2
+; RV32I-NEXT: andi a3, a4, 4
+; RV32I-NEXT: andi a5, a4, 8
+; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t2, 2
-; RV32I-NEXT: slli a7, t2, 3
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: slli a6, t0, 2
+; RV32I-NEXT: slli a7, t0, 3
+; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: andi a5, a3, 16
-; RV32I-NEXT: xor a4, a2, a4
-; RV32I-NEXT: seqz a2, a5
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: andi a5, a3, 32
+; RV32I-NEXT: xor a3, a3, a5
+; RV32I-NEXT: andi a5, a4, 16
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: seqz a3, a5
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: andi a5, a4, 32
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli a6, t2, 4
-; RV32I-NEXT: and a2, a2, a6
+; RV32I-NEXT: slli a6, t0, 4
+; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t2, 5
-; RV32I-NEXT: andi a7, a3, 64
+; RV32I-NEXT: slli a6, t0, 5
+; RV32I-NEXT: andi a7, a4, 64
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 6
-; RV32I-NEXT: xor a2, a2, a5
+; RV32I-NEXT: slli a7, t0, 6
+; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: and a5, a6, a7
; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: xor a5, a2, a5
-; RV32I-NEXT: or a2, a0, a1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: slli a0, t2, 7
-; RV32I-NEXT: andi a1, a3, 128
-; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: andi a5, a3, 256
-; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: xor a3, a3, a5
+; RV32I-NEXT: or a1, a0, a1
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slli a0, t0, 7
+; RV32I-NEXT: andi a3, a4, 128
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: andi a5, a4, 256
+; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t2, 8
-; RV32I-NEXT: and a0, a1, a0
-; RV32I-NEXT: and a1, a5, a6
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: andi a1, a3, 512
-; RV32I-NEXT: slli a5, t2, 9
-; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: andi a6, a3, 1024
-; RV32I-NEXT: and a1, a1, a5
+; RV32I-NEXT: slli a6, t0, 8
+; RV32I-NEXT: and a0, a3, a0
+; RV32I-NEXT: and a3, a5, a6
+; RV32I-NEXT: xor a0, a0, a3
+; RV32I-NEXT: andi a3, a4, 512
+; RV32I-NEXT: slli a5, t0, 9
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: andi a6, a4, 1024
+; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t2, 10
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: and a1, a5, a6
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: and a1, a3, t1
-; RV32I-NEXT: xor a0, a4, a0
-; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: lui a4, 1
-; RV32I-NEXT: and a4, a3, a4
-; RV32I-NEXT: slli a5, t2, 11
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a1, a1, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: slli a5, t2, 12
+; RV32I-NEXT: slli a6, t0, 10
+; RV32I-NEXT: xor a0, a0, a3
+; RV32I-NEXT: and a3, a5, a6
+; RV32I-NEXT: xor a0, a0, a3
+; RV32I-NEXT: and a3, a4, t3
+; RV32I-NEXT: xor a0, a2, a0
+; RV32I-NEXT: seqz a2, a3
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: lui a3, 1
+; RV32I-NEXT: and a3, a4, a3
+; RV32I-NEXT: slli a5, t0, 11
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: and a2, a2, a5
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: slli a5, t0, 12
; RV32I-NEXT: lui a6, 2
-; RV32I-NEXT: and a6, a3, a6
-; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: and a6, a4, a6
+; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t2, 13
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: and a4, a5, a6
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: lui a4, 4
-; RV32I-NEXT: and a4, a3, a4
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a1, a4
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a4, a3, t5
-; RV32I-NEXT: slli a5, t2, 14
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a1, a1, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: slli a5, t2, 15
+; RV32I-NEXT: slli a6, t0, 13
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: and a3, a5, a6
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: lui a3, 4
+; RV32I-NEXT: and a3, a4, a3
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: seqz a2, a3
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a3, a4, t6
+; RV32I-NEXT: slli a5, t0, 14
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: and a2, a2, a5
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: slli a5, t0, 15
; RV32I-NEXT: lui a6, 16
-; RV32I-NEXT: and a6, a3, a6
-; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: and a6, a4, a6
+; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a4, t2, 16
-; RV32I-NEXT: and a6, a3, t6
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: slli a3, t0, 16
+; RV32I-NEXT: and s0, a4, s0
+; RV32I-NEXT: and a3, a5, a3
+; RV32I-NEXT: seqz a5, s0
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a4, t2, 17
-; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: seqz a5, s1
+; RV32I-NEXT: slli a3, t0, 17
+; RV32I-NEXT: and a6, a4, s2
+; RV32I-NEXT: and a3, a5, a3
+; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t2, 18
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: and a4, a5, a6
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: and s0, a3, s0
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a1, s0
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a4, a3, s2
-; RV32I-NEXT: slli a5, t2, 19
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a1, a1, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: slli a5, t2, 20
-; RV32I-NEXT: and a6, a3, s3
-; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: slli a6, t0, 18
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: and a3, a5, a6
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: and s1, a4, s1
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: seqz a2, s1
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a3, a4, s3
+; RV32I-NEXT: slli a5, t0, 19
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: and a2, a2, a5
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: slli a5, t0, 20
+; RV32I-NEXT: and a6, a4, s4
+; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a4, t2, 21
-; RV32I-NEXT: and a6, a3, s4
-; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: slli a3, t0, 21
+; RV32I-NEXT: and a6, a4, s6
+; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a4, t2, 22
-; RV32I-NEXT: and a6, a3, s5
-; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: slli a3, t0, 22
+; RV32I-NEXT: and a6, a4, s5
+; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a4, t2, 23
-; RV32I-NEXT: and a6, a3, s6
-; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: slli a3, t0, 23
+; RV32I-NEXT: and a6, a4, s7
+; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: lw a4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, a3, s7
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a5, a3, s8
-; RV32I-NEXT: slli a6, t2, 25
+; RV32I-NEXT: lw a3, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a5, a3
+; RV32I-NEXT: and a5, a4, s8
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: seqz a3, a5
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: and a5, a4, s9
+; RV32I-NEXT: slli a6, t0, 25
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, t2, 26
-; RV32I-NEXT: and a7, a3, s9
+; RV32I-NEXT: slli a6, t0, 26
+; RV32I-NEXT: and a7, a4, s10
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 27
-; RV32I-NEXT: and a7, a3, t4
+; RV32I-NEXT: slli a5, t0, 27
+; RV32I-NEXT: and a7, a4, s11
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 28
-; RV32I-NEXT: and a7, a3, t3
+; RV32I-NEXT: slli a5, t0, 28
+; RV32I-NEXT: and a7, a4, ra
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 29
-; RV32I-NEXT: and a7, a3, ra
+; RV32I-NEXT: slli a5, t0, 29
+; RV32I-NEXT: and a7, a4, t5
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 30
-; RV32I-NEXT: srli a3, a3, 31
+; RV32I-NEXT: slli a5, t0, 30
+; RV32I-NEXT: srli a4, a4, 31
; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli t2, t2, 31
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a3, a3, t2
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a3, a4, a3
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: slli t0, t0, 31
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: xor a3, a3, a5
+; RV32I-NEXT: and a4, a4, t0
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a0, a0, a3
-; RV32I-NEXT: srli a1, a2, 1
+; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
@@ -15837,353 +15841,352 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: .cfi_offset s10, -48
; RV32I-NEXT: .cfi_offset s11, -52
-; RV32I-NEXT: mv t5, a2
-; RV32I-NEXT: sw a0, 284(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 280(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a5, 4(a1)
-; RV32I-NEXT: sw a5, 544(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 552(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: lw s4, 8(a1)
; RV32I-NEXT: lw a3, 12(a1)
-; RV32I-NEXT: sw a3, 276(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a2, a0, -256
+; RV32I-NEXT: sw a3, 272(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s0, a0, -256
; RV32I-NEXT: lui t4, 16
; RV32I-NEXT: srli a0, a5, 8
; RV32I-NEXT: srli a3, a5, 24
-; RV32I-NEXT: and a4, a5, a2
+; RV32I-NEXT: and a4, a5, s0
; RV32I-NEXT: slli a5, a5, 24
; RV32I-NEXT: sw a5, 644(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a3, a5, a4
; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: or a0, a3, a0
-; RV32I-NEXT: addi s11, a4, -241
+; RV32I-NEXT: addi t5, a4, -241
; RV32I-NEXT: srli a3, a0, 4
-; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: and a3, a3, s11
+; RV32I-NEXT: and a0, a0, t5
+; RV32I-NEXT: and a3, a3, t5
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: srli a4, a0, 2
-; RV32I-NEXT: addi t6, a3, 819
-; RV32I-NEXT: and a3, a4, t6
-; RV32I-NEXT: and a0, a0, t6
+; RV32I-NEXT: addi s1, a3, 819
+; RV32I-NEXT: and a3, a4, s1
+; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: lui s8, 349525
+; RV32I-NEXT: lui a4, 349525
; RV32I-NEXT: or a0, a3, a0
-; RV32I-NEXT: addi s5, s8, 1365
+; RV32I-NEXT: addi s11, a4, 1365
; RV32I-NEXT: srli a3, a0, 1
-; RV32I-NEXT: and a0, a0, s5
-; RV32I-NEXT: and a3, a3, s5
+; RV32I-NEXT: sw a3, 824(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a0, s11
+; RV32I-NEXT: and a3, a3, s11
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or t2, a3, a0
; RV32I-NEXT: srli a0, t2, 8
-; RV32I-NEXT: lw a6, 4(t5)
-; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: srli a3, t2, 24
-; RV32I-NEXT: and a4, t2, a2
+; RV32I-NEXT: and a4, t2, s0
; RV32I-NEXT: slli a5, t2, 24
-; RV32I-NEXT: sw a5, 824(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 820(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a3, a5, a4
+; RV32I-NEXT: lw t1, 4(a2)
+; RV32I-NEXT: lw s7, 8(a2)
+; RV32I-NEXT: lw a4, 12(a2)
+; RV32I-NEXT: sw a4, 268(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a0, a3, a0
-; RV32I-NEXT: lw s6, 8(t5)
-; RV32I-NEXT: lw a3, 12(t5)
-; RV32I-NEXT: sw a3, 272(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a3, a0, 4
-; RV32I-NEXT: and a3, a3, s11
-; RV32I-NEXT: sw a6, 280(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a4, a6, 8
-; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: and a4, a4, a2
-; RV32I-NEXT: srli a5, a6, 24
-; RV32I-NEXT: and a7, a6, a2
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: slli t0, a6, 24
-; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: or a5, t0, a7
+; RV32I-NEXT: and a0, a0, t5
+; RV32I-NEXT: and a3, a3, t5
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: or a4, a5, a4
-; RV32I-NEXT: srli a5, a4, 4
-; RV32I-NEXT: and a4, a4, s11
-; RV32I-NEXT: and a5, a5, s11
-; RV32I-NEXT: slli a4, a4, 4
; RV32I-NEXT: or a0, a3, a0
-; RV32I-NEXT: or a4, a5, a4
-; RV32I-NEXT: srli a3, a4, 2
-; RV32I-NEXT: and a4, a4, t6
-; RV32I-NEXT: and a3, a3, t6
-; RV32I-NEXT: slli a4, a4, 2
-; RV32I-NEXT: srli a5, a0, 2
-; RV32I-NEXT: or a3, a3, a4
-; RV32I-NEXT: srli a4, a3, 1
-; RV32I-NEXT: and a3, a3, s5
-; RV32I-NEXT: and a4, a4, s5
-; RV32I-NEXT: slli s0, a3, 1
-; RV32I-NEXT: sw s0, 820(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a5, t6
-; RV32I-NEXT: or s0, a4, s0
-; RV32I-NEXT: and a0, a0, t6
-; RV32I-NEXT: srli a4, s0, 8
+; RV32I-NEXT: sw t1, 276(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a3, t1, 8
+; RV32I-NEXT: srli a4, a0, 2
+; RV32I-NEXT: and a3, a3, s0
+; RV32I-NEXT: srli a5, t1, 24
+; RV32I-NEXT: and a6, t1, s0
+; RV32I-NEXT: slli a6, a6, 8
+; RV32I-NEXT: slli t0, t1, 24
+; RV32I-NEXT: or a3, a3, a5
+; RV32I-NEXT: or a5, t0, a6
+; RV32I-NEXT: and a4, a4, s1
+; RV32I-NEXT: or a3, a5, a3
+; RV32I-NEXT: srli a5, a3, 4
+; RV32I-NEXT: and a3, a3, t5
+; RV32I-NEXT: and a5, a5, t5
+; RV32I-NEXT: slli a3, a3, 4
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: or a3, a5, a3
+; RV32I-NEXT: srli a5, a3, 2
+; RV32I-NEXT: and a3, a3, s1
+; RV32I-NEXT: and a5, a5, s1
+; RV32I-NEXT: slli a3, a3, 2
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: and a4, a4, a2
-; RV32I-NEXT: srli a5, s0, 24
-; RV32I-NEXT: and a7, s0, a2
-; RV32I-NEXT: slli t0, s0, 24
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: or a5, t0, a7
-; RV32I-NEXT: or a0, a3, a0
-; RV32I-NEXT: or a4, a5, a4
-; RV32I-NEXT: srli a3, a4, 4
-; RV32I-NEXT: and a4, a4, s11
+; RV32I-NEXT: or a3, a5, a3
+; RV32I-NEXT: srli a5, a3, 1
; RV32I-NEXT: and a3, a3, s11
-; RV32I-NEXT: slli a4, a4, 4
-; RV32I-NEXT: srli a5, a0, 1
-; RV32I-NEXT: or a3, a3, a4
-; RV32I-NEXT: srli a4, a3, 2
-; RV32I-NEXT: and a3, a3, t6
-; RV32I-NEXT: and a4, a4, t6
+; RV32I-NEXT: and a5, a5, s11
+; RV32I-NEXT: slli a3, a3, 1
+; RV32I-NEXT: sw a3, 816(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a4, a4, a0
+; RV32I-NEXT: or s2, a5, a3
+; RV32I-NEXT: srli a0, a4, 1
+; RV32I-NEXT: srli a3, s2, 8
+; RV32I-NEXT: and a5, a0, s11
+; RV32I-NEXT: and a3, a3, s0
+; RV32I-NEXT: srli a6, s2, 24
+; RV32I-NEXT: and t0, s2, s0
+; RV32I-NEXT: slli t1, s2, 24
+; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: or a3, a3, a6
+; RV32I-NEXT: or a6, t1, t0
+; RV32I-NEXT: and a4, a4, s11
+; RV32I-NEXT: or a3, a6, a3
+; RV32I-NEXT: srli a6, a3, 4
+; RV32I-NEXT: and a3, a3, t5
+; RV32I-NEXT: and a6, a6, t5
+; RV32I-NEXT: slli a3, a3, 4
+; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: or a3, a6, a3
+; RV32I-NEXT: srli a6, a3, 2
+; RV32I-NEXT: and a3, a3, s1
+; RV32I-NEXT: and a6, a6, s1
; RV32I-NEXT: slli a3, a3, 2
-; RV32I-NEXT: and a5, a5, s5
-; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: or t0, a5, a4
+; RV32I-NEXT: or a3, a6, a3
; RV32I-NEXT: srli a4, a3, 1
-; RV32I-NEXT: and a3, a3, s5
-; RV32I-NEXT: and a4, a4, s5
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: and a7, a0, s5
-; RV32I-NEXT: or a0, a4, a3
-; RV32I-NEXT: slli a7, a7, 1
-; RV32I-NEXT: andi a4, a0, 1
-; RV32I-NEXT: or a5, a5, a7
+; RV32I-NEXT: and t3, a3, s11
+; RV32I-NEXT: and a3, a4, s11
+; RV32I-NEXT: slli t3, t3, 1
+; RV32I-NEXT: slli a4, t0, 1
+; RV32I-NEXT: or t6, a3, t3
+; RV32I-NEXT: andi a3, t6, 2
+; RV32I-NEXT: andi a5, t6, 1
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: and a4, a5, t0
+; RV32I-NEXT: xor a3, a4, a3
+; RV32I-NEXT: andi a4, t6, 4
+; RV32I-NEXT: andi a5, t6, 8
; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: slli a6, t0, 2
+; RV32I-NEXT: slli t1, t0, 3
+; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: and a5, a5, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: andi a5, t6, 16
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a5, t6, 32
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: slli a6, t0, 4
+; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: slli a6, t0, 5
+; RV32I-NEXT: andi t1, t6, 64
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli t1, t0, 6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: andi a5, t6, 128
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a5, t6, 256
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: slli a6, t0, 7
+; RV32I-NEXT: and a4, a4, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: slli a6, t0, 8
+; RV32I-NEXT: andi t1, t6, 512
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 9
+; RV32I-NEXT: andi t1, t6, 1024
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 10
+; RV32I-NEXT: li t1, 1
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: slli s3, t1, 11
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, t6, s3
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: andi a7, a0, 2
-; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli t0, a5, 1
-; RV32I-NEXT: and a7, a7, t0
-; RV32I-NEXT: andi t0, a0, 4
-; RV32I-NEXT: xor a4, a4, a7
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: andi t0, a0, 8
-; RV32I-NEXT: slli t1, a5, 2
-; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: slli t3, a5, 3
-; RV32I-NEXT: and a7, a7, t1
-; RV32I-NEXT: and t0, t0, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: andi t0, a0, 16
-; RV32I-NEXT: xor a4, a4, a7
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: andi t0, a0, 32
-; RV32I-NEXT: slli t1, a5, 4
-; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: and a7, a7, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: slli t1, a5, 5
-; RV32I-NEXT: andi t3, a0, 64
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t3, a5, 6
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: and t0, t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: andi t0, a0, 128
-; RV32I-NEXT: xor a4, a4, a7
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: andi t0, a0, 256
-; RV32I-NEXT: slli t1, a5, 7
-; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: and a7, a7, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: slli t1, a5, 8
-; RV32I-NEXT: andi t3, a0, 512
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t0, a5, 9
-; RV32I-NEXT: andi t3, a0, 1024
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t0, a5, 10
-; RV32I-NEXT: li t3, 1
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: slli s10, t3, 11
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: and t0, a0, s10
-; RV32I-NEXT: xor a4, a4, a7
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi a7, a7, -1
; RV32I-NEXT: lui a6, 1
-; RV32I-NEXT: slli t0, a5, 11
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: lui s2, 1
-; RV32I-NEXT: and a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui a6, 2
-; RV32I-NEXT: slli t1, a5, 12
-; RV32I-NEXT: and t3, a0, a6
-; RV32I-NEXT: lui s3, 2
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t0, a5, 13
-; RV32I-NEXT: lui a6, 4
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: lui s9, 4
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui a6, 8
-; RV32I-NEXT: slli t1, a5, 14
-; RV32I-NEXT: and t3, a0, a6
-; RV32I-NEXT: lui s7, 8
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t3, a5, 15
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: and t0, t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: and t0, a0, t4
-; RV32I-NEXT: xor a4, a4, a7
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli a5, t0, 11
+; RV32I-NEXT: and a6, t6, a6
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: lui a7, 2
+; RV32I-NEXT: slli a6, t0, 12
+; RV32I-NEXT: and t1, t6, a7
+; RV32I-NEXT: lui s9, 2
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 13
+; RV32I-NEXT: lui a7, 4
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t6, a7
+; RV32I-NEXT: lui s5, 4
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: lui a7, 8
+; RV32I-NEXT: slli a6, t0, 14
+; RV32I-NEXT: and t1, t6, a7
+; RV32I-NEXT: lui s10, 8
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli t1, t0, 15
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, t6, t4
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: lui a6, 32
-; RV32I-NEXT: slli t0, a5, 16
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: and a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui a6, 64
-; RV32I-NEXT: slli t1, a5, 17
-; RV32I-NEXT: and t3, a0, a6
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t0, a5, 18
-; RV32I-NEXT: lui a6, 128
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui a6, 256
-; RV32I-NEXT: slli t1, a5, 19
-; RV32I-NEXT: and t3, a0, a6
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t0, a5, 20
-; RV32I-NEXT: lui a6, 512
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: slli t1, a5, 21
-; RV32I-NEXT: and t0, t0, t1
+; RV32I-NEXT: slli a5, t0, 16
+; RV32I-NEXT: and a6, t6, a6
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: lui a7, 64
+; RV32I-NEXT: slli a6, t0, 17
+; RV32I-NEXT: and t1, t6, a7
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 18
+; RV32I-NEXT: lui a7, 128
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t6, a7
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: lui a7, 256
+; RV32I-NEXT: slli a6, t0, 19
+; RV32I-NEXT: and t1, t6, a7
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 20
+; RV32I-NEXT: lui a7, 512
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t6, a7
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: slli a6, t0, 21
+; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: lui a6, 1024
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: and t0, a0, a6
-; RV32I-NEXT: xor a4, a4, a7
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, t6, a6
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: lui a6, 2048
-; RV32I-NEXT: slli t0, a5, 22
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: lui s1, 2048
-; RV32I-NEXT: and a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui a6, 4096
-; RV32I-NEXT: slli t1, a5, 23
-; RV32I-NEXT: and t3, a0, a6
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t0, a5, 24
-; RV32I-NEXT: lui a6, 8192
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui a6, 16384
-; RV32I-NEXT: slli t1, a5, 25
-; RV32I-NEXT: and t3, a0, a6
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t0, a5, 26
-; RV32I-NEXT: lui a6, 32768
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: and t1, a0, a6
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: seqz t0, t1
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui a6, 65536
-; RV32I-NEXT: slli t1, a5, 27
-; RV32I-NEXT: and t3, a0, a6
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: seqz t1, t3
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli t3, a5, 28
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: and t0, t1, t3
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: lui a6, 131072
-; RV32I-NEXT: xor a4, a4, a7
-; RV32I-NEXT: and a7, a0, a6
-; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: slli a5, t0, 22
+; RV32I-NEXT: and a6, t6, a6
+; RV32I-NEXT: lui ra, 2048
+; RV32I-NEXT: and a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: lui a7, 4096
+; RV32I-NEXT: slli a6, t0, 23
+; RV32I-NEXT: and t1, t6, a7
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 24
+; RV32I-NEXT: lui a7, 8192
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t6, a7
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: lui a7, 16384
+; RV32I-NEXT: slli a6, t0, 25
+; RV32I-NEXT: and t1, t6, a7
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 26
+; RV32I-NEXT: lui a7, 32768
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t6, a7
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: lui a7, 65536
+; RV32I-NEXT: slli a6, t0, 27
+; RV32I-NEXT: and t1, t6, a7
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: seqz a6, t1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a5, t0, 28
+; RV32I-NEXT: lui a7, 131072
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t6, a7
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: slli a4, t0, 29
; RV32I-NEXT: lui a6, 262144
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and a0, a0, a6
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: slli t0, a5, 29
-; RV32I-NEXT: and a7, a7, t0
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: srli a3, a3, 31
-; RV32I-NEXT: slli t0, a5, 30
-; RV32I-NEXT: and a0, a0, t0
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a5, a5, 31
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: xor a0, a7, a0
-; RV32I-NEXT: and a3, a3, a5
-; RV32I-NEXT: xor a0, a0, a3
-; RV32I-NEXT: lw t4, 0(a1)
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: and a5, t6, a6
+; RV32I-NEXT: slli t0, t0, 30
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: srli a6, t3, 31
+; RV32I-NEXT: and a5, a5, t0
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: slli a0, a0, 31
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a0, a6, a0
; RV32I-NEXT: xor a0, a4, a0
+; RV32I-NEXT: lw t4, 0(a1)
+; RV32I-NEXT: xor a0, a3, a0
; RV32I-NEXT: srli a1, a0, 8
-; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: and a1, a1, s0
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: srli a3, t4, 8
-; RV32I-NEXT: and a3, a3, a2
+; RV32I-NEXT: and a3, a3, s0
; RV32I-NEXT: srli a4, t4, 24
; RV32I-NEXT: or a3, a3, a4
; RV32I-NEXT: slli a4, a0, 24
-; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: and a5, t4, a2
+; RV32I-NEXT: and a0, a0, s0
+; RV32I-NEXT: and a5, t4, s0
; RV32I-NEXT: slli a5, a5, 8
; RV32I-NEXT: slli a6, t4, 24
; RV32I-NEXT: sw a6, 296(sp) # 4-byte Folded Spill
@@ -16192,315 +16195,315 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: srli a4, a3, 4
-; RV32I-NEXT: and a3, a3, s11
-; RV32I-NEXT: and a4, a4, s11
+; RV32I-NEXT: and a3, a3, t5
+; RV32I-NEXT: and a4, a4, t5
; RV32I-NEXT: slli a3, a3, 4
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: srli a1, a0, 4
-; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: and a1, a1, s11
+; RV32I-NEXT: and a0, a0, t5
+; RV32I-NEXT: and a1, a1, t5
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: srli a4, a3, 2
-; RV32I-NEXT: and a3, a3, t6
-; RV32I-NEXT: and a4, a4, t6
+; RV32I-NEXT: and a3, a3, s1
+; RV32I-NEXT: and a4, a4, s1
; RV32I-NEXT: slli a3, a3, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: srli a1, a3, 1
-; RV32I-NEXT: and a3, a3, s5
-; RV32I-NEXT: and a1, a1, s5
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: or t1, a1, a3
-; RV32I-NEXT: andi a1, s0, 2
+; RV32I-NEXT: srli s6, a3, 1
+; RV32I-NEXT: and a1, a3, s11
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: and a3, s6, s11
+; RV32I-NEXT: or s8, a3, a1
+; RV32I-NEXT: andi a1, s2, 2
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: andi a3, s0, 1
+; RV32I-NEXT: andi a3, s2, 1
; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 816(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 812(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a3
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 812(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t1, 1
+; RV32I-NEXT: sw a3, 808(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s8, 1
; RV32I-NEXT: sw a1, 640(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a4, a1
-; RV32I-NEXT: and a3, a3, t1
+; RV32I-NEXT: and a3, a3, s8
; RV32I-NEXT: xor a1, a3, a1
-; RV32I-NEXT: andi a3, s0, 4
+; RV32I-NEXT: andi a3, s2, 4
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: andi a4, s0, 8
+; RV32I-NEXT: andi a4, s2, 8
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 808(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 804(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 804(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t1, 2
+; RV32I-NEXT: sw a6, 800(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s8, 2
; RV32I-NEXT: sw a3, 636(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: slli a4, t1, 3
+; RV32I-NEXT: slli a4, s8, 3
; RV32I-NEXT: sw a4, 632(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: andi a5, s0, 16
+; RV32I-NEXT: andi a5, s2, 16
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 800(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, s0, 32
+; RV32I-NEXT: sw a6, 796(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a4, s2, 32
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, s0, 64
+; RV32I-NEXT: andi a5, s2, 64
; RV32I-NEXT: addi a7, a4, -1
-; RV32I-NEXT: sw a7, 796(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 792(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi t0, a4, -1
-; RV32I-NEXT: sw t0, 792(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t1, 4
+; RV32I-NEXT: addi t1, a4, -1
+; RV32I-NEXT: sw t1, 788(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s8, 4
; RV32I-NEXT: sw a4, 628(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: slli a5, t1, 5
+; RV32I-NEXT: slli a5, s8, 5
; RV32I-NEXT: sw a5, 624(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a5, a7, a5
-; RV32I-NEXT: slli a6, t1, 6
+; RV32I-NEXT: slli a6, s8, 6
; RV32I-NEXT: sw a6, 620(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, t0, a6
+; RV32I-NEXT: and a5, t1, a6
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: srli a3, a0, 2
-; RV32I-NEXT: and a0, a0, t6
-; RV32I-NEXT: and a3, a3, t6
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: and a3, a3, s1
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: andi a3, s0, 128
-; RV32I-NEXT: andi a4, s0, 256
+; RV32I-NEXT: andi a3, s2, 128
+; RV32I-NEXT: andi a4, s2, 256
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 788(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 784(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 784(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t1, 7
+; RV32I-NEXT: sw a6, 780(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s8, 7
; RV32I-NEXT: sw a3, 616(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t1, 8
+; RV32I-NEXT: slli a4, s8, 8
; RV32I-NEXT: sw a4, 612(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: andi a4, s0, 512
+; RV32I-NEXT: andi a4, s2, 512
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, s0, 1024
+; RV32I-NEXT: andi a5, s2, 1024
; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 780(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a6, 776(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a7, a4, -1
-; RV32I-NEXT: sw a7, 776(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t1, 9
+; RV32I-NEXT: sw a7, 772(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s8, 9
; RV32I-NEXT: sw a4, 608(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: slli a5, t1, 10
+; RV32I-NEXT: slli a5, s8, 10
; RV32I-NEXT: sw a5, 604(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: and a4, a7, a5
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, s0, s10
-; RV32I-NEXT: sw s10, 288(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 284(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, s2, s3
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 768(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, s0, s2
-; RV32I-NEXT: lui ra, 1
+; RV32I-NEXT: sw a5, 764(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a3, 1
+; RV32I-NEXT: and a3, s2, a3
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: and a4, s0, s3
+; RV32I-NEXT: and a4, s2, s9
; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 764(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a6, 760(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a7, a3, -1
-; RV32I-NEXT: sw a7, 760(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t1, 11
+; RV32I-NEXT: sw a7, 756(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s8, 11
; RV32I-NEXT: sw a3, 600(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: slli a4, t1, 12
+; RV32I-NEXT: slli a4, s8, 12
; RV32I-NEXT: sw a4, 596(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: slli a5, t1, 13
+; RV32I-NEXT: slli a5, s8, 13
; RV32I-NEXT: sw a5, 592(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: and a4, a7, a5
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, s0, s9
-; RV32I-NEXT: lui s3, 4
+; RV32I-NEXT: and a4, s2, s5
+; RV32I-NEXT: lui s9, 4
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, s0, s7
+; RV32I-NEXT: and a5, s2, s10
; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 756(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a6, 752(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a7, a4, -1
-; RV32I-NEXT: sw a7, 752(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t1, 14
+; RV32I-NEXT: sw a7, 748(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s8, 14
; RV32I-NEXT: sw a4, 588(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: slli a5, t1, 15
+; RV32I-NEXT: slli a5, s8, 15
; RV32I-NEXT: sw a5, 584(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: and a4, a7, a5
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: addi a5, s8, 1364
-; RV32I-NEXT: sw a5, 700(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a5, 349525
+; RV32I-NEXT: addi a5, a5, 1364
+; RV32I-NEXT: sw a5, 696(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a4, a0, 1
-; RV32I-NEXT: and a0, a0, s5
+; RV32I-NEXT: and a0, a0, s11
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a4, a0
-; RV32I-NEXT: sw a0, 772(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 768(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a0, a1, a3
; RV32I-NEXT: lui a1, 16
-; RV32I-NEXT: and a1, s0, a1
-; RV32I-NEXT: lui s8, 16
+; RV32I-NEXT: and a1, s2, a1
+; RV32I-NEXT: lui s10, 16
; RV32I-NEXT: lui a3, 32
-; RV32I-NEXT: and a3, s0, a3
-; RV32I-NEXT: lui s9, 32
+; RV32I-NEXT: and a3, s2, a3
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 748(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 744(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 744(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t1, 16
+; RV32I-NEXT: sw a5, 740(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s8, 16
; RV32I-NEXT: sw a1, 580(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t1, 17
+; RV32I-NEXT: slli a3, s8, 17
; RV32I-NEXT: sw a3, 576(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a4, a1
; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: lui a3, 64
-; RV32I-NEXT: and a3, s0, a3
+; RV32I-NEXT: and a3, s2, a3
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: lui a4, 128
-; RV32I-NEXT: and a4, s0, a4
-; RV32I-NEXT: lui s7, 128
+; RV32I-NEXT: and a4, s2, a4
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 740(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 736(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 736(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t1, 18
+; RV32I-NEXT: sw a6, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s8, 18
; RV32I-NEXT: sw a3, 572(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: slli a4, t1, 19
+; RV32I-NEXT: slli a4, s8, 19
; RV32I-NEXT: sw a4, 568(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: and a3, a6, a4
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: lui a3, 256
-; RV32I-NEXT: and a3, s0, a3
+; RV32I-NEXT: and a3, s2, a3
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: lui a4, 1024
-; RV32I-NEXT: and a4, s0, a4
+; RV32I-NEXT: and a4, s2, a4
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 720(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 732(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, s0, s1
+; RV32I-NEXT: sw a6, 728(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, s2, ra
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, t1, 20
+; RV32I-NEXT: slli a4, s8, 20
; RV32I-NEXT: sw a4, 556(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a7, a3, -1
-; RV32I-NEXT: sw a7, 728(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 724(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a5, a4
-; RV32I-NEXT: slli a4, t1, 22
+; RV32I-NEXT: slli a4, s8, 22
; RV32I-NEXT: sw a4, 564(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t1, 23
+; RV32I-NEXT: slli a5, s8, 23
; RV32I-NEXT: sw a5, 560(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: and a5, a7, a5
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lui s1, 512
-; RV32I-NEXT: and a3, s0, s1
-; RV32I-NEXT: lui s2, 4096
-; RV32I-NEXT: and a5, s0, s2
+; RV32I-NEXT: lui s5, 512
+; RV32I-NEXT: and a3, s2, s5
+; RV32I-NEXT: lui a5, 4096
+; RV32I-NEXT: and a5, s2, a5
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a7, a3, -1
-; RV32I-NEXT: sw a7, 716(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 712(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 720(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t1, 21
-; RV32I-NEXT: sw a3, 548(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t1, 24
-; RV32I-NEXT: sw a5, 552(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a6, 716(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s8, 21
+; RV32I-NEXT: sw a3, 544(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, s8, 24
+; RV32I-NEXT: sw a5, 548(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a7, a3
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a6, 0(t5)
-; RV32I-NEXT: lui t5, 8192
-; RV32I-NEXT: and a3, s0, t5
+; RV32I-NEXT: lw a7, 0(a2)
+; RV32I-NEXT: lui a2, 8192
+; RV32I-NEXT: and a3, s2, a2
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and a5, s0, a5
-; RV32I-NEXT: addi a7, a3, -1
-; RV32I-NEXT: sw a7, 712(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a2, 16384
+; RV32I-NEXT: and a5, s2, a2
+; RV32I-NEXT: addi a6, a3, -1
+; RV32I-NEXT: sw a6, 708(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a5
-; RV32I-NEXT: addi t0, a3, -1
-; RV32I-NEXT: sw t0, 708(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t1, 25
-; RV32I-NEXT: sw a3, 540(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a7, a3
-; RV32I-NEXT: slli a5, t1, 26
-; RV32I-NEXT: sw a5, 536(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a5, a3, -1
+; RV32I-NEXT: sw a5, 704(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, s8, 25
+; RV32I-NEXT: sw a2, 540(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a6, a2
+; RV32I-NEXT: slli a2, s8, 26
+; RV32I-NEXT: sw a2, 536(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: and a4, t0, a5
+; RV32I-NEXT: and a4, a5, a2
; RV32I-NEXT: xor a1, a0, a1
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: srli a0, a6, 8
-; RV32I-NEXT: sw a2, 652(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a6, a2
-; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: srli a0, a7, 8
+; RV32I-NEXT: sw s0, 652(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a7, s0
+; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: srli a5, a6, 24
-; RV32I-NEXT: slli a7, a6, 24
+; RV32I-NEXT: srli a5, a7, 24
+; RV32I-NEXT: slli a6, a7, 24
; RV32I-NEXT: or a0, a0, a5
-; RV32I-NEXT: or a4, a7, a4
+; RV32I-NEXT: or a4, a6, a4
; RV32I-NEXT: or a0, a4, a0
-; RV32I-NEXT: lui t0, 32768
-; RV32I-NEXT: and a4, s0, t0
+; RV32I-NEXT: lui ra, 32768
+; RV32I-NEXT: and a4, s2, ra
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: addi a2, a4, -1
-; RV32I-NEXT: sw a2, 704(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a5, s11
-; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: slli a5, t1, 27
+; RV32I-NEXT: sw a2, 700(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t5, 288(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, t5
+; RV32I-NEXT: and a0, a0, t5
+; RV32I-NEXT: slli a5, s8, 27
; RV32I-NEXT: sw a5, 532(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: and a5, a2, a5
; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a4, a0, 2
-; RV32I-NEXT: sw t6, 648(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a0, t6
-; RV32I-NEXT: and a4, a4, t6
+; RV32I-NEXT: sw s1, 648(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a0, s1
+; RV32I-NEXT: and a4, a4, s1
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a4, a0
-; RV32I-NEXT: lui a4, 65536
-; RV32I-NEXT: and a4, s0, a4
+; RV32I-NEXT: lui a2, 65536
+; RV32I-NEXT: and a4, s2, a2
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: srli a5, a0, 1
-; RV32I-NEXT: addi a2, a4, -1
-; RV32I-NEXT: sw a2, 696(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s5, 656(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a5, s5
-; RV32I-NEXT: and a0, a0, s5
-; RV32I-NEXT: slli a5, t1, 28
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 692(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s11, 656(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a5, s11
+; RV32I-NEXT: and a0, a0, s11
+; RV32I-NEXT: slli a5, s8, 28
; RV32I-NEXT: sw a5, 528(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a0, 1
-; RV32I-NEXT: and a0, a2, a5
+; RV32I-NEXT: slli t5, a0, 1
+; RV32I-NEXT: and a0, a6, a5
; RV32I-NEXT: xor a3, a3, a0
-; RV32I-NEXT: or a0, a4, t3
+; RV32I-NEXT: or a0, a4, t5
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: sw a1, 680(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 676(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a0, 2
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: andi a3, a0, 1
@@ -16510,10 +16513,10 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: addi a3, a1, -1
; RV32I-NEXT: sw a3, 520(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, t2, 1
-; RV32I-NEXT: sw a1, 692(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 688(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a4, a1
; RV32I-NEXT: and a3, a3, t2
-; RV32I-NEXT: xor a2, a3, a1
+; RV32I-NEXT: xor a1, a3, a1
; RV32I-NEXT: andi a3, a0, 4
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: andi a4, a0, 8
@@ -16523,36 +16526,36 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: addi a4, a3, -1
; RV32I-NEXT: sw a4, 512(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, t2, 2
-; RV32I-NEXT: sw a3, 688(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 684(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: slli a1, t2, 3
-; RV32I-NEXT: sw a1, 684(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a1
+; RV32I-NEXT: slli a5, t2, 3
+; RV32I-NEXT: sw a5, 680(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: andi a5, a0, 16
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a1, a4, -1
-; RV32I-NEXT: sw a1, 500(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 500(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a4, a0, 32
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: andi a5, a0, 64
-; RV32I-NEXT: addi a7, a4, -1
-; RV32I-NEXT: sw a7, 496(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t0, a4, -1
+; RV32I-NEXT: sw t0, 496(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: sw a4, 492(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t2, 4
-; RV32I-NEXT: sw a5, 668(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, a1, a5
+; RV32I-NEXT: addi t6, a4, -1
+; RV32I-NEXT: sw t6, 492(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, t2, 4
+; RV32I-NEXT: sw a4, 664(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: slli a5, t2, 5
-; RV32I-NEXT: sw a5, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a7, a5
-; RV32I-NEXT: slli t6, t2, 6
-; RV32I-NEXT: sw t6, 660(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a7, a1, a5
-; RV32I-NEXT: and a5, a4, t6
-; RV32I-NEXT: xor a1, a2, a3
-; RV32I-NEXT: xor a4, a7, a5
+; RV32I-NEXT: sw a5, 660(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, t0, a5
+; RV32I-NEXT: slli a6, t2, 6
+; RV32I-NEXT: sw a6, 380(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, t6, a6
+; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: andi a3, a0, 128
; RV32I-NEXT: andi a5, a0, 256
; RV32I-NEXT: seqz a3, a3
@@ -16561,720 +16564,725 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: sw a3, 488(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: sw a5, 484(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 7
-; RV32I-NEXT: sw a2, 380(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, t2, 8
-; RV32I-NEXT: sw a7, 376(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a3, a2
-; RV32I-NEXT: and a5, a5, a7
+; RV32I-NEXT: slli a6, t2, 7
+; RV32I-NEXT: sw a6, 376(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, t2, 8
+; RV32I-NEXT: sw t0, 372(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a3, a6
+; RV32I-NEXT: and a5, a5, t0
; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: andi a5, a0, 512
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: andi a7, a0, 1024
-; RV32I-NEXT: addi a2, a5, -1
-; RV32I-NEXT: sw a2, 480(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a5, a7
-; RV32I-NEXT: addi a7, a5, -1
-; RV32I-NEXT: sw a7, 476(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a6, a0, 1024
+; RV32I-NEXT: addi t0, a5, -1
+; RV32I-NEXT: sw t0, 480(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 476(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, t2, 9
-; RV32I-NEXT: sw a5, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a2, a5
-; RV32I-NEXT: slli a2, t2, 10
-; RV32I-NEXT: sw a2, 368(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 368(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, t0, a5
+; RV32I-NEXT: slli t0, t2, 10
+; RV32I-NEXT: sw t0, 364(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: and a5, a7, a2
+; RV32I-NEXT: and a5, a6, t0
; RV32I-NEXT: xor a1, a1, a4
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lui a4, 131072
-; RV32I-NEXT: and a4, s0, a4
-; RV32I-NEXT: lui a5, 262144
-; RV32I-NEXT: and a5, s0, a5
+; RV32I-NEXT: lui t1, 131072
+; RV32I-NEXT: and a4, s2, t1
+; RV32I-NEXT: lui t3, 262144
+; RV32I-NEXT: and a5, s2, t3
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a2, a4, -1
-; RV32I-NEXT: sw a2, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a7, a5, -1
-; RV32I-NEXT: sw a7, 672(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t1, 29
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 672(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t0, a5, -1
+; RV32I-NEXT: sw t0, 668(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s8, 384(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s8, 29
; RV32I-NEXT: sw a4, 508(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t1, 30
-; RV32I-NEXT: sw t1, 384(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, s8, 30
; RV32I-NEXT: sw a5, 504(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a2, a4
-; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: and a5, t0, a5
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, a0, s10
-; RV32I-NEXT: and a5, a0, ra
+; RV32I-NEXT: and a3, a0, s3
+; RV32I-NEXT: lui a5, 1
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: sw a3, 468(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: sw a5, 464(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 11
-; RV32I-NEXT: sw a2, 364(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, t2, 12
-; RV32I-NEXT: sw a7, 360(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a3, a2
-; RV32I-NEXT: and a5, a5, a7
+; RV32I-NEXT: slli a6, t2, 11
+; RV32I-NEXT: sw a6, 360(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, t2, 12
+; RV32I-NEXT: sw t0, 356(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a3, a6
+; RV32I-NEXT: and a5, a5, t0
; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: lui a5, 2
; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: and a7, a0, s3
-; RV32I-NEXT: addi a2, a5, -1
-; RV32I-NEXT: sw a2, 460(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a5, a7
-; RV32I-NEXT: addi a7, a5, -1
-; RV32I-NEXT: sw a7, 456(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a0, s9
+; RV32I-NEXT: addi t0, a5, -1
+; RV32I-NEXT: sw t0, 460(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 456(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, t2, 13
-; RV32I-NEXT: sw a5, 356(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a2, a5
-; RV32I-NEXT: slli a2, t2, 14
-; RV32I-NEXT: sw a2, 352(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 352(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, t0, a5
+; RV32I-NEXT: slli t0, t2, 14
+; RV32I-NEXT: sw t0, 348(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: and a5, a7, a2
+; RV32I-NEXT: and a5, a6, t0
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 820(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli t0, s6, 31
+; RV32I-NEXT: sw t0, 472(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a5, 816(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a5, a5, 31
+; RV32I-NEXT: lui a6, 8
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lui a2, 8
-; RV32I-NEXT: and a7, a0, a2
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: sw a6, 452(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t2, 15
+; RV32I-NEXT: sw s0, 344(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi t6, a5, -1
-; RV32I-NEXT: sw t6, 820(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a5, a7
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 452(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, t2, 15
-; RV32I-NEXT: sw a7, 348(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t1, 31
-; RV32I-NEXT: sw a2, 472(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a7
+; RV32I-NEXT: sw t6, 816(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a6, s0
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: and a5, t6, a2
-; RV32I-NEXT: xor ra, a4, a5
+; RV32I-NEXT: and a5, t6, t0
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: sw a4, 340(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, a0, s8
-; RV32I-NEXT: and a4, a0, s9
+; RV32I-NEXT: and a3, a0, s10
+; RV32I-NEXT: lui a4, 32
+; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: sw a3, 448(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: sw a4, 444(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s9, t2, 16
-; RV32I-NEXT: slli s10, t2, 17
-; RV32I-NEXT: and a3, a3, s9
-; RV32I-NEXT: and a4, a4, s10
+; RV32I-NEXT: slli s10, t2, 16
+; RV32I-NEXT: slli s11, t2, 17
+; RV32I-NEXT: and a3, a3, s10
+; RV32I-NEXT: and a4, a4, s11
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: lui a4, 64
; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a0, s7
-; RV32I-NEXT: addi a2, a4, -1
-; RV32I-NEXT: sw a2, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a5, 128
+; RV32I-NEXT: and a5, a0, a5
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 440(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a5, a4, -1
; RV32I-NEXT: sw a5, 436(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli s8, t2, 18
-; RV32I-NEXT: and a4, a2, s8
-; RV32I-NEXT: slli s7, t2, 19
+; RV32I-NEXT: and a4, a6, s8
+; RV32I-NEXT: slli s9, t2, 19
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, a5, s7
+; RV32I-NEXT: and a4, a5, s9
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: lui a4, 256
; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, a0, s1
-; RV32I-NEXT: addi a2, a4, -1
-; RV32I-NEXT: sw a2, 432(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a0, s5
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 432(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a5, a4, -1
; RV32I-NEXT: sw a5, 428(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s3, t2, 20
-; RV32I-NEXT: and a4, a2, s3
-; RV32I-NEXT: slli s5, t2, 21
+; RV32I-NEXT: slli s5, t2, 20
+; RV32I-NEXT: and a4, a6, s5
+; RV32I-NEXT: slli s6, t2, 21
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, a5, s5
+; RV32I-NEXT: and a4, a5, s6
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: lui a4, 1024
; RV32I-NEXT: and a4, a0, a4
-; RV32I-NEXT: xor t1, a1, a3
+; RV32I-NEXT: xor t0, a1, a3
; RV32I-NEXT: seqz a1, a4
-; RV32I-NEXT: addi a2, a1, -1
-; RV32I-NEXT: sw a2, 424(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a4, a1, -1
+; RV32I-NEXT: sw a4, 424(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 2048
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: and a3, a0, s2
-; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 420(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a3, 4096
+; RV32I-NEXT: and a3, a0, a3
+; RV32I-NEXT: addi a5, a1, -1
+; RV32I-NEXT: sw a5, 420(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a3
; RV32I-NEXT: slli s2, t2, 22
-; RV32I-NEXT: slli s1, t2, 23
-; RV32I-NEXT: and a3, a2, s2
-; RV32I-NEXT: and a4, a4, s1
+; RV32I-NEXT: slli s3, t2, 23
+; RV32I-NEXT: and a3, a4, s2
+; RV32I-NEXT: and a4, a5, s3
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: sw a1, 416(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s0, 824(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, s0
-; RV32I-NEXT: and a4, a0, t5
+; RV32I-NEXT: lw s1, 820(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, s1
+; RV32I-NEXT: lui a4, 8192
+; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: xor a1, a3, a1
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: sw a3, 412(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t6, t2, 25
-; RV32I-NEXT: and a3, a3, t6
+; RV32I-NEXT: slli s0, t2, 25
+; RV32I-NEXT: and a3, a3, s0
; RV32I-NEXT: lui a4, 16384
; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: sw a3, 408(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t5, t2, 26
-; RV32I-NEXT: and a3, a3, t5
-; RV32I-NEXT: and a4, a0, t0
+; RV32I-NEXT: slli t6, t2, 26
+; RV32I-NEXT: and a3, a3, t6
+; RV32I-NEXT: and a4, a0, ra
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: sw a3, 404(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, t2, 27
-; RV32I-NEXT: and a3, a3, t0
-; RV32I-NEXT: lui a4, 65536
-; RV32I-NEXT: and a4, a0, a4
+; RV32I-NEXT: slli a6, t2, 27
+; RV32I-NEXT: and a3, a3, a6
+; RV32I-NEXT: and a4, a0, a2
; RV32I-NEXT: xor a2, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: sw a3, 400(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, t2, 28
-; RV32I-NEXT: and a3, a3, a7
-; RV32I-NEXT: lui a1, 131072
-; RV32I-NEXT: and a1, a0, a1
-; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slli a5, t2, 28
+; RV32I-NEXT: and a3, a3, a5
+; RV32I-NEXT: and a1, a0, t1
+; RV32I-NEXT: xor a3, a2, a3
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 396(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a1, 262144
-; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: addi a2, a1, -1
+; RV32I-NEXT: sw a2, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a0, t3
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: srli a1, t3, 31
-; RV32I-NEXT: addi a4, a0, -1
-; RV32I-NEXT: sw a4, 388(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a0, a1
+; RV32I-NEXT: srli a1, t5, 31
; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: sw a0, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 388(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: lw t5, 824(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli t5, t5, 31
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: sw a1, 396(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t3, t2, 29
-; RV32I-NEXT: and a5, a3, t3
-; RV32I-NEXT: slli a3, t2, 30
-; RV32I-NEXT: and a1, a4, a3
-; RV32I-NEXT: slli a4, t2, 31
-; RV32I-NEXT: xor a5, a5, a1
-; RV32I-NEXT: and a1, a0, a4
-; RV32I-NEXT: xor a2, t1, a2
-; RV32I-NEXT: xor a1, a5, a1
-; RV32I-NEXT: lw a0, 680(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, ra
-; RV32I-NEXT: xor ra, a2, a1
-; RV32I-NEXT: lw a1, 816(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 692(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: lw a2, 812(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a2, t2
-; RV32I-NEXT: lw a5, 808(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 688(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, t1
-; RV32I-NEXT: lw a5, 804(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 684(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: xor a2, t1, t2
-; RV32I-NEXT: lw a5, 800(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 668(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, t1
-; RV32I-NEXT: lw a5, 796(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 664(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 792(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 660(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, t1, t2
-; RV32I-NEXT: lw a5, 788(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 380(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, t1
-; RV32I-NEXT: lw a5, 784(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 376(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 780(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 776(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, t1, t2
-; RV32I-NEXT: lw a5, 768(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, t1
-; RV32I-NEXT: lw a5, 764(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 760(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 356(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 756(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 352(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 752(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 348(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, t2
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, t1, t2
-; RV32I-NEXT: lw a5, 748(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, s9
-; RV32I-NEXT: lw a5, 744(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, s10
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 740(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, s8
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 736(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, s7
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 724(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, s3
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: lw a5, 716(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t2, a5, s5
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, t1, t2
-; RV32I-NEXT: xor a0, ra, a0
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 732(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a2, s2
-; RV32I-NEXT: lw a5, 728(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, s1
+; RV32I-NEXT: slli a4, t2, 30
+; RV32I-NEXT: and a2, a2, t3
+; RV32I-NEXT: and ra, a0, a4
+; RV32I-NEXT: xor a0, a2, ra
+; RV32I-NEXT: and ra, a1, t5
+; RV32I-NEXT: xor a2, t0, a3
+; RV32I-NEXT: xor t0, a0, ra
+; RV32I-NEXT: lw a0, 676(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 340(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t1, a0, a1
+; RV32I-NEXT: xor ra, a2, t0
+; RV32I-NEXT: lw a0, 812(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 688(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a0, a2
+; RV32I-NEXT: lw a0, 808(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, a0, t2
+; RV32I-NEXT: lw a0, 804(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a0, a1
+; RV32I-NEXT: lw a0, 800(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: xor a2, t0, a2
+; RV32I-NEXT: xor a0, t2, a0
+; RV32I-NEXT: lw a1, 796(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 664(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, a1, a3
+; RV32I-NEXT: lw a1, 792(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 660(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 788(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor a0, a2, a0
+; RV32I-NEXT: xor a2, t0, t2
+; RV32I-NEXT: lw a1, 784(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 376(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, a1, a3
+; RV32I-NEXT: lw a1, 780(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 372(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 776(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 368(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 772(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 364(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: xor a2, t0, t2
+; RV32I-NEXT: lw a1, 764(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 360(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, a1, a3
+; RV32I-NEXT: lw a1, 760(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 356(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 756(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 352(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 752(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 348(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 748(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, a3
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: xor a2, t0, t2
+; RV32I-NEXT: lw a1, 744(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, a1, s10
+; RV32I-NEXT: lw a1, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, s11
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 736(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, s8
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, s9
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 720(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, s5
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a1, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, a1, s6
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: xor a2, t0, t2
+; RV32I-NEXT: xor t0, ra, t1
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: lw a1, 728(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: lw a1, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t1, a1, s3
; RV32I-NEXT: xor a2, a2, t1
-; RV32I-NEXT: lw a5, 720(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, s0
+; RV32I-NEXT: lw a1, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t1, a1, s1
; RV32I-NEXT: xor a2, a2, t1
-; RV32I-NEXT: lw a5, 712(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, t6
+; RV32I-NEXT: lw a1, 708(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t1, a1, s0
; RV32I-NEXT: xor a2, a2, t1
-; RV32I-NEXT: lw a5, 708(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, t5
+; RV32I-NEXT: lw a1, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t1, a1, t6
; RV32I-NEXT: xor a2, a2, t1
-; RV32I-NEXT: lw a5, 704(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t0, a5, t0
-; RV32I-NEXT: xor a2, a2, t0
-; RV32I-NEXT: lw a5, 696(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, a5, a7
-; RV32I-NEXT: xor a2, a2, a7
-; RV32I-NEXT: lw a5, 772(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a7, a5, 1
-; RV32I-NEXT: xor a0, a7, a0
+; RV32I-NEXT: lw a1, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a6, a1, a6
+; RV32I-NEXT: xor a2, a2, a6
+; RV32I-NEXT: lw a1, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a1, a5
+; RV32I-NEXT: xor a2, a2, a5
+; RV32I-NEXT: lw a5, 768(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a5, a5, 1
+; RV32I-NEXT: xor a5, a5, t0
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: lw a1, 672(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a1, t3
+; RV32I-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: lw a2, 816(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, t5
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 676(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a2, t3
-; RV32I-NEXT: lw a5, 672(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a3, 820(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, a4
-; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: srli a3, a0, 8
-; RV32I-NEXT: lw a5, 652(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, a5
+; RV32I-NEXT: srli a2, a5, 8
+; RV32I-NEXT: lw a6, 652(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, a6
+; RV32I-NEXT: srli a3, a5, 24
+; RV32I-NEXT: or a2, a2, a3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: slli a1, a5, 24
+; RV32I-NEXT: and a3, a5, a6
+; RV32I-NEXT: slli a3, a3, 8
+; RV32I-NEXT: srli a4, a0, 8
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: and a3, a4, a6
; RV32I-NEXT: srli a4, a0, 24
-; RV32I-NEXT: or a3, a3, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: slli a2, a0, 24
-; RV32I-NEXT: and a0, a0, a5
-; RV32I-NEXT: slli a0, a0, 8
-; RV32I-NEXT: srli a4, a1, 8
-; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: and a2, a4, a5
-; RV32I-NEXT: srli a4, a1, 24
-; RV32I-NEXT: and a5, a1, a5
-; RV32I-NEXT: slli a1, a1, 24
+; RV32I-NEXT: and a5, a0, a6
+; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: slli a5, a5, 8
-; RV32I-NEXT: or a2, a2, a4
-; RV32I-NEXT: or a1, a1, a5
-; RV32I-NEXT: or a0, a0, a3
+; RV32I-NEXT: or a3, a3, a4
+; RV32I-NEXT: or a0, a0, a5
; RV32I-NEXT: or a1, a1, a2
-; RV32I-NEXT: srli a2, a0, 4
-; RV32I-NEXT: mv s5, s11
-; RV32I-NEXT: and a0, a0, s11
-; RV32I-NEXT: and a2, a2, s11
-; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: srli a3, a1, 4
-; RV32I-NEXT: and a1, a1, s11
-; RV32I-NEXT: and a3, a3, s11
+; RV32I-NEXT: or a0, a0, a3
+; RV32I-NEXT: srli a2, a1, 4
+; RV32I-NEXT: lw a4, 288(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: slli a1, a1, 4
-; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: or a1, a3, a1
-; RV32I-NEXT: srli a2, a0, 2
-; RV32I-NEXT: lw a4, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a3, a0, 4
; RV32I-NEXT: and a0, a0, a4
-; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: srli a3, a1, 2
-; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or a1, a2, a1
+; RV32I-NEXT: or a0, a3, a0
+; RV32I-NEXT: srli a2, a1, 2
+; RV32I-NEXT: lw a4, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: or a3, a3, a1
-; RV32I-NEXT: sw a3, 268(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a1, a0, 1
+; RV32I-NEXT: srli a3, a0, 2
+; RV32I-NEXT: and a0, a0, a4
+; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a1, a2, a1
+; RV32I-NEXT: or a3, a3, a0
+; RV32I-NEXT: sw a3, 264(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: lw a2, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: lw a2, 700(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: lw a2, 696(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a3, 1
-; RV32I-NEXT: sw a1, 264(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 260(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: slli a1, a1, 31
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: sw a0, 208(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, a6, 2
+; RV32I-NEXT: sw a0, 204(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, a7, 2
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, a6, 1
+; RV32I-NEXT: andi a1, a7, 1
; RV32I-NEXT: addi a2, a0, -1
-; RV32I-NEXT: sw a2, 760(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 768(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a0, a1
; RV32I-NEXT: addi a1, a0, -1
-; RV32I-NEXT: sw a1, 756(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 764(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, s4, 1
-; RV32I-NEXT: sw a0, 244(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 240(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: andi a1, a6, 4
+; RV32I-NEXT: andi a1, a7, 4
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: andi a2, a6, 8
+; RV32I-NEXT: andi a2, a7, 8
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 744(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 752(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a2
; RV32I-NEXT: addi a2, a1, -1
-; RV32I-NEXT: sw a2, 740(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 748(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, s4, 2
-; RV32I-NEXT: sw a1, 240(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 236(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: slli a3, s4, 3
-; RV32I-NEXT: sw a3, 248(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 244(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: andi a3, a6, 16
+; RV32I-NEXT: andi a3, a7, 16
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 300(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a2, a6, 32
+; RV32I-NEXT: sw a4, 740(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a2, a7, 32
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: andi a3, a6, 64
+; RV32I-NEXT: andi a3, a7, 64
; RV32I-NEXT: addi a5, a2, -1
-; RV32I-NEXT: sw a5, 728(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 732(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: addi a7, a2, -1
-; RV32I-NEXT: sw a7, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a6, a2, -1
+; RV32I-NEXT: sw a6, 724(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a2, s4, 4
-; RV32I-NEXT: sw a2, 216(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 212(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: slli a3, s4, 5
-; RV32I-NEXT: sw a3, 232(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 228(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: slli a4, s4, 6
-; RV32I-NEXT: sw a4, 236(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 232(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, a7, a4
+; RV32I-NEXT: and a3, a6, a4
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: andi a1, a6, 128
+; RV32I-NEXT: andi a1, a7, 128
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: andi a2, a6, 256
+; RV32I-NEXT: andi a2, a7, 256
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 712(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 716(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a2
; RV32I-NEXT: addi a2, a1, -1
-; RV32I-NEXT: sw a2, 708(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 712(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, s4, 7
-; RV32I-NEXT: sw a1, 224(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 220(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: slli a3, s4, 8
-; RV32I-NEXT: sw a3, 220(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 216(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: andi a3, a6, 512
+; RV32I-NEXT: andi a3, a7, 512
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 704(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 708(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, s4, 9
-; RV32I-NEXT: sw a3, 228(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 224(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: andi a3, a6, 1024
+; RV32I-NEXT: andi a3, a7, 1024
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 824(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 704(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, s4, 10
-; RV32I-NEXT: sw a3, 212(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 208(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: lw s11, 288(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a6, s11
+; RV32I-NEXT: lw a5, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a7, a5
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 820(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a2, 1
-; RV32I-NEXT: and a2, a6, a2
+; RV32I-NEXT: sw a4, 700(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s6, 1
+; RV32I-NEXT: and a2, a7, s6
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: lui s8, 2
-; RV32I-NEXT: and a3, a6, s8
-; RV32I-NEXT: addi a7, a2, -1
-; RV32I-NEXT: sw a7, 816(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t1, 2
+; RV32I-NEXT: and a3, a7, t1
+; RV32I-NEXT: addi a6, a2, -1
+; RV32I-NEXT: sw a6, 824(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: addi t1, a2, -1
-; RV32I-NEXT: sw t1, 812(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t2, a2, -1
+; RV32I-NEXT: sw t2, 820(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a2, s4, 11
-; RV32I-NEXT: sw a2, 184(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 180(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: slli a3, s4, 12
-; RV32I-NEXT: sw a3, 200(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a7, a3
+; RV32I-NEXT: sw a3, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a6, a3
; RV32I-NEXT: slli a4, s4, 13
-; RV32I-NEXT: sw a4, 204(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 200(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, t1, a4
+; RV32I-NEXT: and a3, t2, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: lui a3, 4
-; RV32I-NEXT: and a3, a6, a3
+; RV32I-NEXT: and a3, a7, a3
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: lui t6, 8
-; RV32I-NEXT: and a4, a6, t6
-; RV32I-NEXT: addi a7, a3, -1
-; RV32I-NEXT: sw a7, 808(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t3, 8
+; RV32I-NEXT: and a4, a7, t3
+; RV32I-NEXT: addi a6, a3, -1
+; RV32I-NEXT: sw a6, 816(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a4, a3, -1
-; RV32I-NEXT: sw a4, 804(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 812(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, s4, 14
-; RV32I-NEXT: sw a3, 192(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a7, a3
-; RV32I-NEXT: slli a5, s4, 15
-; RV32I-NEXT: sw a5, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a6, a3
+; RV32I-NEXT: slli a6, s4, 15
+; RV32I-NEXT: sw a6, 192(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, a4, a5
+; RV32I-NEXT: and a3, a4, a6
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lui s1, 16
-; RV32I-NEXT: and a1, a6, s1
-; RV32I-NEXT: lui t3, 32
-; RV32I-NEXT: and a3, a6, t3
+; RV32I-NEXT: lui s0, 16
+; RV32I-NEXT: and a1, a7, s0
+; RV32I-NEXT: lui t5, 32
+; RV32I-NEXT: and a3, a7, t5
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: sw a1, 800(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 808(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: sw a3, 796(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, s4, 16
-; RV32I-NEXT: sw a5, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 804(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, s4, 16
+; RV32I-NEXT: sw a6, 172(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a4, s4, 17
-; RV32I-NEXT: sw a4, 188(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, a1, a5
+; RV32I-NEXT: sw a4, 184(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lui t5, 64
-; RV32I-NEXT: and a3, a6, t5
+; RV32I-NEXT: lui s1, 64
+; RV32I-NEXT: and a3, a7, s1
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: lui s3, 128
-; RV32I-NEXT: and a4, a6, s3
-; RV32I-NEXT: addi t2, a3, -1
-; RV32I-NEXT: sw t2, 792(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s2, 128
+; RV32I-NEXT: and a4, a7, s2
+; RV32I-NEXT: addi t6, a3, -1
+; RV32I-NEXT: sw t6, 800(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a4, a3, -1
-; RV32I-NEXT: sw a4, 788(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 796(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, s4, 18
-; RV32I-NEXT: sw a3, 164(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, t2, a3
-; RV32I-NEXT: slli a5, s4, 19
-; RV32I-NEXT: sw a5, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 160(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, t6, a3
+; RV32I-NEXT: slli a6, s4, 19
+; RV32I-NEXT: sw a6, 176(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, a4, a5
+; RV32I-NEXT: and a3, a4, a6
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lui s2, 256
-; RV32I-NEXT: and a3, a6, s2
+; RV32I-NEXT: lui s3, 256
+; RV32I-NEXT: and a3, a7, s3
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: lui t1, 512
-; RV32I-NEXT: and a4, a6, t1
-; RV32I-NEXT: addi t2, a3, -1
-; RV32I-NEXT: sw t2, 784(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t0, 512
+; RV32I-NEXT: and a4, a7, t0
+; RV32I-NEXT: addi t6, a3, -1
+; RV32I-NEXT: sw t6, 792(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a4, a3, -1
-; RV32I-NEXT: sw a4, 780(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 788(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, s4, 20
-; RV32I-NEXT: sw a3, 152(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, t2, a3
-; RV32I-NEXT: slli a5, s4, 21
-; RV32I-NEXT: sw a5, 172(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 148(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, t6, a3
+; RV32I-NEXT: slli a6, s4, 21
+; RV32I-NEXT: sw a6, 168(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, a4, a5
+; RV32I-NEXT: and a3, a4, a6
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: xor a5, a0, a1
-; RV32I-NEXT: lui t0, 1024
-; RV32I-NEXT: and a1, a6, t0
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: lui s9, 1024
+; RV32I-NEXT: and a1, a7, s9
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: lui ra, 2048
-; RV32I-NEXT: and a2, a6, ra
+; RV32I-NEXT: lui s11, 2048
+; RV32I-NEXT: and a2, a7, s11
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 776(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 784(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a2
; RV32I-NEXT: addi a2, a1, -1
-; RV32I-NEXT: sw a2, 772(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 780(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, s4, 22
-; RV32I-NEXT: sw a1, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a3, a1
-; RV32I-NEXT: slli a0, s4, 23
-; RV32I-NEXT: sw a0, 168(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: lui a7, 4096
-; RV32I-NEXT: and a3, a6, a7
+; RV32I-NEXT: slli a3, s4, 23
+; RV32I-NEXT: sw a3, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: lui ra, 4096
+; RV32I-NEXT: and a3, a7, ra
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 768(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s9, s4, 24
-; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: sw s9, 136(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 776(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s10, s4, 24
+; RV32I-NEXT: and a2, a2, s10
+; RV32I-NEXT: sw s10, 132(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui t2, 8192
-; RV32I-NEXT: and a3, a6, t2
+; RV32I-NEXT: and a3, a7, t2
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 764(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, s4, 25
-; RV32I-NEXT: sw a0, 160(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: lui s0, 16384
-; RV32I-NEXT: and a3, a6, s0
+; RV32I-NEXT: sw a2, 772(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 25
+; RV32I-NEXT: sw a3, 156(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: lui a6, 16384
+; RV32I-NEXT: and a3, a7, a6
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 752(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, s4, 26
-; RV32I-NEXT: sw a0, 148(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: lui a0, 32768
-; RV32I-NEXT: and a3, a6, a0
+; RV32I-NEXT: sw a2, 760(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 26
+; RV32I-NEXT: sw a3, 144(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: lui a3, 32768
+; RV32I-NEXT: and a3, a7, a3
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 748(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, s4, 27
-; RV32I-NEXT: sw a0, 156(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: lui s7, 65536
-; RV32I-NEXT: and a3, a6, s7
+; RV32I-NEXT: sw a2, 756(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 27
+; RV32I-NEXT: sw a3, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: lui s5, 65536
+; RV32I-NEXT: and a3, a7, s5
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 736(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, s4, 28
-; RV32I-NEXT: sw a0, 144(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: lui a0, 131072
-; RV32I-NEXT: and a3, a6, a0
+; RV32I-NEXT: sw a2, 744(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 28
+; RV32I-NEXT: sw a3, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: lui a3, 131072
+; RV32I-NEXT: and a3, a7, a3
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: addi a0, a2, -1
-; RV32I-NEXT: sw a0, 732(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a4, a2, -1
+; RV32I-NEXT: sw a4, 736(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a2, 262144
-; RV32I-NEXT: and a2, a6, a2
+; RV32I-NEXT: and a2, a7, a2
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: srli a3, a6, 31
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 724(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a3, a7, 31
+; RV32I-NEXT: addi a7, a2, -1
+; RV32I-NEXT: sw a7, 728(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 716(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, s4, 29
-; RV32I-NEXT: sw a3, 256(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a0, a3
+; RV32I-NEXT: addi t6, a2, -1
+; RV32I-NEXT: sw t6, 720(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, s4, 29
+; RV32I-NEXT: sw a2, 252(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: slli a3, s4, 30
-; RV32I-NEXT: sw a3, 252(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a4, a3
-; RV32I-NEXT: slli a6, s4, 31
-; RV32I-NEXT: sw a6, 260(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a4, a0, a3
-; RV32I-NEXT: and a3, a2, a6
-; RV32I-NEXT: xor a0, a5, a1
-; RV32I-NEXT: xor a2, a4, a3
-; RV32I-NEXT: xor s10, a0, a2
-; RV32I-NEXT: andi a0, s6, 2
+; RV32I-NEXT: sw a3, 248(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a7, a3
+; RV32I-NEXT: slli a4, s4, 31
+; RV32I-NEXT: sw a4, 256(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: and a3, t6, a4
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: xor s8, a0, a2
+; RV32I-NEXT: andi a0, s7, 2
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s6, 1
+; RV32I-NEXT: andi a1, s7, 1
; RV32I-NEXT: addi a3, a0, -1
-; RV32I-NEXT: sw a3, 124(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 120(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a0, a1
; RV32I-NEXT: addi a1, a0, -1
-; RV32I-NEXT: sw a1, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 116(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, t4, 1
; RV32I-NEXT: sw a0, 380(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a3, a0
; RV32I-NEXT: and a1, a1, t4
; RV32I-NEXT: xor a2, a1, a0
-; RV32I-NEXT: andi a1, s6, 4
+; RV32I-NEXT: andi a1, s7, 4
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: andi a3, s6, 8
+; RV32I-NEXT: andi a3, s7, 8
; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 116(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 112(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a3
-; RV32I-NEXT: addi a5, a1, -1
-; RV32I-NEXT: sw a5, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a7, a1, -1
+; RV32I-NEXT: sw a7, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, t4, 2
; RV32I-NEXT: sw a1, 376(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a4, a1
; RV32I-NEXT: slli a3, t4, 3
; RV32I-NEXT: sw a3, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: andi a4, s6, 16
+; RV32I-NEXT: and a3, a7, a3
+; RV32I-NEXT: andi a4, s7, 16
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
-; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 108(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a3, s6, 32
+; RV32I-NEXT: addi a7, a3, -1
+; RV32I-NEXT: sw a7, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a3, s7, 32
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: andi a4, s6, 64
+; RV32I-NEXT: andi a4, s7, 64
; RV32I-NEXT: addi a0, a3, -1
; RV32I-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
-; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t6, a3, -1
+; RV32I-NEXT: sw t6, 100(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, t4, 4
; RV32I-NEXT: sw a3, 368(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a5, a3
+; RV32I-NEXT: and a3, a7, a3
; RV32I-NEXT: slli a4, t4, 5
; RV32I-NEXT: sw a4, 364(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a0, a4
-; RV32I-NEXT: slli a5, t4, 6
-; RV32I-NEXT: sw a5, 360(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, t4, 6
+; RV32I-NEXT: sw a7, 360(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: and a4, t6, a7
; RV32I-NEXT: xor a0, a2, a1
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a0, a0, a3
-; RV32I-NEXT: andi a1, s6, 128
+; RV32I-NEXT: andi a1, s7, 128
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: andi a3, s6, 256
+; RV32I-NEXT: andi a3, s7, 256
; RV32I-NEXT: addi a2, a1, -1
; RV32I-NEXT: sw a2, 92(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a3
@@ -17286,7 +17294,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: slli a3, t4, 8
; RV32I-NEXT: sw a3, 352(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a4, a3
-; RV32I-NEXT: andi a4, s6, 512
+; RV32I-NEXT: andi a4, s7, 512
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a2, a3, -1
@@ -17294,7 +17302,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: slli a3, t4, 9
; RV32I-NEXT: sw a3, 348(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a2, a3
-; RV32I-NEXT: andi a4, s6, 1024
+; RV32I-NEXT: andi a4, s7, 1024
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a2, a3, -1
@@ -17302,765 +17310,766 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: slli a3, t4, 10
; RV32I-NEXT: sw a3, 344(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a2, a3
-; RV32I-NEXT: and a4, s6, s11
+; RV32I-NEXT: and a4, s7, a5
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a2, a3, -1
; RV32I-NEXT: sw a2, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a3, 1
-; RV32I-NEXT: and a3, s6, a3
+; RV32I-NEXT: and a3, s7, s6
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: and a4, s6, s8
+; RV32I-NEXT: and a4, s7, t1
; RV32I-NEXT: addi a5, a3, -1
; RV32I-NEXT: sw a5, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
-; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a7, a3, -1
+; RV32I-NEXT: sw a7, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, t4, 11
; RV32I-NEXT: sw a3, 340(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a2, a3
; RV32I-NEXT: slli a4, t4, 12
-; RV32I-NEXT: sw a4, 696(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 336(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: slli a5, t4, 13
-; RV32I-NEXT: sw a5, 336(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 332(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: and a4, a7, a5
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: lui a2, 4
-; RV32I-NEXT: and a4, s6, a2
+; RV32I-NEXT: and a4, s7, a2
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, s6, t6
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, s7, t3
+; RV32I-NEXT: addi a7, a4, -1
+; RV32I-NEXT: sw a7, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a2, a4, -1
; RV32I-NEXT: sw a2, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a4, t4, 14
-; RV32I-NEXT: sw a4, 332(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: sw a4, 328(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a7, a4
; RV32I-NEXT: slli a5, t4, 15
-; RV32I-NEXT: sw a5, 328(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 324(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: and a4, a2, a5
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a0, a0, a3
-; RV32I-NEXT: and a1, s6, s1
-; RV32I-NEXT: seqz s1, a1
-; RV32I-NEXT: and a1, s6, t3
-; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: and a1, s7, s0
+; RV32I-NEXT: seqz s0, a1
+; RV32I-NEXT: and a1, s7, t5
+; RV32I-NEXT: addi s0, s0, -1
; RV32I-NEXT: seqz t6, a1
; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a1, t4, 16
-; RV32I-NEXT: sw a1, 324(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, s1, a1
+; RV32I-NEXT: sw a1, 320(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a1, s0, a1
; RV32I-NEXT: slli a3, t4, 17
-; RV32I-NEXT: sw a3, 320(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 692(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, t6, a3
-; RV32I-NEXT: and a4, s6, t5
+; RV32I-NEXT: and a4, s7, s1
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz t5, a4
; RV32I-NEXT: addi t5, t5, -1
; RV32I-NEXT: slli a3, t4, 18
-; RV32I-NEXT: sw a3, 316(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 688(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, t5, a3
-; RV32I-NEXT: and a4, s6, s3
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: seqz s3, a4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: sw s3, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t4, 19
-; RV32I-NEXT: sw a3, 312(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, s3, a3
-; RV32I-NEXT: and a4, s6, s2
+; RV32I-NEXT: and a4, s7, s2
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz t3, a4
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: slli a3, t4, 20
-; RV32I-NEXT: sw a3, 692(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, t4, 19
+; RV32I-NEXT: sw a3, 316(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, t3, a3
-; RV32I-NEXT: and a4, s6, t1
+; RV32I-NEXT: and a4, s7, s3
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz t1, a4
; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: slli a3, t4, 21
-; RV32I-NEXT: sw a3, 688(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, t4, 20
+; RV32I-NEXT: sw a3, 684(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, t1, a3
-; RV32I-NEXT: and a4, s6, t0
+; RV32I-NEXT: and a4, s7, t0
+; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: seqz t0, a4
+; RV32I-NEXT: addi t0, t0, -1
+; RV32I-NEXT: slli a3, t4, 21
+; RV32I-NEXT: sw a3, 312(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, t0, a3
+; RV32I-NEXT: and a4, s7, s9
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a3, -1
; RV32I-NEXT: sw a2, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, s6, ra
-; RV32I-NEXT: and a3, s6, a7
-; RV32I-NEXT: seqz a7, a1
-; RV32I-NEXT: seqz t0, a3
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: addi t0, t0, -1
+; RV32I-NEXT: and a1, s7, s11
+; RV32I-NEXT: and a3, s7, ra
+; RV32I-NEXT: seqz a4, a1
+; RV32I-NEXT: seqz a5, a3
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: slli a1, t4, 22
; RV32I-NEXT: sw a1, 308(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t4, 23
-; RV32I-NEXT: sw a4, 684(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, t4, 23
+; RV32I-NEXT: sw a7, 680(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a2, a1
-; RV32I-NEXT: and a3, a7, a4
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw ra, 296(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, t0, ra
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, s6, t2
-; RV32I-NEXT: seqz a5, a3
-; RV32I-NEXT: and a3, s6, s0
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a4, a3
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: sw a4, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t4, 25
-; RV32I-NEXT: sw a3, 304(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: slli a6, t4, 26
-; RV32I-NEXT: sw a6, 680(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a4, a7
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, a4, a6
+; RV32I-NEXT: lw s11, 296(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a5, s11
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lui a2, 32768
-; RV32I-NEXT: and a3, s6, a2
-; RV32I-NEXT: seqz s2, a3
-; RV32I-NEXT: and a3, s6, s7
+; RV32I-NEXT: and a3, s7, t2
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: and a6, s7, a6
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: sw a3, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz s2, a6
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: sw s2, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz s0, a3
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: sw s0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, t4, 27
-; RV32I-NEXT: sw a3, 676(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, s2, a3
-; RV32I-NEXT: slli a6, t4, 28
-; RV32I-NEXT: sw a6, 672(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, s0, a6
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: sw s4, 132(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a3, s4, 8
-; RV32I-NEXT: lw a5, 652(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, a5
-; RV32I-NEXT: and a6, s4, a5
-; RV32I-NEXT: slli a6, a6, 8
+; RV32I-NEXT: sw s2, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, t4, 25
+; RV32I-NEXT: sw a6, 304(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a3, a6
+; RV32I-NEXT: slli a7, t4, 26
+; RV32I-NEXT: sw a7, 300(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a1, a1, a6
+; RV32I-NEXT: and a6, s2, a7
+; RV32I-NEXT: xor a1, a1, a6
+; RV32I-NEXT: lui a2, 32768
+; RV32I-NEXT: and a6, s7, a2
+; RV32I-NEXT: seqz s3, a6
+; RV32I-NEXT: and a6, s7, s5
+; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz s1, a6
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: sw s1, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, t4, 27
+; RV32I-NEXT: sw a6, 676(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, s3, a6
+; RV32I-NEXT: slli a7, t4, 28
+; RV32I-NEXT: sw a7, 672(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a1, a1, a6
+; RV32I-NEXT: and a6, s1, a7
+; RV32I-NEXT: xor a1, a1, a6
+; RV32I-NEXT: sw s4, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a6, s4, 8
+; RV32I-NEXT: lw a3, 652(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a6, a6, a3
+; RV32I-NEXT: and a7, s4, a3
+; RV32I-NEXT: slli a7, a7, 8
; RV32I-NEXT: srli t2, s4, 24
-; RV32I-NEXT: or a3, a3, t2
-; RV32I-NEXT: or a6, s9, a6
+; RV32I-NEXT: or a6, a6, t2
+; RV32I-NEXT: or a7, s10, a7
; RV32I-NEXT: xor s4, a0, a1
-; RV32I-NEXT: or a0, a6, a3
+; RV32I-NEXT: or a0, a7, a6
; RV32I-NEXT: lui a1, 131072
-; RV32I-NEXT: and a1, s6, a1
+; RV32I-NEXT: and a1, s7, a1
; RV32I-NEXT: lui a2, 262144
-; RV32I-NEXT: and a3, s6, a2
+; RV32I-NEXT: and a6, s7, a2
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: seqz t2, a3
-; RV32I-NEXT: addi s3, a1, -1
-; RV32I-NEXT: addi s11, t2, -1
+; RV32I-NEXT: seqz t2, a6
+; RV32I-NEXT: addi s2, a1, -1
+; RV32I-NEXT: addi s3, t2, -1
+; RV32I-NEXT: mv s1, t4
+; RV32I-NEXT: slli a1, t4, 29
+; RV32I-NEXT: sw a1, 668(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, t4, 30
+; RV32I-NEXT: sw a7, 664(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a1, s2, a1
+; RV32I-NEXT: and a7, s3, a7
+; RV32I-NEXT: xor a7, a1, a7
; RV32I-NEXT: srli a1, a0, 4
-; RV32I-NEXT: and a0, a0, s5
-; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: lw a4, 288(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: mv s2, t4
-; RV32I-NEXT: slli a3, t4, 29
-; RV32I-NEXT: sw a3, 668(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, t4, 30
-; RV32I-NEXT: sw t2, 664(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, s3, a3
-; RV32I-NEXT: and s7, s11, t2
-; RV32I-NEXT: xor a6, a6, s7
+; RV32I-NEXT: srli s5, s7, 31
; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: srli a1, a0, 2
+; RV32I-NEXT: seqz a1, s5
+; RV32I-NEXT: srli s5, a0, 2
; RV32I-NEXT: lw t2, 648(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a0, t2
-; RV32I-NEXT: and a1, a1, t2
+; RV32I-NEXT: and s5, s5, t2
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: or a1, a1, a0
-; RV32I-NEXT: srli a0, s6, 31
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: srli s7, a1, 1
-; RV32I-NEXT: addi s0, a0, -1
-; RV32I-NEXT: lw a4, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a4
-; RV32I-NEXT: and a1, a1, a4
-; RV32I-NEXT: slli a0, t4, 31
-; RV32I-NEXT: sw t4, 292(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw a0, 660(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: and s8, s0, a0
-; RV32I-NEXT: xor a6, a6, s8
-; RV32I-NEXT: or a1, s7, a1
-; RV32I-NEXT: xor a6, s4, a6
-; RV32I-NEXT: slli s4, a1, 1
-; RV32I-NEXT: lw a0, 524(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: lw a0, 520(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, a1
-; RV32I-NEXT: xor a2, a6, s10
-; RV32I-NEXT: xor a6, s7, s4
-; RV32I-NEXT: slli s4, a1, 2
-; RV32I-NEXT: slli s7, a1, 3
-; RV32I-NEXT: lw a0, 516(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: lw a0, 512(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: slli s7, a1, 4
-; RV32I-NEXT: lw a0, 500(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
-; RV32I-NEXT: slli s8, a1, 5
-; RV32I-NEXT: lw a0, 496(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, a0, s8
-; RV32I-NEXT: slli s10, a1, 6
-; RV32I-NEXT: xor s7, s7, s8
-; RV32I-NEXT: lw a0, 492(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, a0, s10
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: xor s4, s7, s8
-; RV32I-NEXT: lw a0, 208(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: sw a0, 208(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a2, a6, s4
-; RV32I-NEXT: slli a6, a1, 7
-; RV32I-NEXT: slli s4, a1, 8
-; RV32I-NEXT: lw a0, 488(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a0, a6
-; RV32I-NEXT: lw a0, 484(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: slli s4, a1, 9
-; RV32I-NEXT: lw a0, 480(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: slli s7, a1, 10
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: lw a0, 476(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s7
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: slli s4, a1, 11
-; RV32I-NEXT: lw a0, 468(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: slli s7, a1, 12
-; RV32I-NEXT: lw a0, 464(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
-; RV32I-NEXT: slli s8, a1, 13
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 460(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s8
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: slli s7, a1, 14
-; RV32I-NEXT: lw a0, 456(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
-; RV32I-NEXT: slli s8, a1, 15
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 452(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s8
-; RV32I-NEXT: xor a2, a2, a6
-; RV32I-NEXT: xor a6, s4, s7
-; RV32I-NEXT: slli s4, a1, 16
-; RV32I-NEXT: slli s7, a1, 17
-; RV32I-NEXT: lw a0, 448(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: lw a0, 444(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: slli s7, a1, 18
-; RV32I-NEXT: lw a0, 440(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
-; RV32I-NEXT: slli s8, a1, 19
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 436(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s8
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: slli s7, a1, 20
-; RV32I-NEXT: lw a0, 432(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
-; RV32I-NEXT: slli s8, a1, 21
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 428(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s8
-; RV32I-NEXT: xor a2, a2, a6
-; RV32I-NEXT: xor a6, s4, s7
-; RV32I-NEXT: xor a2, a2, a6
-; RV32I-NEXT: slli a6, a1, 22
-; RV32I-NEXT: lw a0, 424(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a0, a6
-; RV32I-NEXT: slli s4, a1, 23
-; RV32I-NEXT: lw a0, 420(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: slli s7, a1, 24
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: lw a0, 416(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s7
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: slli s4, a1, 25
-; RV32I-NEXT: lw a0, 412(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: slli s7, a1, 26
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: lw a0, 408(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s7
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: slli s4, a1, 27
-; RV32I-NEXT: lw a0, 404(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: slli s7, a1, 28
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: lw a0, 400(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s7
-; RV32I-NEXT: xor a6, a6, s4
-; RV32I-NEXT: slli s4, a1, 29
-; RV32I-NEXT: lw a0, 396(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a0, s4
-; RV32I-NEXT: slli s7, a1, 30
-; RV32I-NEXT: lw a0, 388(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
+; RV32I-NEXT: or s5, s5, a0
+; RV32I-NEXT: addi a6, a1, -1
+; RV32I-NEXT: srli a1, s5, 1
+; RV32I-NEXT: lw a0, 656(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, a0
+; RV32I-NEXT: slli s5, s5, 1
+; RV32I-NEXT: slli t4, t4, 31
+; RV32I-NEXT: sw s1, 292(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t4, 660(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s6, a6, t4
+; RV32I-NEXT: and s9, a1, a0
+; RV32I-NEXT: xor a7, a7, s6
+; RV32I-NEXT: or s6, s9, s5
+; RV32I-NEXT: xor a7, s4, a7
+; RV32I-NEXT: slli s4, s6, 1
+; RV32I-NEXT: lw s5, 524(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: lw s5, 520(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: xor a2, a7, s8
+; RV32I-NEXT: xor a7, s5, s4
+; RV32I-NEXT: slli s4, s6, 2
+; RV32I-NEXT: slli s5, s6, 3
+; RV32I-NEXT: lw s9, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s9, s4
+; RV32I-NEXT: lw s9, 512(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: slli s5, s6, 4
+; RV32I-NEXT: lw s9, 500(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: slli s9, s6, 5
+; RV32I-NEXT: lw ra, 496(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, ra, s9
+; RV32I-NEXT: slli ra, s6, 6
+; RV32I-NEXT: xor s5, s5, s9
+; RV32I-NEXT: lw s9, 492(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, s9, ra
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: xor s4, s5, s9
+; RV32I-NEXT: lw t4, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, t4, a2
+; RV32I-NEXT: sw a2, 204(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a2, a7, s4
+; RV32I-NEXT: slli a7, s6, 7
+; RV32I-NEXT: slli s4, s6, 8
+; RV32I-NEXT: lw s5, 488(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, s5, a7
+; RV32I-NEXT: lw s5, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: slli s4, s6, 9
+; RV32I-NEXT: lw s5, 480(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: slli s5, s6, 10
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 476(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: slli s4, s6, 11
+; RV32I-NEXT: lw s5, 468(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: slli s5, s6, 12
+; RV32I-NEXT: lw s9, 464(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: slli s9, s6, 13
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, s9
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: slli s5, s6, 14
+; RV32I-NEXT: lw s9, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: slli s9, s6, 15
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, s9
+; RV32I-NEXT: xor a2, a2, a7
+; RV32I-NEXT: xor a7, s4, s5
+; RV32I-NEXT: slli s4, s6, 16
+; RV32I-NEXT: slli s5, s6, 17
+; RV32I-NEXT: lw s9, 448(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s9, s4
+; RV32I-NEXT: lw s9, 444(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: slli s5, s6, 18
+; RV32I-NEXT: lw s9, 440(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: slli s9, s6, 19
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 436(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, s9
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: slli s5, s6, 20
+; RV32I-NEXT: lw s9, 432(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: slli s9, s6, 21
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 428(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, s9
+; RV32I-NEXT: xor a2, a2, a7
+; RV32I-NEXT: xor a7, s4, s5
+; RV32I-NEXT: xor a2, a2, a7
+; RV32I-NEXT: slli a7, s6, 22
+; RV32I-NEXT: lw s4, 424(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, s4, a7
+; RV32I-NEXT: slli s4, s6, 23
+; RV32I-NEXT: lw s5, 420(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: slli s5, s6, 24
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 416(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: slli s4, s6, 25
+; RV32I-NEXT: lw s5, 412(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: slli s5, s6, 26
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 408(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: slli s4, s6, 27
+; RV32I-NEXT: lw s5, 404(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: slli s5, s6, 28
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: lw s4, 400(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: xor a7, a7, s4
+; RV32I-NEXT: slli s4, s6, 29
+; RV32I-NEXT: lw t4, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, t4, s4
+; RV32I-NEXT: slli s6, s6, 30
+; RV32I-NEXT: lw t4, 388(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, t4, s6
; RV32I-NEXT: slli a1, a1, 31
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 392(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a0, a1
-; RV32I-NEXT: xor a2, a2, a6
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw t4, 396(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, t4, a1
+; RV32I-NEXT: xor a2, a2, a7
; RV32I-NEXT: xor a1, s4, a1
; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: srli a2, s6, 8
-; RV32I-NEXT: and a2, a2, a5
-; RV32I-NEXT: srli a6, s6, 24
-; RV32I-NEXT: or a2, a2, a6
-; RV32I-NEXT: and a6, s6, a5
-; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: slli t4, s6, 24
-; RV32I-NEXT: or a6, t4, a6
+; RV32I-NEXT: srli a2, s7, 8
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: srli a7, s7, 24
+; RV32I-NEXT: or a2, a2, a7
+; RV32I-NEXT: and a7, s7, a3
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t4, s7, 24
+; RV32I-NEXT: or a7, t4, a7
; RV32I-NEXT: srli t4, a1, 8
-; RV32I-NEXT: and t4, t4, a5
+; RV32I-NEXT: and t4, t4, a3
; RV32I-NEXT: srli s4, a1, 24
; RV32I-NEXT: or t4, t4, s4
-; RV32I-NEXT: or a2, a6, a2
-; RV32I-NEXT: srli a6, a2, 4
-; RV32I-NEXT: and a2, a2, s5
-; RV32I-NEXT: and a6, a6, s5
+; RV32I-NEXT: or a2, a7, a2
+; RV32I-NEXT: srli a7, a2, 4
+; RV32I-NEXT: mv s7, a4
+; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: and a7, a7, a4
; RV32I-NEXT: slli a2, a2, 4
-; RV32I-NEXT: or a2, a6, a2
-; RV32I-NEXT: and a6, a1, a5
+; RV32I-NEXT: or a2, a7, a2
+; RV32I-NEXT: and a7, a1, a3
; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: slli a6, a6, 8
+; RV32I-NEXT: slli a7, a7, 8
; RV32I-NEXT: srli s4, a2, 2
+; RV32I-NEXT: mv s8, t2
; RV32I-NEXT: and a2, a2, t2
; RV32I-NEXT: and s4, s4, t2
-; RV32I-NEXT: mv s9, t2
; RV32I-NEXT: slli a2, a2, 2
-; RV32I-NEXT: or a1, a1, a6
+; RV32I-NEXT: or a1, a1, a7
; RV32I-NEXT: or a2, s4, a2
-; RV32I-NEXT: srli a6, a2, 1
-; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: and a6, a6, a4
+; RV32I-NEXT: srli a7, a2, 1
+; RV32I-NEXT: mv a4, a0
+; RV32I-NEXT: and a2, a2, a0
+; RV32I-NEXT: and a7, a7, a0
; RV32I-NEXT: slli a2, a2, 1
; RV32I-NEXT: or a1, a1, t4
-; RV32I-NEXT: or s8, a6, a2
-; RV32I-NEXT: andi a6, s8, 2
-; RV32I-NEXT: andi t4, s8, 1
-; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: or s9, a7, a2
+; RV32I-NEXT: andi a7, s9, 2
+; RV32I-NEXT: andi t4, s9, 1
+; RV32I-NEXT: seqz a7, a7
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: addi a7, a7, -1
; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: lw s4, 640(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, s4
-; RV32I-NEXT: lw a0, 384(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, t4, a0
-; RV32I-NEXT: xor a6, t4, a6
-; RV32I-NEXT: andi t4, s8, 4
+; RV32I-NEXT: and a7, a7, s4
+; RV32I-NEXT: lw s4, 384(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t4, t4, s4
+; RV32I-NEXT: xor a7, t4, a7
+; RV32I-NEXT: andi t4, s9, 4
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: andi s4, s8, 8
+; RV32I-NEXT: andi s4, s9, 8
; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: lw s7, 636(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, t4, s7
+; RV32I-NEXT: lw s5, 636(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t4, t4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lw s7, 632(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, s7
-; RV32I-NEXT: andi s7, s8, 16
+; RV32I-NEXT: lw s5, 632(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: andi s5, s9, 16
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: seqz s4, s7
-; RV32I-NEXT: xor a6, a6, t4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: xor a7, a7, t4
; RV32I-NEXT: addi s4, s4, -1
; RV32I-NEXT: lw t4, 628(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t4, s4, t4
-; RV32I-NEXT: andi s4, s8, 32
+; RV32I-NEXT: andi s4, s9, 32
; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: andi s7, s8, 64
+; RV32I-NEXT: andi s5, s9, 64
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: seqz s7, s7
-; RV32I-NEXT: lw a0, 624(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: addi s7, s7, -1
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: lw s6, 624(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: addi s5, s5, -1
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: lw a0, 620(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s7, a0
+; RV32I-NEXT: lw s4, 620(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: andi s4, s8, 128
-; RV32I-NEXT: xor a6, a6, t4
+; RV32I-NEXT: andi s4, s9, 128
+; RV32I-NEXT: xor a7, a7, t4
; RV32I-NEXT: seqz t4, s4
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: andi s4, s8, 256
-; RV32I-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: andi s4, s9, 256
+; RV32I-NEXT: lw s5, 616(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t4, t4, s5
; RV32I-NEXT: seqz s4, s4
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: andi s7, s8, 512
-; RV32I-NEXT: lw a0, 612(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: andi s5, s9, 512
+; RV32I-NEXT: lw s6, 612(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s7, a0
-; RV32I-NEXT: andi s7, s8, 1024
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lw s4, 608(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: andi s5, s9, 1024
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: seqz s4, s7
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lw t2, 288(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s8, t2
-; RV32I-NEXT: lw a0, 604(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: lw t2, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s9, t2
+; RV32I-NEXT: lw s6, 604(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s7, a0
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lw s4, 600(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: and s5, s9, a0
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: lui a0, 2
-; RV32I-NEXT: and s10, s8, a0
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: seqz s10, s10
-; RV32I-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
-; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s10, a0
-; RV32I-NEXT: xor s4, s4, s7
+; RV32I-NEXT: and s6, s9, a0
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: seqz s6, s6
+; RV32I-NEXT: lw ra, 596(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, ra
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 592(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: xor s4, s4, s5
; RV32I-NEXT: lui a0, 4
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: and s5, s9, a0
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: lui a0, 8
-; RV32I-NEXT: and s10, s8, a0
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: seqz s10, s10
-; RV32I-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
-; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 584(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s10, a0
-; RV32I-NEXT: xor a6, a6, t4
-; RV32I-NEXT: xor t4, s4, s7
+; RV32I-NEXT: and s6, s9, a0
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: seqz s6, s6
+; RV32I-NEXT: lw ra, 588(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, ra
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 584(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: xor a7, a7, t4
+; RV32I-NEXT: xor t4, s4, s5
; RV32I-NEXT: lui a0, 16
-; RV32I-NEXT: and s4, s8, a0
+; RV32I-NEXT: and s4, s9, a0
; RV32I-NEXT: lui a0, 32
-; RV32I-NEXT: and s7, s8, a0
+; RV32I-NEXT: and s5, s9, a0
; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: lw a0, 580(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: lw a0, 576(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
-; RV32I-NEXT: xor s4, s4, s7
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lw s6, 580(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: lw s6, 576(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: xor s4, s4, s5
; RV32I-NEXT: lui a0, 64
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: and s5, s9, a0
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: lui a0, 128
-; RV32I-NEXT: and s10, s8, a0
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: seqz s10, s10
-; RV32I-NEXT: lw a0, 572(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
-; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s10, a0
-; RV32I-NEXT: xor s4, s4, s7
+; RV32I-NEXT: and s6, s9, a0
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: seqz s6, s6
+; RV32I-NEXT: lw ra, 572(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, ra
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 568(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: xor s4, s4, s5
; RV32I-NEXT: lui a0, 256
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: and s5, s9, a0
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: lui a0, 512
-; RV32I-NEXT: and s10, s8, a0
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: seqz s10, s10
-; RV32I-NEXT: lw a0, 556(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
-; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 548(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s10, a0
-; RV32I-NEXT: xor a6, a6, t4
-; RV32I-NEXT: xor t4, s4, s7
-; RV32I-NEXT: xor a6, a6, t4
-; RV32I-NEXT: lui s6, 1024
-; RV32I-NEXT: and t4, s8, s6
+; RV32I-NEXT: and s6, s9, a0
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: seqz s6, s6
+; RV32I-NEXT: lw ra, 556(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, ra
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: xor a7, a7, t4
+; RV32I-NEXT: xor t4, s4, s5
+; RV32I-NEXT: xor a7, a7, t4
+; RV32I-NEXT: lui a0, 1024
+; RV32I-NEXT: and t4, s9, a0
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: lui a0, 2048
-; RV32I-NEXT: and s4, s8, a0
+; RV32I-NEXT: and s4, s9, a0
; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: lw a0, 564(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: lw s5, 564(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t4, t4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lw a0, 560(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: lui s10, 4096
-; RV32I-NEXT: and s7, s8, s10
+; RV32I-NEXT: lw s5, 560(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: lui a0, 4096
+; RV32I-NEXT: and s5, s9, a0
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: seqz s4, s7
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
; RV32I-NEXT: lui a0, 8192
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: lw a0, 552(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: and s5, s9, a0
+; RV32I-NEXT: lw s6, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: lw a0, 540(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s7, a0
-; RV32I-NEXT: lui a0, 16384
-; RV32I-NEXT: and s7, s8, a0
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lw s4, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: lui s10, 16384
+; RV32I-NEXT: and s5, s9, s10
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: seqz s4, s7
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
; RV32I-NEXT: lui a0, 32768
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: lw a0, 536(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: and s5, s9, a0
+; RV32I-NEXT: lw s6, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: lw a0, 532(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s7, a0
-; RV32I-NEXT: lui a0, 65536
-; RV32I-NEXT: and s7, s8, a0
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lw s4, 532(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: lui ra, 65536
+; RV32I-NEXT: and s5, s9, ra
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: seqz s4, s7
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lui a0, 131072
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: lw a0, 528(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: lui s5, 131072
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: lw s6, 528(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: lw a0, 508(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s7, a0
-; RV32I-NEXT: lui a0, 262144
-; RV32I-NEXT: and s7, s8, a0
-; RV32I-NEXT: seqz s7, s7
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lw s4, 508(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: lui s5, 262144
+; RV32I-NEXT: and s5, s9, s5
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: srli a2, a2, 31
-; RV32I-NEXT: addi s7, s7, -1
+; RV32I-NEXT: addi s5, s5, -1
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: lw a0, 504(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: lw s6, 504(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s5, s6
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a0, 472(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a2, a0
-; RV32I-NEXT: xor a6, a6, t4
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw s5, 472(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, s5
+; RV32I-NEXT: xor a7, a7, t4
; RV32I-NEXT: xor a2, s4, a2
-; RV32I-NEXT: xor a2, a6, a2
-; RV32I-NEXT: srli a6, a1, 4
-; RV32I-NEXT: and a6, a6, s5
-; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: xor a2, a7, a2
+; RV32I-NEXT: srli a7, a1, 4
+; RV32I-NEXT: and a7, a7, s7
+; RV32I-NEXT: and a1, a1, s7
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: srli t4, a2, 8
-; RV32I-NEXT: or a1, a6, a1
-; RV32I-NEXT: and a6, t4, a5
+; RV32I-NEXT: or a1, a7, a1
+; RV32I-NEXT: and a7, t4, a3
; RV32I-NEXT: srli t4, a2, 24
-; RV32I-NEXT: and s4, a2, a5
+; RV32I-NEXT: and s4, a2, a3
; RV32I-NEXT: slli a2, a2, 24
; RV32I-NEXT: slli s4, s4, 8
-; RV32I-NEXT: or a6, a6, t4
+; RV32I-NEXT: or a7, a7, t4
; RV32I-NEXT: or a2, a2, s4
; RV32I-NEXT: srli t4, a1, 2
-; RV32I-NEXT: and a1, a1, s9
-; RV32I-NEXT: and t4, t4, s9
+; RV32I-NEXT: and a1, a1, s8
+; RV32I-NEXT: and t4, t4, s8
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, t4, a1
-; RV32I-NEXT: or a2, a2, a6
-; RV32I-NEXT: srli a6, a1, 1
+; RV32I-NEXT: or a2, a2, a7
+; RV32I-NEXT: srli a7, a1, 1
; RV32I-NEXT: and a1, a1, a4
-; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, a0
+; RV32I-NEXT: lw s9, 696(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, a7, s9
; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: or a1, a6, a1
-; RV32I-NEXT: srli a6, a2, 4
-; RV32I-NEXT: sw s5, 104(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, a6, s5
-; RV32I-NEXT: and a2, a2, s5
+; RV32I-NEXT: or a1, a7, a1
+; RV32I-NEXT: srli a7, a2, 4
+; RV32I-NEXT: and a7, a7, s7
+; RV32I-NEXT: and a2, a2, s7
; RV32I-NEXT: slli a2, a2, 4
-; RV32I-NEXT: lw s5, 544(sp) # 4-byte Folded Reload
-; RV32I-NEXT: slli a3, s5, 1
-; RV32I-NEXT: sw a3, 128(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 124(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, a5, a3
+; RV32I-NEXT: lw s6, 552(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli a0, s6, 1
+; RV32I-NEXT: sw a0, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a3, 120(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a3, s5
-; RV32I-NEXT: or a2, a6, a2
-; RV32I-NEXT: xor a6, s4, t4
-; RV32I-NEXT: slli a3, s5, 2
-; RV32I-NEXT: sw a3, 124(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s4, s5, 3
-; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 116(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, a5, a3
-; RV32I-NEXT: lw a3, 112(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a3, s4
-; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: slli a3, s5, 4
+; RV32I-NEXT: and t4, a3, a0
+; RV32I-NEXT: lw a0, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, a0, s6
+; RV32I-NEXT: or a2, a7, a2
+; RV32I-NEXT: xor a7, s4, t4
+; RV32I-NEXT: slli a0, s6, 2
+; RV32I-NEXT: sw a0, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s6, 3
; RV32I-NEXT: sw a3, 116(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 108(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a5, a3
-; RV32I-NEXT: slli a3, s5, 5
-; RV32I-NEXT: sw a3, 112(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 96(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a5, a3
-; RV32I-NEXT: slli a3, s5, 6
-; RV32I-NEXT: sw a3, 108(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a5, 100(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a5, a3
-; RV32I-NEXT: xor a6, a6, t4
-; RV32I-NEXT: xor t4, s4, s7
+; RV32I-NEXT: lw t4, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: lw a0, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, a0, a3
+; RV32I-NEXT: xor t4, t4, s4
+; RV32I-NEXT: slli a0, s6, 4
+; RV32I-NEXT: sw a0, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 104(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, a3, a0
+; RV32I-NEXT: slli a0, s6, 5
+; RV32I-NEXT: sw a0, 108(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 96(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a3, a0
+; RV32I-NEXT: slli a0, s6, 6
+; RV32I-NEXT: sw a0, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw a3, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a3, a0
+; RV32I-NEXT: xor a7, a7, t4
+; RV32I-NEXT: xor t4, s4, s5
; RV32I-NEXT: srli s4, a2, 2
-; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: and s4, s4, s9
+; RV32I-NEXT: and a2, a2, s8
+; RV32I-NEXT: and s4, s4, s8
; RV32I-NEXT: slli a2, a2, 2
; RV32I-NEXT: or a2, s4, a2
-; RV32I-NEXT: xor a6, a6, t4
-; RV32I-NEXT: slli a3, s5, 7
-; RV32I-NEXT: sw a3, 100(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s4, s5, 8
-; RV32I-NEXT: sw s4, 96(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 92(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, a5, a3
-; RV32I-NEXT: lw a3, 88(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a3, s4
+; RV32I-NEXT: xor a7, a7, t4
+; RV32I-NEXT: slli a0, s6, 7
+; RV32I-NEXT: sw a0, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s6, 8
+; RV32I-NEXT: sw a3, 96(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t4, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, a0, a3
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: slli a3, s5, 9
-; RV32I-NEXT: sw a3, 92(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 84(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a5, a3
-; RV32I-NEXT: slli a3, s5, 10
-; RV32I-NEXT: sw a3, 88(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, s6, 9
+; RV32I-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, a3, a0
+; RV32I-NEXT: slli a0, s6, 10
+; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: lw a5, 80(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a5, a3
+; RV32I-NEXT: lw a3, 80(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, a3, a0
; RV32I-NEXT: xor t4, t4, s4
-; RV32I-NEXT: slli a3, s5, 11
-; RV32I-NEXT: sw a3, 84(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 76(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a5, a3
-; RV32I-NEXT: slli a3, s5, 12
-; RV32I-NEXT: sw a3, 80(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 68(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a5, a3
-; RV32I-NEXT: slli a3, s5, 13
-; RV32I-NEXT: sw a3, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a5, 72(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a5, a3
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: slli a3, s5, 14
-; RV32I-NEXT: sw a3, 72(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 60(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a5, a3
-; RV32I-NEXT: slli a3, s5, 15
-; RV32I-NEXT: sw a3, 68(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor s4, s4, s7
-; RV32I-NEXT: lw a5, 64(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a5, a3
-; RV32I-NEXT: xor a6, a6, t4
-; RV32I-NEXT: xor t4, s4, s7
-; RV32I-NEXT: slli a3, s5, 16
-; RV32I-NEXT: sw a3, 64(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s4, s5, 17
-; RV32I-NEXT: sw s4, 60(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s1, s1, a3
-; RV32I-NEXT: and t6, t6, s4
-; RV32I-NEXT: xor t6, s1, t6
-; RV32I-NEXT: slli a3, s5, 18
-; RV32I-NEXT: sw a3, 56(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t5, t5, a3
-; RV32I-NEXT: slli a3, s5, 19
-; RV32I-NEXT: sw a3, 52(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, s6, 11
+; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 76(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, a3, a0
+; RV32I-NEXT: slli a0, s6, 12
+; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a3, a0
+; RV32I-NEXT: slli a0, s6, 13
+; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw a3, 72(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a3, a0
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: slli a0, s6, 14
+; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a3, a0
+; RV32I-NEXT: slli a0, s6, 15
+; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lw a3, 64(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a3, a0
+; RV32I-NEXT: xor a7, a7, t4
+; RV32I-NEXT: xor t4, s4, s5
+; RV32I-NEXT: slli a0, s6, 16
+; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s6, 17
+; RV32I-NEXT: sw a3, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s0, s0, a0
+; RV32I-NEXT: and t6, t6, a3
+; RV32I-NEXT: xor t6, s0, t6
+; RV32I-NEXT: slli a0, s6, 18
+; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t5, t5, a0
+; RV32I-NEXT: slli a0, s6, 19
+; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor t5, t6, t5
-; RV32I-NEXT: lw a5, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t6, a5, a3
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: slli a3, s5, 20
-; RV32I-NEXT: sw a3, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t3, t3, a3
-; RV32I-NEXT: slli a3, s5, 21
-; RV32I-NEXT: sw a3, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t3, t3, a0
; RV32I-NEXT: xor t3, t5, t3
-; RV32I-NEXT: and t1, t1, a3
-; RV32I-NEXT: xor a6, a6, t4
+; RV32I-NEXT: slli a0, s6, 20
+; RV32I-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t1, t1, a0
+; RV32I-NEXT: slli a0, s6, 21
+; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor t1, t3, t1
-; RV32I-NEXT: srli t3, a2, 1
+; RV32I-NEXT: and t0, t0, a0
+; RV32I-NEXT: xor a7, a7, t4
+; RV32I-NEXT: xor t0, t1, t0
+; RV32I-NEXT: srli t1, a2, 1
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: and t3, t3, a0
+; RV32I-NEXT: and t1, t1, s9
; RV32I-NEXT: slli a2, a2, 1
-; RV32I-NEXT: or a2, t3, a2
-; RV32I-NEXT: xor a6, a6, t1
-; RV32I-NEXT: slli a0, s5, 22
+; RV32I-NEXT: or a2, t1, a2
+; RV32I-NEXT: xor a7, a7, t0
+; RV32I-NEXT: slli a0, s6, 22
; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, s5, 23
+; RV32I-NEXT: slli a3, s6, 23
; RV32I-NEXT: sw a3, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a4, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a4, a0
-; RV32I-NEXT: and a7, a7, a3
-; RV32I-NEXT: xor a7, t1, a7
-; RV32I-NEXT: lw t1, 644(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: xor a7, a7, t0
-; RV32I-NEXT: slli a0, s5, 25
+; RV32I-NEXT: and t0, a4, a0
+; RV32I-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, a3
+; RV32I-NEXT: xor a4, t0, a4
+; RV32I-NEXT: lw t0, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, t0
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: slli a0, s6, 25
; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, a0
-; RV32I-NEXT: slli a0, s5, 26
+; RV32I-NEXT: lw a3, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, a0
+; RV32I-NEXT: slli a0, s6, 26
; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a5, a7, a5
+; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: lw a4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, a0
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: slli a0, s5, 27
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: slli a0, s6, 27
; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, a0
-; RV32I-NEXT: slli a0, s5, 28
+; RV32I-NEXT: lw a4, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, a0
+; RV32I-NEXT: slli a0, s6, 28
; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, a0
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: slli a0, s5, 29
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: lw a4, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, a0
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: slli a0, s6, 29
; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, s3, a0
-; RV32I-NEXT: slli a0, s5, 30
+; RV32I-NEXT: and a4, s2, a0
+; RV32I-NEXT: slli a0, s6, 30
; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, s11, a0
-; RV32I-NEXT: slli a0, s5, 31
+; RV32I-NEXT: and a5, s3, a0
+; RV32I-NEXT: slli a0, s6, 31
; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: and a0, s0, a0
-; RV32I-NEXT: xor a4, a6, a4
-; RV32I-NEXT: xor a0, a3, a0
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a0, a6, a0
+; RV32I-NEXT: xor a3, a7, a3
+; RV32I-NEXT: xor a0, a4, a0
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a0, a4, a0
-; RV32I-NEXT: lw a6, 272(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a3, a0
+; RV32I-NEXT: lw a6, 268(sp) # 4-byte Folded Reload
; RV32I-NEXT: andi a1, a6, 2
; RV32I-NEXT: andi a2, a6, 1
; RV32I-NEXT: seqz a1, a1
@@ -18069,7 +18078,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: lw a3, 380(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: and a2, a2, s1
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: andi a2, a6, 4
; RV32I-NEXT: seqz a2, a2
@@ -18121,7 +18130,6 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: mv t1, t2
; RV32I-NEXT: and a4, a6, t2
; RV32I-NEXT: lw a5, 344(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a5
@@ -18130,78 +18138,78 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: lw a3, 340(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
-; RV32I-NEXT: lui t2, 1
-; RV32I-NEXT: and a4, a6, t2
+; RV32I-NEXT: lui t3, 1
+; RV32I-NEXT: and a4, a6, t3
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: lui t3, 2
-; RV32I-NEXT: and a5, a6, t3
+; RV32I-NEXT: lui t4, 2
+; RV32I-NEXT: and a5, a6, t4
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lw a7, 696(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 336(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 336(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 332(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lui t4, 4
-; RV32I-NEXT: and a4, a6, t4
+; RV32I-NEXT: lui s1, 4
+; RV32I-NEXT: and a4, a6, s1
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: lui t5, 8
-; RV32I-NEXT: and a5, a6, t5
+; RV32I-NEXT: lui s2, 8
+; RV32I-NEXT: and a5, a6, s2
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lw a7, 332(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 328(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 328(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 324(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lui s0, 16
-; RV32I-NEXT: and a2, a6, s0
+; RV32I-NEXT: lui s4, 16
+; RV32I-NEXT: and a2, a6, s4
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: lui s3, 32
-; RV32I-NEXT: and a3, a6, s3
+; RV32I-NEXT: lui s6, 32
+; RV32I-NEXT: and a3, a6, s6
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: lw a4, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 320(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: lw a4, 320(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 692(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
-; RV32I-NEXT: lui s5, 64
-; RV32I-NEXT: and a4, a6, s5
+; RV32I-NEXT: lui a4, 64
+; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: lui a4, 128
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: lw a5, 316(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 688(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: lw a3, 312(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 316(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: lui a4, 256
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: lui s11, 256
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: lui a4, 512
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: lw a5, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 684(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: lw a3, 688(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 312(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
-; RV32I-NEXT: and a4, a6, s6
+; RV32I-NEXT: lui a4, 1024
+; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: seqz a3, a4
; RV32I-NEXT: xor a1, a1, a2
@@ -18211,35 +18219,36 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: lui a3, 2048
; RV32I-NEXT: and a3, a6, a3
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: and a4, a6, s10
+; RV32I-NEXT: lui a4, 4096
+; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: lw a5, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 680(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, a4, ra
+; RV32I-NEXT: and a3, a4, s11
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: lui a3, 8192
; RV32I-NEXT: and a3, a6, a3
-; RV32I-NEXT: lui s2, 8192
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: lui a4, 16384
-; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: and a4, a6, s10
+; RV32I-NEXT: lui s5, 16384
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: lw a5, 304(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a3, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 300(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: lui a3, 32768
; RV32I-NEXT: and a3, a6, a3
+; RV32I-NEXT: lui s8, 32768
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: lui a4, 65536
-; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: and a4, a6, ra
+; RV32I-NEXT: lui s10, 65536
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: lw a5, 676(sp) # 4-byte Folded Reload
@@ -18268,30 +18277,30 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: lw a3, 660(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
-; RV32I-NEXT: lw t0, 276(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 272(sp) # 4-byte Folded Reload
; RV32I-NEXT: slli a4, t0, 1
-; RV32I-NEXT: lw a5, 760(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 768(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: lw a5, 756(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 764(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, t0
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a4, a5, a4
; RV32I-NEXT: slli a3, t0, 2
; RV32I-NEXT: slli a5, t0, 3
-; RV32I-NEXT: lw a6, 744(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 752(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a6, a3
-; RV32I-NEXT: lw a6, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 748(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: slli a5, t0, 4
-; RV32I-NEXT: lw s6, 300(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, s6, a5
+; RV32I-NEXT: lw a6, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: slli a6, t0, 5
-; RV32I-NEXT: lw a7, 728(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 732(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a6, a7, a6
; RV32I-NEXT: slli a7, t0, 6
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 720(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 724(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: xor a4, a5, a6
@@ -18299,36 +18308,36 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: slli a2, t0, 7
; RV32I-NEXT: slli a4, t0, 8
-; RV32I-NEXT: lw a5, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 716(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: lw a5, 708(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 712(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: slli a4, t0, 9
-; RV32I-NEXT: lw a5, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 708(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: slli a5, t0, 10
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 824(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 704(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: slli a4, t0, 11
-; RV32I-NEXT: lw a5, 820(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 700(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: slli a5, t0, 12
-; RV32I-NEXT: lw a6, 816(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 824(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: slli a6, t0, 13
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 812(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 820(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: slli a5, t0, 14
-; RV32I-NEXT: lw a6, 808(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 816(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: slli a6, t0, 15
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 804(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 812(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: xor a2, a3, a2
; RV32I-NEXT: xor a4, a4, a5
@@ -18337,693 +18346,700 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: slli a0, t0, 16
; RV32I-NEXT: slli a1, t0, 17
-; RV32I-NEXT: lw a3, 800(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 808(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a3, a0
-; RV32I-NEXT: lw a3, 796(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 804(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: slli a1, t0, 18
-; RV32I-NEXT: lw a3, 792(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 800(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: slli a3, t0, 19
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 788(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 796(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: slli a1, t0, 20
-; RV32I-NEXT: lw a3, 784(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 792(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: slli a3, t0, 21
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 780(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 788(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: slli a1, t0, 22
-; RV32I-NEXT: lw a3, 776(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 784(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: slli a3, t0, 23
-; RV32I-NEXT: lw a4, 772(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 780(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: slli a4, t0, 24
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 768(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 776(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: slli a3, t0, 25
-; RV32I-NEXT: lw a4, 764(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 772(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: slli a4, t0, 26
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 752(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 760(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: slli a3, t0, 27
-; RV32I-NEXT: lw a4, 748(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 756(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: slli a4, t0, 28
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 736(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 744(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: xor a0, a2, a0
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: xor s8, a0, a1
+; RV32I-NEXT: xor s9, a0, a1
; RV32I-NEXT: slli a0, t0, 29
-; RV32I-NEXT: lw a1, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 736(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: slli a1, t0, 30
-; RV32I-NEXT: lw a2, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 728(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: slli a2, t0, 31
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 720(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: xor ra, a0, a1
-; RV32I-NEXT: lw s7, 280(sp) # 4-byte Folded Reload
-; RV32I-NEXT: andi a0, s7, 2
+; RV32I-NEXT: xor t1, a0, a1
+; RV32I-NEXT: lw s11, 276(sp) # 4-byte Folded Reload
+; RV32I-NEXT: andi a0, s11, 2
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a1, s7, 1
+; RV32I-NEXT: andi a1, s11, 1
; RV32I-NEXT: addi a2, a0, -1
-; RV32I-NEXT: sw a2, 276(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 272(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a0, a1
-; RV32I-NEXT: lw a1, 244(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 240(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: addi a2, a0, -1
-; RV32I-NEXT: sw a2, 272(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a2, 268(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 128(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a2, a0
-; RV32I-NEXT: andi a2, s7, 4
+; RV32I-NEXT: andi a2, s11, 4
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a1, a2
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 244(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a1, s7, 8
-; RV32I-NEXT: lw a2, 240(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a3, 240(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a1, s11, 8
+; RV32I-NEXT: lw a2, 236(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 240(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a1, s7, 16
-; RV32I-NEXT: lw a3, 248(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a4, 236(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a1, s11, 16
+; RV32I-NEXT: lw a3, 244(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 248(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a1, 216(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a3, 244(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 212(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a3, a1
-; RV32I-NEXT: andi a3, s7, 32
+; RV32I-NEXT: andi a3, s11, 32
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: andi a4, s7, 64
+; RV32I-NEXT: andi a4, s11, 64
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 216(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 212(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a3, a4
-; RV32I-NEXT: lw a4, 232(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 228(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 232(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 228(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: lw a3, 236(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 232(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a5, a3
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: andi a1, s7, 128
+; RV32I-NEXT: andi a1, s11, 128
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: andi a2, s7, 256
+; RV32I-NEXT: andi a2, s11, 256
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 236(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 232(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a1, a2
-; RV32I-NEXT: lw a2, 224(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 220(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: addi a3, a1, -1
-; RV32I-NEXT: sw a3, 224(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a1, 220(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a3, 220(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 216(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a3, a1
-; RV32I-NEXT: andi a3, s7, 512
+; RV32I-NEXT: andi a3, s11, 512
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 220(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a2, s7, 1024
-; RV32I-NEXT: lw a3, 228(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a4, 216(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a2, s11, 1024
+; RV32I-NEXT: lw a3, 224(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
-; RV32I-NEXT: seqz a2, a2
+; RV32I-NEXT: seqz ra, a2
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: addi a3, a2, -1
-; RV32I-NEXT: sw a3, 228(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a2, 212(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a3, a2
-; RV32I-NEXT: and a3, s7, t1
+; RV32I-NEXT: addi ra, ra, -1
+; RV32I-NEXT: lw a2, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, ra, a2
+; RV32I-NEXT: and a3, s11, t2
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: seqz s9, a3
+; RV32I-NEXT: seqz s0, a3
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: addi s9, s9, -1
-; RV32I-NEXT: sw s9, 288(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a1, 184(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, s9, a1
-; RV32I-NEXT: and a2, s7, t2
-; RV32I-NEXT: seqz s4, a2
-; RV32I-NEXT: and a2, s7, t3
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: sw s4, 212(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz s1, a2
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: sw s0, 284(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, s0, a1
+; RV32I-NEXT: and a2, s11, t3
+; RV32I-NEXT: seqz t6, a2
+; RV32I-NEXT: and a2, s11, t4
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: sw t6, 224(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz t5, a2
+; RV32I-NEXT: lw a2, 196(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, t6, a2
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: sw t5, 208(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: lw a2, 200(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, s4, a2
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: sw s1, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, t5, a2
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, s11, s1
+; RV32I-NEXT: seqz s1, a2
+; RV32I-NEXT: and a2, s11, s2
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: seqz s3, a2
+; RV32I-NEXT: lw a2, 188(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, s1, a2
+; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: sw s3, 200(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: and a2, s7, t4
-; RV32I-NEXT: seqz t6, a2
-; RV32I-NEXT: and a2, s7, t5
-; RV32I-NEXT: addi s4, t6, -1
-; RV32I-NEXT: seqz t4, a2
; RV32I-NEXT: lw a2, 192(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, s4, a2
-; RV32I-NEXT: addi s1, t4, -1
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 196(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, s1, a2
+; RV32I-NEXT: and a2, s3, a2
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: and a2, s7, s0
-; RV32I-NEXT: xor t1, a0, a1
-; RV32I-NEXT: seqz t3, a2
-; RV32I-NEXT: addi t6, t3, -1
-; RV32I-NEXT: and a0, s7, s3
-; RV32I-NEXT: lw a1, 176(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, t6, a1
-; RV32I-NEXT: seqz a7, a0
-; RV32I-NEXT: addi t4, a7, -1
-; RV32I-NEXT: and a0, s7, s5
-; RV32I-NEXT: lw a2, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, t4, a2
-; RV32I-NEXT: seqz a6, a0
+; RV32I-NEXT: and a2, s11, s4
+; RV32I-NEXT: xor a5, a0, a1
+; RV32I-NEXT: seqz a6, a2
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: sw a6, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, s11, s6
+; RV32I-NEXT: lw a1, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a6, a1
+; RV32I-NEXT: seqz s4, a0
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: sw s4, 192(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a0, 64
+; RV32I-NEXT: and a0, s11, a0
+; RV32I-NEXT: lw a2, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, s4, a2
+; RV32I-NEXT: seqz s2, a0
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: addi t3, a6, -1
-; RV32I-NEXT: lw a0, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, t3, a0
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: sw s2, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 160(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, s2, a0
; RV32I-NEXT: lui a2, 128
-; RV32I-NEXT: and a2, s7, a2
+; RV32I-NEXT: and a2, s11, a2
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: seqz a5, a2
-; RV32I-NEXT: addi a7, a5, -1
-; RV32I-NEXT: and a1, s7, s11
-; RV32I-NEXT: lw a2, 180(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a7, a2
-; RV32I-NEXT: seqz s0, a1
+; RV32I-NEXT: seqz a4, a2
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: sw a4, 184(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 256
+; RV32I-NEXT: and a1, s11, a1
+; RV32I-NEXT: lw a2, 176(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a4, a2
+; RV32I-NEXT: seqz s6, a1
; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: sw s0, 204(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a1, 152(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, s0, a1
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: sw s6, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, s6, a1
; RV32I-NEXT: lui a2, 512
-; RV32I-NEXT: and a2, s7, a2
+; RV32I-NEXT: and a2, s11, a2
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz s3, a2
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: sw s3, 192(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz t4, a2
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: sw t4, 176(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 1024
-; RV32I-NEXT: and a1, s7, a1
-; RV32I-NEXT: lw a2, 172(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, s3, a2
+; RV32I-NEXT: and a1, s11, a1
+; RV32I-NEXT: lw a2, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, t4, a2
; RV32I-NEXT: seqz a3, a1
-; RV32I-NEXT: xor t5, a0, a2
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: sw a3, 196(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 140(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a3, a0
+; RV32I-NEXT: xor t3, a0, a2
+; RV32I-NEXT: addi t4, a3, -1
+; RV32I-NEXT: lw a0, 136(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, t4, a0
; RV32I-NEXT: lui a1, 2048
-; RV32I-NEXT: and a1, s7, a1
+; RV32I-NEXT: and a1, s11, a1
; RV32I-NEXT: seqz t0, a1
-; RV32I-NEXT: and a1, s7, s10
+; RV32I-NEXT: lui a1, 4096
+; RV32I-NEXT: and a1, s11, a1
; RV32I-NEXT: addi t0, t0, -1
; RV32I-NEXT: seqz t2, a1
-; RV32I-NEXT: lw a1, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 164(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, t0, a1
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: sw t2, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t2, 172(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 136(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 132(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, t2, a1
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: and a1, s7, s2
-; RV32I-NEXT: seqz a4, a1
-; RV32I-NEXT: lui a1, 16384
-; RV32I-NEXT: and a1, s7, a1
-; RV32I-NEXT: addi a5, a4, -1
+; RV32I-NEXT: lui a1, 8192
+; RV32I-NEXT: and a1, s11, a1
+; RV32I-NEXT: seqz a7, a1
+; RV32I-NEXT: and a1, s11, s5
+; RV32I-NEXT: addi a7, a7, -1
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: lw a2, 160(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: addi a4, a1, -1
+; RV32I-NEXT: lw a2, 156(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a7, a2
+; RV32I-NEXT: addi a6, a1, -1
; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: lw a2, 148(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: xor s2, a0, a2
-; RV32I-NEXT: lui a0, 32768
-; RV32I-NEXT: and a0, s7, a0
+; RV32I-NEXT: lw a1, 144(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a6, a1
+; RV32I-NEXT: xor s5, a0, a2
+; RV32I-NEXT: and a0, s11, s8
; RV32I-NEXT: seqz a2, a0
-; RV32I-NEXT: lui a0, 65536
-; RV32I-NEXT: and a0, s7, a0
-; RV32I-NEXT: mv a1, s7
-; RV32I-NEXT: addi a3, a2, -1
+; RV32I-NEXT: and a0, s11, s10
+; RV32I-NEXT: mv a1, s11
+; RV32I-NEXT: addi a4, a2, -1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: lw a2, 156(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a3, a2
-; RV32I-NEXT: addi a2, a0, -1
-; RV32I-NEXT: xor s2, s2, s7
-; RV32I-NEXT: lw a0, 144(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, a0
-; RV32I-NEXT: xor t5, t1, t5
-; RV32I-NEXT: xor s2, s2, s7
-; RV32I-NEXT: xor t1, s8, ra
-; RV32I-NEXT: xor t5, t5, s2
+; RV32I-NEXT: lw a2, 152(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s10, a4, a2
+; RV32I-NEXT: addi a3, a0, -1
+; RV32I-NEXT: xor s5, s5, s10
+; RV32I-NEXT: lw a0, 140(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s10, a3, a0
+; RV32I-NEXT: xor a5, a5, t3
+; RV32I-NEXT: xor t3, s5, s10
+; RV32I-NEXT: xor t1, s9, t1
+; RV32I-NEXT: xor t3, a5, t3
; RV32I-NEXT: lw a0, 640(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 524(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s2, s2, a0
+; RV32I-NEXT: lw a5, 524(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, a0
; RV32I-NEXT: lw a0, 520(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 384(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, a0, t2
+; RV32I-NEXT: lw a2, 384(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a0, a2
; RV32I-NEXT: lw a0, 636(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 516(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: lw a2, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a0
; RV32I-NEXT: lw a0, 632(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 512(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s2, s5, s2
-; RV32I-NEXT: xor s5, s7, s8
+; RV32I-NEXT: lw a2, 512(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor a5, s5, a5
+; RV32I-NEXT: xor s5, s8, s9
; RV32I-NEXT: lw a0, 628(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 500(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: lw a2, 500(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a0
; RV32I-NEXT: lw a0, 624(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 496(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 496(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 620(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 492(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s8
+; RV32I-NEXT: lw a2, 492(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor a5, a5, s5
+; RV32I-NEXT: xor s5, s8, s9
; RV32I-NEXT: lw a0, 616(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 488(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: lw a2, 488(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a0
; RV32I-NEXT: lw a0, 612(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 484(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 608(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 480(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 480(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 604(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 476(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s8
+; RV32I-NEXT: lw a2, 476(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor a5, a5, s5
+; RV32I-NEXT: xor s5, s8, s9
; RV32I-NEXT: lw a0, 600(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 468(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: lw a2, 468(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a0
; RV32I-NEXT: lw a0, 596(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 464(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 464(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 592(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 460(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 588(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 456(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 584(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 452(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s8
+; RV32I-NEXT: lw a2, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor a5, a5, s5
+; RV32I-NEXT: xor s5, s8, s9
; RV32I-NEXT: lw a0, 580(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 448(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: lw a2, 448(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a0
; RV32I-NEXT: lw a0, 576(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 444(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 444(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 572(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 440(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 440(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 568(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 436(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 436(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 556(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 432(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
-; RV32I-NEXT: lw a0, 548(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 428(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s8
+; RV32I-NEXT: lw a2, 432(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
+; RV32I-NEXT: lw a0, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 428(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor a5, a5, s5
+; RV32I-NEXT: xor s5, s8, s9
; RV32I-NEXT: lw a0, 564(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 424(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: lw a2, 424(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a0
; RV32I-NEXT: lw a0, 560(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 420(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
-; RV32I-NEXT: lw a0, 552(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 416(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 420(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
+; RV32I-NEXT: lw a0, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 416(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 540(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 412(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, s8, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 412(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 536(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 408(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, t2, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 408(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 532(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 404(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, t2, a0
-; RV32I-NEXT: xor s7, s7, s8
+; RV32I-NEXT: lw a2, 404(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor s8, s8, s9
; RV32I-NEXT: lw a0, 528(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 400(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s8, t2, a0
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s8
+; RV32I-NEXT: lw a2, 400(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s9, a2, a0
+; RV32I-NEXT: xor a5, a5, s5
+; RV32I-NEXT: xor s5, s8, s9
; RV32I-NEXT: lui a0, 131072
-; RV32I-NEXT: and s7, a1, a0
+; RV32I-NEXT: and s8, s11, a0
; RV32I-NEXT: lui a0, 262144
-; RV32I-NEXT: and s8, a1, a0
-; RV32I-NEXT: seqz s7, s7
-; RV32I-NEXT: seqz ra, s8
-; RV32I-NEXT: addi s7, s7, -1
-; RV32I-NEXT: sw s7, 640(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi ra, ra, -1
-; RV32I-NEXT: sw ra, 636(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 256(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a0
+; RV32I-NEXT: and s9, s11, a0
+; RV32I-NEXT: seqz s8, s8
+; RV32I-NEXT: seqz s10, s9
+; RV32I-NEXT: addi s8, s8, -1
+; RV32I-NEXT: sw s8, 640(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s10, s10, -1
+; RV32I-NEXT: sw s10, 636(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 252(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s10, ra, a0
-; RV32I-NEXT: xor s7, s7, s10
-; RV32I-NEXT: xor s2, s2, s5
+; RV32I-NEXT: and s8, s8, a0
+; RV32I-NEXT: lw a0, 248(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, s10, a0
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: xor s5, a5, s5
; RV32I-NEXT: lw a0, 508(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 396(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, t2, a0
+; RV32I-NEXT: lw a5, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, a0
; RV32I-NEXT: lw a0, 504(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 388(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s10, t2, a0
-; RV32I-NEXT: xor s5, s5, s10
-; RV32I-NEXT: srli s10, a1, 31
+; RV32I-NEXT: lw a2, 388(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a0
+; RV32I-NEXT: xor a5, a5, s11
+; RV32I-NEXT: srli s11, a1, 31
; RV32I-NEXT: lw a0, 472(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 392(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: seqz s10, s10
-; RV32I-NEXT: xor s5, s5, s11
-; RV32I-NEXT: addi s10, s10, -1
-; RV32I-NEXT: sw s10, 632(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: lw a0, 260(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, s10, a0
-; RV32I-NEXT: xor s5, s7, s5
-; RV32I-NEXT: srli s7, s2, 8
-; RV32I-NEXT: xor t5, t5, s5
-; RV32I-NEXT: lw a0, 652(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, s7, a0
-; RV32I-NEXT: and s7, s2, a0
-; RV32I-NEXT: srli s11, s2, 24
-; RV32I-NEXT: slli s2, s2, 24
-; RV32I-NEXT: slli s7, s7, 8
+; RV32I-NEXT: lw a1, 396(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: seqz s11, s11
+; RV32I-NEXT: xor a0, a5, a0
+; RV32I-NEXT: addi s11, s11, -1
+; RV32I-NEXT: sw s11, 632(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a0, s5, a0
+; RV32I-NEXT: lw a1, 256(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s11, a1
+; RV32I-NEXT: xor s5, s8, s5
+; RV32I-NEXT: srli s8, a0, 8
+; RV32I-NEXT: xor t3, t3, s5
+; RV32I-NEXT: lw a1, 652(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, s8, a1
+; RV32I-NEXT: and s8, a0, a1
+; RV32I-NEXT: srli s11, a0, 24
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: slli s8, s8, 8
; RV32I-NEXT: or s5, s5, s11
-; RV32I-NEXT: or s2, s2, s7
-; RV32I-NEXT: xor t1, t5, t1
-; RV32I-NEXT: or t5, s2, s5
-; RV32I-NEXT: lw a0, 0(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor t1, a0, t1
-; RV32I-NEXT: srli s2, t5, 4
-; RV32I-NEXT: lw a0, 104(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s2, s2, a0
-; RV32I-NEXT: and t5, t5, a0
-; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 264(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, a1, a0
-; RV32I-NEXT: lw a1, 268(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t2, 656(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a1, t2
-; RV32I-NEXT: slli s7, s7, 1
-; RV32I-NEXT: slli t5, t5, 4
-; RV32I-NEXT: or s5, s5, s7
-; RV32I-NEXT: or t5, s2, t5
-; RV32I-NEXT: srli s2, t5, 2
-; RV32I-NEXT: lw a1, 648(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t5, t5, a1
-; RV32I-NEXT: and s2, s2, a1
-; RV32I-NEXT: slli t5, t5, 2
-; RV32I-NEXT: or t5, s2, t5
-; RV32I-NEXT: srli s2, s5, 1
-; RV32I-NEXT: xor t1, s2, t1
-; RV32I-NEXT: srli s2, t5, 1
-; RV32I-NEXT: and s2, s2, a0
-; RV32I-NEXT: and t5, t5, t2
-; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli s5, a0, 1
-; RV32I-NEXT: slli s7, t5, 1
-; RV32I-NEXT: xor a0, t1, s5
-; RV32I-NEXT: sw a0, 700(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a0, s2, s7
+; RV32I-NEXT: or a0, a0, s8
+; RV32I-NEXT: xor t1, t3, t1
+; RV32I-NEXT: or a0, a0, s5
+; RV32I-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t1, a1, t1
+; RV32I-NEXT: srli t3, a0, 4
+; RV32I-NEXT: and t3, t3, s7
+; RV32I-NEXT: and a0, a0, s7
+; RV32I-NEXT: lw a1, 696(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 260(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a2, a1
+; RV32I-NEXT: lw a2, 264(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 656(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a5
+; RV32I-NEXT: slli s8, s8, 1
+; RV32I-NEXT: slli a0, a0, 4
+; RV32I-NEXT: or s5, s5, s8
+; RV32I-NEXT: or a0, t3, a0
+; RV32I-NEXT: srli t3, a0, 2
+; RV32I-NEXT: lw a2, 648(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: and t3, t3, a2
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, t3, a0
+; RV32I-NEXT: srli t3, s5, 1
+; RV32I-NEXT: xor t1, t3, t1
+; RV32I-NEXT: srli t3, a0, 1
+; RV32I-NEXT: and s5, t3, a1
+; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli t3, a1, 1
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: xor a1, t1, t3
+; RV32I-NEXT: sw a1, 696(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a0, s5, a0
; RV32I-NEXT: sw a0, 656(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 128(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 768(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: lw a1, 552(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 764(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s5, a2, a1
+; RV32I-NEXT: lw a1, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 752(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a1
+; RV32I-NEXT: lw a1, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 748(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a1
+; RV32I-NEXT: xor a0, s5, a0
+; RV32I-NEXT: xor s5, s8, s11
+; RV32I-NEXT: lw a1, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a1
+; RV32I-NEXT: lw a1, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a1
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 104(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a1
+; RV32I-NEXT: xor a0, a0, s5
+; RV32I-NEXT: xor s5, s8, s11
+; RV32I-NEXT: lw a1, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a1
+; RV32I-NEXT: lw a1, 96(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a1
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 708(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a1
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 704(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a1
+; RV32I-NEXT: xor a0, a0, s5
+; RV32I-NEXT: xor s5, s8, s11
+; RV32I-NEXT: lw a1, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, a1
+; RV32I-NEXT: lw a1, 824(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 80(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 820(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 76(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 816(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 72(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 812(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor a0, a0, s5
+; RV32I-NEXT: xor s5, s8, s11
+; RV32I-NEXT: lw a1, 808(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 64(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a1, a2
+; RV32I-NEXT: lw a1, 804(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 800(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 796(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 52(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 792(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 48(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 788(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor a0, a0, s5
+; RV32I-NEXT: xor s5, s8, s11
+; RV32I-NEXT: lw a1, 784(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a1, a2
+; RV32I-NEXT: lw a1, 780(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 644(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 776(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a2, a1
+; RV32I-NEXT: xor s8, s8, s11
+; RV32I-NEXT: lw a1, 772(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
; RV32I-NEXT: lw a1, 760(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s2, a1, a0
-; RV32I-NEXT: lw a0, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
; RV32I-NEXT: lw a1, 756(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, a1, a0
-; RV32I-NEXT: lw a0, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
; RV32I-NEXT: lw a1, 744(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a1, a0
-; RV32I-NEXT: lw a0, 120(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 740(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: xor s2, s5, s2
-; RV32I-NEXT: xor s5, s7, s11
-; RV32I-NEXT: lw a0, 116(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s6, a0
-; RV32I-NEXT: lw a0, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor a0, a0, s5
+; RV32I-NEXT: xor s5, s8, s11
+; RV32I-NEXT: lw a1, 736(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a1, a2
; RV32I-NEXT: lw a1, 728(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor s8, s8, s11
; RV32I-NEXT: lw a1, 720(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s11
-; RV32I-NEXT: lw a0, 100(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 712(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a1, a0
-; RV32I-NEXT: lw a0, 96(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 708(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 704(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 824(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 88(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s11
-; RV32I-NEXT: lw a0, 820(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 84(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, a1
-; RV32I-NEXT: lw a0, 816(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 80(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 812(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 76(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 808(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 72(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 804(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 68(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s11
-; RV32I-NEXT: lw a0, 800(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 64(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, a1
-; RV32I-NEXT: lw a0, 796(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 792(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 56(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 788(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 52(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 784(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 780(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s11
-; RV32I-NEXT: lw a0, 776(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, a1
-; RV32I-NEXT: lw a0, 772(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 644(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 768(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 764(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 752(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 748(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 736(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s2, s2, s5
-; RV32I-NEXT: xor s5, s7, s11
-; RV32I-NEXT: lw a0, 732(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, a1
-; RV32I-NEXT: lw a0, 724(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor s7, s7, s11
-; RV32I-NEXT: lw a0, 716(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a0, a1
-; RV32I-NEXT: xor a0, s2, s5
+; RV32I-NEXT: lw a2, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s11, a1, a2
+; RV32I-NEXT: xor a0, a0, s5
; RV32I-NEXT: sw a0, 652(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a0, s7, s11
+; RV32I-NEXT: xor a0, s8, s11
; RV32I-NEXT: sw a0, 648(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t1, 380(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a0, 276(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, a0, t1
+; RV32I-NEXT: lw a5, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 272(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: lw a0, 292(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 272(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, a1, a0
-; RV32I-NEXT: lw t2, 376(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a0, 244(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a0, t2
-; RV32I-NEXT: lw t5, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a0, 240(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, t5
-; RV32I-NEXT: xor s5, s11, s5
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: lw s0, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 248(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, s0
-; RV32I-NEXT: lw s2, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 216(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, s3, s2
-; RV32I-NEXT: xor a1, a1, s11
-; RV32I-NEXT: lw s3, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 232(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, s6, s3
-; RV32I-NEXT: xor a0, s5, a0
-; RV32I-NEXT: xor a1, a1, s11
-; RV32I-NEXT: lw s6, 356(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s5, 236(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, s5, s6
-; RV32I-NEXT: lw s7, 352(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 224(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, s8, s7
-; RV32I-NEXT: xor s5, s5, s11
-; RV32I-NEXT: lw s8, 348(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s10, 220(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, s10, s8
-; RV32I-NEXT: xor s5, s5, s11
-; RV32I-NEXT: lw s10, 344(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s11, 228(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, s11, s10
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, s5, s11
-; RV32I-NEXT: lw ra, 340(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s5, 288(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, s5, ra
-; RV32I-NEXT: lw s11, 696(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 212(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s11, s9, s11
-; RV32I-NEXT: xor s5, s5, s11
-; RV32I-NEXT: lw s11, 336(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 200(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s9, s9, s11
-; RV32I-NEXT: xor s5, s5, s9
-; RV32I-NEXT: lw s9, 332(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, s9
-; RV32I-NEXT: xor s4, s5, s4
-; RV32I-NEXT: lw s5, 328(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s1, s1, s5
+; RV32I-NEXT: lw a1, 268(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a1, a0
+; RV32I-NEXT: lw t1, 376(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 240(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a0, t1
+; RV32I-NEXT: lw t2, 372(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 236(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, t2
+; RV32I-NEXT: xor a2, s8, a2
+; RV32I-NEXT: xor a0, a1, a0
+; RV32I-NEXT: lw t3, 368(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 244(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, t3
+; RV32I-NEXT: lw s2, 364(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 212(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s0, s2
+; RV32I-NEXT: xor a1, a1, s8
+; RV32I-NEXT: lw s3, 360(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 228(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s0, s3
+; RV32I-NEXT: xor a0, a2, a0
+; RV32I-NEXT: xor a1, a1, s8
+; RV32I-NEXT: lw s4, 356(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 232(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, s4
+; RV32I-NEXT: lw s5, 352(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 220(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s0, s5
+; RV32I-NEXT: xor a2, a2, s8
+; RV32I-NEXT: lw s6, 348(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 216(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s0, s6
+; RV32I-NEXT: xor a2, a2, s8
+; RV32I-NEXT: lw s7, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, ra, s7
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, s4, s1
-; RV32I-NEXT: lw s1, 324(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t6, t6, s1
-; RV32I-NEXT: lw s4, 320(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t4, t4, s4
-; RV32I-NEXT: xor t4, t6, t4
-; RV32I-NEXT: lw t6, 316(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t3, t3, t6
-; RV32I-NEXT: xor t3, t4, t3
-; RV32I-NEXT: lw t4, 312(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, a7, t4
-; RV32I-NEXT: xor a7, t3, a7
-; RV32I-NEXT: lw t3, 692(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 204(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t3, a6, t3
-; RV32I-NEXT: xor a7, a7, t3
-; RV32I-NEXT: lw t3, 688(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 192(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t3, a6, t3
+; RV32I-NEXT: xor a1, a2, s8
+; RV32I-NEXT: lw s9, 340(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, s9
+; RV32I-NEXT: lw s10, 336(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 224(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s0, s10
+; RV32I-NEXT: xor a2, a2, s8
+; RV32I-NEXT: lw s11, 332(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s0, s11
+; RV32I-NEXT: xor a2, a2, s8
+; RV32I-NEXT: lw s8, 328(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s1, s1, s8
+; RV32I-NEXT: xor a2, a2, s1
+; RV32I-NEXT: lw ra, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 200(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s1, s0, ra
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a7, t3
-; RV32I-NEXT: lw t3, 308(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 196(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, t3
-; RV32I-NEXT: lw a7, 684(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, t0, a7
-; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: lw t0, 296(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 188(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, s1
+; RV32I-NEXT: lw s1, 320(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 196(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, s1
+; RV32I-NEXT: lw s0, 692(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 192(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s0, t6, s0
+; RV32I-NEXT: xor a1, a1, s0
+; RV32I-NEXT: lw s0, 688(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 188(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s0, t6, s0
+; RV32I-NEXT: xor a1, a1, s0
+; RV32I-NEXT: lw s0, 316(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t6, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t6, t6, s0
+; RV32I-NEXT: xor a1, a1, t6
+; RV32I-NEXT: lw t6, 684(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t5, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t6, t5, t6
+; RV32I-NEXT: xor a1, a1, t6
+; RV32I-NEXT: lw t6, 312(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t5, 176(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: xor a1, a1, t5
+; RV32I-NEXT: lw t5, 308(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, t4, t5
+; RV32I-NEXT: lw t4, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, t0, t4
+; RV32I-NEXT: xor a2, a2, t0
+; RV32I-NEXT: lw t4, 296(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t0, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, t0, t4
+; RV32I-NEXT: xor a2, a2, t0
+; RV32I-NEXT: lw t0, 304(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a7, a7, t0
-; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: lw a7, 304(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: xor a5, a6, a5
-; RV32I-NEXT: lw a6, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a2, a7
+; RV32I-NEXT: lw a7, 300(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a6, a6, a7
+; RV32I-NEXT: xor a2, a2, a6
+; RV32I-NEXT: lw a6, 676(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: lw a5, 676(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, a5
-; RV32I-NEXT: xor a3, a4, a3
+; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: lw a4, 672(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a2, a3, a2
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: lw a1, 668(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a3, 640(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a3, a1
@@ -19040,109 +19056,108 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: lw a3, 648(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: lw a2, 760(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a2, t1
+; RV32I-NEXT: lw a2, 768(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: lw a3, 292(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 756(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 764(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a4, a3
-; RV32I-NEXT: lw a4, 744(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, t2
-; RV32I-NEXT: lw a5, 740(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, t5
+; RV32I-NEXT: lw a4, 752(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, t1
+; RV32I-NEXT: lw a5, 748(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, t2
; RV32I-NEXT: xor a2, a3, a2
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a3, 300(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, s0
-; RV32I-NEXT: lw a5, 728(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 740(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, t3
+; RV32I-NEXT: lw a5, 732(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s2
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 720(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 724(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s3
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a4, 712(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, s6
+; RV32I-NEXT: lw a4, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, s4
+; RV32I-NEXT: lw a5, 712(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, s5
+; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: lw a5, 708(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, s7
+; RV32I-NEXT: and a5, a5, s6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: lw a5, 704(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, s8
+; RV32I-NEXT: and a5, a5, s7
+; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a3, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: lw a5, 824(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s10
-; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a3, 820(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, ra
-; RV32I-NEXT: lw a5, 816(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 696(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 812(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 820(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s11
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 808(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, s9
+; RV32I-NEXT: lw a5, 816(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, s8
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 804(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, s5
+; RV32I-NEXT: lw a5, 812(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, ra
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a4, 800(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 808(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s1
-; RV32I-NEXT: lw a5, 796(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, s4
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 792(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, t6
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 788(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, t4
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 784(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 804(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 692(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 780(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 800(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 688(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a3, 776(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, t3
-; RV32I-NEXT: lw a5, 772(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 796(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, s0
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 792(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 684(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 788(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, t6
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a3, 784(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, t5
+; RV32I-NEXT: lw a5, 780(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 680(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 768(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 776(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, t4
+; RV32I-NEXT: xor a3, a3, a5
+; RV32I-NEXT: lw a5, 772(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, t0
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 764(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 760(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 752(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 680(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 748(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 756(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 676(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 736(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 744(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 672(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: xor a3, a3, a5
; RV32I-NEXT: xor a0, a1, a0
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a1, 732(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 736(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a3, 668(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: lw a3, 724(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 728(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a4, 664(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 716(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 720(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a4, 660(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: xor a1, a1, a3
@@ -19150,12 +19165,12 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV32I-NEXT: srli a3, a3, 1
; RV32I-NEXT: xor a0, a3, a0
; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: lw a2, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 280(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: sw a0, 4(a2)
-; RV32I-NEXT: lw a0, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 204(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 8(a2)
-; RV32I-NEXT: lw a0, 700(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 696(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 12(a2)
; RV32I-NEXT: lw ra, 876(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 872(sp) # 4-byte Folded Reload
@@ -19217,7 +19232,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: .cfi_offset s9, -88
; RV64I-NEXT: .cfi_offset s10, -96
; RV64I-NEXT: .cfi_offset s11, -104
-; RV64I-NEXT: mv s5, a3
+; RV64I-NEXT: mv s6, a3
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: srli a5, a0, 24
; RV64I-NEXT: lui a4, 4080
@@ -19229,7 +19244,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: srli t1, a3, 40
; RV64I-NEXT: addi a5, a0, -256
-; RV64I-NEXT: lui s6, 16
+; RV64I-NEXT: lui s7, 16
; RV64I-NEXT: and t1, t1, a5
; RV64I-NEXT: srli t2, a3, 56
; RV64I-NEXT: or a7, t0, a7
@@ -19266,509 +19281,510 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: lui t3, 349525
; RV64I-NEXT: slli t1, t1, 2
; RV64I-NEXT: addi t3, t3, 1365
-; RV64I-NEXT: or t2, t2, t1
+; RV64I-NEXT: or t4, t2, t1
; RV64I-NEXT: slli t1, t3, 32
-; RV64I-NEXT: srli t4, t2, 1
+; RV64I-NEXT: srli t2, t4, 1
; RV64I-NEXT: add t1, t3, t1
-; RV64I-NEXT: and t3, t4, t1
-; RV64I-NEXT: srli t4, a2, 24
-; RV64I-NEXT: srli t5, a2, 8
-; RV64I-NEXT: and t4, t4, a4
-; RV64I-NEXT: and t5, t5, a6
-; RV64I-NEXT: or t4, t5, t4
-; RV64I-NEXT: srli t5, a2, 40
-; RV64I-NEXT: and t5, t5, a5
-; RV64I-NEXT: srli t6, a2, 56
-; RV64I-NEXT: or t5, t5, t6
-; RV64I-NEXT: and t6, a2, a4
-; RV64I-NEXT: slli t6, t6, 24
-; RV64I-NEXT: srliw s0, a2, 24
-; RV64I-NEXT: slli s0, s0, 32
-; RV64I-NEXT: and s1, a2, a5
-; RV64I-NEXT: slli s1, s1, 40
-; RV64I-NEXT: slli s2, a2, 56
+; RV64I-NEXT: and t3, t2, t1
+; RV64I-NEXT: srli t5, a2, 24
+; RV64I-NEXT: srli t6, a2, 8
+; RV64I-NEXT: and t5, t5, a4
+; RV64I-NEXT: and t6, t6, a6
+; RV64I-NEXT: or t5, t6, t5
+; RV64I-NEXT: srli t6, a2, 40
+; RV64I-NEXT: and t6, t6, a5
+; RV64I-NEXT: srli s0, a2, 56
; RV64I-NEXT: or t6, t6, s0
-; RV64I-NEXT: or s0, s2, s1
-; RV64I-NEXT: or t4, t4, t5
-; RV64I-NEXT: or t5, s0, t6
-; RV64I-NEXT: and t2, t2, t1
-; RV64I-NEXT: or t4, t5, t4
-; RV64I-NEXT: srli t5, t4, 4
-; RV64I-NEXT: and t4, t4, a7
+; RV64I-NEXT: and s0, a2, a4
+; RV64I-NEXT: slli s0, s0, 24
+; RV64I-NEXT: srliw s1, a2, 24
+; RV64I-NEXT: slli s1, s1, 32
+; RV64I-NEXT: and s2, a2, a5
+; RV64I-NEXT: slli s2, s2, 40
+; RV64I-NEXT: slli s3, a2, 56
+; RV64I-NEXT: or s0, s0, s1
+; RV64I-NEXT: or s1, s3, s2
+; RV64I-NEXT: or t5, t5, t6
+; RV64I-NEXT: or s0, s1, s0
+; RV64I-NEXT: and t4, t4, t1
+; RV64I-NEXT: or t5, s0, t5
+; RV64I-NEXT: srli t6, t5, 4
; RV64I-NEXT: and t5, t5, a7
-; RV64I-NEXT: slli t4, t4, 4
-; RV64I-NEXT: slli t2, t2, 1
-; RV64I-NEXT: or t4, t5, t4
-; RV64I-NEXT: srli t5, t4, 2
-; RV64I-NEXT: and t4, t4, t0
+; RV64I-NEXT: and t6, t6, a7
+; RV64I-NEXT: slli t5, t5, 4
+; RV64I-NEXT: slli t4, t4, 1
+; RV64I-NEXT: or t5, t6, t5
+; RV64I-NEXT: srli t6, t5, 2
; RV64I-NEXT: and t5, t5, t0
-; RV64I-NEXT: slli t4, t4, 2
-; RV64I-NEXT: or t2, t3, t2
-; RV64I-NEXT: or t3, t5, t4
-; RV64I-NEXT: srli t4, t3, 1
-; RV64I-NEXT: and t3, t3, t1
+; RV64I-NEXT: and t6, t6, t0
+; RV64I-NEXT: slli t5, t5, 2
+; RV64I-NEXT: or t3, t3, t4
+; RV64I-NEXT: or t4, t6, t5
+; RV64I-NEXT: srli t5, t4, 1
; RV64I-NEXT: and t4, t4, t1
-; RV64I-NEXT: slli t3, t3, 1
-; RV64I-NEXT: slli t5, t2, 1
-; RV64I-NEXT: or t4, t4, t3
-; RV64I-NEXT: andi t6, t4, 2
-; RV64I-NEXT: andi s0, t4, 1
-; RV64I-NEXT: seqz t6, t6
+; RV64I-NEXT: and t5, t5, t1
+; RV64I-NEXT: slli t4, t4, 1
+; RV64I-NEXT: slli t6, t3, 1
+; RV64I-NEXT: or t5, t5, t4
+; RV64I-NEXT: andi s0, t5, 2
+; RV64I-NEXT: andi s1, t5, 1
; RV64I-NEXT: seqz s0, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: and t5, t6, t5
-; RV64I-NEXT: and t6, s0, t2
-; RV64I-NEXT: slli s0, t2, 2
-; RV64I-NEXT: andi s1, t4, 4
; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: andi s2, t4, 8
+; RV64I-NEXT: addi s0, s0, -1
; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: and t6, s0, t6
+; RV64I-NEXT: and s0, s1, t3
+; RV64I-NEXT: slli s1, t3, 2
+; RV64I-NEXT: andi s2, t5, 4
; RV64I-NEXT: seqz s2, s2
-; RV64I-NEXT: slli s3, t2, 3
+; RV64I-NEXT: andi s3, t5, 8
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s0, s1, s0
-; RV64I-NEXT: and s1, s2, s3
-; RV64I-NEXT: xor t5, t6, t5
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: xor t5, t5, s0
-; RV64I-NEXT: andi t6, t4, 16
-; RV64I-NEXT: slli s0, t2, 4
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: andi s1, t4, 32
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: slli s1, t2, 5
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: and s0, s0, s1
-; RV64I-NEXT: andi s1, t4, 64
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: slli s1, t2, 6
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: and s0, s0, s1
-; RV64I-NEXT: andi s1, t4, 128
+; RV64I-NEXT: seqz s3, s3
+; RV64I-NEXT: slli s4, t3, 3
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: and s1, s2, s1
+; RV64I-NEXT: and s2, s3, s4
+; RV64I-NEXT: xor t6, s0, t6
+; RV64I-NEXT: xor s0, s1, s2
; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: slli s1, t2, 7
+; RV64I-NEXT: andi s0, t5, 16
+; RV64I-NEXT: slli s1, t3, 4
+; RV64I-NEXT: seqz s0, s0
; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: andi s2, t5, 32
; RV64I-NEXT: and s0, s0, s1
-; RV64I-NEXT: andi s1, t4, 256
-; RV64I-NEXT: slli s2, t2, 8
-; RV64I-NEXT: seqz s1, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: slli s2, t3, 5
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: andi s3, t4, 512
; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: slli s3, t2, 9
-; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: andi s2, t5, 64
; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: and s1, s2, s3
-; RV64I-NEXT: xor t6, t5, t6
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: slli s1, t2, 10
-; RV64I-NEXT: andi t5, t4, 1024
-; RV64I-NEXT: seqz s2, t5
-; RV64I-NEXT: li t5, 1
-; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli a0, t5, 11
-; RV64I-NEXT: sd a0, 424(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: slli s2, t3, 6
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: andi s2, t5, 128
; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: slli s2, t2, 11
+; RV64I-NEXT: slli s2, t3, 7
; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: slli s2, t2, 12
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: seqz s3, s3
-; RV64I-NEXT: lui a0, 2
-; RV64I-NEXT: addi s3, s3, -1
-; RV64I-NEXT: and s4, t4, a0
-; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: andi s2, t5, 256
+; RV64I-NEXT: slli s3, t3, 8
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: andi s4, t5, 512
+; RV64I-NEXT: and s2, s2, s3
; RV64I-NEXT: seqz s3, s4
-; RV64I-NEXT: slli s4, t2, 13
+; RV64I-NEXT: slli s4, t3, 9
; RV64I-NEXT: addi s3, s3, -1
; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: and s2, s3, s4
+; RV64I-NEXT: xor s0, t6, s0
; RV64I-NEXT: xor s1, s1, s2
-; RV64I-NEXT: lui a0, 4
-; RV64I-NEXT: slli s2, t2, 14
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: seqz s3, s3
-; RV64I-NEXT: lui a0, 8
+; RV64I-NEXT: slli s2, t3, 10
+; RV64I-NEXT: andi t6, t5, 1024
+; RV64I-NEXT: seqz s3, t6
+; RV64I-NEXT: li t6, 1
; RV64I-NEXT: addi s3, s3, -1
-; RV64I-NEXT: and s4, t4, a0
+; RV64I-NEXT: slli a0, t6, 11
+; RV64I-NEXT: sd a0, 424(sp) # 8-byte Folded Spill
; RV64I-NEXT: and s2, s3, s2
-; RV64I-NEXT: seqz s3, s4
-; RV64I-NEXT: slli s4, t2, 15
-; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: and s3, t5, a0
; RV64I-NEXT: xor s1, s1, s2
-; RV64I-NEXT: and s2, s3, s4
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: xor s0, s1, s2
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: slli s0, t2, 16
-; RV64I-NEXT: and s1, t4, s6
-; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: lui a0, 32
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: and s0, s1, s0
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: slli s2, t2, 17
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: lui a0, 64
+; RV64I-NEXT: seqz s2, s3
+; RV64I-NEXT: slli s3, t3, 11
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: lui a0, 1
+; RV64I-NEXT: slli s3, t3, 12
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: seqz s4, s4
+; RV64I-NEXT: lui a0, 2
+; RV64I-NEXT: addi s4, s4, -1
+; RV64I-NEXT: and s5, t5, a0
+; RV64I-NEXT: and s3, s4, s3
+; RV64I-NEXT: seqz s4, s5
+; RV64I-NEXT: slli s5, t3, 13
+; RV64I-NEXT: addi s4, s4, -1
+; RV64I-NEXT: xor s2, s2, s3
+; RV64I-NEXT: and s3, s4, s5
+; RV64I-NEXT: xor s2, s2, s3
+; RV64I-NEXT: lui a0, 4
+; RV64I-NEXT: slli s3, t3, 14
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: seqz s4, s4
+; RV64I-NEXT: lui a0, 8
+; RV64I-NEXT: addi s4, s4, -1
+; RV64I-NEXT: and s5, t5, a0
+; RV64I-NEXT: and s3, s4, s3
+; RV64I-NEXT: seqz s4, s5
+; RV64I-NEXT: slli s5, t3, 15
+; RV64I-NEXT: addi s4, s4, -1
+; RV64I-NEXT: xor s2, s2, s3
+; RV64I-NEXT: and s3, s4, s5
; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: and s1, t4, a0
-; RV64I-NEXT: slli s2, t2, 18
-; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: lui a0, 128
-; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: and s2, t4, a0
+; RV64I-NEXT: xor s1, s2, s3
; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: lui a0, 256
-; RV64I-NEXT: slli s2, t2, 19
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: slli s1, t3, 16
+; RV64I-NEXT: and s2, t5, s7
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: lui a0, 32
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: and s1, s2, s1
+; RV64I-NEXT: seqz s2, s3
+; RV64I-NEXT: slli s3, t3, 17
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: lui a0, 64
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: and s2, t5, a0
+; RV64I-NEXT: slli s3, t3, 18
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: lui s4, 128
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: and s3, t5, s4
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 20
+; RV64I-NEXT: lui a0, 256
+; RV64I-NEXT: slli s3, t3, 19
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 20
; RV64I-NEXT: lui a0, 512
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli s2, t2, 21
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: seqz s2, s3
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: slli s3, t3, 21
+; RV64I-NEXT: and s2, s2, s3
; RV64I-NEXT: lui a0, 1024
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: and s2, t5, a0
; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: and s1, t4, a0
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: lui a0, 2048
-; RV64I-NEXT: slli s1, t2, 22
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: and s0, s0, s1
; RV64I-NEXT: seqz s1, s2
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: lui s3, 4096
-; RV64I-NEXT: slli s2, t2, 23
-; RV64I-NEXT: and s3, t4, s3
+; RV64I-NEXT: lui a0, 2048
+; RV64I-NEXT: slli s2, t3, 22
+; RV64I-NEXT: and s3, t5, a0
; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 24
+; RV64I-NEXT: lui s4, 4096
+; RV64I-NEXT: slli s3, t3, 23
+; RV64I-NEXT: and s4, t5, s4
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 24
; RV64I-NEXT: lui a0, 8192
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: lui a0, 16384
-; RV64I-NEXT: slli s2, t2, 25
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 26
+; RV64I-NEXT: lui a0, 16384
+; RV64I-NEXT: slli s3, t3, 25
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 26
; RV64I-NEXT: lui a0, 32768
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: lui s3, 65536
-; RV64I-NEXT: slli s2, t2, 27
-; RV64I-NEXT: and s3, t4, s3
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s3, t2, 28
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: and s1, s2, s3
-; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: lui s4, 65536
+; RV64I-NEXT: slli s3, t3, 27
+; RV64I-NEXT: and s4, t5, s4
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s4, t3, 28
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: and s2, s3, s4
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: lui a0, 131072
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: and s0, t4, a0
-; RV64I-NEXT: seqz s0, s0
-; RV64I-NEXT: lui a0, 262144
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: and s1, t4, a0
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: and s1, t5, a0
; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: slli s2, t2, 29
-; RV64I-NEXT: and s0, s0, s2
+; RV64I-NEXT: lui a0, 262144
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli s2, t2, 30
-; RV64I-NEXT: sraiw s3, t4, 31
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, t5, a0
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: slli s3, t3, 29
+; RV64I-NEXT: and s1, s1, s3
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: slli s3, t3, 30
+; RV64I-NEXT: sraiw s4, t5, 31
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 31
+; RV64I-NEXT: slli s7, t6, 32
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, s7
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 31
-; RV64I-NEXT: slli s6, t5, 32
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, s6
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 33
+; RV64I-NEXT: slli a0, t6, 33
; RV64I-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 32
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: slli s3, t3, 32
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 33
+; RV64I-NEXT: slli s11, t6, 34
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, s11
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 33
-; RV64I-NEXT: slli s10, t5, 34
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, s10
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli s11, t5, 35
-; RV64I-NEXT: slli s2, t2, 34
-; RV64I-NEXT: and s3, t4, s11
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: slli s9, t6, 35
+; RV64I-NEXT: slli s3, t3, 34
+; RV64I-NEXT: and s4, t5, s9
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 35
+; RV64I-NEXT: slli s10, t6, 36
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, s10
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 35
-; RV64I-NEXT: slli ra, t5, 36
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, ra
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli s2, t2, 36
-; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: slli a0, t5, 37
+; RV64I-NEXT: slli s3, t3, 36
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: slli a0, t6, 37
; RV64I-NEXT: sd a0, 400(sp) # 8-byte Folded Spill
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: and s2, t5, a0
; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: and s1, t4, a0
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli s9, t5, 38
-; RV64I-NEXT: slli s1, t2, 37
-; RV64I-NEXT: and s2, t4, s9
-; RV64I-NEXT: and s0, s0, s1
; RV64I-NEXT: seqz s1, s2
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli s8, t5, 39
-; RV64I-NEXT: slli s2, t2, 38
-; RV64I-NEXT: and s3, t4, s8
+; RV64I-NEXT: slli a0, t6, 38
+; RV64I-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s2, t3, 37
+; RV64I-NEXT: and s3, t5, a0
; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 39
-; RV64I-NEXT: slli a0, t5, 40
-; RV64I-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 41
+; RV64I-NEXT: slli ra, t6, 39
+; RV64I-NEXT: slli s3, t3, 38
+; RV64I-NEXT: and s4, t5, ra
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 39
+; RV64I-NEXT: slli a0, t6, 40
; RV64I-NEXT: sd a0, 384(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 40
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 41
-; RV64I-NEXT: slli a0, t5, 42
+; RV64I-NEXT: slli a0, t6, 41
; RV64I-NEXT: sd a0, 376(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 43
+; RV64I-NEXT: slli s3, t3, 40
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 41
+; RV64I-NEXT: slli a0, t6, 42
; RV64I-NEXT: sd a0, 368(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 42
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 43
-; RV64I-NEXT: slli a0, t5, 44
+; RV64I-NEXT: slli a0, t6, 43
; RV64I-NEXT: sd a0, 360(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 45
+; RV64I-NEXT: slli s3, t3, 42
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 43
+; RV64I-NEXT: slli a0, t6, 44
; RV64I-NEXT: sd a0, 352(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 44
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s3, t2, 45
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: and s1, s2, s3
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: slli a0, t5, 46
-; RV64I-NEXT: sd a0, 336(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: and s0, t4, a0
-; RV64I-NEXT: seqz s0, s0
-; RV64I-NEXT: slli a0, t5, 47
+; RV64I-NEXT: slli a0, t6, 45
; RV64I-NEXT: sd a0, 344(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: and s1, t4, a0
-; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: slli s2, t2, 46
-; RV64I-NEXT: and s0, s0, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli s2, t2, 47
-; RV64I-NEXT: slli a0, t5, 48
+; RV64I-NEXT: slli s3, t3, 44
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s4, t3, 45
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: and s2, s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: slli a0, t6, 46
; RV64I-NEXT: sd a0, 328(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: and s2, t4, a0
; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: and s1, t5, a0
+; RV64I-NEXT: seqz s1, s1
+; RV64I-NEXT: slli a0, t6, 47
+; RV64I-NEXT: sd a0, 336(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 49
+; RV64I-NEXT: and s2, t5, a0
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: slli s3, t3, 46
+; RV64I-NEXT: and s1, s1, s3
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: slli s3, t3, 47
+; RV64I-NEXT: slli a0, t6, 48
; RV64I-NEXT: sd a0, 320(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 48
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 49
-; RV64I-NEXT: slli a0, t5, 50
+; RV64I-NEXT: slli a0, t6, 49
+; RV64I-NEXT: sd a0, 312(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s3, t3, 48
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 49
+; RV64I-NEXT: slli a0, t6, 50
; RV64I-NEXT: sd a0, 1000(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 51
-; RV64I-NEXT: sd a0, 1040(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 50
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 51
-; RV64I-NEXT: slli a0, t5, 52
+; RV64I-NEXT: slli a0, t6, 51
+; RV64I-NEXT: sd a0, 1040(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s3, t3, 50
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: xor s1, s1, s2
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s2, t3, 51
+; RV64I-NEXT: slli a0, t6, 52
; RV64I-NEXT: sd a0, 1032(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 53
-; RV64I-NEXT: sd a0, 1024(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 52
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 53
-; RV64I-NEXT: slli a0, t5, 54
-; RV64I-NEXT: sd a0, 1016(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, a0
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 55
-; RV64I-NEXT: sd a0, 1008(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 54
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
-; RV64I-NEXT: seqz s2, s3
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli s1, t2, 55
-; RV64I-NEXT: slli s7, t5, 56
-; RV64I-NEXT: and s1, s2, s1
-; RV64I-NEXT: and s2, t4, s7
-; RV64I-NEXT: sd s7, 304(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor s0, s0, s1
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: slli a0, t5, 57
-; RV64I-NEXT: sd a0, 288(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s2, t2, 56
-; RV64I-NEXT: and s3, t4, a0
-; RV64I-NEXT: and s1, s1, s2
+; RV64I-NEXT: and s2, s3, s2
+; RV64I-NEXT: and s3, t5, a0
+; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli a0, t5, 58
-; RV64I-NEXT: sd a0, 992(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s3, t2, 57
-; RV64I-NEXT: and s4, t4, a0
+; RV64I-NEXT: slli a0, t6, 53
+; RV64I-NEXT: sd a0, 1024(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s3, t3, 52
+; RV64I-NEXT: and s4, t5, a0
; RV64I-NEXT: and s2, s2, s3
; RV64I-NEXT: seqz s3, s4
; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: addi s3, s3, -1
-; RV64I-NEXT: slli s2, t2, 58
-; RV64I-NEXT: slli a0, t5, 59
-; RV64I-NEXT: sd a0, 984(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s2, t3, 53
+; RV64I-NEXT: slli a0, t6, 54
+; RV64I-NEXT: sd a0, 1016(sp) # 8-byte Folded Spill
; RV64I-NEXT: and s2, s3, s2
-; RV64I-NEXT: and s3, t4, a0
+; RV64I-NEXT: and s3, t5, a0
; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli a0, t5, 60
-; RV64I-NEXT: sd a0, 976(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s3, t2, 59
-; RV64I-NEXT: and s4, t4, a0
+; RV64I-NEXT: slli a0, t6, 55
+; RV64I-NEXT: sd a0, 1008(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s3, t3, 54
+; RV64I-NEXT: and s4, t5, a0
; RV64I-NEXT: and s2, s2, s3
; RV64I-NEXT: seqz s3, s4
; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: addi s3, s3, -1
-; RV64I-NEXT: slli s2, t2, 60
-; RV64I-NEXT: slli a0, t5, 61
-; RV64I-NEXT: sd a0, 960(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s2, t3, 55
+; RV64I-NEXT: slli s8, t6, 56
; RV64I-NEXT: and s2, s3, s2
-; RV64I-NEXT: and s3, t4, a0
+; RV64I-NEXT: and s3, t5, s8
+; RV64I-NEXT: sd s8, 296(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor s1, s1, s2
; RV64I-NEXT: seqz s2, s3
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: slli t5, t5, 62
-; RV64I-NEXT: sd t5, 968(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t4, t4, t5
-; RV64I-NEXT: slli t5, t2, 61
-; RV64I-NEXT: and t5, s2, t5
+; RV64I-NEXT: slli a0, t6, 57
+; RV64I-NEXT: sd a0, 280(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s3, t3, 56
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: and s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli a0, t6, 58
+; RV64I-NEXT: sd a0, 992(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s4, t3, 57
+; RV64I-NEXT: and s5, t5, a0
+; RV64I-NEXT: and s3, s3, s4
+; RV64I-NEXT: seqz s4, s5
+; RV64I-NEXT: xor s2, s2, s3
+; RV64I-NEXT: addi s4, s4, -1
+; RV64I-NEXT: slli s3, t3, 58
+; RV64I-NEXT: slli a0, t6, 59
+; RV64I-NEXT: sd a0, 984(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and s3, s4, s3
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: xor s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli a0, t6, 60
+; RV64I-NEXT: sd a0, 976(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s4, t3, 59
+; RV64I-NEXT: and s5, t5, a0
+; RV64I-NEXT: and s3, s3, s4
+; RV64I-NEXT: seqz s4, s5
+; RV64I-NEXT: xor s2, s2, s3
+; RV64I-NEXT: addi s4, s4, -1
+; RV64I-NEXT: slli s3, t3, 60
+; RV64I-NEXT: slli a0, t6, 61
+; RV64I-NEXT: sd a0, 968(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and s3, s4, s3
+; RV64I-NEXT: and s4, t5, a0
+; RV64I-NEXT: xor s2, s2, s3
+; RV64I-NEXT: seqz s3, s4
+; RV64I-NEXT: addi s3, s3, -1
+; RV64I-NEXT: slli s4, t3, 61
+; RV64I-NEXT: and s3, s3, s4
+; RV64I-NEXT: slli a0, t6, 62
+; RV64I-NEXT: sd a0, 960(sp) # 8-byte Folded Spill
+; RV64I-NEXT: xor t6, s2, s3
+; RV64I-NEXT: and t5, t5, a0
+; RV64I-NEXT: slli t3, t3, 62
+; RV64I-NEXT: seqz t5, t5
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: srli t4, t4, 63
+; RV64I-NEXT: and t3, t5, t3
; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: xor t5, s1, t5
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: srli t3, t3, 63
-; RV64I-NEXT: slli s1, t2, 62
-; RV64I-NEXT: and t4, t4, s1
-; RV64I-NEXT: seqz t3, t3
; RV64I-NEXT: slli t2, t2, 63
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: xor t4, t5, t4
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: xor t3, t6, s0
-; RV64I-NEXT: xor t2, t4, t2
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: xor t3, t6, t3
+; RV64I-NEXT: and t2, t4, t2
+; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: xor t2, t3, t2
+; RV64I-NEXT: xor t2, s0, t2
; RV64I-NEXT: srli t3, t2, 40
; RV64I-NEXT: and t3, t3, a5
; RV64I-NEXT: srli t4, t2, 56
@@ -20046,7 +20062,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: sd a7, 688(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 31
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: and a7, a2, s6
+; RV64I-NEXT: and a7, a2, s7
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: xor a4, a4, a5
@@ -20061,21 +20077,21 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: sd a7, 672(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 33
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: and a7, a2, s10
+; RV64I-NEXT: and a7, a2, s11
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 664(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 34
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: and a7, a2, s11
+; RV64I-NEXT: and a7, a2, s9
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 656(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 35
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: and a7, a2, ra
+; RV64I-NEXT: and a7, a2, s10
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
@@ -20090,77 +20106,78 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: sd a7, 640(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 37
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: and a7, a2, s9
+; RV64I-NEXT: ld t2, 392(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, t2
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 632(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 38
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: and a7, a2, s8
+; RV64I-NEXT: and a7, a2, ra
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: xor a4, a4, a5
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 624(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a5, a1, 39
-; RV64I-NEXT: ld t2, 392(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a6, a2, t2
+; RV64I-NEXT: ld t3, 384(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, a2, t3
; RV64I-NEXT: and a5, a7, a5
; RV64I-NEXT: seqz a6, a6
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 616(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 40
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld t3, 384(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a2, t3
+; RV64I-NEXT: ld t4, 376(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, t4
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 608(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 41
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld t4, 376(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a2, t4
+; RV64I-NEXT: ld t5, 368(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, t5
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 600(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 42
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld t5, 368(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a2, t5
+; RV64I-NEXT: ld t6, 360(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, t6
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 592(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 43
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld t6, 360(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a2, t6
+; RV64I-NEXT: ld s0, 352(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, s0
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 584(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 44
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld s0, 352(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a2, s0
+; RV64I-NEXT: ld s1, 344(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, s1
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 576(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 45
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld s1, 336(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a2, s1
+; RV64I-NEXT: ld s2, 328(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, s2
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 568(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 46
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld s3, 344(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 336(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a7, a2, s3
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
@@ -20168,16 +20185,16 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 560(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a5, a1, 47
-; RV64I-NEXT: ld s2, 328(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a6, a2, s2
+; RV64I-NEXT: ld s4, 320(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, a2, s4
; RV64I-NEXT: and a5, a7, a5
; RV64I-NEXT: seqz a6, a6
; RV64I-NEXT: addi a7, a6, -1
; RV64I-NEXT: sd a7, 552(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 48
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: ld s4, 320(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a2, s4
+; RV64I-NEXT: ld s5, 312(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a2, s5
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: addi a7, a6, -1
@@ -20232,7 +20249,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: sd a7, 496(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a1, 55
; RV64I-NEXT: and a6, a7, a6
-; RV64I-NEXT: and a7, a2, s7
+; RV64I-NEXT: and a7, a2, s8
; RV64I-NEXT: xor a5, a5, a6
; RV64I-NEXT: seqz a6, a7
; RV64I-NEXT: xor a4, a4, a5
@@ -20240,7 +20257,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: addi a6, a6, -1
; RV64I-NEXT: sd a6, 488(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a4, a1, 56
-; RV64I-NEXT: ld a7, 288(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a7, 280(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a5, a2, a7
; RV64I-NEXT: and a4, a6, a4
; RV64I-NEXT: seqz a5, a5
@@ -20272,7 +20289,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: sd a6, 456(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a5, a1, 60
; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: ld a6, 960(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a6, 968(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a6, a2, a6
; RV64I-NEXT: xor a4, a4, a5
; RV64I-NEXT: seqz a5, a6
@@ -20280,7 +20297,7 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: sd a6, 448(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a5, a1, 61
; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: ld a6, 968(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a6, 960(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a6, a2, a6
; RV64I-NEXT: xor a4, a4, a5
; RV64I-NEXT: seqz a5, a6
@@ -20295,288 +20312,288 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: sd a2, 432(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a1, a2, a1
-; RV64I-NEXT: andi a2, s5, 2
+; RV64I-NEXT: andi a2, s6, 2
; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: andi a5, s5, 1
+; RV64I-NEXT: andi a5, s6, 1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: slli a6, a3, 1
-; RV64I-NEXT: sd a6, 312(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a6, 304(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a6
; RV64I-NEXT: and a5, a5, a3
; RV64I-NEXT: xor a1, a4, a1
-; RV64I-NEXT: sd a1, 296(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a1, 288(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor a2, a5, a2
-; RV64I-NEXT: andi a1, s5, 4
-; RV64I-NEXT: andi a4, s5, 8
+; RV64I-NEXT: andi a1, s6, 4
+; RV64I-NEXT: andi a4, s6, 8
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: slli a5, a3, 2
-; RV64I-NEXT: sd a5, 280(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a5, 272(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a6, a3, 3
-; RV64I-NEXT: sd a6, 272(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a6, 264(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a1, a1, a5
; RV64I-NEXT: and a4, a4, a6
; RV64I-NEXT: xor a1, a1, a4
-; RV64I-NEXT: andi a4, s5, 16
+; RV64I-NEXT: andi a4, s6, 16
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: andi a4, s5, 32
+; RV64I-NEXT: andi a4, s6, 32
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a5, a3, 4
-; RV64I-NEXT: sd a5, 264(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a5, 256(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: slli a6, a3, 5
-; RV64I-NEXT: sd a6, 256(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a5, s5, 64
+; RV64I-NEXT: sd a6, 248(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a5, s6, 64
; RV64I-NEXT: and a4, a4, a6
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: slli a6, a3, 6
-; RV64I-NEXT: sd a6, 248(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a6, 240(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: and a4, a5, a6
; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: andi a4, s5, 128
+; RV64I-NEXT: andi a4, s6, 128
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: andi a4, s5, 256
+; RV64I-NEXT: andi a4, s6, 256
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a5, a3, 7
-; RV64I-NEXT: sd a5, 240(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a5, 232(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: slli a6, a3, 8
-; RV64I-NEXT: sd a6, 232(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a5, s5, 512
+; RV64I-NEXT: sd a6, 224(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a5, s6, 512
; RV64I-NEXT: and a4, a4, a6
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: slli a6, a3, 9
-; RV64I-NEXT: sd a6, 224(sp) # 8-byte Folded Spill
-; RV64I-NEXT: andi a4, s5, 1024
+; RV64I-NEXT: sd a6, 216(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a4, s6, 1024
; RV64I-NEXT: and a5, a5, a6
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: slli a6, a3, 10
-; RV64I-NEXT: sd a6, 216(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a6, 208(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: and a4, a4, a6
; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a0, a3, 11
; RV64I-NEXT: sd a0, 424(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: lui a5, 2
-; RV64I-NEXT: and a5, s5, a5
+; RV64I-NEXT: and a5, s6, a5
; RV64I-NEXT: slli a0, a3, 12
-; RV64I-NEXT: sd a0, 208(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 200(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: slli a0, a3, 13
-; RV64I-NEXT: sd a0, 200(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 192(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: and a4, a5, a0
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: lui a0, 4
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: lui a4, 8
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a0, a3, 14
-; RV64I-NEXT: sd a0, 192(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 184(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: lui a5, 16
-; RV64I-NEXT: and a5, s5, a5
+; RV64I-NEXT: and a5, s6, a5
; RV64I-NEXT: slli a0, a3, 15
-; RV64I-NEXT: sd a0, 184(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a0, 32
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: lui a4, 32
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: slli a0, a3, 16
-; RV64I-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: lui a5, 64
-; RV64I-NEXT: and a5, s5, a5
+; RV64I-NEXT: and a5, s6, a5
; RV64I-NEXT: slli a0, a3, 17
-; RV64I-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: slli a0, a3, 18
-; RV64I-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: and a4, a5, a0
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: lui a4, 128
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: lui a4, 256
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a0, a3, 19
-; RV64I-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: lui a5, 512
-; RV64I-NEXT: and a5, s5, a5
+; RV64I-NEXT: and a5, s6, a5
; RV64I-NEXT: slli a0, a3, 20
-; RV64I-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: lui a4, 1024
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: slli a0, a3, 21
-; RV64I-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: lui a5, 2048
-; RV64I-NEXT: and a5, s5, a5
+; RV64I-NEXT: and a5, s6, a5
; RV64I-NEXT: slli a0, a3, 22
-; RV64I-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: lui a4, 4096
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: slli a0, a3, 23
-; RV64I-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: slli a0, a3, 24
-; RV64I-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: lui a4, 8192
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: lui a4, 16384
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a0, a3, 25
-; RV64I-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: lui a5, 32768
-; RV64I-NEXT: and a5, s5, a5
+; RV64I-NEXT: and a5, s6, a5
; RV64I-NEXT: slli a0, a3, 26
-; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: lui a4, 65536
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: slli a0, a3, 27
-; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: lui a0, 131072
-; RV64I-NEXT: and a5, s5, a0
+; RV64I-NEXT: and a5, s6, a0
; RV64I-NEXT: slli a0, a3, 28
-; RV64I-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: lui a4, 262144
-; RV64I-NEXT: and a4, s5, a4
+; RV64I-NEXT: and a4, s6, a4
; RV64I-NEXT: slli a0, a3, 29
-; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: slli a0, a3, 30
-; RV64I-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sraiw a5, s5, 31
+; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sraiw a5, s6, 31
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: slli a0, a3, 31
-; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: and a4, a5, a0
; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, s5, s6
+; RV64I-NEXT: and a4, s6, s7
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and a4, s5, t0
+; RV64I-NEXT: and a4, s6, t0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a0, a3, 32
; RV64I-NEXT: sd a0, 408(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a5, s5, s10
+; RV64I-NEXT: and a5, s6, s11
; RV64I-NEXT: slli a0, a3, 33
-; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a4, s5, s11
+; RV64I-NEXT: and a4, s6, s9
; RV64I-NEXT: slli a0, a3, 34
-; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a5, s5, ra
+; RV64I-NEXT: and a5, s6, s10
; RV64I-NEXT: slli a0, a3, 35
-; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a4, s5, t1
+; RV64I-NEXT: and a4, s6, t1
; RV64I-NEXT: slli a0, a3, 36
; RV64I-NEXT: sd a0, 400(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a5, s5, s9
+; RV64I-NEXT: and a5, s6, t2
; RV64I-NEXT: slli a0, a3, 37
-; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
@@ -20585,49 +20602,49 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: and a4, a5, a0
; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, s5, s8
+; RV64I-NEXT: and a4, s6, ra
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: seqz a2, a4
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and a4, s5, t2
+; RV64I-NEXT: and a4, s6, t3
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: slli a0, a3, 39
-; RV64I-NEXT: sd a0, 392(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 384(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a2, a2, a0
; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a5, s5, t3
+; RV64I-NEXT: and a5, s6, t4
; RV64I-NEXT: slli a0, a3, 40
-; RV64I-NEXT: sd a0, 384(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 376(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a4, a4, a0
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a4, s5, t4
+; RV64I-NEXT: and a4, s6, t5
; RV64I-NEXT: slli a0, a3, 41
-; RV64I-NEXT: sd a0, 376(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd a0, 368(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a5, a5, a0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a5, s5, t5
+; RV64I-NEXT: and a5, s6, t6
; RV64I-NEXT: slli ra, a3, 42
; RV64I-NEXT: and a4, a4, ra
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a4, s5, t6
+; RV64I-NEXT: and a4, s6, s0
; RV64I-NEXT: slli s11, a3, 43
; RV64I-NEXT: and a5, a5, s11
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and a5, s5, s0
+; RV64I-NEXT: and a5, s6, s1
; RV64I-NEXT: slli s10, a3, 44
; RV64I-NEXT: and a4, a4, s10
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a4, s5, s1
+; RV64I-NEXT: and a4, s6, s2
; RV64I-NEXT: slli s9, a3, 45
; RV64I-NEXT: and a5, a5, s9
; RV64I-NEXT: seqz a4, a4
@@ -20636,58 +20653,58 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: and a4, a4, s8
; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, s5, s3
+; RV64I-NEXT: and a4, s6, s3
; RV64I-NEXT: xor s3, a1, a2
; RV64I-NEXT: seqz a1, a4
; RV64I-NEXT: addi a1, a1, -1
-; RV64I-NEXT: and a2, s5, s2
+; RV64I-NEXT: and a2, s6, s4
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: slli s7, a3, 47
; RV64I-NEXT: and a1, a1, s7
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and a4, s5, s4
+; RV64I-NEXT: and a4, s6, s5
; RV64I-NEXT: slli s4, a3, 48
; RV64I-NEXT: and a2, a2, s4
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: ld a0, 1000(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a2, s5, a0
-; RV64I-NEXT: slli s6, a3, 49
-; RV64I-NEXT: and a4, a4, s6
+; RV64I-NEXT: and a2, s6, a0
+; RV64I-NEXT: slli s5, a3, 49
+; RV64I-NEXT: and a4, a4, s5
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: xor a1, a1, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: ld a0, 1040(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: slli s2, a3, 50
; RV64I-NEXT: and a2, a2, s2
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: ld a0, 1032(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a2, s5, a0
+; RV64I-NEXT: and a2, s6, a0
; RV64I-NEXT: slli s1, a3, 51
; RV64I-NEXT: and a4, a4, s1
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: xor a1, a1, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: ld a0, 1024(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: slli s0, a3, 52
; RV64I-NEXT: and a2, a2, s0
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: ld a0, 1016(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a2, s5, a0
+; RV64I-NEXT: and a2, s6, a0
; RV64I-NEXT: slli t5, a3, 53
; RV64I-NEXT: and a4, a4, t5
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: xor a1, a1, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: ld a0, 1008(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: slli t4, a3, 54
; RV64I-NEXT: and a2, a2, t4
; RV64I-NEXT: seqz a4, a4
@@ -20696,252 +20713,252 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: and a2, a4, t3
; RV64I-NEXT: xor t2, a1, a2
-; RV64I-NEXT: ld a0, 304(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a1, s5, a0
+; RV64I-NEXT: ld a0, 296(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a1, s6, a0
; RV64I-NEXT: seqz a1, a1
-; RV64I-NEXT: and a2, s5, a7
+; RV64I-NEXT: and a2, s6, a7
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: ld t6, 944(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a1, a1, t6
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: ld a0, 992(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: slli t1, a3, 57
; RV64I-NEXT: and a2, a2, t1
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: ld a0, 984(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a2, s5, a0
+; RV64I-NEXT: and a2, s6, a0
; RV64I-NEXT: slli t0, a3, 58
; RV64I-NEXT: and a4, a4, t0
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: xor a1, a1, a4
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: ld a0, 976(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, s5, a0
+; RV64I-NEXT: and a4, s6, a0
; RV64I-NEXT: slli a7, a3, 59
; RV64I-NEXT: and a2, a2, a7
; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: addi a2, a4, -1
-; RV64I-NEXT: ld a0, 960(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a0, s5, a0
+; RV64I-NEXT: ld a0, 968(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a0, s6, a0
; RV64I-NEXT: slli a6, a3, 60
; RV64I-NEXT: and a2, a2, a6
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: xor a2, a1, a2
; RV64I-NEXT: addi a1, a0, -1
-; RV64I-NEXT: ld a0, 968(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a0, s5, a0
+; RV64I-NEXT: ld a0, 960(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a0, s6, a0
; RV64I-NEXT: slli a5, a3, 61
; RV64I-NEXT: and a1, a1, a5
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: xor a2, a2, a1
; RV64I-NEXT: addi a1, a0, -1
-; RV64I-NEXT: srli s5, s5, 63
+; RV64I-NEXT: srli s6, s6, 63
; RV64I-NEXT: slli a4, a3, 62
; RV64I-NEXT: and a0, a1, a4
-; RV64I-NEXT: seqz a1, s5
-; RV64I-NEXT: addi s5, a1, -1
+; RV64I-NEXT: seqz a1, s6
+; RV64I-NEXT: addi s6, a1, -1
; RV64I-NEXT: slli a1, a3, 63
; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: and a2, s5, a1
+; RV64I-NEXT: and a2, s6, a1
; RV64I-NEXT: xor t2, s3, t2
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: ld a2, 416(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 296(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 288(sp) # 8-byte Folded Reload
; RV64I-NEXT: xor a2, a2, s3
; RV64I-NEXT: sd a2, 1040(sp) # 8-byte Folded Spill
; RV64I-NEXT: xor t2, t2, a0
; RV64I-NEXT: ld a0, 936(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a2, 312(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld a2, 304(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ld a2, 928(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: ld a3, 920(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 280(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 272(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 912(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 272(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 264(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 904(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 264(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 256(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 896(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 256(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 248(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 888(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 248(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 240(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 880(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 240(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 232(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 872(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 232(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 224(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 864(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 224(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 216(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 856(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 216(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 208(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 848(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 424(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 840(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 208(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 200(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 832(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 200(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 192(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 824(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 192(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 184(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 816(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 184(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 176(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 808(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 176(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 168(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 800(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 168(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 160(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 792(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 160(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 152(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 784(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 152(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 144(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 776(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 768(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 760(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 752(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 744(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 736(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 96(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 728(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 720(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 712(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 704(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 696(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 688(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 680(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 408(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 672(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 664(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 656(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 648(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 400(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 400(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 640(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 392(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 632(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
+; RV64I-NEXT: ld s6, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 624(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 392(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 384(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: ld s3, 616(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 384(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 376(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 608(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 376(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s5
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: ld s6, 368(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and s6, s3, s6
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 600(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, ra
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: and s6, s3, ra
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 592(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s11
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: and s6, s3, s11
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 584(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s10
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: and s6, s3, s10
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 576(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s9
-; RV64I-NEXT: xor a3, a3, s5
+; RV64I-NEXT: and s6, s3, s9
+; RV64I-NEXT: xor a3, a3, s6
; RV64I-NEXT: ld s3, 568(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s5, s3, s8
+; RV64I-NEXT: and s6, s3, s8
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: xor a2, a3, s5
+; RV64I-NEXT: xor a2, a3, s6
; RV64I-NEXT: ld a3, 560(sp) # 8-byte Folded Reload
; RV64I-NEXT: and a3, a3, s7
; RV64I-NEXT: ld s3, 552(sp) # 8-byte Folded Reload
; RV64I-NEXT: and s4, s3, s4
; RV64I-NEXT: xor a3, a3, s4
; RV64I-NEXT: ld s3, 544(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and s3, s3, s6
+; RV64I-NEXT: and s3, s3, s5
; RV64I-NEXT: xor a3, a3, s3
; RV64I-NEXT: ld s3, 536(sp) # 8-byte Folded Reload
; RV64I-NEXT: and s2, s3, s2
@@ -25881,21 +25898,21 @@ define i128 @clmul_i128(i128 %x, i128 %y) {
define i128 @clmul_i128_zext(i64 %x, i64 %y) {
; RV32I-LABEL: clmul_i128_zext:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -544
-; RV32I-NEXT: .cfi_def_cfa_offset 544
-; RV32I-NEXT: sw ra, 540(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 536(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 532(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 528(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 524(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s4, 520(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s5, 516(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s6, 512(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s7, 508(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s8, 504(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s9, 500(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s10, 496(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s11, 492(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi sp, sp, -560
+; RV32I-NEXT: .cfi_def_cfa_offset 560
+; RV32I-NEXT: sw ra, 556(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 552(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 548(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 544(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 540(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 536(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s5, 532(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s6, 528(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s7, 524(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s8, 520(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s9, 516(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s10, 512(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s11, 508(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
@@ -25909,73 +25926,74 @@ define i128 @clmul_i128_zext(i64 %x, i64 %y) {
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: .cfi_offset s10, -48
; RV32I-NEXT: .cfi_offset s11, -52
-; RV32I-NEXT: mv t6, a4
-; RV32I-NEXT: mv t2, a2
-; RV32I-NEXT: mv s6, a1
-; RV32I-NEXT: sw a0, 480(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s2, a4
+; RV32I-NEXT: mv s1, a2
+; RV32I-NEXT: mv s4, a1
+; RV32I-NEXT: sw a0, 496(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: srli a0, a2, 8
-; RV32I-NEXT: addi s10, a1, -256
-; RV32I-NEXT: lui s1, 16
-; RV32I-NEXT: and a0, a0, s10
+; RV32I-NEXT: addi s9, a1, -256
+; RV32I-NEXT: lui t0, 16
+; RV32I-NEXT: and a0, a0, s9
; RV32I-NEXT: srli a1, a2, 24
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: and a1, a2, s10
+; RV32I-NEXT: and a1, a2, s9
; RV32I-NEXT: slli a1, a1, 8
-; RV32I-NEXT: slli a2, a2, 24
-; RV32I-NEXT: sw a2, 476(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a1, a2, a1
+; RV32I-NEXT: slli a4, a2, 24
+; RV32I-NEXT: sw a4, 492(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: addi s5, a4, -241
+; RV32I-NEXT: addi s6, a4, -241
; RV32I-NEXT: srli a1, a0, 4
-; RV32I-NEXT: and a0, a0, s5
-; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: and a0, a0, s6
+; RV32I-NEXT: and a1, a1, s6
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: addi s7, a1, 819
-; RV32I-NEXT: and a1, a4, s7
+; RV32I-NEXT: and a4, a4, s7
; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: slli a4, a0, 2
+; RV32I-NEXT: slli a1, a0, 2
; RV32I-NEXT: lui a0, 349525
-; RV32I-NEXT: or a1, a1, a4
-; RV32I-NEXT: addi s0, a0, 1365
+; RV32I-NEXT: or a1, a4, a1
+; RV32I-NEXT: addi t3, a0, 1365
; RV32I-NEXT: srli a4, a1, 1
-; RV32I-NEXT: and a1, a1, s0
-; RV32I-NEXT: and a4, a4, s0
+; RV32I-NEXT: sw a4, 484(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a1, a1, t3
+; RV32I-NEXT: and a4, a4, t3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or t1, a4, a1
; RV32I-NEXT: srli a1, t1, 8
-; RV32I-NEXT: and a1, a1, s10
+; RV32I-NEXT: and a1, a1, s9
; RV32I-NEXT: srli a4, t1, 24
-; RV32I-NEXT: and a5, t1, s10
+; RV32I-NEXT: and a5, t1, s9
; RV32I-NEXT: slli a6, t1, 24
-; RV32I-NEXT: sw a6, 468(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a6, 480(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a5, 8
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: or a4, a6, a5
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 4
-; RV32I-NEXT: and a1, a1, s5
-; RV32I-NEXT: and a4, a4, s5
+; RV32I-NEXT: and a1, a1, s6
+; RV32I-NEXT: and a4, a4, s6
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a4, a1
-; RV32I-NEXT: srli a4, t6, 8
+; RV32I-NEXT: srli a4, s2, 8
; RV32I-NEXT: srli a5, a1, 2
-; RV32I-NEXT: and a4, a4, s10
-; RV32I-NEXT: srli a6, t6, 24
-; RV32I-NEXT: and a7, t6, s10
+; RV32I-NEXT: and a4, a4, s9
+; RV32I-NEXT: srli a6, s2, 24
+; RV32I-NEXT: and a7, s2, s9
; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: slli t0, t6, 24
+; RV32I-NEXT: slli t2, s2, 24
; RV32I-NEXT: or a4, a4, a6
-; RV32I-NEXT: or a6, t0, a7
+; RV32I-NEXT: or a6, t2, a7
; RV32I-NEXT: and a5, a5, s7
; RV32I-NEXT: or a4, a6, a4
; RV32I-NEXT: srli a6, a4, 4
-; RV32I-NEXT: and a4, a4, s5
-; RV32I-NEXT: and a6, a6, s5
+; RV32I-NEXT: and a4, a4, s6
+; RV32I-NEXT: and a6, a6, s6
; RV32I-NEXT: slli a4, a4, 4
; RV32I-NEXT: and a1, a1, s7
; RV32I-NEXT: or a4, a6, a4
@@ -25986,761 +26004,763 @@ define i128 @clmul_i128_zext(i64 %x, i64 %y) {
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a4, a6, a4
; RV32I-NEXT: srli a6, a4, 1
-; RV32I-NEXT: and a4, a4, s0
-; RV32I-NEXT: and a6, a6, s0
+; RV32I-NEXT: mv a7, t3
+; RV32I-NEXT: and a4, a4, t3
+; RV32I-NEXT: and a6, a6, t3
; RV32I-NEXT: slli a4, a4, 1
-; RV32I-NEXT: sw a4, 464(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 460(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a1, a5, a1
-; RV32I-NEXT: or s2, a6, a4
+; RV32I-NEXT: or t3, a6, a4
; RV32I-NEXT: srli a4, a1, 1
-; RV32I-NEXT: srli a5, s2, 8
-; RV32I-NEXT: and a4, a4, s0
-; RV32I-NEXT: and a5, a5, s10
-; RV32I-NEXT: srli a6, s2, 24
-; RV32I-NEXT: and a7, s2, s10
-; RV32I-NEXT: slli t0, s2, 24
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: or a5, a5, a6
-; RV32I-NEXT: or a6, t0, a7
-; RV32I-NEXT: and a1, a1, s0
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: srli a6, a5, 4
-; RV32I-NEXT: and a5, a5, s5
-; RV32I-NEXT: and a6, a6, s5
+; RV32I-NEXT: srli a5, t3, 8
+; RV32I-NEXT: and a6, a4, a7
+; RV32I-NEXT: mv t6, a7
+; RV32I-NEXT: and a5, a5, s9
+; RV32I-NEXT: srli a7, t3, 24
+; RV32I-NEXT: and t2, t3, s9
+; RV32I-NEXT: slli t4, t3, 24
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: or a5, a5, a7
+; RV32I-NEXT: or a7, t4, t2
+; RV32I-NEXT: and a1, a1, t6
+; RV32I-NEXT: or a5, a7, a5
+; RV32I-NEXT: srli a7, a5, 4
+; RV32I-NEXT: and a5, a5, s6
+; RV32I-NEXT: and a7, a7, s6
; RV32I-NEXT: slli a5, a5, 4
; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: srli a6, a5, 2
+; RV32I-NEXT: or a5, a7, a5
+; RV32I-NEXT: srli a7, a5, 2
; RV32I-NEXT: and a5, a5, s7
-; RV32I-NEXT: and a6, a6, s7
+; RV32I-NEXT: and a7, a7, s7
; RV32I-NEXT: slli a5, a5, 2
-; RV32I-NEXT: or t0, a4, a1
-; RV32I-NEXT: or a1, a6, a5
-; RV32I-NEXT: srli a4, a1, 1
-; RV32I-NEXT: and a1, a1, s0
-; RV32I-NEXT: and a4, a4, s0
+; RV32I-NEXT: or t2, a6, a1
+; RV32I-NEXT: or a1, a7, a5
+; RV32I-NEXT: srli a5, a1, 1
+; RV32I-NEXT: and a1, a1, t6
+; RV32I-NEXT: and a5, a5, t6
; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: slli a5, t0, 1
-; RV32I-NEXT: or t3, a4, a1
-; RV32I-NEXT: andi a4, t3, 2
-; RV32I-NEXT: andi a6, t3, 1
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: and a5, a6, t0
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: andi a5, t3, 4
-; RV32I-NEXT: slli a6, t0, 2
+; RV32I-NEXT: slli a6, t2, 1
+; RV32I-NEXT: or t4, a5, a1
+; RV32I-NEXT: andi a5, t4, 2
+; RV32I-NEXT: andi a7, t4, 1
; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: seqz a7, a7
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: andi a7, t3, 8
+; RV32I-NEXT: addi a7, a7, -1
; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, t0, 3
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 16
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, t0, 4
+; RV32I-NEXT: and a6, a7, t2
+; RV32I-NEXT: xor a5, a6, a5
+; RV32I-NEXT: andi a6, t4, 4
+; RV32I-NEXT: slli a7, t2, 2
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: andi t5, t4, 8
; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 32
-; RV32I-NEXT: slli t4, t0, 5
-; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: slli t5, t2, 3
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: andi t5, t3, 64
-; RV32I-NEXT: and a7, a7, t4
-; RV32I-NEXT: seqz t4, t5
-; RV32I-NEXT: slli t5, t0, 6
-; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: andi t5, t4, 16
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and a7, t4, t5
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: xor a5, a6, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: andi a5, t3, 128
-; RV32I-NEXT: slli a6, t0, 7
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: andi a7, t3, 256
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, t0, 8
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 512
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: slli t5, t2, 4
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: andi t5, t4, 32
+; RV32I-NEXT: slli s0, t2, 5
+; RV32I-NEXT: seqz t5, t5
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: andi s3, t4, 64
+; RV32I-NEXT: and t5, t5, s0
+; RV32I-NEXT: seqz s0, s3
+; RV32I-NEXT: slli s3, t2, 6
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: xor a7, a7, t5
+; RV32I-NEXT: and t5, s0, s3
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, t0, 9
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 1024
+; RV32I-NEXT: xor a6, a7, t5
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, t0, 10
+; RV32I-NEXT: andi a6, t4, 128
+; RV32I-NEXT: slli a7, t2, 7
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: andi t5, t4, 256
; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: li a7, 1
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: slli s3, a7, 11
-; RV32I-NEXT: slli a6, t0, 11
-; RV32I-NEXT: and a7, t3, s3
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: lui a2, 1
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and t4, t3, a2
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: seqz a7, t4
-; RV32I-NEXT: slli t4, t0, 12
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: slli t5, t2, 8
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and a7, a7, t4
-; RV32I-NEXT: lui a2, 2
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: andi t5, t4, 512
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and a7, t3, a2
-; RV32I-NEXT: slli t4, t0, 13
-; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: slli t5, t2, 9
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: lui a2, 4
-; RV32I-NEXT: and a7, a7, t4
-; RV32I-NEXT: and t4, t3, a2
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: andi t5, t4, 1024
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: seqz a7, t4
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: slli t5, t2, 10
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: lui a2, 8
-; RV32I-NEXT: slli t4, t0, 14
-; RV32I-NEXT: and t5, t3, a2
-; RV32I-NEXT: and a7, a7, t4
-; RV32I-NEXT: seqz t4, t5
-; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t5, t0, 15
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: li t5, 1
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and a7, t4, t5
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: xor a5, a6, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, t3, s1
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lui a2, 32
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, t3, a2
-; RV32I-NEXT: lui s11, 32
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: slli a7, t0, 16
-; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t0, 17
-; RV32I-NEXT: lui a2, 64
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: and a7, t3, a2
-; RV32I-NEXT: lui s9, 64
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui a2, 128
-; RV32I-NEXT: slli a7, t0, 18
-; RV32I-NEXT: and t4, t3, a2
-; RV32I-NEXT: lui t5, 128
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, t4
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, t0, 19
-; RV32I-NEXT: lui a2, 256
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, t3, a2
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui a2, 512
-; RV32I-NEXT: slli a7, t0, 20
-; RV32I-NEXT: and t4, t3, a2
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, t4
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli t4, t0, 21
+; RV32I-NEXT: slli s11, t5, 11
+; RV32I-NEXT: slli a7, t2, 11
+; RV32I-NEXT: and t5, t4, s11
+; RV32I-NEXT: seqz t5, t5
+; RV32I-NEXT: lui s0, 1
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: and s0, t4, s0
+; RV32I-NEXT: and a7, t5, a7
+; RV32I-NEXT: seqz t5, s0
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: lui s3, 2
+; RV32I-NEXT: slli s0, t2, 12
+; RV32I-NEXT: and s3, t4, s3
+; RV32I-NEXT: and t5, t5, s0
+; RV32I-NEXT: seqz s0, s3
+; RV32I-NEXT: xor a7, a7, t5
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: slli t5, t2, 13
+; RV32I-NEXT: lui s3, 4
+; RV32I-NEXT: and t5, s0, t5
+; RV32I-NEXT: and s0, t4, s3
+; RV32I-NEXT: xor a7, a7, t5
+; RV32I-NEXT: seqz t5, s0
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: lui s3, 8
+; RV32I-NEXT: slli s0, t2, 14
+; RV32I-NEXT: and s3, t4, s3
+; RV32I-NEXT: and t5, t5, s0
+; RV32I-NEXT: seqz s0, s3
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: slli s3, t2, 15
+; RV32I-NEXT: xor a7, a7, t5
+; RV32I-NEXT: and t5, s0, s3
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, t4
+; RV32I-NEXT: xor a6, a7, t5
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lui a2, 1024
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, t3, a2
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lui a2, 2048
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, t3, a2
+; RV32I-NEXT: and a6, t4, t0
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: slli a7, t0, 22
-; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t0, 23
-; RV32I-NEXT: lui a2, 4096
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: and a7, t3, a2
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui a2, 8192
-; RV32I-NEXT: slli a7, t0, 24
-; RV32I-NEXT: and t4, t3, a2
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, t4
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, t0, 25
-; RV32I-NEXT: lui a2, 16384
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, t3, a2
-; RV32I-NEXT: lui ra, 16384
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: lui a7, 32
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui a2, 32768
-; RV32I-NEXT: slli a7, t0, 26
-; RV32I-NEXT: and t4, t3, a2
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, t4
-; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: and a7, t4, a7
+; RV32I-NEXT: lui s8, 32
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: slli t5, t2, 16
+; RV32I-NEXT: and a6, a6, t5
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, t0, 27
-; RV32I-NEXT: lui a2, 65536
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, t3, a2
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t0, 28
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a2, 131072
+; RV32I-NEXT: slli t5, t2, 17
+; RV32I-NEXT: lui s0, 64
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: and t5, t4, s0
+; RV32I-NEXT: lui s10, 64
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui s0, 128
+; RV32I-NEXT: slli t5, t2, 18
+; RV32I-NEXT: and s0, t4, s0
+; RV32I-NEXT: lui s5, 128
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: seqz t5, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: slli a7, t2, 19
+; RV32I-NEXT: lui s0, 256
+; RV32I-NEXT: and a7, t5, a7
+; RV32I-NEXT: and t5, t4, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui s0, 512
+; RV32I-NEXT: slli t5, t2, 20
+; RV32I-NEXT: and s0, t4, s0
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: seqz t5, s0
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: slli s0, t2, 21
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: and a7, t5, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lui a7, 1024
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, t3, a2
+; RV32I-NEXT: and a6, t4, a7
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: lui a2, 262144
+; RV32I-NEXT: lui a7, 2048
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a7, t3, a2
+; RV32I-NEXT: and a7, t4, a7
; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: slli t3, t0, 29
-; RV32I-NEXT: and a6, a6, t3
+; RV32I-NEXT: slli t5, t2, 22
+; RV32I-NEXT: and a6, a6, t5
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t5, t2, 23
+; RV32I-NEXT: lui s0, 4096
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: and t5, t4, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui s0, 8192
+; RV32I-NEXT: slli t5, t2, 24
+; RV32I-NEXT: and s0, t4, s0
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: seqz t5, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: slli a7, t2, 25
+; RV32I-NEXT: lui s0, 16384
+; RV32I-NEXT: and a7, t5, a7
+; RV32I-NEXT: and t5, t4, s0
+; RV32I-NEXT: lui ra, 16384
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t5
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui s0, 32768
+; RV32I-NEXT: slli t5, t2, 26
+; RV32I-NEXT: and s0, t4, s0
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: seqz t5, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: slli a7, t2, 27
+; RV32I-NEXT: lui s0, 65536
+; RV32I-NEXT: and a7, t5, a7
+; RV32I-NEXT: and t5, t4, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t5
; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui s0, 131072
+; RV32I-NEXT: slli t5, t2, 28
+; RV32I-NEXT: and s0, t4, s0
+; RV32I-NEXT: and a7, a7, t5
+; RV32I-NEXT: seqz t5, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: slli a7, t2, 29
+; RV32I-NEXT: lui s0, 262144
+; RV32I-NEXT: and a7, t5, a7
+; RV32I-NEXT: and t4, t4, s0
+; RV32I-NEXT: slli t2, t2, 30
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: srli a1, a1, 31
-; RV32I-NEXT: slli t3, t0, 30
-; RV32I-NEXT: and a7, a7, t3
+; RV32I-NEXT: and t2, t4, t2
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: slli t0, t0, 31
+; RV32I-NEXT: slli a4, a4, 31
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and a1, a1, t0
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: xor a1, a6, a1
+; RV32I-NEXT: xor a7, a7, t2
+; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: xor a4, a5, a6
+; RV32I-NEXT: xor a1, a7, a1
; RV32I-NEXT: xor a1, a4, a1
; RV32I-NEXT: srli a4, a1, 8
-; RV32I-NEXT: and a4, a4, s10
+; RV32I-NEXT: and a4, a4, s9
; RV32I-NEXT: srli a5, a1, 24
-; RV32I-NEXT: and a6, a1, s10
+; RV32I-NEXT: and a6, a1, s9
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: slli a6, a6, 8
; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: srli a4, a1, 4
-; RV32I-NEXT: and a4, a4, s5
-; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: and a4, a4, s6
+; RV32I-NEXT: and a1, a1, s6
; RV32I-NEXT: slli a1, a1, 4
-; RV32I-NEXT: srli a5, s6, 8
+; RV32I-NEXT: srli a5, s4, 8
; RV32I-NEXT: or a1, a4, a1
-; RV32I-NEXT: and a4, a5, s10
+; RV32I-NEXT: and a4, a5, s9
; RV32I-NEXT: srli a5, a1, 2
-; RV32I-NEXT: srli a6, s6, 24
+; RV32I-NEXT: srli a6, s4, 24
; RV32I-NEXT: or a4, a4, a6
; RV32I-NEXT: and a5, a5, s7
; RV32I-NEXT: and a1, a1, s7
-; RV32I-NEXT: and a6, s6, s10
+; RV32I-NEXT: and a6, s4, s9
; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: slli a2, s6, 24
-; RV32I-NEXT: sw a2, 472(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, s4, 24
+; RV32I-NEXT: sw a7, 488(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: or a6, a2, a6
+; RV32I-NEXT: or a6, a7, a6
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a4, a6, a4
; RV32I-NEXT: srli a5, a4, 4
-; RV32I-NEXT: and a4, a4, s5
-; RV32I-NEXT: and a5, a5, s5
+; RV32I-NEXT: and a4, a4, s6
+; RV32I-NEXT: and a5, a5, s6
; RV32I-NEXT: slli a4, a4, 4
; RV32I-NEXT: or a4, a5, a4
-; RV32I-NEXT: addi a2, a0, 1364
-; RV32I-NEXT: sw a2, 484(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a5, a0, 1364
+; RV32I-NEXT: sw a5, 500(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a0, a1, 1
-; RV32I-NEXT: and a1, a1, s0
-; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: and a1, a1, t6
+; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a5, a4, 2
; RV32I-NEXT: and a4, a4, s7
; RV32I-NEXT: and a5, a5, s7
; RV32I-NEXT: slli a4, a4, 2
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: sw a0, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a4, a5, a4
-; RV32I-NEXT: srli a0, a4, 1
-; RV32I-NEXT: and a1, a4, s0
-; RV32I-NEXT: and a0, a0, s0
-; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: or a2, a0, a1
-; RV32I-NEXT: andi a0, s2, 2
+; RV32I-NEXT: sw a0, 384(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a5, a5, a4
+; RV32I-NEXT: srli a4, a5, 1
+; RV32I-NEXT: and a0, a5, t6
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: and a1, a4, t6
+; RV32I-NEXT: or a2, a1, a0
+; RV32I-NEXT: andi a0, t3, 2
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: andi a4, s2, 1
-; RV32I-NEXT: addi a1, a0, -1
-; RV32I-NEXT: sw a1, 400(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a0, a4
-; RV32I-NEXT: addi a4, a0, -1
-; RV32I-NEXT: sw a4, 396(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, t3, 1
+; RV32I-NEXT: addi a6, a0, -1
+; RV32I-NEXT: sw a6, 412(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a0, a5
+; RV32I-NEXT: addi a5, a0, -1
+; RV32I-NEXT: sw a5, 408(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a2, 1
-; RV32I-NEXT: sw a0, 460(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a1, a0
-; RV32I-NEXT: and a4, a4, a2
-; RV32I-NEXT: xor a0, a4, a0
-; RV32I-NEXT: andi a4, s2, 4
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, s2, 8
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 384(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 380(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 2
-; RV32I-NEXT: sw a1, 456(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a6, a1
-; RV32I-NEXT: slli a1, a2, 3
-; RV32I-NEXT: sw a1, 452(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: andi a6, s2, 16
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a7, a5, -1
-; RV32I-NEXT: sw a7, 360(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a5, s2, 32
+; RV32I-NEXT: sw a0, 476(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a6, a0
+; RV32I-NEXT: and a5, a5, a2
+; RV32I-NEXT: xor a0, a5, a0
+; RV32I-NEXT: andi a5, t3, 4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: andi a6, s2, 64
-; RV32I-NEXT: addi t0, a5, -1
-; RV32I-NEXT: sw t0, 356(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a6, t3, 8
+; RV32I-NEXT: addi a7, a5, -1
+; RV32I-NEXT: sw a7, 396(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi t3, a5, -1
-; RV32I-NEXT: sw t3, 352(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 4
-; RV32I-NEXT: sw a1, 448(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a7, a1
-; RV32I-NEXT: slli a1, a2, 5
-; RV32I-NEXT: sw a1, 444(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: slli a1, a2, 6
-; RV32I-NEXT: sw a1, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t2, a5, -1
+; RV32I-NEXT: sw t2, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a2, 2
+; RV32I-NEXT: sw a5, 472(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: slli a6, a2, 3
+; RV32I-NEXT: sw a6, 468(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: andi a7, t3, 16
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, t3, a1
-; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: xor a4, a5, a6
-; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: andi a4, s2, 128
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, s2, 256
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 344(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 340(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 7
-; RV32I-NEXT: sw a1, 436(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a6, a1
-; RV32I-NEXT: slli a1, a2, 8
-; RV32I-NEXT: sw a1, 432(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: andi a6, s2, 512
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 328(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 9
-; RV32I-NEXT: sw a1, 428(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: andi a6, s2, 1024
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 320(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 10
-; RV32I-NEXT: sw a1, 424(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: sw s3, 288(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, s2, s3
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a7, a5, -1
-; RV32I-NEXT: sw a7, 308(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s1, 1
-; RV32I-NEXT: and a5, s2, s1
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi t2, a6, -1
+; RV32I-NEXT: sw t2, 372(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a6, t3, 32
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: andi a7, t3, 64
+; RV32I-NEXT: addi t4, a6, -1
+; RV32I-NEXT: sw t4, 368(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi t5, a6, -1
+; RV32I-NEXT: sw t5, 364(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 4
+; RV32I-NEXT: sw a6, 464(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: slli a7, a2, 5
+; RV32I-NEXT: sw a7, 456(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t4, a7
+; RV32I-NEXT: slli t2, a2, 6
+; RV32I-NEXT: sw t2, 452(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: and a7, t5, t2
+; RV32I-NEXT: xor a0, a0, a5
+; RV32I-NEXT: xor a5, a6, a7
+; RV32I-NEXT: xor a0, a0, a5
+; RV32I-NEXT: andi a5, t3, 128
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lui s8, 2
-; RV32I-NEXT: and a6, s2, s8
-; RV32I-NEXT: addi t0, a5, -1
-; RV32I-NEXT: sw t0, 304(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a6, t3, 256
+; RV32I-NEXT: addi a7, a5, -1
+; RV32I-NEXT: sw a7, 356(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi t4, a5, -1
-; RV32I-NEXT: sw t4, 300(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 11
-; RV32I-NEXT: sw a1, 420(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a7, a1
-; RV32I-NEXT: slli a1, a2, 12
-; RV32I-NEXT: sw a1, 416(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: slli a1, a2, 13
-; RV32I-NEXT: sw a1, 412(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t2, a5, -1
+; RV32I-NEXT: sw t2, 352(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a2, 7
+; RV32I-NEXT: sw a5, 448(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: slli a6, a2, 8
+; RV32I-NEXT: sw a6, 444(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: andi a7, t3, 512
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, t4, a1
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 340(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 9
+; RV32I-NEXT: sw a6, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: andi a7, t3, 1024
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lui t3, 4
-; RV32I-NEXT: and a6, s2, t3
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: lui a1, 8
-; RV32I-NEXT: and a7, s2, a1
-; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 296(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 292(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 14
-; RV32I-NEXT: sw a1, 408(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: slli a1, a2, 15
-; RV32I-NEXT: sw a1, 404(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 332(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 10
+; RV32I-NEXT: sw a6, 436(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: mv a1, s11
+; RV32I-NEXT: sw s11, 300(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t3, s11
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, a1
-; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: xor a4, a5, a6
-; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: lui s4, 16
-; RV32I-NEXT: and a4, s2, s4
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: and a5, s2, s11
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 284(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 280(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 16
-; RV32I-NEXT: sw a1, 392(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a6, a1
-; RV32I-NEXT: slli a1, a2, 17
-; RV32I-NEXT: sw a1, 388(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: and a6, s2, s9
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 276(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 18
-; RV32I-NEXT: sw a1, 376(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: and a6, s2, t5
-; RV32I-NEXT: lui s9, 128
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 272(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 19
-; RV32I-NEXT: sw a1, 368(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: lui a1, 256
-; RV32I-NEXT: and a6, s2, a1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 264(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 20
-; RV32I-NEXT: sw a1, 364(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: lui a1, 512
-; RV32I-NEXT: and a6, s2, a1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 260(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 21
-; RV32I-NEXT: sw a1, 348(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: lui a1, 1024
-; RV32I-NEXT: and a6, s2, a1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a7, a5, -1
-; RV32I-NEXT: sw a7, 252(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a1, 2048
-; RV32I-NEXT: and a5, s2, a1
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi t2, a6, -1
+; RV32I-NEXT: sw t2, 320(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s11, 1
+; RV32I-NEXT: and a6, t3, s11
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: lui t0, 2
+; RV32I-NEXT: and a7, t3, t0
+; RV32I-NEXT: addi t4, a6, -1
+; RV32I-NEXT: sw t4, 316(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi t5, a6, -1
+; RV32I-NEXT: sw t5, 312(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 11
+; RV32I-NEXT: sw a6, 432(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: slli a7, a2, 12
+; RV32I-NEXT: sw a7, 428(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t4, a7
+; RV32I-NEXT: slli t2, a2, 13
+; RV32I-NEXT: sw t2, 424(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: and a7, t5, t2
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lui s3, 4
+; RV32I-NEXT: and a7, t3, s3
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: lui t2, 8
+; RV32I-NEXT: and t2, t3, t2
+; RV32I-NEXT: addi t4, a7, -1
+; RV32I-NEXT: sw t4, 308(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a7, t2
+; RV32I-NEXT: addi t5, a7, -1
+; RV32I-NEXT: sw t5, 304(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a2, 14
+; RV32I-NEXT: sw a7, 420(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t4, a7
+; RV32I-NEXT: slli t2, a2, 15
+; RV32I-NEXT: sw t2, 416(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: and a7, t5, t2
+; RV32I-NEXT: xor a0, a0, a5
+; RV32I-NEXT: xor a5, a6, a7
+; RV32I-NEXT: xor a0, a0, a5
+; RV32I-NEXT: lui t5, 16
+; RV32I-NEXT: and a5, t3, t5
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lui a1, 4096
-; RV32I-NEXT: and a6, s2, a1
-; RV32I-NEXT: addi t0, a5, -1
-; RV32I-NEXT: sw t0, 248(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t3, s8
+; RV32I-NEXT: addi a7, a5, -1
+; RV32I-NEXT: sw a7, 296(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi t4, a5, -1
-; RV32I-NEXT: sw t4, 244(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 22
-; RV32I-NEXT: sw a1, 336(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a7, a1
-; RV32I-NEXT: slli a1, a2, 23
-; RV32I-NEXT: sw a1, 332(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: slli a1, a2, 24
-; RV32I-NEXT: sw a1, 324(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t2, a5, -1
+; RV32I-NEXT: sw t2, 292(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a2, 16
+; RV32I-NEXT: sw a5, 404(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: slli a6, a2, 17
+; RV32I-NEXT: sw a6, 400(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: and a7, t3, s10
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, t4, a1
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 288(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 18
+; RV32I-NEXT: sw a6, 388(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a7, t3, s5
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lui a1, 8192
-; RV32I-NEXT: and a6, s2, a1
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: and a7, s2, ra
-; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 240(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 236(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 25
-; RV32I-NEXT: sw a1, 316(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: slli a1, a2, 26
-; RV32I-NEXT: sw a1, 312(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 284(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 19
+; RV32I-NEXT: sw a6, 380(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: lui a7, 256
+; RV32I-NEXT: and a7, t3, a7
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, a1
-; RV32I-NEXT: xor a4, a0, a4
-; RV32I-NEXT: xor a0, a5, a6
-; RV32I-NEXT: srli a5, a3, 8
-; RV32I-NEXT: sw s10, 168(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, a3, s10
-; RV32I-NEXT: and a5, a5, s10
-; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: srli a7, a3, 24
-; RV32I-NEXT: slli t0, a3, 24
-; RV32I-NEXT: or a5, a5, a7
-; RV32I-NEXT: or a6, t0, a6
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: lui t5, 32768
-; RV32I-NEXT: and a6, s2, t5
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: srli a7, a5, 4
-; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 224(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, a7, s5
-; RV32I-NEXT: and a5, a5, s5
-; RV32I-NEXT: slli a1, a2, 27
-; RV32I-NEXT: sw a1, 268(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a5, 4
-; RV32I-NEXT: and a7, t0, a1
-; RV32I-NEXT: xor a0, a0, a7
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: srli a6, a5, 2
-; RV32I-NEXT: and a5, a5, s7
-; RV32I-NEXT: and a6, a6, s7
-; RV32I-NEXT: slli a5, a5, 2
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: lui s10, 65536
-; RV32I-NEXT: and a6, s2, s10
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: srli a7, a5, 1
-; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 212(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 488(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, a7, s0
-; RV32I-NEXT: and a5, a5, s0
-; RV32I-NEXT: slli a1, a2, 28
-; RV32I-NEXT: sw a1, 256(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t4, a5, 1
-; RV32I-NEXT: and a5, t0, a1
-; RV32I-NEXT: xor a5, a0, a5
-; RV32I-NEXT: or a0, a6, t4
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: sw a4, 132(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a4, a0, 2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a0, 1
-; RV32I-NEXT: addi a1, a4, -1
-; RV32I-NEXT: sw a1, 232(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 228(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t1, 1
-; RV32I-NEXT: sw a4, 156(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a1, a4
-; RV32I-NEXT: and a5, a5, t1
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: andi a5, a0, 4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: andi a6, a0, 8
-; RV32I-NEXT: addi a1, a5, -1
-; RV32I-NEXT: sw a1, 220(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 216(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, t1, 2
-; RV32I-NEXT: sw a5, 144(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a1, a5
-; RV32I-NEXT: slli a1, t1, 3
-; RV32I-NEXT: sw a1, 136(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, a6, a1
-; RV32I-NEXT: andi a7, a0, 16
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 276(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 20
+; RV32I-NEXT: sw a6, 376(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: lui a7, 512
+; RV32I-NEXT: and a7, t3, a7
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a1, a6, -1
-; RV32I-NEXT: sw a1, 200(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a6, a0, 32
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 272(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 21
+; RV32I-NEXT: sw a6, 360(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: lui a7, 1024
+; RV32I-NEXT: and a7, t3, a7
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi t2, a6, -1
+; RV32I-NEXT: sw t2, 264(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a6, 2048
+; RV32I-NEXT: and a6, t3, a6
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: andi a7, a0, 64
-; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a7, 4096
+; RV32I-NEXT: and a7, t3, a7
+; RV32I-NEXT: addi t4, a6, -1
+; RV32I-NEXT: sw t4, 260(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi s0, a6, -1
-; RV32I-NEXT: sw s0, 192(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, t1, 4
-; RV32I-NEXT: sw a6, 112(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, a1, a6
-; RV32I-NEXT: slli a1, t1, 5
-; RV32I-NEXT: sw a1, 108(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a7, t0, a1
-; RV32I-NEXT: slli a1, t1, 6
-; RV32I-NEXT: sw a1, 104(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and a7, s0, a1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: xor a5, a6, a7
-; RV32I-NEXT: andi a6, a0, 128
-; RV32I-NEXT: andi a7, a0, 256
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: sw a6, 188(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: sw a7, 184(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t1, 7
-; RV32I-NEXT: sw a1, 92(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, t1, 8
-; RV32I-NEXT: sw t0, 88(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, a6, a1
-; RV32I-NEXT: and a7, a7, t0
+; RV32I-NEXT: sw s0, 256(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a2, 22
+; RV32I-NEXT: sw a6, 348(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: slli a7, a2, 23
+; RV32I-NEXT: sw a7, 344(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t4, a7
+; RV32I-NEXT: slli t2, a2, 24
+; RV32I-NEXT: sw t2, 336(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: andi a7, a0, 512
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: andi t0, a0, 1024
-; RV32I-NEXT: addi a1, a7, -1
-; RV32I-NEXT: sw a1, 180(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi t0, a7, -1
-; RV32I-NEXT: sw t0, 176(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, t1, 9
-; RV32I-NEXT: sw a7, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a7, a1, a7
-; RV32I-NEXT: slli a1, t1, 10
-; RV32I-NEXT: sw a1, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, s0, t2
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and a7, t0, a1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: xor a5, a6, a7
-; RV32I-NEXT: lui a1, 131072
-; RV32I-NEXT: and a6, s2, a1
-; RV32I-NEXT: lui ra, 262144
-; RV32I-NEXT: and a7, s2, ra
-; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: lui a7, 8192
+; RV32I-NEXT: and a7, t3, a7
; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, t3, ra
+; RV32I-NEXT: addi t4, a7, -1
+; RV32I-NEXT: sw t4, 252(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a7, t2
; RV32I-NEXT: addi s0, a7, -1
-; RV32I-NEXT: sw s0, 124(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a2, 29
-; RV32I-NEXT: sw a6, 208(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, a2, 30
-; RV32I-NEXT: sw a7, 204(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a6, t0, a6
-; RV32I-NEXT: and a7, s0, a7
+; RV32I-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a2, 25
+; RV32I-NEXT: sw a7, 328(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t4, a7
+; RV32I-NEXT: slli t2, a2, 26
+; RV32I-NEXT: sw t2, 324(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, a0, s3
-; RV32I-NEXT: and a7, a0, s1
+; RV32I-NEXT: and a7, s0, t2
+; RV32I-NEXT: xor a5, a0, a5
+; RV32I-NEXT: xor a0, a6, a7
+; RV32I-NEXT: srli a6, a3, 8
+; RV32I-NEXT: sw s9, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, a3, s9
+; RV32I-NEXT: and a6, a6, s9
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: srli t2, a3, 24
+; RV32I-NEXT: slli t4, a3, 24
+; RV32I-NEXT: or a6, a6, t2
+; RV32I-NEXT: or a7, t4, a7
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: lui s0, 32768
+; RV32I-NEXT: and a7, t3, s0
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: srli t2, a6, 4
+; RV32I-NEXT: addi t4, a7, -1
+; RV32I-NEXT: sw t4, 236(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t2, s6
+; RV32I-NEXT: and a6, a6, s6
+; RV32I-NEXT: slli t2, a2, 27
+; RV32I-NEXT: sw t2, 280(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a6, 4
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: xor a0, a0, t2
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: srli a7, a6, 2
+; RV32I-NEXT: and a6, a6, s7
+; RV32I-NEXT: and a7, a7, s7
+; RV32I-NEXT: slli a6, a6, 2
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: lui a7, 65536
+; RV32I-NEXT: and a7, t3, a7
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: srli t2, a6, 1
+; RV32I-NEXT: addi t4, a7, -1
+; RV32I-NEXT: sw t4, 224(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t6, 504(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t2, t6
+; RV32I-NEXT: and a6, a6, t6
+; RV32I-NEXT: slli t2, a2, 28
+; RV32I-NEXT: sw t2, 268(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t6, a6, 1
+; RV32I-NEXT: sw t6, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t4, t2
+; RV32I-NEXT: xor a6, a0, a6
+; RV32I-NEXT: or a0, a7, t6
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: sw a5, 148(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a5, a0, 2
; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: andi a6, a0, 1
+; RV32I-NEXT: addi a7, a5, -1
+; RV32I-NEXT: sw a7, 244(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 240(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, t1, 1
+; RV32I-NEXT: sw a5, 168(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a6, a6, t1
+; RV32I-NEXT: xor a5, a6, a5
+; RV32I-NEXT: andi a6, a0, 4
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: andi a7, a0, 8
+; RV32I-NEXT: addi t2, a6, -1
+; RV32I-NEXT: sw t2, 232(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 228(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, t1, 2
+; RV32I-NEXT: sw a6, 156(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: slli t2, t1, 3
+; RV32I-NEXT: sw t2, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, a7, t2
+; RV32I-NEXT: andi t2, a0, 16
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t2
+; RV32I-NEXT: addi t4, a7, -1
+; RV32I-NEXT: sw t4, 212(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a7, a0, 32
; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi t2, a0, 64
+; RV32I-NEXT: addi t6, a7, -1
+; RV32I-NEXT: sw t6, 208(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a7, t2
+; RV32I-NEXT: addi s9, a7, -1
+; RV32I-NEXT: sw s9, 204(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, t1, 4
+; RV32I-NEXT: sw a7, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, t4, a7
+; RV32I-NEXT: slli t2, t1, 5
+; RV32I-NEXT: sw t2, 124(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, t6, t2
+; RV32I-NEXT: slli t4, t1, 6
+; RV32I-NEXT: sw t4, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a7, a7, t2
+; RV32I-NEXT: and t2, s9, t4
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: xor a6, a7, t2
+; RV32I-NEXT: andi a7, a0, 128
+; RV32I-NEXT: andi t2, a0, 256
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: sw a7, 160(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, t1, 11
-; RV32I-NEXT: sw t0, 44(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t1, 12
-; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, t0
-; RV32I-NEXT: and a7, a7, s0
-; RV32I-NEXT: xor a5, a5, a7
-; RV32I-NEXT: and a7, a0, s8
+; RV32I-NEXT: sw a7, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: sw t2, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t4, t1, 7
+; RV32I-NEXT: sw t4, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t6, t1, 8
+; RV32I-NEXT: sw t6, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a7, a7, t4
+; RV32I-NEXT: and t2, t2, t6
+; RV32I-NEXT: xor a7, a7, t2
+; RV32I-NEXT: andi t2, a0, 512
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: andi t4, a0, 1024
+; RV32I-NEXT: addi t6, t2, -1
+; RV32I-NEXT: sw t6, 192(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz t2, t4
+; RV32I-NEXT: addi t4, t2, -1
+; RV32I-NEXT: sw t4, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, t1, 9
+; RV32I-NEXT: sw t2, 88(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, t6, t2
+; RV32I-NEXT: slli t6, t1, 10
+; RV32I-NEXT: sw t6, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a7, a7, t2
+; RV32I-NEXT: and t2, t4, t6
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: xor a6, a7, t2
+; RV32I-NEXT: lui s9, 131072
+; RV32I-NEXT: and a7, t3, s9
+; RV32I-NEXT: lui ra, 262144
+; RV32I-NEXT: and t2, t3, ra
; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: and t0, a0, t3
+; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi t3, a7, -1
-; RV32I-NEXT: sw t3, 152(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi t0, a7, -1
-; RV32I-NEXT: sw t0, 148(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, t1, 13
-; RV32I-NEXT: sw a7, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t3, 144(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t4, t2, -1
+; RV32I-NEXT: sw t4, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a2, 29
+; RV32I-NEXT: sw a7, 220(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 30
+; RV32I-NEXT: sw t2, 216(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: slli t3, t1, 14
-; RV32I-NEXT: sw t3, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a5, a5, a7
-; RV32I-NEXT: and a7, t0, t3
-; RV32I-NEXT: xor a5, a5, a7
-; RV32I-NEXT: lw a7, 464(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a7, a7, 31
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: lui t0, 8
-; RV32I-NEXT: and t0, a0, t0
-; RV32I-NEXT: addi t3, a7, -1
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: xor a7, a7, t2
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: and a6, a0, a1
+; RV32I-NEXT: and t2, a0, s11
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: sw a6, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: sw t2, 172(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, t1, 11
; RV32I-NEXT: sw t3, 56(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a7, t0
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: sw a7, 140(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t1, 15
-; RV32I-NEXT: sw s0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, a2, 31
-; RV32I-NEXT: sw t0, 172(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a7, a7, s0
-; RV32I-NEXT: xor a5, a5, a7
-; RV32I-NEXT: and a7, t3, t0
-; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: sw a6, 464(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, a0, s4
-; RV32I-NEXT: and a6, a0, s11
+; RV32I-NEXT: slli t4, t1, 12
+; RV32I-NEXT: sw t4, 52(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a6, a6, t3
+; RV32I-NEXT: and t2, t2, t4
+; RV32I-NEXT: xor a6, a6, t2
+; RV32I-NEXT: and t2, a0, t0
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: and t3, a0, s3
+; RV32I-NEXT: addi t0, t2, -1
+; RV32I-NEXT: sw t0, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz t2, t3
+; RV32I-NEXT: addi t3, t2, -1
+; RV32I-NEXT: sw t3, 160(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, t1, 13
+; RV32I-NEXT: sw t2, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, t0, t2
+; RV32I-NEXT: slli t0, t1, 14
+; RV32I-NEXT: sw t0, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a6, a6, t2
+; RV32I-NEXT: and t2, t3, t0
+; RV32I-NEXT: xor a6, a6, t2
+; RV32I-NEXT: slli t0, a4, 31
+; RV32I-NEXT: sw t0, 184(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a4, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a4, a4, 31
+; RV32I-NEXT: lui t2, 8
+; RV32I-NEXT: and t2, a0, t2
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: sw t2, 460(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, t1, 15
+; RV32I-NEXT: sw a1, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t3, a4, -1
+; RV32I-NEXT: sw t3, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, t2, a1
+; RV32I-NEXT: xor a4, a6, a4
+; RV32I-NEXT: and a6, t3, t0
+; RV32I-NEXT: xor a1, a7, a6
+; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a4, a5, a4
+; RV32I-NEXT: and a5, a0, t5
+; RV32I-NEXT: and a6, a0, s8
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: sw a6, 116(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, t1, 16
-; RV32I-NEXT: sw a7, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, t1, 17
-; RV32I-NEXT: sw t0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: and a6, a6, t0
+; RV32I-NEXT: sw a6, 132(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, t1, 16
+; RV32I-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, t1, 17
+; RV32I-NEXT: sw a7, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a5, a1
+; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lui a6, 64
-; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a6, a0, s10
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: and a7, a0, s9
+; RV32I-NEXT: and a7, a0, s5
; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t0, 116(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 96(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli s11, t1, 18
; RV32I-NEXT: and a6, t0, s11
-; RV32I-NEXT: slli t0, t1, 19
-; RV32I-NEXT: sw t0, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, t1, 19
+; RV32I-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, t0
+; RV32I-NEXT: and a6, a7, a1
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: lui a6, 256
; RV32I-NEXT: and a6, a0, a6
@@ -26748,1000 +26768,1007 @@ define i128 @clmul_i128_zext(i64 %x, i64 %y) {
; RV32I-NEXT: lui a7, 512
; RV32I-NEXT: and a7, a0, a7
; RV32I-NEXT: addi t0, a6, -1
-; RV32I-NEXT: sw t0, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw t0, 96(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 80(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s9, t1, 20
-; RV32I-NEXT: and a6, t0, s9
-; RV32I-NEXT: slli s8, t1, 21
+; RV32I-NEXT: sw a7, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s8, t1, 20
+; RV32I-NEXT: and a6, t0, s8
+; RV32I-NEXT: slli s10, t1, 21
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, s8
+; RV32I-NEXT: and a6, a7, s10
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: lui a6, 1024
; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: xor t3, a4, a5
; RV32I-NEXT: seqz a4, a6
; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a6, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a4, 2048
; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: lui a5, 4096
; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: addi a7, a4, -1
-; RV32I-NEXT: sw a7, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: slli s3, t1, 22
-; RV32I-NEXT: slli s4, t1, 23
+; RV32I-NEXT: slli s5, t1, 23
; RV32I-NEXT: and a5, a6, s3
-; RV32I-NEXT: and a6, a7, s4
+; RV32I-NEXT: and a6, a7, s5
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: sw a4, 60(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s2, 468(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, s2
+; RV32I-NEXT: sw a4, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw t6, 480(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, t6
; RV32I-NEXT: lui a6, 8192
; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: xor a4, a5, a4
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 52(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t1, 25
-; RV32I-NEXT: and a5, a5, s1
+; RV32I-NEXT: sw a5, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t5, t1, 25
+; RV32I-NEXT: and a5, a5, t5
; RV32I-NEXT: lui a6, 16384
; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t1, 26
-; RV32I-NEXT: and a5, a5, s0
-; RV32I-NEXT: and a6, a0, t5
+; RV32I-NEXT: sw a5, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t4, t1, 26
+; RV32I-NEXT: and a5, a5, t4
+; RV32I-NEXT: and a6, a0, s0
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 36(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t5, t1, 27
-; RV32I-NEXT: and a5, a5, t5
-; RV32I-NEXT: and a6, a0, s10
+; RV32I-NEXT: sw a5, 48(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t1, 27
+; RV32I-NEXT: and a5, a5, s0
+; RV32I-NEXT: lui a6, 65536
+; RV32I-NEXT: and a6, a0, a6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, t1, 28
-; RV32I-NEXT: and a5, a5, t0
-; RV32I-NEXT: and s10, a0, a1
+; RV32I-NEXT: sw a5, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, t1, 28
+; RV32I-NEXT: and a5, a5, t2
+; RV32I-NEXT: and s9, a0, s9
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, s10
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: sw a5, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a5, s9
+; RV32I-NEXT: addi a1, a5, -1
+; RV32I-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, ra
-; RV32I-NEXT: seqz s10, a0
-; RV32I-NEXT: srli a0, t4, 31
-; RV32I-NEXT: addi s10, s10, -1
; RV32I-NEXT: seqz ra, a0
+; RV32I-NEXT: lw a0, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a5, a0, 31
; RV32I-NEXT: addi ra, ra, -1
-; RV32I-NEXT: slli a7, t1, 29
-; RV32I-NEXT: and a1, a5, a7
-; RV32I-NEXT: slli a6, t1, 30
-; RV32I-NEXT: and a0, s10, a6
-; RV32I-NEXT: slli a5, t1, 31
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: and a1, ra, a5
+; RV32I-NEXT: sw ra, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz s9, a5
+; RV32I-NEXT: lw a7, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli a7, a7, 31
+; RV32I-NEXT: addi s9, s9, -1
+; RV32I-NEXT: slli a6, t1, 29
+; RV32I-NEXT: slli a5, t1, 30
+; RV32I-NEXT: and a1, a1, a6
+; RV32I-NEXT: and ra, ra, a5
+; RV32I-NEXT: xor a0, a1, ra
+; RV32I-NEXT: and ra, s9, a7
; RV32I-NEXT: xor a4, t3, a4
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 132(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 464(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a1, a1, t3
+; RV32I-NEXT: xor a0, a0, ra
+; RV32I-NEXT: lw t0, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor t3, t0, a1
; RV32I-NEXT: xor a0, a4, a0
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a1, a1, 1
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: srli a1, a0, 8
-; RV32I-NEXT: lw t4, 168(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, t4
-; RV32I-NEXT: srli a4, a0, 24
-; RV32I-NEXT: and t3, a0, t4
+; RV32I-NEXT: xor a0, a0, t3
+; RV32I-NEXT: lw a4, 384(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a4, a4, 1
+; RV32I-NEXT: xor a0, a4, a0
+; RV32I-NEXT: srli a4, a0, 8
+; RV32I-NEXT: lw t0, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, t0
+; RV32I-NEXT: srli t3, a0, 24
+; RV32I-NEXT: and ra, a0, t0
; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: slli t3, t3, 8
-; RV32I-NEXT: or a1, a1, a4
-; RV32I-NEXT: or a0, a0, t3
-; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: srli a1, a0, 4
-; RV32I-NEXT: and a0, a0, s5
-; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: slli ra, ra, 8
+; RV32I-NEXT: or a4, a4, t3
+; RV32I-NEXT: or a0, a0, ra
+; RV32I-NEXT: or a0, a0, a4
+; RV32I-NEXT: srli a4, a0, 4
+; RV32I-NEXT: and a0, a0, s6
+; RV32I-NEXT: and a4, a4, s6
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: srli a1, a0, 2
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and a1, a1, s7
+; RV32I-NEXT: and a4, a4, s7
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: srli a1, a0, 1
-; RV32I-NEXT: lw a4, 488(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, a4
-; RV32I-NEXT: lw a4, 484(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: srli a4, a0, 1
+; RV32I-NEXT: lw t3, 504(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, t3
+; RV32I-NEXT: lw t3, 500(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, t3
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: sw a0, 464(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 400(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 156(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lw a1, 396(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, t1
-; RV32I-NEXT: lw a4, 384(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 144(sp) # 4-byte Folded Reload
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: sw a0, 484(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a0, 412(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, a4
+; RV32I-NEXT: lw a4, 408(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t1
-; RV32I-NEXT: lw t1, 380(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 136(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 396(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t3, 156(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: xor a1, a4, t1
-; RV32I-NEXT: lw a4, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 112(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, t1
-; RV32I-NEXT: lw t1, 356(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t3, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 152(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor a0, a4, a0
+; RV32I-NEXT: xor a4, t1, t3
+; RV32I-NEXT: lw t1, 372(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t3, 128(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 352(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t3, 368(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 364(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: xor a4, t1, t3
+; RV32I-NEXT: lw t1, 356(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw t3, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a4, t1
-; RV32I-NEXT: lw a4, 344(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 92(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, t1
-; RV32I-NEXT: lw t1, 340(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 88(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 328(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 76(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
+; RV32I-NEXT: lw t3, 352(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 340(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 332(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: xor a4, t1, t3
; RV32I-NEXT: lw t1, 320(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 72(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a4, t1
-; RV32I-NEXT: lw a4, 308(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, t1
-; RV32I-NEXT: lw t1, 304(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t3, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 300(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
+; RV32I-NEXT: lw t3, 316(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 52(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 312(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 308(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, ra
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 304(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, a1
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: xor a4, t1, t3
; RV32I-NEXT: lw t1, 296(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 292(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a4, t1
-; RV32I-NEXT: lw a4, 284(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t1, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, t1
-; RV32I-NEXT: lw t1, 280(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 276(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, s11
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 272(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t3, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t3
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 264(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, s9
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 260(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, s8
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a4, t1
-; RV32I-NEXT: lw a4, 252(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, s3
-; RV32I-NEXT: lw t1, 248(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, s4
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 244(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, s2
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 240(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, s1
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 236(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, s0
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 224(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t5
-; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 212(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a4, t0
-; RV32I-NEXT: lw a4, 128(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, a7
-; RV32I-NEXT: lw a7, 124(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a4, a4, a6
-; RV32I-NEXT: lw a6, 56(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a1, 460(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 232(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: lw a5, 228(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: lw a5, 456(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 220(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t1, t1, a1
+; RV32I-NEXT: lw t3, 292(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, a1
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 288(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, s11
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, a1
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 276(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, s8
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 272(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, s10
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: xor a4, t1, t3
+; RV32I-NEXT: lw t1, 264(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t1, t1, s3
+; RV32I-NEXT: lw t3, 260(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, s5
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 256(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, t6
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 252(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, t5
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 248(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 236(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t3, s0
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lw t3, 224(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t2, t3, t2
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: xor a4, t1, t2
+; RV32I-NEXT: lw t1, 144(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a6, t1, a6
+; RV32I-NEXT: lw t1, 140(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, t1, a5
+; RV32I-NEXT: xor a5, a6, a5
+; RV32I-NEXT: lw a6, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a6, a6, a7
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: xor a4, a5, a6
+; RV32I-NEXT: lw a5, 476(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 244(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: lw a6, 452(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 216(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 240(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a6, a2
+; RV32I-NEXT: lw a6, 472(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 232(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: xor a2, a5, a6
-; RV32I-NEXT: lw a5, 448(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 200(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: lw a6, 444(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 196(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 468(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 228(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: xor a5, a6, a7
+; RV32I-NEXT: lw a6, 464(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 212(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 440(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 192(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: xor a5, a6, a7
+; RV32I-NEXT: lw a6, 448(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 200(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, a5, a6
-; RV32I-NEXT: lw a5, 436(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: lw a7, 444(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 196(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 440(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 192(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 436(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 188(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: xor a5, a6, a7
; RV32I-NEXT: lw a6, 432(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 184(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 428(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 180(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 424(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a7, 176(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, a5, a6
-; RV32I-NEXT: lw a5, 420(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: lw a6, 416(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 160(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 412(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 152(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 408(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 148(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: lw a7, 428(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 424(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 164(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 420(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 160(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 416(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: xor a5, a6, a7
; RV32I-NEXT: lw a6, 404(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 140(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, a5, a6
-; RV32I-NEXT: lw a5, 392(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 120(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: lw a6, 388(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 116(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 376(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 100(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 96(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 84(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 348(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a7, 80(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a7, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, a5, a6
+; RV32I-NEXT: lw a7, 400(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 388(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 376(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 96(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: lw a7, 360(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: xor a5, a6, a7
; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 336(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 68(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: lw a4, 332(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 64(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 324(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 60(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 316(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 52(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 312(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 268(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 256(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: lw a4, 348(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 80(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: srli a4, a0, 8
-; RV32I-NEXT: and a4, a4, t4
-; RV32I-NEXT: srli a5, a0, 24
-; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw a2, 208(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: lw a5, 204(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, s10, a5
-; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: lw a5, 172(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, ra, a5
-; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, a0, t4
+; RV32I-NEXT: lw a5, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 76(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 336(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 72(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 328(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 64(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 280(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 48(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: lw a5, 268(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: srli a5, a0, 8
+; RV32I-NEXT: and a5, a5, t0
+; RV32I-NEXT: srli a6, a0, 24
+; RV32I-NEXT: or a5, a5, a6
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: lw a4, 220(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a2, a4
+; RV32I-NEXT: lw a6, 216(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a6, a2, a6
+; RV32I-NEXT: xor a4, a4, a6
+; RV32I-NEXT: lw a6, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a6, s9, a6
+; RV32I-NEXT: xor a4, a4, a6
+; RV32I-NEXT: and a6, a0, t0
; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: slli a6, a6, 8
+; RV32I-NEXT: or a0, a0, a6
+; RV32I-NEXT: xor a1, a1, a4
; RV32I-NEXT: or a0, a0, a5
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: or a0, a0, a4
-; RV32I-NEXT: srli a2, a1, 8
-; RV32I-NEXT: and a2, a2, t4
-; RV32I-NEXT: srli a4, a1, 24
-; RV32I-NEXT: or a2, a2, a4
-; RV32I-NEXT: and a4, a1, t4
+; RV32I-NEXT: srli a4, a1, 8
+; RV32I-NEXT: and a4, a4, t0
+; RV32I-NEXT: srli a5, a1, 24
+; RV32I-NEXT: or a4, a4, a5
+; RV32I-NEXT: and a5, a1, t0
; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: slli a4, a4, 8
+; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: or a1, a1, a5
+; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: or a1, a1, a4
-; RV32I-NEXT: srli a4, a0, 4
-; RV32I-NEXT: or a1, a1, a2
-; RV32I-NEXT: and a2, a4, s5
-; RV32I-NEXT: and a0, a0, s5
-; RV32I-NEXT: srli a4, a1, 4
-; RV32I-NEXT: and a4, a4, s5
-; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: and a4, a5, s6
+; RV32I-NEXT: and a0, a0, s6
+; RV32I-NEXT: srli a5, a1, 4
+; RV32I-NEXT: and a5, a5, s6
+; RV32I-NEXT: and a1, a1, s6
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: slli a1, a1, 4
-; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: or a1, a4, a1
-; RV32I-NEXT: srli a2, a0, 2
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: or a1, a5, a1
+; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and a2, a2, s7
+; RV32I-NEXT: and a4, a4, s7
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: sw a0, 468(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a0, a4, a0
+; RV32I-NEXT: sw a0, 480(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a0, a1, 2
; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: and a1, a1, s7
; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: andi a2, a3, 2
-; RV32I-NEXT: or a4, a0, a1
-; RV32I-NEXT: sw a4, 444(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a0, a2
-; RV32I-NEXT: addi a2, a0, -1
-; RV32I-NEXT: sw a2, 460(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a4, a3, 2
+; RV32I-NEXT: or a5, a0, a1
+; RV32I-NEXT: sw a5, 460(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a0, a4
+; RV32I-NEXT: addi a4, a0, -1
+; RV32I-NEXT: sw a4, 476(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, a3, 1
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: slli a1, t2, 1
-; RV32I-NEXT: and a1, a2, a1
-; RV32I-NEXT: addi a2, a0, -1
-; RV32I-NEXT: sw a2, 456(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a0, a4, 1
-; RV32I-NEXT: and a2, a2, t2
-; RV32I-NEXT: lw a4, 484(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, a4
-; RV32I-NEXT: sw a0, 448(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: slli a1, s1, 1
+; RV32I-NEXT: and a1, a4, a1
+; RV32I-NEXT: addi a4, a0, -1
+; RV32I-NEXT: sw a4, 472(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a0, a5, 1
+; RV32I-NEXT: and a4, a4, s1
+; RV32I-NEXT: lw a5, 500(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: sw a0, 464(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a1, a4, a1
; RV32I-NEXT: andi a0, a3, 4
-; RV32I-NEXT: andi a2, a3, 8
+; RV32I-NEXT: andi a4, a3, 8
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: addi a4, a0, -1
-; RV32I-NEXT: sw a4, 484(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a5, a2, -1
-; RV32I-NEXT: sw a5, 452(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, t2, 2
-; RV32I-NEXT: slli a2, t2, 3
-; RV32I-NEXT: and a0, a4, a0
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: andi a2, a3, 16
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: addi a5, a0, -1
+; RV32I-NEXT: sw a5, 500(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 468(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, s1, 2
+; RV32I-NEXT: slli a4, s1, 3
+; RV32I-NEXT: and a0, a5, a0
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: xor a0, a0, a4
+; RV32I-NEXT: andi a4, a3, 16
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: seqz a1, a2
-; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a1, a4
+; RV32I-NEXT: addi a5, a1, -1
+; RV32I-NEXT: sw a5, 456(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a3, 32
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: slli a2, t2, 4
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: addi a5, a1, -1
-; RV32I-NEXT: sw a5, 436(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t2, 5
-; RV32I-NEXT: andi a4, a3, 64
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 432(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t2, 6
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: and a2, a5, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: andi a2, a3, 128
+; RV32I-NEXT: slli a4, s1, 4
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: addi a6, a1, -1
+; RV32I-NEXT: sw a6, 452(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s1, 5
+; RV32I-NEXT: andi a5, a3, 64
+; RV32I-NEXT: and a1, a6, a1
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 448(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, s1, 6
+; RV32I-NEXT: xor a1, a4, a1
+; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: andi a4, a3, 128
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a1, a2
-; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 428(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a1, a4
+; RV32I-NEXT: addi a5, a1, -1
+; RV32I-NEXT: sw a5, 444(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a3, 256
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: slli a2, t2, 7
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: addi a5, a1, -1
-; RV32I-NEXT: sw a5, 424(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t2, 8
-; RV32I-NEXT: andi a4, a3, 512
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 420(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 9
-; RV32I-NEXT: andi a4, a3, 1024
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 416(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t2, 10
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: and a2, a5, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lw s5, 288(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a3, s5
+; RV32I-NEXT: slli a4, s1, 7
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: addi a6, a1, -1
+; RV32I-NEXT: sw a6, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s1, 8
+; RV32I-NEXT: andi a5, a3, 512
+; RV32I-NEXT: and a1, a6, a1
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: xor a1, a4, a1
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 436(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 9
+; RV32I-NEXT: andi a5, a3, 1024
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 432(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, s1, 10
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: lw s7, 300(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a3, s7
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a1, a2
-; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 412(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s2, 1
-; RV32I-NEXT: and a1, a3, s2
-; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: slli a2, t2, 11
-; RV32I-NEXT: and a2, a4, a2
+; RV32I-NEXT: seqz a1, a4
; RV32I-NEXT: addi a5, a1, -1
-; RV32I-NEXT: sw a5, 408(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t2, 12
-; RV32I-NEXT: lui s7, 2
-; RV32I-NEXT: and a4, a3, s7
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 404(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t2, 13
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: and a2, a5, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lui s4, 4
-; RV32I-NEXT: and a2, a3, s4
+; RV32I-NEXT: sw a5, 428(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s5, 1
+; RV32I-NEXT: and a1, a3, s5
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: slli a4, s1, 11
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: addi a6, a1, -1
+; RV32I-NEXT: sw a6, 424(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s1, 12
+; RV32I-NEXT: lui s8, 2
+; RV32I-NEXT: and a5, a3, s8
+; RV32I-NEXT: and a1, a6, a1
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 420(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, s1, 13
+; RV32I-NEXT: xor a1, a4, a1
+; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: lui s6, 4
+; RV32I-NEXT: and a4, a3, s6
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a1, a2
-; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 400(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a1, a4
+; RV32I-NEXT: addi a5, a1, -1
+; RV32I-NEXT: sw a5, 416(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s9, 8
; RV32I-NEXT: and a1, a3, s9
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: slli a2, t2, 14
-; RV32I-NEXT: and a2, a4, a2
+; RV32I-NEXT: slli a4, s1, 14
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: addi a6, a1, -1
+; RV32I-NEXT: sw a6, 412(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s1, 15
+; RV32I-NEXT: lui a5, 16
+; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: and a1, a6, a1
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: xor a1, a4, a1
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 408(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 16
+; RV32I-NEXT: lui ra, 32
+; RV32I-NEXT: and a5, a3, ra
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 404(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 17
+; RV32I-NEXT: lui t1, 64
+; RV32I-NEXT: and a5, a3, t1
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 400(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, s1, 18
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: lui t2, 128
+; RV32I-NEXT: and a4, a3, t2
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a1, a4
; RV32I-NEXT: addi a5, a1, -1
; RV32I-NEXT: sw a5, 396(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t2, 15
-; RV32I-NEXT: lui s8, 16
-; RV32I-NEXT: and a4, a3, s8
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 392(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 16
-; RV32I-NEXT: lui s3, 32
-; RV32I-NEXT: and a4, a3, s3
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 388(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 17
-; RV32I-NEXT: lui a7, 64
-; RV32I-NEXT: and a4, a3, a7
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 384(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, t2, 18
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: and a2, a5, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: lui t0, 128
-; RV32I-NEXT: and a2, a3, t0
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: seqz a1, a2
-; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 380(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui t1, 256
-; RV32I-NEXT: and a1, a3, t1
+; RV32I-NEXT: lui t3, 256
+; RV32I-NEXT: and a1, a3, t3
; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: slli a2, t2, 19
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: addi a5, a1, -1
+; RV32I-NEXT: slli a4, s1, 19
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: addi a6, a1, -1
+; RV32I-NEXT: sw a6, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s1, 20
+; RV32I-NEXT: lui t4, 512
+; RV32I-NEXT: and a5, a3, t4
+; RV32I-NEXT: and a1, a6, a1
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: xor a1, a4, a1
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 388(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 21
+; RV32I-NEXT: lui t5, 1024
+; RV32I-NEXT: and a5, a3, t5
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 384(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 22
+; RV32I-NEXT: lui t6, 2048
+; RV32I-NEXT: and a5, a3, t6
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 380(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 23
+; RV32I-NEXT: lui s0, 4096
+; RV32I-NEXT: and a5, a3, s0
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: sw a5, 376(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t2, 20
-; RV32I-NEXT: lui t3, 512
-; RV32I-NEXT: and a4, a3, t3
+; RV32I-NEXT: lw a4, 492(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: lui t0, 8192
+; RV32I-NEXT: and a5, a3, t0
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: addi a5, a4, -1
+; RV32I-NEXT: sw a5, 492(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, s1, 25
+; RV32I-NEXT: lui s3, 16384
+; RV32I-NEXT: and a4, a3, s3
; RV32I-NEXT: and a1, a5, a1
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: addi a5, a4, -1
; RV32I-NEXT: sw a5, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 21
-; RV32I-NEXT: lui t4, 1024
-; RV32I-NEXT: and a4, a3, t4
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: slli a4, s1, 26
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: lui a6, 32768
+; RV32I-NEXT: and a5, a3, a6
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a5, a4, -1
; RV32I-NEXT: sw a5, 368(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 22
-; RV32I-NEXT: lui t5, 2048
-; RV32I-NEXT: and a4, a3, t5
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: slli a4, s1, 27
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: lui a7, 65536
+; RV32I-NEXT: and a5, a3, a7
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a5, a4, -1
; RV32I-NEXT: sw a5, 364(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 23
-; RV32I-NEXT: lui s0, 4096
-; RV32I-NEXT: and a4, a3, s0
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: sw a4, 360(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a2, 476(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: lui s1, 8192
-; RV32I-NEXT: and a4, a3, s1
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: seqz a2, a4
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 476(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t2, 25
-; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and a2, a3, a5
-; RV32I-NEXT: and a1, a4, a1
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 356(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 26
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: lui a6, 32768
-; RV32I-NEXT: and a4, a3, a6
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: seqz a2, a4
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 352(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 27
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: lui a4, 65536
-; RV32I-NEXT: and a4, a3, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: seqz a2, a4
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 348(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 28
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: lui a4, 131072
-; RV32I-NEXT: and a4, a3, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: seqz a2, a4
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 344(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 29
-; RV32I-NEXT: and a2, a4, a2
-; RV32I-NEXT: lui a4, 262144
-; RV32I-NEXT: and a4, a3, a4
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: seqz a2, a4
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 340(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t2, 30
-; RV32I-NEXT: and a2, a4, a2
+; RV32I-NEXT: slli a4, s1, 28
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: lui a5, 131072
+; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a5, a4, -1
+; RV32I-NEXT: sw a5, 360(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 29
+; RV32I-NEXT: and a4, a5, a4
+; RV32I-NEXT: lui a5, 262144
+; RV32I-NEXT: and a5, a3, a5
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a5, a4, -1
+; RV32I-NEXT: sw a5, 356(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, s1, 30
+; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: srli a3, a3, 31
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: seqz a2, a3
-; RV32I-NEXT: slli t2, t2, 31
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: sw a2, 336(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, t2
-; RV32I-NEXT: andi a3, t6, 2
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: slli a2, s1, 31
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: sw a3, 352(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a3, a2
+; RV32I-NEXT: andi a3, s2, 2
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: sw a0, 328(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a1, s6, 1
-; RV32I-NEXT: sw a1, 332(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a0, t6, 1
+; RV32I-NEXT: slli a1, s4, 1
+; RV32I-NEXT: sw a1, 348(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a0, s2, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: andi a2, t6, 4
-; RV32I-NEXT: and a0, a0, s6
+; RV32I-NEXT: andi a2, s2, 4
+; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s6, 2
-; RV32I-NEXT: sw a3, 324(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a1, t6, 8
+; RV32I-NEXT: slli a3, s4, 2
+; RV32I-NEXT: sw a3, 340(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a1, s2, 8
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a3, s6, 3
-; RV32I-NEXT: sw a3, 320(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 3
+; RV32I-NEXT: sw a3, 336(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: andi a3, t6, 16
+; RV32I-NEXT: andi a3, s2, 16
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s6, 4
-; RV32I-NEXT: sw a3, 316(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a1, t6, 32
+; RV32I-NEXT: slli a3, s4, 4
+; RV32I-NEXT: sw a3, 332(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a1, s2, 32
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a3, s6, 5
-; RV32I-NEXT: sw a3, 312(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 5
+; RV32I-NEXT: sw a3, 328(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: andi a3, t6, 64
+; RV32I-NEXT: andi a3, s2, 64
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s6, 6
-; RV32I-NEXT: sw a3, 308(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 6
+; RV32I-NEXT: sw a3, 324(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: andi a3, t6, 128
+; RV32I-NEXT: andi a3, s2, 128
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s6, 7
-; RV32I-NEXT: sw a3, 304(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a1, t6, 256
+; RV32I-NEXT: slli a3, s4, 7
+; RV32I-NEXT: sw a3, 320(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a1, s2, 256
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a3, s6, 8
-; RV32I-NEXT: sw a3, 300(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 8
+; RV32I-NEXT: sw a3, 316(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: andi a3, t6, 512
+; RV32I-NEXT: andi a3, s2, 512
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s6, 9
-; RV32I-NEXT: sw a3, 296(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 9
+; RV32I-NEXT: sw a3, 312(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: andi a3, t6, 1024
+; RV32I-NEXT: andi a3, s2, 1024
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli a3, s6, 10
-; RV32I-NEXT: sw a3, 292(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 10
+; RV32I-NEXT: sw a3, 308(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: and a3, t6, s5
+; RV32I-NEXT: and a3, s2, s7
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a1, t6, s2
-; RV32I-NEXT: slli a3, s6, 11
-; RV32I-NEXT: sw a3, 288(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a1, s2, s5
+; RV32I-NEXT: slli a3, s4, 11
+; RV32I-NEXT: sw a3, 304(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a3, s6, 12
-; RV32I-NEXT: sw a3, 284(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a3, s4, 12
+; RV32I-NEXT: sw a3, 300(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: and a3, t6, s7
+; RV32I-NEXT: and a3, s2, s8
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli ra, s6, 13
-; RV32I-NEXT: and a2, a2, ra
-; RV32I-NEXT: and a3, t6, s4
+; RV32I-NEXT: slli a3, s4, 13
+; RV32I-NEXT: sw a3, 296(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a3
+; RV32I-NEXT: and a3, s2, s6
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a1, t6, s9
-; RV32I-NEXT: slli s11, s6, 14
+; RV32I-NEXT: and a1, s2, s9
+; RV32I-NEXT: slli s11, s4, 14
; RV32I-NEXT: and a2, a2, s11
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli s10, s6, 15
+; RV32I-NEXT: slli s10, s4, 15
; RV32I-NEXT: and a1, a1, s10
-; RV32I-NEXT: and a3, t6, s8
+; RV32I-NEXT: lui a3, 16
+; RV32I-NEXT: and a3, s2, a3
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli s9, s6, 16
+; RV32I-NEXT: slli s9, s4, 16
; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: and a3, t6, s3
+; RV32I-NEXT: and a3, s2, ra
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli s5, s6, 17
-; RV32I-NEXT: and a2, a2, s5
-; RV32I-NEXT: and a3, t6, a7
+; RV32I-NEXT: slli s8, s4, 17
+; RV32I-NEXT: and a2, a2, s8
+; RV32I-NEXT: and a3, s2, t1
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli s4, s6, 18
-; RV32I-NEXT: and a2, a2, s4
-; RV32I-NEXT: and a3, t6, t0
+; RV32I-NEXT: slli s7, s4, 18
+; RV32I-NEXT: and a2, a2, s7
+; RV32I-NEXT: and a3, s2, t2
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a1, t6, t1
-; RV32I-NEXT: slli s8, s6, 19
-; RV32I-NEXT: and a2, a2, s8
+; RV32I-NEXT: and a1, s2, t3
+; RV32I-NEXT: slli s6, s4, 19
+; RV32I-NEXT: and a2, a2, s6
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli s2, s6, 20
-; RV32I-NEXT: and a1, a1, s2
-; RV32I-NEXT: and a3, t6, t3
+; RV32I-NEXT: slli s5, s4, 20
+; RV32I-NEXT: and a1, a1, s5
+; RV32I-NEXT: and a3, s2, t4
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli t3, s6, 21
-; RV32I-NEXT: and a2, a2, t3
-; RV32I-NEXT: and a3, t6, t4
+; RV32I-NEXT: slli t4, s4, 21
+; RV32I-NEXT: and a2, a2, t4
+; RV32I-NEXT: and a3, s2, t5
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli t1, s6, 22
-; RV32I-NEXT: and a2, a2, t1
-; RV32I-NEXT: and a3, t6, t5
+; RV32I-NEXT: slli t3, s4, 22
+; RV32I-NEXT: and a2, a2, t3
+; RV32I-NEXT: and a3, s2, t6
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a3, a2, -1
-; RV32I-NEXT: and a2, t6, s0
+; RV32I-NEXT: and a2, s2, s0
; RV32I-NEXT: seqz a4, a2
-; RV32I-NEXT: slli s3, s6, 23
-; RV32I-NEXT: and a3, a3, s3
+; RV32I-NEXT: slli a5, s4, 23
+; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw t0, 472(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a4, t0
+; RV32I-NEXT: lw t1, 488(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a4, t1
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a3, t6, s1
+; RV32I-NEXT: and a3, s2, t0
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a1, a3
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a3, t6, a5
+; RV32I-NEXT: and a3, s2, s3
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli s1, s6, 25
-; RV32I-NEXT: and a1, a1, s1
+; RV32I-NEXT: slli s0, s4, 25
+; RV32I-NEXT: and a1, a1, s0
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a4, t6, a6
-; RV32I-NEXT: slli a6, s6, 26
+; RV32I-NEXT: and a4, s2, a6
+; RV32I-NEXT: slli a6, s4, 26
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: lui a2, 65536
-; RV32I-NEXT: and a3, t6, a2
-; RV32I-NEXT: slli a7, s6, 27
+; RV32I-NEXT: and a3, s2, a7
+; RV32I-NEXT: slli a7, s4, 27
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a1, a1, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: lui a2, 131072
-; RV32I-NEXT: and a4, t6, a2
-; RV32I-NEXT: slli t4, s6, 28
-; RV32I-NEXT: and a3, a3, t4
+; RV32I-NEXT: and a4, s2, a2
+; RV32I-NEXT: slli t5, s4, 28
+; RV32I-NEXT: and a3, a3, t5
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: lui a2, 262144
-; RV32I-NEXT: and a3, t6, a2
-; RV32I-NEXT: slli t5, s6, 29
-; RV32I-NEXT: and a4, a4, t5
+; RV32I-NEXT: and a3, s2, a2
+; RV32I-NEXT: slli t6, s4, 29
+; RV32I-NEXT: and a4, a4, t6
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a1, a1, a4
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: srli a4, t6, 31
-; RV32I-NEXT: slli t2, s6, 30
-; RV32I-NEXT: and a3, a3, t2
+; RV32I-NEXT: srli a4, s2, 31
+; RV32I-NEXT: slli t0, s4, 30
+; RV32I-NEXT: and a3, a3, t0
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: slli s0, s6, 31
+; RV32I-NEXT: slli s1, s4, 31
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: and a4, a4, s0
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: lw a2, 488(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 444(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, a2
-; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: and a4, a4, s1
+; RV32I-NEXT: xor a4, a1, a4
+; RV32I-NEXT: lw a1, 504(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, a1
+; RV32I-NEXT: xor a0, a0, a4
; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: lw a1, 448(sp) # 4-byte Folded Reload
-; RV32I-NEXT: or a1, a1, a3
-; RV32I-NEXT: lw a5, 328(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a5, a0, a5
-; RV32I-NEXT: lw a3, 464(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a3, a3, 1
-; RV32I-NEXT: lw a0, 468(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli t6, a0, 1
-; RV32I-NEXT: srli a1, a1, 1
-; RV32I-NEXT: slli a4, t6, 31
-; RV32I-NEXT: or s7, a3, a4
-; RV32I-NEXT: xor a4, a1, a5
-; RV32I-NEXT: and a3, t6, a2
-; RV32I-NEXT: and a2, a0, a2
-; RV32I-NEXT: lw a0, 460(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 332(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t6, a0, a1
-; RV32I-NEXT: lw a0, 456(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a0, s6
-; RV32I-NEXT: lw a0, 484(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 464(sp) # 4-byte Folded Reload
+; RV32I-NEXT: or a4, a4, a3
+; RV32I-NEXT: lw a2, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a2, a0, a2
+; RV32I-NEXT: lw a3, 484(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli s3, a3, 1
+; RV32I-NEXT: lw a3, 480(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a0, a3, 1
+; RV32I-NEXT: srli t2, a4, 1
+; RV32I-NEXT: slli a4, a0, 31
+; RV32I-NEXT: or s3, s3, a4
+; RV32I-NEXT: xor t2, t2, a2
+; RV32I-NEXT: and a4, a0, a1
+; RV32I-NEXT: and a3, a3, a1
+; RV32I-NEXT: lw a0, 476(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 348(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a0, a2
+; RV32I-NEXT: lw a0, 472(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, a0, s4
+; RV32I-NEXT: lw a0, 500(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 340(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a0, a1
-; RV32I-NEXT: lw a0, 452(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 320(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a0, a0, a5
-; RV32I-NEXT: xor t6, s6, t6
+; RV32I-NEXT: lw a0, 468(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 336(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a0, a0, ra
+; RV32I-NEXT: xor a2, s2, a2
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: lw a1, 440(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a5, 316(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a1, a1, a5
-; RV32I-NEXT: lw a5, 436(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 312(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s6
-; RV32I-NEXT: xor a1, a1, s6
-; RV32I-NEXT: lw a5, 432(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 308(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s6
-; RV32I-NEXT: xor a0, t6, a0
-; RV32I-NEXT: xor a1, a1, s6
-; RV32I-NEXT: lw a5, 428(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t6, 304(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t6, a5, t6
-; RV32I-NEXT: lw a5, 424(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 300(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s6
-; RV32I-NEXT: xor t6, t6, s6
-; RV32I-NEXT: lw a5, 420(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 296(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s6
-; RV32I-NEXT: xor t6, t6, s6
-; RV32I-NEXT: lw a5, 416(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 292(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s6
+; RV32I-NEXT: lw a1, 456(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 332(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, s2
+; RV32I-NEXT: lw s2, 452(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 328(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, ra
+; RV32I-NEXT: xor a1, a1, s2
+; RV32I-NEXT: lw s2, 448(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 324(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, ra
+; RV32I-NEXT: xor a0, a2, a0
+; RV32I-NEXT: xor a1, a1, s2
+; RV32I-NEXT: lw a2, 444(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 320(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: lw s2, 440(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 316(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, ra
+; RV32I-NEXT: xor a2, a2, s2
+; RV32I-NEXT: lw s2, 436(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 312(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, ra
+; RV32I-NEXT: xor a2, a2, s2
+; RV32I-NEXT: lw s2, 432(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 308(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s4
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, t6, s6
-; RV32I-NEXT: lw a5, 412(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw t6, 288(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t6, a5, t6
-; RV32I-NEXT: lw a5, 408(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 284(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s6
-; RV32I-NEXT: xor t6, t6, s6
-; RV32I-NEXT: lw a5, 404(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, ra
+; RV32I-NEXT: xor a1, a2, s2
+; RV32I-NEXT: lw a2, 428(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 304(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: lw s2, 424(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 300(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s4
+; RV32I-NEXT: xor a2, a2, s2
+; RV32I-NEXT: lw s2, 420(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 296(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s4
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, t6, s6
-; RV32I-NEXT: lw a5, 400(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t6, a5, s11
-; RV32I-NEXT: lw a5, 396(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s10
-; RV32I-NEXT: xor t6, t6, s6
-; RV32I-NEXT: lw a5, 392(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s6, a5, s9
-; RV32I-NEXT: xor t6, t6, s6
-; RV32I-NEXT: lw a5, 388(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s5, a5, s5
-; RV32I-NEXT: xor t6, t6, s5
-; RV32I-NEXT: lw a5, 384(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, a5, s4
+; RV32I-NEXT: xor a1, a2, s2
+; RV32I-NEXT: lw a2, 416(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, s11
+; RV32I-NEXT: lw s2, 412(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s10
+; RV32I-NEXT: xor a2, a2, s2
+; RV32I-NEXT: lw s2, 408(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s9
+; RV32I-NEXT: xor a2, a2, s2
+; RV32I-NEXT: lw s2, 404(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s8
+; RV32I-NEXT: xor a2, a2, s2
+; RV32I-NEXT: lw s2, 400(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s7
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, t6, s4
-; RV32I-NEXT: lw a5, 380(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t6, a5, s8
+; RV32I-NEXT: xor a1, a2, s2
+; RV32I-NEXT: lw a2, 396(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a2, a2, s6
+; RV32I-NEXT: lw s2, 392(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s2, s2, s5
+; RV32I-NEXT: xor a2, a2, s2
+; RV32I-NEXT: lw s2, 388(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t4, s2, t4
+; RV32I-NEXT: xor a2, a2, t4
+; RV32I-NEXT: lw t4, 384(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t3, t4, t3
+; RV32I-NEXT: xor a2, a2, t3
+; RV32I-NEXT: lw t3, 380(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, t3, a5
+; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: lw a5, 376(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s2, a5, s2
-; RV32I-NEXT: xor t6, t6, s2
+; RV32I-NEXT: and a5, a5, t1
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: xor a2, a2, a5
+; RV32I-NEXT: lw a1, 492(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, s0
; RV32I-NEXT: lw a5, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t3, a5, t3
-; RV32I-NEXT: xor t3, t6, t3
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: xor a1, a1, a5
; RV32I-NEXT: lw a5, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, a5, t1
-; RV32I-NEXT: xor t1, t3, t1
+; RV32I-NEXT: and a5, a5, a7
+; RV32I-NEXT: xor a1, a1, a5
; RV32I-NEXT: lw a5, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a5, a5, s3
-; RV32I-NEXT: xor a5, t1, a5
-; RV32I-NEXT: lw t1, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and t1, t1, t0
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a5, t1
-; RV32I-NEXT: lw a5, 476(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, t5
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: lw a5, 360(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, t6
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: lw a5, 356(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a5, a5, t0
+; RV32I-NEXT: xor a1, a1, a5
+; RV32I-NEXT: lw a5, 352(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s1
-; RV32I-NEXT: lw t0, 356(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, t0, a6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 352(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 348(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, t4
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 344(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, t5
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 340(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, t2
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lw a6, 336(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a6, a6, s0
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a5, a6
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: xor a1, a1, a5
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: slli a2, a2, 1
-; RV32I-NEXT: or a2, a3, a2
-; RV32I-NEXT: lw a1, 480(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli a3, a3, 1
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: lw a1, 496(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 0(a1)
-; RV32I-NEXT: sw a4, 4(a1)
-; RV32I-NEXT: srli a2, a2, 1
-; RV32I-NEXT: sw s7, 8(a1)
-; RV32I-NEXT: sw a2, 12(a1)
-; RV32I-NEXT: lw ra, 540(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 536(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 532(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 528(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 524(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 520(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s5, 516(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s6, 512(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 508(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 504(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s9, 500(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s10, 496(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s11, 492(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw t2, 4(a1)
+; RV32I-NEXT: srli a3, a3, 1
+; RV32I-NEXT: sw s3, 8(a1)
+; RV32I-NEXT: sw a3, 12(a1)
+; RV32I-NEXT: lw ra, 556(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 552(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 548(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 544(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 540(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 536(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s5, 532(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s6, 528(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s7, 524(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 520(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s9, 516(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s10, 512(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s11, 508(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
@@ -27755,7 +27782,7 @@ define i128 @clmul_i128_zext(i64 %x, i64 %y) {
; RV32I-NEXT: .cfi_restore s9
; RV32I-NEXT: .cfi_restore s10
; RV32I-NEXT: .cfi_restore s11
-; RV32I-NEXT: addi sp, sp, 544
+; RV32I-NEXT: addi sp, sp, 560
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
@@ -27789,577 +27816,579 @@ define i128 @clmul_i128_zext(i64 %x, i64 %y) {
; RV64I-NEXT: .cfi_offset s9, -88
; RV64I-NEXT: .cfi_offset s10, -96
; RV64I-NEXT: .cfi_offset s11, -104
-; RV64I-NEXT: mv a6, a1
-; RV64I-NEXT: mv s10, a0
-; RV64I-NEXT: lui a5, 4080
+; RV64I-NEXT: mv t2, a1
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lui a6, 4080
; RV64I-NEXT: srli a0, a0, 24
-; RV64I-NEXT: li t6, 255
-; RV64I-NEXT: and a0, a0, a5
-; RV64I-NEXT: srli a1, s10, 8
-; RV64I-NEXT: slli s2, t6, 24
-; RV64I-NEXT: and a1, a1, s2
+; RV64I-NEXT: li s2, 255
+; RV64I-NEXT: and a0, a0, a6
+; RV64I-NEXT: srli a1, s0, 8
+; RV64I-NEXT: slli s3, s2, 24
+; RV64I-NEXT: and a1, a1, s3
; RV64I-NEXT: lui a2, 16
-; RV64I-NEXT: srli a3, s10, 40
-; RV64I-NEXT: addi s1, a2, -256
-; RV64I-NEXT: lui s3, 16
-; RV64I-NEXT: and a3, a3, s1
-; RV64I-NEXT: srli a4, s10, 56
+; RV64I-NEXT: srli a4, s0, 40
+; RV64I-NEXT: addi s2, a2, -256
+; RV64I-NEXT: lui a3, 16
+; RV64I-NEXT: and a4, a4, s2
+; RV64I-NEXT: srli a5, s0, 56
; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: or a3, a3, a4
-; RV64I-NEXT: or a0, a0, a3
-; RV64I-NEXT: and a1, s10, a5
-; RV64I-NEXT: srliw a3, s10, 24
+; RV64I-NEXT: or a4, a4, a5
+; RV64I-NEXT: or a0, a0, a4
+; RV64I-NEXT: and a1, s0, a6
+; RV64I-NEXT: srliw a4, s0, 24
; RV64I-NEXT: slli a1, a1, 24
-; RV64I-NEXT: slli a3, a3, 32
-; RV64I-NEXT: or a1, a1, a3
-; RV64I-NEXT: and a3, s10, s1
-; RV64I-NEXT: slli a3, a3, 40
-; RV64I-NEXT: slli a2, s10, 56
+; RV64I-NEXT: slli a4, a4, 32
+; RV64I-NEXT: or a1, a1, a4
+; RV64I-NEXT: and a4, s0, s2
+; RV64I-NEXT: slli a4, a4, 40
+; RV64I-NEXT: slli a2, s0, 56
; RV64I-NEXT: sd a2, 160(sp) # 8-byte Folded Spill
-; RV64I-NEXT: or a3, a2, a3
-; RV64I-NEXT: lui a4, 61681
-; RV64I-NEXT: or a1, a3, a1
-; RV64I-NEXT: addi a7, a4, -241
+; RV64I-NEXT: or a4, a2, a4
+; RV64I-NEXT: lui a5, 61681
+; RV64I-NEXT: or a1, a4, a1
+; RV64I-NEXT: addi a7, a5, -241
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slli a1, a7, 32
-; RV64I-NEXT: srli a3, a0, 4
-; RV64I-NEXT: add t6, a7, a1
-; RV64I-NEXT: and a1, a3, t6
-; RV64I-NEXT: and a0, a0, t6
-; RV64I-NEXT: lui a3, 209715
+; RV64I-NEXT: srli a4, a0, 4
+; RV64I-NEXT: add a7, a7, a1
+; RV64I-NEXT: and a1, a4, a7
+; RV64I-NEXT: and a0, a0, a7
+; RV64I-NEXT: lui a4, 209715
; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: addi t0, a3, 819
+; RV64I-NEXT: addi t0, a4, 819
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slli a1, t0, 32
-; RV64I-NEXT: srli a3, a0, 2
+; RV64I-NEXT: srli a4, a0, 2
; RV64I-NEXT: add t0, t0, a1
-; RV64I-NEXT: and a1, a3, t0
+; RV64I-NEXT: and a1, a4, t0
; RV64I-NEXT: and a0, a0, t0
-; RV64I-NEXT: lui a3, 349525
+; RV64I-NEXT: lui a4, 349525
; RV64I-NEXT: slli a0, a0, 2
-; RV64I-NEXT: addi t1, a3, 1365
+; RV64I-NEXT: addi t1, a4, 1365
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slli a1, t1, 32
-; RV64I-NEXT: srli a3, a0, 1
+; RV64I-NEXT: srli a2, a0, 1
+; RV64I-NEXT: sd a2, 144(sp) # 8-byte Folded Spill
; RV64I-NEXT: add t1, t1, a1
-; RV64I-NEXT: and a1, a3, t1
-; RV64I-NEXT: srli a3, a6, 24
-; RV64I-NEXT: srli a4, a6, 8
+; RV64I-NEXT: and a1, a2, t1
+; RV64I-NEXT: srli a4, t2, 24
+; RV64I-NEXT: srli a5, t2, 8
; RV64I-NEXT: lui a2, 4080
-; RV64I-NEXT: and a3, a3, a2
-; RV64I-NEXT: and a4, a4, s2
-; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a4, a6, 40
-; RV64I-NEXT: and a4, a4, s1
-; RV64I-NEXT: srli a5, a6, 56
+; RV64I-NEXT: and a4, a4, a2
+; RV64I-NEXT: and a5, a5, s3
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a5, t2, 40
+; RV64I-NEXT: and a5, a5, s2
+; RV64I-NEXT: srli a6, t2, 56
+; RV64I-NEXT: or a5, a5, a6
+; RV64I-NEXT: and a6, t2, a2
+; RV64I-NEXT: slli a6, a6, 24
+; RV64I-NEXT: srliw t3, t2, 24
+; RV64I-NEXT: slli t3, t3, 32
+; RV64I-NEXT: and t4, t2, s2
+; RV64I-NEXT: slli t4, t4, 40
+; RV64I-NEXT: slli t5, t2, 56
+; RV64I-NEXT: or a6, a6, t3
+; RV64I-NEXT: or t3, t5, t4
; RV64I-NEXT: or a4, a4, a5
-; RV64I-NEXT: and a5, a6, a2
-; RV64I-NEXT: slli a5, a5, 24
-; RV64I-NEXT: srliw t2, a6, 24
-; RV64I-NEXT: slli t2, t2, 32
-; RV64I-NEXT: and t3, a6, s1
-; RV64I-NEXT: slli t3, t3, 40
-; RV64I-NEXT: slli t4, a6, 56
-; RV64I-NEXT: or a5, a5, t2
-; RV64I-NEXT: or t2, t4, t3
-; RV64I-NEXT: or a3, a3, a4
-; RV64I-NEXT: or a4, t2, a5
+; RV64I-NEXT: or a5, t3, a6
; RV64I-NEXT: and a0, a0, t1
-; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a4, a3, 4
-; RV64I-NEXT: and a3, a3, t6
-; RV64I-NEXT: and a4, a4, t6
-; RV64I-NEXT: slli a3, a3, 4
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a5, a4, 4
+; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, a5, a7
+; RV64I-NEXT: slli a4, a4, 4
; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a4, a3, 2
-; RV64I-NEXT: and a3, a3, t0
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a5, a4, 2
; RV64I-NEXT: and a4, a4, t0
-; RV64I-NEXT: slli a3, a3, 2
+; RV64I-NEXT: and a5, a5, t0
+; RV64I-NEXT: slli a4, a4, 2
; RV64I-NEXT: or a1, a1, a0
-; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a0, a3, 1
-; RV64I-NEXT: and s5, a3, t1
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a0, a4, 1
+; RV64I-NEXT: and s6, a4, t1
; RV64I-NEXT: and a0, a0, t1
-; RV64I-NEXT: slli s9, s5, 1
-; RV64I-NEXT: slli a3, a1, 1
-; RV64I-NEXT: or a0, a0, s9
-; RV64I-NEXT: andi a4, a0, 2
-; RV64I-NEXT: andi a5, a0, 1
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: slli s10, s6, 1
+; RV64I-NEXT: slli a4, a1, 1
+; RV64I-NEXT: or a0, a0, s10
+; RV64I-NEXT: andi a5, a0, 2
+; RV64I-NEXT: andi a6, a0, 1
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: seqz a6, a6
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a3, a4, a3
-; RV64I-NEXT: and a5, a5, a1
-; RV64I-NEXT: slli a4, a1, 2
-; RV64I-NEXT: andi t2, a0, 4
-; RV64I-NEXT: seqz t2, t2
-; RV64I-NEXT: andi t3, a0, 8
-; RV64I-NEXT: addi t2, t2, -1
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: and a4, a5, a4
+; RV64I-NEXT: and a5, a6, a1
+; RV64I-NEXT: slli a6, a1, 2
+; RV64I-NEXT: andi t3, a0, 4
; RV64I-NEXT: seqz t3, t3
-; RV64I-NEXT: slli t4, a1, 3
+; RV64I-NEXT: andi t4, a0, 8
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: and a4, t2, a4
-; RV64I-NEXT: and t2, t3, t4
-; RV64I-NEXT: xor a3, a5, a3
-; RV64I-NEXT: xor a4, a4, t2
-; RV64I-NEXT: xor a3, a3, a4
-; RV64I-NEXT: andi a4, a0, 16
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: andi t2, a0, 32
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: seqz a5, t2
-; RV64I-NEXT: slli t2, a1, 5
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a5, a5, t2
-; RV64I-NEXT: andi t2, a0, 64
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, t2
-; RV64I-NEXT: slli t2, a1, 6
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a5, a5, t2
-; RV64I-NEXT: andi t2, a0, 128
+; RV64I-NEXT: seqz t4, t4
+; RV64I-NEXT: slli t5, a1, 3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: and a6, t3, a6
+; RV64I-NEXT: and t3, t4, t5
+; RV64I-NEXT: xor a4, a5, a4
+; RV64I-NEXT: xor a5, a6, t3
; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, t2
-; RV64I-NEXT: slli t2, a1, 7
+; RV64I-NEXT: andi a5, a0, 16
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and a5, a5, t2
-; RV64I-NEXT: andi t2, a0, 256
-; RV64I-NEXT: slli t3, a1, 8
-; RV64I-NEXT: seqz t2, t2
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: andi t4, a0, 512
-; RV64I-NEXT: and t2, t2, t3
-; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: slli t4, a1, 9
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: and t2, t3, t4
-; RV64I-NEXT: xor a4, a3, a4
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: slli t2, a1, 10
-; RV64I-NEXT: andi a3, a0, 1024
-; RV64I-NEXT: seqz t3, a3
-; RV64I-NEXT: li s0, 1
+; RV64I-NEXT: andi t3, a0, 32
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: slli t3, a1, 5
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: andi t3, a0, 64
+; RV64I-NEXT: xor a5, a5, a6
+; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: slli t3, a1, 6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: andi t3, a0, 128
+; RV64I-NEXT: xor a5, a5, a6
+; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: slli t3, a1, 7
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: andi t3, a0, 256
+; RV64I-NEXT: slli t4, a1, 8
+; RV64I-NEXT: seqz t3, t3
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli a2, s0, 11
-; RV64I-NEXT: sd a2, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: slli t3, a1, 11
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: and t2, t2, t3
-; RV64I-NEXT: lui a2, 1
-; RV64I-NEXT: slli t3, a1, 12
-; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: lui a2, 2
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and t5, a0, a2
-; RV64I-NEXT: and t3, t4, t3
+; RV64I-NEXT: andi t5, a0, 512
+; RV64I-NEXT: and t3, t3, t4
; RV64I-NEXT: seqz t4, t5
-; RV64I-NEXT: slli t5, a1, 13
+; RV64I-NEXT: slli t5, a1, 9
; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: and t3, t4, t5
-; RV64I-NEXT: xor t2, t2, t3
-; RV64I-NEXT: lui a2, 4
-; RV64I-NEXT: slli t3, a1, 14
-; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: lui a2, 8
+; RV64I-NEXT: xor a5, a4, a5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: slli t3, a1, 10
+; RV64I-NEXT: andi a4, a0, 1024
+; RV64I-NEXT: seqz t4, a4
+; RV64I-NEXT: li s1, 1
; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: slli a2, s1, 11
+; RV64I-NEXT: sd a2, 152(sp) # 8-byte Folded Spill
; RV64I-NEXT: and t3, t4, t3
-; RV64I-NEXT: seqz t4, t5
-; RV64I-NEXT: slli t5, a1, 15
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor t2, t2, t3
-; RV64I-NEXT: and t3, t4, t5
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: xor a5, t2, t3
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 16
-; RV64I-NEXT: and t2, a0, s3
-; RV64I-NEXT: seqz t2, t2
+; RV64I-NEXT: and t4, a0, a2
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: seqz t3, t4
+; RV64I-NEXT: slli t4, a1, 11
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: lui a2, 1
+; RV64I-NEXT: slli t4, a1, 12
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: seqz t5, t5
+; RV64I-NEXT: lui a2, 2
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: and t6, a0, a2
+; RV64I-NEXT: and t4, t5, t4
+; RV64I-NEXT: seqz t5, t6
+; RV64I-NEXT: slli t6, a1, 13
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: xor t3, t3, t4
+; RV64I-NEXT: and t4, t5, t6
+; RV64I-NEXT: xor t3, t3, t4
+; RV64I-NEXT: lui a2, 4
+; RV64I-NEXT: slli t4, a1, 14
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: seqz t5, t5
+; RV64I-NEXT: lui a2, 8
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: and t6, a0, a2
+; RV64I-NEXT: and t4, t5, t4
+; RV64I-NEXT: seqz t5, t6
+; RV64I-NEXT: slli t6, a1, 15
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: xor t3, t3, t4
+; RV64I-NEXT: and t4, t5, t6
+; RV64I-NEXT: xor a5, a5, a6
+; RV64I-NEXT: xor a6, t3, t4
+; RV64I-NEXT: xor a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 16
+; RV64I-NEXT: and t3, a0, a3
+; RV64I-NEXT: seqz t3, t3
; RV64I-NEXT: lui a2, 32
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: and a5, t2, a5
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: slli t3, a1, 17
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: and t4, a0, a2
+; RV64I-NEXT: and a6, t3, a6
+; RV64I-NEXT: seqz t3, t4
+; RV64I-NEXT: slli t4, a1, 17
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: and t3, t3, t4
; RV64I-NEXT: lui a2, 64
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: and t2, a0, a2
-; RV64I-NEXT: slli t3, a1, 18
-; RV64I-NEXT: seqz t2, t2
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: lui a2, 128
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: slli t3, a1, 19
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: slli t4, a1, 18
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: lui a2, 128
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: and t4, a0, a2
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: seqz t3, t4
+; RV64I-NEXT: slli t4, a1, 19
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: and t3, t3, t4
; RV64I-NEXT: lui a2, 256
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: and t2, a0, a2
-; RV64I-NEXT: slli t3, a1, 20
-; RV64I-NEXT: seqz t2, t2
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: lui a2, 512
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: slli t3, a1, 21
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: slli t4, a1, 20
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: lui a2, 512
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: and t4, a0, a2
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: seqz t3, t4
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: slli t4, a1, 21
+; RV64I-NEXT: and t3, t3, t4
; RV64I-NEXT: lui a2, 1024
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: and t2, a0, a2
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, t2
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a2, 2048
-; RV64I-NEXT: slli t2, a1, 22
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: and a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: lui a2, 4096
-; RV64I-NEXT: slli t3, a1, 23
+; RV64I-NEXT: xor a5, a5, a6
+; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: lui a2, 2048
+; RV64I-NEXT: slli t3, a1, 22
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: and a6, a6, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 24
+; RV64I-NEXT: lui a2, 4096
+; RV64I-NEXT: slli t4, a1, 23
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 24
; RV64I-NEXT: lui a2, 8192
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: lui a2, 16384
-; RV64I-NEXT: slli t3, a1, 25
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 26
+; RV64I-NEXT: lui a2, 16384
+; RV64I-NEXT: slli t4, a1, 25
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 26
; RV64I-NEXT: lui a2, 32768
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: lui a2, 65536
-; RV64I-NEXT: slli t3, a1, 27
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t4, a1, 28
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: and t2, t3, t4
-; RV64I-NEXT: xor a5, a5, t2
+; RV64I-NEXT: lui a2, 65536
+; RV64I-NEXT: slli t4, a1, 27
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t5, a1, 28
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: and t3, t4, t5
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: lui a2, 131072
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: and a5, a0, a2
-; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: xor a5, a5, a6
+; RV64I-NEXT: and a6, a0, a2
+; RV64I-NEXT: seqz a6, a6
; RV64I-NEXT: lui a2, 262144
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and t2, a0, a2
-; RV64I-NEXT: seqz t2, t2
-; RV64I-NEXT: slli t3, a1, 29
-; RV64I-NEXT: and a5, a5, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli t3, a1, 30
-; RV64I-NEXT: sraiw t4, a0, 31
-; RV64I-NEXT: and t2, t2, t3
-; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 31
-; RV64I-NEXT: slli a2, s0, 32
-; RV64I-NEXT: sd a2, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t3, t2
+; RV64I-NEXT: addi a6, a6, -1
; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli a2, s0, 33
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: slli t4, a1, 29
+; RV64I-NEXT: and a6, a6, t4
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: slli t4, a1, 30
+; RV64I-NEXT: sraiw t5, a0, 31
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 31
+; RV64I-NEXT: slli a2, s1, 32
; RV64I-NEXT: sd a2, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, a1, 32
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 33
-; RV64I-NEXT: slli a2, s0, 34
+; RV64I-NEXT: slli a2, s1, 33
; RV64I-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli a2, s0, 35
+; RV64I-NEXT: slli t4, a1, 32
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 33
+; RV64I-NEXT: slli a2, s1, 34
; RV64I-NEXT: sd a2, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, a1, 34
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 35
-; RV64I-NEXT: slli a2, s0, 36
+; RV64I-NEXT: slli a2, s1, 35
; RV64I-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli t3, a1, 36
-; RV64I-NEXT: and t2, t2, t3
-; RV64I-NEXT: slli a2, s0, 37
-; RV64I-NEXT: sd a2, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: and t2, a0, a2
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, t2
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a2, s0, 38
-; RV64I-NEXT: sd a2, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t2, a1, 37
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: and a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli a2, s0, 39
+; RV64I-NEXT: slli t4, a1, 34
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 35
+; RV64I-NEXT: slli a2, s1, 36
; RV64I-NEXT: sd a2, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, a1, 38
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 39
-; RV64I-NEXT: slli a2, s0, 40
+; RV64I-NEXT: slli t4, a1, 36
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: slli a2, s1, 37
; RV64I-NEXT: sd a2, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t3, t2
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli a2, s0, 41
+; RV64I-NEXT: xor a5, a5, a6
+; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli a2, s1, 38
+; RV64I-NEXT: sd a2, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t3, a1, 37
+; RV64I-NEXT: and t4, a0, a2
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: seqz t3, t4
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: slli a2, s1, 39
+; RV64I-NEXT: sd a2, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t4, a1, 38
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 39
+; RV64I-NEXT: slli a2, s1, 40
; RV64I-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, a1, 40
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 41
-; RV64I-NEXT: slli a2, s0, 42
+; RV64I-NEXT: slli a2, s1, 41
; RV64I-NEXT: sd a2, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli a2, s0, 43
+; RV64I-NEXT: slli t4, a1, 40
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 41
+; RV64I-NEXT: slli a2, s1, 42
; RV64I-NEXT: sd a2, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, a1, 42
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a5, a5, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 43
-; RV64I-NEXT: slli a2, s0, 44
+; RV64I-NEXT: slli a2, s1, 43
; RV64I-NEXT: sd a2, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli a2, s0, 45
+; RV64I-NEXT: slli t4, a1, 42
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 43
+; RV64I-NEXT: slli a2, s1, 44
; RV64I-NEXT: sd a2, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, a1, 44
+; RV64I-NEXT: and t3, t4, t3
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: seqz t3, t4
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t4, a1, 45
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: and t2, t3, t4
-; RV64I-NEXT: xor a5, a5, t2
-; RV64I-NEXT: slli a2, s0, 46
-; RV64I-NEXT: sd a2, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor a7, a4, a5
-; RV64I-NEXT: and a4, a0, a2
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a2, s0, 47
+; RV64I-NEXT: slli a2, s1, 45
; RV64I-NEXT: sd a2, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: and t2, a0, a2
-; RV64I-NEXT: seqz t2, t2
-; RV64I-NEXT: slli t3, a1, 46
-; RV64I-NEXT: and a4, a4, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli t3, a1, 47
-; RV64I-NEXT: slli a2, s0, 48
+; RV64I-NEXT: slli t4, a1, 44
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t5, a1, 45
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: and t3, t4, t5
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: slli a2, s1, 46
; RV64I-NEXT: sd a2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a6, a5, a6
+; RV64I-NEXT: and a5, a0, a2
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: slli a2, s1, 47
+; RV64I-NEXT: sd a2, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a5, a5, -1
; RV64I-NEXT: and t3, a0, a2
-; RV64I-NEXT: xor a4, a4, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli a2, s0, 49
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: slli t4, a1, 46
+; RV64I-NEXT: and a5, a5, t4
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: slli t4, a1, 47
+; RV64I-NEXT: slli a2, s1, 48
; RV64I-NEXT: sd a2, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t3, a1, 48
+; RV64I-NEXT: and t3, t3, t4
; RV64I-NEXT: and t4, a0, a2
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: xor a5, a5, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a4, a4, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 49
-; RV64I-NEXT: slli ra, s0, 50
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, ra
-; RV64I-NEXT: xor a4, a4, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli s11, s0, 51
-; RV64I-NEXT: slli t3, a1, 50
-; RV64I-NEXT: and t4, a0, s11
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: slli a2, s1, 49
+; RV64I-NEXT: sd a2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli t4, a1, 48
+; RV64I-NEXT: and t5, a0, a2
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a5, a5, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 49
+; RV64I-NEXT: slli ra, s1, 50
+; RV64I-NEXT: and t3, t4, t3
+; RV64I-NEXT: and t4, a0, ra
+; RV64I-NEXT: xor a5, a5, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a4, a4, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 51
-; RV64I-NEXT: slli s8, s0, 52
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, s8
-; RV64I-NEXT: xor a4, a4, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli s7, s0, 53
-; RV64I-NEXT: slli t3, a1, 52
-; RV64I-NEXT: and t4, a0, s7
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: slli s11, s1, 51
+; RV64I-NEXT: slli t4, a1, 50
+; RV64I-NEXT: and t5, a0, s11
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a5, a5, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 51
+; RV64I-NEXT: slli s9, s1, 52
+; RV64I-NEXT: and t3, t4, t3
+; RV64I-NEXT: and t4, a0, s9
+; RV64I-NEXT: xor a5, a5, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a4, a4, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 53
-; RV64I-NEXT: slli s6, s0, 54
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, s6
-; RV64I-NEXT: xor a4, a4, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli s5, s0, 55
-; RV64I-NEXT: slli t3, a1, 54
-; RV64I-NEXT: and t4, a0, s5
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: slli s8, s1, 53
+; RV64I-NEXT: slli t4, a1, 52
+; RV64I-NEXT: and t5, a0, s8
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a5, a5, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 53
+; RV64I-NEXT: slli s7, s1, 54
+; RV64I-NEXT: and t3, t4, t3
+; RV64I-NEXT: and t4, a0, s7
+; RV64I-NEXT: xor a5, a5, t3
; RV64I-NEXT: seqz t3, t4
-; RV64I-NEXT: xor a4, a4, t2
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t2, a1, 55
-; RV64I-NEXT: slli s4, s0, 56
-; RV64I-NEXT: and t2, t3, t2
-; RV64I-NEXT: and t3, a0, s4
-; RV64I-NEXT: xor a5, a4, t2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli s3, s0, 57
-; RV64I-NEXT: slli t3, a1, 56
-; RV64I-NEXT: and t4, a0, s3
-; RV64I-NEXT: and t2, t2, t3
+; RV64I-NEXT: slli s6, s1, 55
+; RV64I-NEXT: slli t4, a1, 54
+; RV64I-NEXT: and t5, a0, s6
+; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: xor a5, a5, t3
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t3, a1, 55
+; RV64I-NEXT: slli s5, s1, 56
+; RV64I-NEXT: and t3, t4, t3
+; RV64I-NEXT: and t4, a0, s5
+; RV64I-NEXT: xor a5, a5, t3
; RV64I-NEXT: seqz t3, t4
; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: slli t5, s0, 58
-; RV64I-NEXT: slli t4, a1, 57
-; RV64I-NEXT: and a2, a0, t5
+; RV64I-NEXT: slli s4, s1, 57
+; RV64I-NEXT: slli t4, a1, 56
+; RV64I-NEXT: and t5, a0, s4
; RV64I-NEXT: and t3, t3, t4
+; RV64I-NEXT: seqz t4, t5
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: slli t6, s1, 58
+; RV64I-NEXT: slli t5, a1, 57
+; RV64I-NEXT: and a2, a0, t6
+; RV64I-NEXT: and t4, t4, t5
; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: xor t2, t2, t3
+; RV64I-NEXT: xor t3, t3, t4
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli t3, a1, 58
-; RV64I-NEXT: slli t4, s0, 59
-; RV64I-NEXT: and a2, a2, t3
-; RV64I-NEXT: and t3, a0, t4
-; RV64I-NEXT: xor a4, t2, a2
-; RV64I-NEXT: seqz t2, t3
-; RV64I-NEXT: addi t2, t2, -1
-; RV64I-NEXT: slli t3, s0, 60
+; RV64I-NEXT: slli t4, a1, 58
+; RV64I-NEXT: slli t5, s1, 59
+; RV64I-NEXT: and a2, a2, t4
+; RV64I-NEXT: and t4, a0, t5
+; RV64I-NEXT: xor a4, t3, a2
+; RV64I-NEXT: seqz t3, t4
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: slli t4, s1, 60
; RV64I-NEXT: slli a2, a1, 59
-; RV64I-NEXT: and a3, a0, t3
-; RV64I-NEXT: and a2, t2, a2
+; RV64I-NEXT: and a3, a0, t4
+; RV64I-NEXT: and a2, t3, a2
; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a4, a2
; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: slli a4, a1, 60
-; RV64I-NEXT: slli t2, s0, 61
+; RV64I-NEXT: slli t3, s1, 61
; RV64I-NEXT: and a3, a3, a4
-; RV64I-NEXT: and a4, a0, t2
+; RV64I-NEXT: and a4, a0, t3
; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: seqz a3, a4
-; RV64I-NEXT: addi a4, a3, -1
-; RV64I-NEXT: slli a3, s0, 62
-; RV64I-NEXT: and a0, a0, a3
-; RV64I-NEXT: slli s0, a1, 61
-; RV64I-NEXT: and a4, a4, s0
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a4, a1, 61
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slli a4, s1, 62
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a0, a0, a4
+; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: srli a4, s9, 63
-; RV64I-NEXT: slli s0, a1, 62
-; RV64I-NEXT: and a0, a0, s0
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a1, a1, 63
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: srli a3, s10, 63
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: seqz a1, a3
+; RV64I-NEXT: ld a3, 144(sp) # 8-byte Folded Reload
+; RV64I-NEXT: slli a3, a3, 63
+; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: and a1, a4, a1
-; RV64I-NEXT: xor a2, a7, a5
+; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: xor a2, a6, a5
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: srli a1, a0, 40
-; RV64I-NEXT: and a1, a1, s1
+; RV64I-NEXT: and a1, a1, s2
; RV64I-NEXT: srli a2, a0, 56
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: srli a2, a0, 24
-; RV64I-NEXT: srli a4, a0, 8
-; RV64I-NEXT: and a4, a4, s2
+; RV64I-NEXT: srli a3, a0, 8
+; RV64I-NEXT: and a3, a3, s3
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: or a2, a4, a2
-; RV64I-NEXT: srliw a4, a0, 24
-; RV64I-NEXT: slli a4, a4, 32
+; RV64I-NEXT: or a2, a3, a2
+; RV64I-NEXT: srliw a3, a0, 24
+; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: and a5, a0, a5
; RV64I-NEXT: slli a5, a5, 24
-; RV64I-NEXT: and a7, a0, s1
+; RV64I-NEXT: and a6, a0, s2
; RV64I-NEXT: slli a0, a0, 56
-; RV64I-NEXT: slli a7, a7, 40
-; RV64I-NEXT: or a4, a5, a4
-; RV64I-NEXT: or a0, a0, a7
+; RV64I-NEXT: slli a6, a6, 40
+; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: or a0, a0, a6
; RV64I-NEXT: or a1, a2, a1
-; RV64I-NEXT: or a0, a0, a4
+; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: and a0, a0, t6
-; RV64I-NEXT: and a1, a1, t6
+; RV64I-NEXT: and a0, a0, a7
+; RV64I-NEXT: and a1, a1, a7
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
@@ -28369,428 +28398,428 @@ define i128 @clmul_i128_zext(i64 %x, i64 %y) {
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a1, a1, t1
-; RV64I-NEXT: andi a2, a6, 2
+; RV64I-NEXT: andi a2, t2, 2
; RV64I-NEXT: and a0, a0, t1
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: andi a4, a6, 1
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 1
+; RV64I-NEXT: andi a3, t2, 1
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 1
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: and a4, a4, s10
+; RV64I-NEXT: and a3, a3, s0
; RV64I-NEXT: or a1, a1, a0
-; RV64I-NEXT: xor a2, a4, a2
-; RV64I-NEXT: andi a0, a6, 4
-; RV64I-NEXT: andi a4, a6, 8
+; RV64I-NEXT: xor a2, a3, a2
+; RV64I-NEXT: andi a0, t2, 4
+; RV64I-NEXT: andi a3, t2, 8
; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s10, 2
-; RV64I-NEXT: slli a7, s10, 3
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a5, s0, 2
+; RV64I-NEXT: slli a6, s0, 3
; RV64I-NEXT: and a0, a0, a5
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: xor a0, a0, a4
-; RV64I-NEXT: andi a4, a6, 16
+; RV64I-NEXT: and a3, a3, a6
+; RV64I-NEXT: xor a0, a0, a3
+; RV64I-NEXT: andi a3, t2, 16
; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: andi a4, a6, 32
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 4
+; RV64I-NEXT: andi a3, t2, 32
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 4
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s10, 5
-; RV64I-NEXT: andi a7, a6, 64
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a5, s0, 5
+; RV64I-NEXT: andi a6, t2, 64
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: seqz a5, a6
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 6
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: andi a4, a6, 128
+; RV64I-NEXT: slli a6, s0, 6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: andi a3, t2, 128
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: andi a4, a6, 256
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 7
+; RV64I-NEXT: andi a3, t2, 256
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 7
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s10, 8
-; RV64I-NEXT: andi a7, a6, 512
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a5, s0, 8
+; RV64I-NEXT: andi a6, t2, 512
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 9
-; RV64I-NEXT: andi a7, a6, 1024
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
+; RV64I-NEXT: slli a3, s0, 9
+; RV64I-NEXT: andi a6, t2, 1024
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 10
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: ld a4, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
+; RV64I-NEXT: slli a6, s0, 10
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: ld a3, 152(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: lui a4, 1
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 11
+; RV64I-NEXT: lui a3, 1
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 11
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: lui a5, 2
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 12
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 12
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 13
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: lui a4, 4
-; RV64I-NEXT: and a4, a6, a4
+; RV64I-NEXT: slli a6, s0, 13
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: lui a3, 4
+; RV64I-NEXT: and a3, t2, a3
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: lui a4, 8
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 14
+; RV64I-NEXT: lui a3, 8
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 14
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: lui a5, 16
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 15
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 15
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 32
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 16
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: lui a3, 32
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 16
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: lui a5, 64
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 17
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 17
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 18
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: lui a4, 128
-; RV64I-NEXT: and a4, a6, a4
+; RV64I-NEXT: slli a6, s0, 18
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: lui a3, 128
+; RV64I-NEXT: and a3, t2, a3
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: lui a4, 256
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 19
+; RV64I-NEXT: lui a3, 256
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 19
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: lui a5, 512
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 20
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 20
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 1024
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 21
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: lui a3, 1024
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 21
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: lui a5, 2048
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 22
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 22
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 4096
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 23
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, s10, 24
+; RV64I-NEXT: lui a3, 4096
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 23
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a6, s0, 24
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: lui a4, 8192
-; RV64I-NEXT: and a4, a6, a4
+; RV64I-NEXT: and a3, a3, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: lui a3, 8192
+; RV64I-NEXT: and a3, t2, a3
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: lui a4, 16384
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 25
+; RV64I-NEXT: lui a3, 16384
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 25
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: lui a5, 32768
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 26
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 26
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 65536
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 27
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: lui a3, 65536
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 27
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: lui a5, 131072
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 28
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 28
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 262144
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 29
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: lui a3, 262144
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 29
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s10, 30
-; RV64I-NEXT: sraiw a7, a6, 31
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a5, s0, 30
+; RV64I-NEXT: sraiw a6, t2, 31
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: seqz a5, a6
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 31
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: ld a4, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
+; RV64I-NEXT: slli a6, s0, 31
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: ld a3, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: ld a4, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 32
+; RV64I-NEXT: ld a3, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 32
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: ld a5, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 33
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: ld a5, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 33
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: ld a4, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 34
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: ld a3, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 34
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: ld a5, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 35
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: ld a5, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 35
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: ld a4, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 36
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: ld a3, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 36
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: ld a5, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 37
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: ld a5, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 37
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 38
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: ld a4, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
+; RV64I-NEXT: slli a6, s0, 38
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: ld a3, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: ld a4, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: slli a5, s10, 39
+; RV64I-NEXT: ld a3, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: slli a5, s0, 39
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: ld a5, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a5, a6, a5
-; RV64I-NEXT: slli a7, s10, 40
-; RV64I-NEXT: and a4, a4, a7
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: ld a5, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a5, t2, a5
+; RV64I-NEXT: slli a6, s0, 40
+; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: ld a4, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a7, s10, 41
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: ld a3, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a6, s0, 41
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s10, 42
-; RV64I-NEXT: ld a7, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a6, a7
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a5, s0, 42
+; RV64I-NEXT: ld a6, 48(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, t2, a6
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 43
-; RV64I-NEXT: ld a7, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a6, a7
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: slli a3, s0, 43
+; RV64I-NEXT: ld a6, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, t2, a6
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 44
-; RV64I-NEXT: ld a7, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a6, a7
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: slli a3, s0, 44
+; RV64I-NEXT: ld a6, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, t2, a6
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 45
-; RV64I-NEXT: ld a7, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a6, a7
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
+; RV64I-NEXT: slli a3, s0, 45
+; RV64I-NEXT: ld a6, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, t2, a6
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 46
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: ld a4, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
+; RV64I-NEXT: slli a6, s0, 46
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a3, a5, a6
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: ld a3, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
; RV64I-NEXT: xor a0, a0, a2
-; RV64I-NEXT: seqz a2, a4
+; RV64I-NEXT: seqz a2, a3
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: ld a4, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a6, a4
-; RV64I-NEXT: slli a5, s10, 47
-; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: ld a3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a3, t2, a3
+; RV64I-NEXT: slli a5, s0, 47
+; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: and a2, a2, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a5, s10, 48
-; RV64I-NEXT: ld a7, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a6, a7
-; RV64I-NEXT: and a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 49
-; RV64I-NEXT: and a7, a6, ra
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a5, s0, 48
+; RV64I-NEXT: ld a6, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, t2, a6
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 50
-; RV64I-NEXT: and a7, a6, s11
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: slli a3, s0, 49
+; RV64I-NEXT: and a6, t2, ra
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 51
-; RV64I-NEXT: and a7, a6, s8
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: slli a3, s0, 50
+; RV64I-NEXT: and a6, t2, s11
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 52
-; RV64I-NEXT: and a7, a6, s7
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: slli a3, s0, 51
+; RV64I-NEXT: and a6, t2, s9
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 53
-; RV64I-NEXT: and a7, a6, s6
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
+; RV64I-NEXT: slli a3, s0, 52
+; RV64I-NEXT: and a6, t2, s8
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, s10, 54
-; RV64I-NEXT: and a7, a6, s5
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
+; RV64I-NEXT: slli a3, s0, 53
+; RV64I-NEXT: and a6, t2, s7
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 55
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: and a4, a5, a7
-; RV64I-NEXT: xor a4, a2, a4
-; RV64I-NEXT: and a2, a6, s4
+; RV64I-NEXT: slli a3, s0, 54
+; RV64I-NEXT: and a6, t2, s6
+; RV64I-NEXT: and a3, a5, a3
+; RV64I-NEXT: seqz a5, a6
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, s0, 55
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: xor a5, a2, a5
+; RV64I-NEXT: and a2, t2, s5
; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: and a5, a6, s3
+; RV64I-NEXT: and a3, t2, s4
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: ld a7, 160(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a2, a2, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, s10, 57
-; RV64I-NEXT: and t0, a6, t5
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a7, t0
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: slli a5, s10, 58
-; RV64I-NEXT: and t0, a6, t4
-; RV64I-NEXT: and a5, a7, a5
-; RV64I-NEXT: seqz a7, t0
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: slli a5, s10, 59
-; RV64I-NEXT: and t0, a6, t3
-; RV64I-NEXT: and a5, a7, a5
-; RV64I-NEXT: seqz a7, t0
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: slli a5, s10, 60
-; RV64I-NEXT: and t0, a6, t2
-; RV64I-NEXT: and a5, a7, a5
-; RV64I-NEXT: seqz a7, t0
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: slli a5, s10, 61
-; RV64I-NEXT: and a3, a6, a3
-; RV64I-NEXT: and a5, a7, a5
; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: ld a6, 160(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a2, a2, a6
; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: slli a5, s10, 62
-; RV64I-NEXT: srli a6, a6, 63
-; RV64I-NEXT: and a3, a3, a5
-; RV64I-NEXT: seqz a5, a6
-; RV64I-NEXT: slli s10, s10, 63
-; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: slli a6, s0, 57
+; RV64I-NEXT: and a7, t2, t6
+; RV64I-NEXT: and a3, a3, a6
+; RV64I-NEXT: seqz a6, a7
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli a3, s0, 58
+; RV64I-NEXT: and a7, t2, t5
+; RV64I-NEXT: and a3, a6, a3
+; RV64I-NEXT: seqz a6, a7
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli a3, s0, 59
+; RV64I-NEXT: and a7, t2, t4
+; RV64I-NEXT: and a3, a6, a3
+; RV64I-NEXT: seqz a6, a7
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli a3, s0, 60
+; RV64I-NEXT: and a7, t2, t3
+; RV64I-NEXT: and a3, a6, a3
+; RV64I-NEXT: seqz a6, a7
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli a3, s0, 61
+; RV64I-NEXT: and a4, t2, a4
+; RV64I-NEXT: and a3, a6, a3
+; RV64I-NEXT: seqz a4, a4
; RV64I-NEXT: xor a2, a2, a3
-; RV64I-NEXT: and a3, a5, s10
-; RV64I-NEXT: xor a0, a0, a4
+; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: slli a3, s0, 62
+; RV64I-NEXT: srli a6, t2, 63
+; RV64I-NEXT: and a3, a4, a3
+; RV64I-NEXT: seqz a4, a6
+; RV64I-NEXT: slli s0, s0, 63
+; RV64I-NEXT: addi a4, a4, -1
; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: and a4, a4, s0
+; RV64I-NEXT: xor a0, a0, a5
+; RV64I-NEXT: xor a2, a2, a4
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: srli a1, a1, 1
; RV64I-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
@@ -33058,12 +33087,12 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: lw t3, 4(a0)
; RV32I-NEXT: lw a4, 8(a0)
; RV32I-NEXT: lw a7, 12(a0)
-; RV32I-NEXT: addi s9, a2, -256
+; RV32I-NEXT: addi s10, a2, -256
; RV32I-NEXT: lui t1, 16
; RV32I-NEXT: srli a0, a5, 8
; RV32I-NEXT: srli a2, a5, 24
-; RV32I-NEXT: and a3, a5, s9
-; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a3, a5, s10
+; RV32I-NEXT: and a0, a0, s10
; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: slli a2, a5, 24
@@ -33071,10 +33100,10 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: addi s8, a3, -241
+; RV32I-NEXT: addi s9, a3, -241
; RV32I-NEXT: srli a3, a0, 4
-; RV32I-NEXT: and a0, a0, s8
-; RV32I-NEXT: and a3, a3, s8
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: lui a3, 209715
@@ -33086,261 +33115,261 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: lw t2, 0(a1)
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw t0, 8(a1)
-; RV32I-NEXT: lw s7, 12(a1)
-; RV32I-NEXT: or t5, a6, t4
-; RV32I-NEXT: srli t6, t5, 1
+; RV32I-NEXT: lw s8, 12(a1)
+; RV32I-NEXT: or t6, a6, t4
+; RV32I-NEXT: srli t5, t6, 1
; RV32I-NEXT: lui t4, 349525
-; RV32I-NEXT: addi s10, t4, 1365
+; RV32I-NEXT: addi s11, t4, 1365
; RV32I-NEXT: srli s0, t2, 8
-; RV32I-NEXT: and t6, t6, s10
+; RV32I-NEXT: and s1, t5, s11
+; RV32I-NEXT: and s0, s0, s10
+; RV32I-NEXT: srli s2, t2, 24
+; RV32I-NEXT: and s3, t2, s10
+; RV32I-NEXT: slli s3, s3, 8
+; RV32I-NEXT: slli s4, t2, 24
+; RV32I-NEXT: or s0, s0, s2
+; RV32I-NEXT: or s2, s4, s3
+; RV32I-NEXT: and t6, t6, s11
+; RV32I-NEXT: or s0, s2, s0
+; RV32I-NEXT: srli s2, s0, 4
; RV32I-NEXT: and s0, s0, s9
-; RV32I-NEXT: srli s1, t2, 24
-; RV32I-NEXT: and s2, t2, s9
-; RV32I-NEXT: slli s2, s2, 8
-; RV32I-NEXT: slli s3, t2, 24
-; RV32I-NEXT: or s0, s0, s1
-; RV32I-NEXT: or s1, s3, s2
-; RV32I-NEXT: and t5, t5, s10
-; RV32I-NEXT: or s0, s1, s0
-; RV32I-NEXT: srli s1, s0, 4
-; RV32I-NEXT: and s0, s0, s8
-; RV32I-NEXT: and s1, s1, s8
+; RV32I-NEXT: and s2, s2, s9
; RV32I-NEXT: slli s0, s0, 4
-; RV32I-NEXT: slli t5, t5, 1
-; RV32I-NEXT: or s0, s1, s0
-; RV32I-NEXT: srli s1, s0, 2
+; RV32I-NEXT: slli t6, t6, 1
+; RV32I-NEXT: or s0, s2, s0
+; RV32I-NEXT: srli s2, s0, 2
; RV32I-NEXT: and s0, s0, a3
-; RV32I-NEXT: and s1, s1, a3
+; RV32I-NEXT: and s2, s2, a3
; RV32I-NEXT: slli s0, s0, 2
-; RV32I-NEXT: or t5, t6, t5
-; RV32I-NEXT: or s0, s1, s0
-; RV32I-NEXT: srli t6, s0, 1
-; RV32I-NEXT: and s0, s0, s10
-; RV32I-NEXT: and s1, t6, s10
-; RV32I-NEXT: slli t6, s0, 1
-; RV32I-NEXT: slli s2, t5, 1
-; RV32I-NEXT: or s0, s1, t6
-; RV32I-NEXT: andi s1, s0, 2
-; RV32I-NEXT: andi s3, s0, 1
-; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: or t6, s1, t6
+; RV32I-NEXT: or s0, s2, s0
+; RV32I-NEXT: srli s1, s0, 1
+; RV32I-NEXT: and s0, s0, s11
+; RV32I-NEXT: and s1, s1, s11
+; RV32I-NEXT: slli s0, s0, 1
+; RV32I-NEXT: slli s2, t6, 1
+; RV32I-NEXT: or s1, s1, s0
+; RV32I-NEXT: andi s3, s1, 2
+; RV32I-NEXT: andi s4, s1, 1
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, s3, t5
-; RV32I-NEXT: xor s1, s2, s1
-; RV32I-NEXT: andi s2, s0, 4
-; RV32I-NEXT: slli s3, t5, 2
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: andi s4, s0, 8
-; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 3
+; RV32I-NEXT: seqz s4, s4
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 16
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 4
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and s2, s3, s2
+; RV32I-NEXT: and s3, s4, t6
+; RV32I-NEXT: xor s2, s3, s2
+; RV32I-NEXT: andi s3, s1, 4
+; RV32I-NEXT: slli s4, t6, 2
+; RV32I-NEXT: seqz s3, s3
; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: andi s5, s1, 8
; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 32
-; RV32I-NEXT: slli s5, t5, 5
-; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: andi s6, s0, 64
; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: slli s6, t5, 6
-; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: andi s5, s1, 16
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: xor s2, s3, s4
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: andi s2, s0, 128
-; RV32I-NEXT: slli s3, t5, 7
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: andi s4, s0, 256
-; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 8
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 512
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 4
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: andi s5, s1, 32
+; RV32I-NEXT: slli s6, t6, 5
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: andi s7, s1, 64
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: slli s7, t6, 6
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 9
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 1024
+; RV32I-NEXT: xor s3, s4, s5
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 10
+; RV32I-NEXT: andi s3, s1, 128
+; RV32I-NEXT: slli s4, t6, 7
+; RV32I-NEXT: seqz s3, s3
; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: andi s5, s1, 256
; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: li s4, 1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: slli a6, s4, 11
-; RV32I-NEXT: slli s3, t5, 11
-; RV32I-NEXT: and s4, s0, a6
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: lui a1, 1
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: and s5, s0, a1
-; RV32I-NEXT: and s3, s4, s3
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: slli s5, t5, 12
+; RV32I-NEXT: slli s5, t6, 8
; RV32I-NEXT: addi s4, s4, -1
; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: andi s5, s1, 512
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s0, a1
-; RV32I-NEXT: slli s5, t5, 13
-; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 9
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lui a1, 4
; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: and s5, s0, a1
+; RV32I-NEXT: andi s5, s1, 1024
; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 10
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lui a1, 8
-; RV32I-NEXT: slli s5, t5, 14
-; RV32I-NEXT: and s6, s0, a1
; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: li s5, 1
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: slli a6, s5, 11
+; RV32I-NEXT: slli s4, t6, 11
+; RV32I-NEXT: and s5, s1, a6
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: lui a1, 1
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: and s6, s1, a1
+; RV32I-NEXT: and s4, s5, s4
; RV32I-NEXT: seqz s5, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t5, 15
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: xor s2, s3, s4
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: and s2, s0, t1
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: lui a1, 32
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, a1
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: slli s6, t6, 12
+; RV32I-NEXT: and s7, s1, a1
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, t6, 13
+; RV32I-NEXT: lui a1, 4
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and s6, s1, a1
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui a1, 8
+; RV32I-NEXT: slli s6, t6, 14
+; RV32I-NEXT: and s7, s1, a1
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, t6, 15
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: xor s3, s4, s5
+; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: and s3, s1, t1
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: slli s4, t5, 16
-; RV32I-NEXT: and s2, s2, s4
+; RV32I-NEXT: lui a1, 32
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t5, 17
+; RV32I-NEXT: and s4, s1, a1
+; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: slli s5, t6, 16
+; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: slli s5, t6, 17
; RV32I-NEXT: lui a1, 64
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: and s4, s0, a1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a1, 128
-; RV32I-NEXT: slli s4, t5, 18
-; RV32I-NEXT: and s5, s0, a1
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: and s5, s1, a1
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t5, 19
+; RV32I-NEXT: lui a1, 128
+; RV32I-NEXT: slli s5, t6, 18
+; RV32I-NEXT: and s6, s1, a1
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 19
; RV32I-NEXT: lui a1, 256
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a1, 512
-; RV32I-NEXT: slli s4, t5, 20
-; RV32I-NEXT: and s5, s0, a1
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s5, s1, a1
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t5, 21
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: and s3, s4, s5
-; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: lui a1, 512
+; RV32I-NEXT: slli s5, t6, 20
+; RV32I-NEXT: and s6, s1, a1
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s6, t6, 21
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: and s4, s5, s6
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: lui a1, 1024
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: and s2, s0, a1
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: lui a1, 2048
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, a1
+; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: and s3, s1, a1
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: slli s4, t5, 22
-; RV32I-NEXT: and s2, s2, s4
+; RV32I-NEXT: lui a1, 2048
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t5, 23
+; RV32I-NEXT: and s4, s1, a1
+; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: slli s5, t6, 22
+; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: slli s5, t6, 23
; RV32I-NEXT: lui a1, 4096
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: and s4, s0, a1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a1, 8192
-; RV32I-NEXT: slli s4, t5, 24
-; RV32I-NEXT: and s5, s0, a1
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: and s5, s1, a1
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t5, 25
+; RV32I-NEXT: lui a1, 8192
+; RV32I-NEXT: slli s5, t6, 24
+; RV32I-NEXT: and s6, s1, a1
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 25
; RV32I-NEXT: lui a1, 16384
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a1, 32768
-; RV32I-NEXT: slli s4, t5, 26
-; RV32I-NEXT: and s5, s0, a1
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s5, s1, a1
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t5, 27
+; RV32I-NEXT: lui a1, 32768
+; RV32I-NEXT: slli s5, t6, 26
+; RV32I-NEXT: and s6, s1, a1
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 27
; RV32I-NEXT: lui a1, 65536
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t5, 28
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s5, s1, a1
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
; RV32I-NEXT: lui a1, 131072
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: and s3, s0, a1
-; RV32I-NEXT: seqz s3, s3
+; RV32I-NEXT: slli s5, t6, 28
+; RV32I-NEXT: and s6, s1, a1
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 29
; RV32I-NEXT: lui a1, 262144
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s0, s0, a1
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s1, s1, a1
+; RV32I-NEXT: slli t6, t6, 30
+; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: srli s0, s0, 31
+; RV32I-NEXT: and t6, s1, t6
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli s4, t5, 29
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: srli t6, t6, 31
-; RV32I-NEXT: slli s4, t5, 30
-; RV32I-NEXT: and s0, s0, s4
-; RV32I-NEXT: seqz t6, t6
; RV32I-NEXT: slli t5, t5, 31
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: xor s0, s3, s0
-; RV32I-NEXT: and t5, t6, t5
-; RV32I-NEXT: xor t6, s1, s2
-; RV32I-NEXT: xor t5, s0, t5
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: xor t6, s4, t6
+; RV32I-NEXT: and t5, s0, t5
+; RV32I-NEXT: xor s0, s2, s3
; RV32I-NEXT: xor t5, t6, t5
+; RV32I-NEXT: xor t5, s0, t5
; RV32I-NEXT: srli t6, t5, 8
-; RV32I-NEXT: and t6, t6, s9
+; RV32I-NEXT: and t6, t6, s10
; RV32I-NEXT: srli s0, t5, 24
-; RV32I-NEXT: and s1, t5, s9
+; RV32I-NEXT: and s1, t5, s10
; RV32I-NEXT: slli t5, t5, 24
; RV32I-NEXT: slli s1, s1, 8
; RV32I-NEXT: or t6, t6, s0
; RV32I-NEXT: or t5, t5, s1
; RV32I-NEXT: or t5, t5, t6
; RV32I-NEXT: srli t6, t5, 4
-; RV32I-NEXT: and t5, t5, s8
-; RV32I-NEXT: and t6, t6, s8
+; RV32I-NEXT: and t5, t5, s9
+; RV32I-NEXT: and t6, t6, s9
; RV32I-NEXT: slli t5, t5, 4
; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: srli t6, t5, 2
@@ -33352,7 +33381,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: sw a0, 212(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli t4, t5, 1
; RV32I-NEXT: and t4, t4, a0
-; RV32I-NEXT: and t5, t5, s10
+; RV32I-NEXT: and t5, t5, s11
; RV32I-NEXT: slli t5, t5, 1
; RV32I-NEXT: andi t6, t2, 2
; RV32I-NEXT: seqz t6, t6
@@ -33435,8 +33464,8 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: seqz t5, t6
; RV32I-NEXT: addi a1, t5, -1
; RV32I-NEXT: sw a1, 396(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s11, 1
-; RV32I-NEXT: and t5, t2, s11
+; RV32I-NEXT: lui ra, 1
+; RV32I-NEXT: and t5, t2, ra
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: slli t6, t3, 11
; RV32I-NEXT: and t6, a1, t6
@@ -33491,8 +33520,8 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: addi a1, s1, -1
; RV32I-NEXT: sw a1, 368(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 18
-; RV32I-NEXT: lui ra, 128
-; RV32I-NEXT: and s1, t2, ra
+; RV32I-NEXT: lui s7, 128
+; RV32I-NEXT: and s1, t2, s7
; RV32I-NEXT: and t6, a1, t6
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t5, t5, t6
@@ -33674,7 +33703,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor t2, t2, t3
; RV32I-NEXT: seqz t3, t4
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t4, a2, s11
+; RV32I-NEXT: and t4, a2, ra
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: slli a0, a5, 11
; RV32I-NEXT: sw a0, 272(sp) # 4-byte Folded Spill
@@ -33725,7 +33754,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: addi t5, t5, -1
; RV32I-NEXT: slli a0, a5, 18
; RV32I-NEXT: sw a0, 244(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t4, a2, ra
+; RV32I-NEXT: and t4, a2, s7
; RV32I-NEXT: and t5, t5, a0
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: xor t3, t3, t5
@@ -33789,15 +33818,15 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor t5, t4, t5
; RV32I-NEXT: srli t3, a4, 8
; RV32I-NEXT: srli t4, t0, 8
-; RV32I-NEXT: and t3, t3, s9
-; RV32I-NEXT: and t4, t4, s9
+; RV32I-NEXT: and t3, t3, s10
+; RV32I-NEXT: and t4, t4, s10
; RV32I-NEXT: srli t6, a4, 24
; RV32I-NEXT: srli s2, t0, 24
; RV32I-NEXT: or t3, t3, t6
; RV32I-NEXT: or t4, t4, s2
-; RV32I-NEXT: and t6, a4, s9
-; RV32I-NEXT: and s2, t0, s9
-; RV32I-NEXT: mv a0, s9
+; RV32I-NEXT: and t6, a4, s10
+; RV32I-NEXT: and s2, t0, s10
+; RV32I-NEXT: mv a0, s10
; RV32I-NEXT: slli t6, t6, 8
; RV32I-NEXT: slli s2, s2, 8
; RV32I-NEXT: slli a1, a4, 24
@@ -33808,12 +33837,12 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: or t3, t6, t3
; RV32I-NEXT: or t4, s2, t4
; RV32I-NEXT: srli t6, t3, 4
-; RV32I-NEXT: and t3, t3, s8
-; RV32I-NEXT: and t6, t6, s8
+; RV32I-NEXT: and t3, t3, s9
+; RV32I-NEXT: and t6, t6, s9
; RV32I-NEXT: slli t3, t3, 4
; RV32I-NEXT: srli s2, t4, 4
-; RV32I-NEXT: and t4, t4, s8
-; RV32I-NEXT: and s2, s2, s8
+; RV32I-NEXT: and t4, t4, s9
+; RV32I-NEXT: and s2, s2, s9
; RV32I-NEXT: slli t4, t4, 4
; RV32I-NEXT: or t3, t6, t3
; RV32I-NEXT: or t4, s2, t4
@@ -33821,236 +33850,237 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: and t3, t3, a3
; RV32I-NEXT: and t6, t6, a3
; RV32I-NEXT: slli t3, t3, 2
-; RV32I-NEXT: or t6, t6, t3
-; RV32I-NEXT: srli t3, t4, 2
-; RV32I-NEXT: and t3, t3, a3
+; RV32I-NEXT: srli s2, t4, 2
; RV32I-NEXT: and t4, t4, a3
+; RV32I-NEXT: and s2, s2, a3
; RV32I-NEXT: slli t4, t4, 2
-; RV32I-NEXT: srli s2, t6, 1
-; RV32I-NEXT: or t3, t3, t4
-; RV32I-NEXT: and t4, s2, s10
-; RV32I-NEXT: srli s2, t3, 1
-; RV32I-NEXT: and t3, t3, s10
-; RV32I-NEXT: and s2, s2, s10
-; RV32I-NEXT: slli t3, t3, 1
-; RV32I-NEXT: and s3, t6, s10
-; RV32I-NEXT: or t6, s2, t3
-; RV32I-NEXT: slli s3, s3, 1
-; RV32I-NEXT: andi s2, t6, 2
-; RV32I-NEXT: or t4, t4, s3
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: slli s3, t4, 1
-; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: lui a1, 32768
-; RV32I-NEXT: and s3, a2, a1
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: andi s4, t6, 1
+; RV32I-NEXT: or t6, t6, t3
+; RV32I-NEXT: or t4, s2, t4
+; RV32I-NEXT: srli t3, t6, 1
+; RV32I-NEXT: and t6, t6, s11
+; RV32I-NEXT: srli s2, t4, 1
+; RV32I-NEXT: and t4, t4, s11
+; RV32I-NEXT: and s2, s2, s11
+; RV32I-NEXT: slli t4, t4, 1
+; RV32I-NEXT: slli s3, t6, 1
+; RV32I-NEXT: or t6, s2, t4
+; RV32I-NEXT: and s2, t3, s11
+; RV32I-NEXT: andi s4, t6, 2
+; RV32I-NEXT: or s2, s2, s3
+; RV32I-NEXT: seqz s3, s4
; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: slli s4, s2, 1
+; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: lui a1, 32768
+; RV32I-NEXT: and s4, a2, a1
; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: andi s5, t6, 1
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, a5, 27
-; RV32I-NEXT: sw s5, 208(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s3, s3, s5
-; RV32I-NEXT: and s4, s4, t4
-; RV32I-NEXT: xor t5, t5, s3
-; RV32I-NEXT: xor s2, s4, s2
-; RV32I-NEXT: andi s3, t6, 4
-; RV32I-NEXT: andi s4, t6, 8
-; RV32I-NEXT: seqz s3, s3
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s6, a5, 27
+; RV32I-NEXT: sw s6, 208(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: and s5, s5, s2
+; RV32I-NEXT: xor t5, t5, s4
+; RV32I-NEXT: xor s3, s5, s3
+; RV32I-NEXT: andi s4, t6, 4
+; RV32I-NEXT: andi s5, t6, 8
; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 2
-; RV32I-NEXT: slli s6, t4, 3
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s6, s2, 2
+; RV32I-NEXT: slli s7, s2, 3
; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: and s5, s5, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: andi s5, t6, 16
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: andi s4, t6, 16
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: andi s4, t6, 32
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 4
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 5
-; RV32I-NEXT: andi s6, t6, 64
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: andi s5, t6, 32
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 4
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
+; RV32I-NEXT: slli s6, s2, 5
+; RV32I-NEXT: andi s7, t6, 64
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 6
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: andi s5, t6, 128
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: andi s4, t6, 128
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: andi s4, t6, 256
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 7
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 8
-; RV32I-NEXT: andi s6, t6, 512
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 9
-; RV32I-NEXT: andi s6, t6, 1024
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: andi s5, t6, 256
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 7
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 10
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
+; RV32I-NEXT: slli s6, s2, 8
+; RV32I-NEXT: andi s7, t6, 512
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 9
+; RV32I-NEXT: andi s7, t6, 1024
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 10
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: mv s10, a6
+; RV32I-NEXT: and s5, t6, a6
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: mv s9, a6
-; RV32I-NEXT: and s4, t6, a6
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s4, t6, s11
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 11
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 12
-; RV32I-NEXT: lui a6, 2
-; RV32I-NEXT: and s6, t6, a6
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: and s5, t6, ra
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 11
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 13
+; RV32I-NEXT: slli s6, s2, 12
+; RV32I-NEXT: lui a6, 2
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 13
; RV32I-NEXT: lui a6, 4
-; RV32I-NEXT: and s6, t6, a6
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 14
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 14
; RV32I-NEXT: lui a6, 8
-; RV32I-NEXT: and s6, t6, a6
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 15
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 15
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
; RV32I-NEXT: lui a6, 16
-; RV32I-NEXT: and s4, t6, a6
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a6, 32
-; RV32I-NEXT: and s4, t6, a6
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 16
-; RV32I-NEXT: and s3, s3, s5
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 17
-; RV32I-NEXT: lui a6, 64
-; RV32I-NEXT: and s6, t6, a6
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 18
-; RV32I-NEXT: and s6, t6, ra
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: and s5, t6, a6
; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: lui a6, 32
+; RV32I-NEXT: and s5, t6, a6
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 16
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 19
+; RV32I-NEXT: slli s6, s2, 17
+; RV32I-NEXT: lui a6, 64
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 18
+; RV32I-NEXT: lui a6, 128
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 19
; RV32I-NEXT: lui a6, 256
-; RV32I-NEXT: and s6, t6, a6
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 20
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 20
; RV32I-NEXT: lui a6, 512
-; RV32I-NEXT: and s6, t6, a6
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 21
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 21
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
; RV32I-NEXT: lui a6, 1024
-; RV32I-NEXT: and s4, t6, a6
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a6, 2048
-; RV32I-NEXT: and s4, t6, a6
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 22
-; RV32I-NEXT: and s3, s3, s5
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 23
-; RV32I-NEXT: lui a6, 4096
-; RV32I-NEXT: and s6, t6, a6
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 24
-; RV32I-NEXT: and s6, t6, s0
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 25
-; RV32I-NEXT: and s6, t6, t1
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 26
-; RV32I-NEXT: and s6, t6, a1
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: and s5, t6, a6
; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: lui a6, 2048
+; RV32I-NEXT: and s5, t6, a6
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 22
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 27
+; RV32I-NEXT: slli s6, s2, 23
+; RV32I-NEXT: lui a6, 4096
+; RV32I-NEXT: and s7, t6, a6
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 24
+; RV32I-NEXT: and s7, t6, s0
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 25
+; RV32I-NEXT: and s7, t6, t1
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 26
+; RV32I-NEXT: and s7, t6, a1
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 27
; RV32I-NEXT: lui a1, 65536
-; RV32I-NEXT: and s6, t6, a1
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 28
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: and s7, t6, a1
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 28
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
; RV32I-NEXT: lui s0, 131072
-; RV32I-NEXT: and s4, t6, s0
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: and s5, t6, s0
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: slli s5, s2, 29
+; RV32I-NEXT: and s4, s4, s5
; RV32I-NEXT: lui s5, 262144
; RV32I-NEXT: and t6, t6, s5
+; RV32I-NEXT: slli s2, s2, 30
; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: slli s4, t4, 29
-; RV32I-NEXT: and s3, s3, s4
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: srli t3, t3, 31
-; RV32I-NEXT: slli s4, t4, 30
-; RV32I-NEXT: and t6, t6, s4
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: slli t4, t4, 31
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: xor t6, s3, t6
-; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: srli t4, t4, 31
+; RV32I-NEXT: and t6, t6, s2
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: slli t3, t3, 31
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: xor t6, s4, t6
+; RV32I-NEXT: and t3, t4, t3
; RV32I-NEXT: xor t3, t6, t3
; RV32I-NEXT: and t4, a2, a1
-; RV32I-NEXT: xor t3, s2, t3
+; RV32I-NEXT: xor t3, s3, t3
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: slli a1, a5, 28
@@ -34068,9 +34098,8 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor t2, t2, t4
; RV32I-NEXT: or t1, t1, t5
; RV32I-NEXT: and t3, a2, s0
-; RV32I-NEXT: lui s11, 131072
+; RV32I-NEXT: lui ra, 131072
; RV32I-NEXT: and t4, a2, s5
-; RV32I-NEXT: lui ra, 262144
; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t3, t3, -1
@@ -34084,8 +34113,8 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor t3, t3, t4
; RV32I-NEXT: srli t4, t1, 4
; RV32I-NEXT: srli a0, a2, 31
-; RV32I-NEXT: and t4, t4, s8
-; RV32I-NEXT: and a2, t1, s8
+; RV32I-NEXT: and t4, t4, s9
+; RV32I-NEXT: and a2, t1, s9
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli t1, a5, 31
@@ -34117,7 +34146,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: slli a0, a7, 1
; RV32I-NEXT: and a0, t1, a0
; RV32I-NEXT: and a3, a3, a7
-; RV32I-NEXT: and a1, a2, s10
+; RV32I-NEXT: and a1, a2, s11
; RV32I-NEXT: sw a1, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a0, a3, a0
; RV32I-NEXT: andi a2, t0, 4
@@ -34182,13 +34211,13 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: and a3, a1, a6
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, t0, s9
+; RV32I-NEXT: and a3, t0, s10
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a1, a2, -1
; RV32I-NEXT: sw a1, 136(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s8, 1
-; RV32I-NEXT: and a2, t0, s8
+; RV32I-NEXT: lui s7, 1
+; RV32I-NEXT: and a2, t0, s7
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: slli a3, a7, 11
; RV32I-NEXT: and a3, a1, a3
@@ -34296,50 +34325,51 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: and a3, a1, a3
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: addi s10, a6, -1
-; RV32I-NEXT: sw s10, 76(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, a6, -1
+; RV32I-NEXT: sw s9, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, a7, 25
; RV32I-NEXT: lui a1, 16384
; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: and a3, s10, a3
+; RV32I-NEXT: and a3, s9, a3
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: addi s10, a6, -1
-; RV32I-NEXT: sw s10, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, a6, -1
+; RV32I-NEXT: sw s9, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, a7, 26
; RV32I-NEXT: lui a1, 32768
; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: and a3, s10, a3
+; RV32I-NEXT: and a3, s9, a3
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: addi s10, a6, -1
-; RV32I-NEXT: sw s10, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, a6, -1
+; RV32I-NEXT: sw s9, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a3, a7, 27
-; RV32I-NEXT: lui a1, 65536
-; RV32I-NEXT: and a6, t0, a1
-; RV32I-NEXT: and a3, s10, a3
+; RV32I-NEXT: lui a6, 65536
+; RV32I-NEXT: and a6, t0, a6
+; RV32I-NEXT: and a3, s9, a3
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a1, a6, -1
-; RV32I-NEXT: sw a1, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, a6, -1
+; RV32I-NEXT: sw s9, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a6, a7, 28
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, a1, a6
+; RV32I-NEXT: and a3, s9, a6
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, t0, s11
-; RV32I-NEXT: lui a1, 131072
+; RV32I-NEXT: and a3, t0, ra
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a6, a2, -1
; RV32I-NEXT: sw a6, 60(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, t0, ra
+; RV32I-NEXT: lui a2, 262144
+; RV32I-NEXT: and a2, t0, a2
+; RV32I-NEXT: lui ra, 262144
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: slli a3, a7, 29
; RV32I-NEXT: and a3, a6, a3
-; RV32I-NEXT: addi s10, a2, -1
-; RV32I-NEXT: sw s10, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, a2, -1
+; RV32I-NEXT: sw s9, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a2, t0, 31
; RV32I-NEXT: slli a6, a7, 30
-; RV32I-NEXT: and a6, s10, a6
+; RV32I-NEXT: and a6, s9, a6
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: slli a7, a7, 31
; RV32I-NEXT: addi t0, a2, -1
@@ -34347,9 +34377,9 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor a2, a3, a6
; RV32I-NEXT: and a3, t0, a7
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: andi a3, s7, 2
+; RV32I-NEXT: andi a3, s8, 2
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: andi a6, s7, 1
+; RV32I-NEXT: andi a6, s8, 1
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
@@ -34359,8 +34389,8 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: and a6, a6, a4
; RV32I-NEXT: xor t0, a0, a2
; RV32I-NEXT: xor a0, a6, a3
-; RV32I-NEXT: andi a2, s7, 4
-; RV32I-NEXT: andi a3, s7, 8
+; RV32I-NEXT: andi a2, s8, 4
+; RV32I-NEXT: andi a3, s8, 8
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a2, a2, -1
@@ -34372,11 +34402,11 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: andi a3, s7, 16
+; RV32I-NEXT: andi a3, s8, 16
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: andi a3, s7, 32
+; RV32I-NEXT: andi a3, s8, 32
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli a6, a4, 4
; RV32I-NEXT: sw a6, 36(sp) # 4-byte Folded Spill
@@ -34384,7 +34414,7 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli a7, a4, 5
; RV32I-NEXT: sw a7, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a6, s7, 64
+; RV32I-NEXT: andi a6, s8, 64
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
@@ -34393,11 +34423,11 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: and a3, a6, a7
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: andi a3, s7, 128
+; RV32I-NEXT: andi a3, s8, 128
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: andi a3, s7, 256
+; RV32I-NEXT: andi a3, s8, 256
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli a6, a4, 7
; RV32I-NEXT: sw a6, 24(sp) # 4-byte Folded Spill
@@ -34405,14 +34435,14 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli a7, a4, 8
; RV32I-NEXT: sw a7, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a6, s7, 512
+; RV32I-NEXT: andi a6, s8, 512
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a6, a6, -1
; RV32I-NEXT: slli a7, a4, 9
; RV32I-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a3, s7, 1024
+; RV32I-NEXT: andi a3, s8, 1024
; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a3, a3, -1
@@ -34421,66 +34451,66 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, s7, s9
+; RV32I-NEXT: and a3, s8, s10
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, s7, s8
+; RV32I-NEXT: and a3, s8, s7
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli a6, a4, 11
; RV32I-NEXT: sw a6, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a6, s7, s6
+; RV32I-NEXT: and a6, s8, s6
; RV32I-NEXT: slli a7, a4, 12
; RV32I-NEXT: sw a7, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a3, s7, s5
+; RV32I-NEXT: and a3, s8, s5
; RV32I-NEXT: slli s11, a4, 13
; RV32I-NEXT: and a6, a6, s11
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a6, s7, s4
+; RV32I-NEXT: and a6, s8, s4
; RV32I-NEXT: slli s10, a4, 14
; RV32I-NEXT: and a3, a3, s10
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli s9, a4, 15
+; RV32I-NEXT: slli s7, a4, 15
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, a6, s9
+; RV32I-NEXT: and a3, a6, s7
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, s7, s1
+; RV32I-NEXT: and a3, s8, s1
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, s7, s2
+; RV32I-NEXT: and a3, s8, s2
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli s8, a4, 16
-; RV32I-NEXT: and a2, a2, s8
+; RV32I-NEXT: slli s9, a4, 16
+; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a6, s7, s3
+; RV32I-NEXT: and a6, s8, s3
; RV32I-NEXT: slli s5, a4, 17
; RV32I-NEXT: and a3, a3, s5
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a3, s7, s0
+; RV32I-NEXT: and a3, s8, s0
; RV32I-NEXT: slli s4, a4, 18
; RV32I-NEXT: and a6, a6, s4
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a6, s7, t6
+; RV32I-NEXT: and a6, s8, t6
; RV32I-NEXT: slli s3, a4, 19
; RV32I-NEXT: and a3, a3, s3
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a3, s7, t5
+; RV32I-NEXT: and a3, s8, t5
; RV32I-NEXT: slli s2, a4, 20
; RV32I-NEXT: and a6, a6, s2
; RV32I-NEXT: seqz a3, a3
@@ -34489,16 +34519,16 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: and a3, a3, s1
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, s7, t1
+; RV32I-NEXT: and a3, s8, t1
; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: seqz a0, a3
; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: and a3, s7, t2
+; RV32I-NEXT: and a3, s8, t2
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli s6, a4, 22
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a6, s7, t3
+; RV32I-NEXT: and a6, s8, t3
; RV32I-NEXT: slli t6, a4, 23
; RV32I-NEXT: and a3, a3, t6
; RV32I-NEXT: seqz a6, a6
@@ -34506,50 +34536,50 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: addi a6, a6, -1
; RV32I-NEXT: lw s0, 204(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a6, s0
-; RV32I-NEXT: and a6, s7, t4
+; RV32I-NEXT: and a6, s8, t4
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: seqz a3, a6
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli t5, a4, 25
; RV32I-NEXT: and a3, a3, t5
; RV32I-NEXT: lui a6, 16384
-; RV32I-NEXT: and a6, s7, a6
+; RV32I-NEXT: and a6, s8, a6
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: seqz a3, a6
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli t4, a4, 26
; RV32I-NEXT: and a3, a3, t4
-; RV32I-NEXT: lui a6, 32768
-; RV32I-NEXT: and a6, s7, a6
+; RV32I-NEXT: and a6, s8, a1
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: seqz a3, a6
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli t3, a4, 27
; RV32I-NEXT: and a3, a3, t3
-; RV32I-NEXT: lui a6, 65536
-; RV32I-NEXT: and a6, s7, a6
+; RV32I-NEXT: lui a1, 65536
+; RV32I-NEXT: and a6, s8, a1
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: seqz a3, a6
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli t2, a4, 28
; RV32I-NEXT: and a3, a3, t2
-; RV32I-NEXT: and a6, s7, a1
+; RV32I-NEXT: lui a1, 131072
+; RV32I-NEXT: and a6, s8, a1
; RV32I-NEXT: xor a1, a0, a3
; RV32I-NEXT: seqz a3, a6
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a6, s7, ra
+; RV32I-NEXT: and a6, s8, ra
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: slli t1, a4, 29
; RV32I-NEXT: and a0, a3, t1
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: srli s7, s7, 31
+; RV32I-NEXT: srli s8, s8, 31
; RV32I-NEXT: slli a7, a4, 30
; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz s7, s7
-; RV32I-NEXT: addi s7, s7, -1
+; RV32I-NEXT: seqz s8, s8
+; RV32I-NEXT: addi s8, s8, -1
; RV32I-NEXT: slli a3, a4, 31
; RV32I-NEXT: xor a0, a0, a6
-; RV32I-NEXT: and a6, s7, a3
+; RV32I-NEXT: and a6, s8, a3
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: xor a0, a0, a6
; RV32I-NEXT: xor a0, a1, a0
@@ -34573,182 +34603,182 @@ define void @commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %p
; RV32I-NEXT: lw a5, 308(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a2, a5
; RV32I-NEXT: lw a2, 428(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 304(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
+; RV32I-NEXT: lw s8, 304(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: xor a1, a5, s7
+; RV32I-NEXT: xor a1, a5, s8
; RV32I-NEXT: lw a2, 424(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a5, 300(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a2, a5
; RV32I-NEXT: lw a2, 420(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 296(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 296(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 416(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 292(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
+; RV32I-NEXT: lw s8, 292(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a5, s7
+; RV32I-NEXT: xor a1, a5, s8
; RV32I-NEXT: lw a2, 412(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a5, 288(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a2, a5
; RV32I-NEXT: lw a2, 408(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 284(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 284(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 404(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 280(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 280(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 400(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 276(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
+; RV32I-NEXT: lw s8, 276(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a5, s7
+; RV32I-NEXT: xor a1, a5, s8
; RV32I-NEXT: lw a2, 396(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a5, 272(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a2, a5
; RV32I-NEXT: lw a2, 392(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 268(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 268(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 388(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 264(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 264(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 384(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 260(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 260(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 380(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 256(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
+; RV32I-NEXT: lw s8, 256(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a5, s7
+; RV32I-NEXT: xor a1, a5, s8
; RV32I-NEXT: lw a2, 376(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a5, 252(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a2, a5
; RV32I-NEXT: lw a2, 372(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 248(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 248(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 368(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 244(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 244(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 364(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 240(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 240(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 360(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 236(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 236(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 356(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 232(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
+; RV32I-NEXT: lw s8, 232(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a5, s7
+; RV32I-NEXT: xor a1, a5, s8
; RV32I-NEXT: lw a2, 352(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a5, 228(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a2, a5
; RV32I-NEXT: lw a2, 348(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 224(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 224(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 456(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 344(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, a2
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, a2
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 340(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 220(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 220(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 336(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 216(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 216(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 332(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 208(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: lw s8, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a2, 328(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 200(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
+; RV32I-NEXT: lw s8, 200(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a5, a5, s7
+; RV32I-NEXT: xor a5, a5, s8
; RV32I-NEXT: lw a1, 324(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a2, 196(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lw a2, 320(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 192(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
-; RV32I-NEXT: xor a1, a1, s7
+; RV32I-NEXT: lw s8, 192(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
+; RV32I-NEXT: xor a1, a1, s8
; RV32I-NEXT: lw a2, 316(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a2, s7
+; RV32I-NEXT: lw s8, 188(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a2, s8
; RV32I-NEXT: xor a5, a0, a5
-; RV32I-NEXT: xor a2, a1, s7
+; RV32I-NEXT: xor a2, a1, s8
; RV32I-NEXT: lw a0, 212(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: lw a0, 184(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: lw a0, 180(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, a0, s7
+; RV32I-NEXT: lw s8, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, a0, s8
; RV32I-NEXT: lw a0, 176(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a0, ra
; RV32I-NEXT: xor a1, a4, a1
-; RV32I-NEXT: xor a0, s7, a0
+; RV32I-NEXT: xor a0, s8, a0
; RV32I-NEXT: lw a4, 172(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, s7
-; RV32I-NEXT: lw s7, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, s8
+; RV32I-NEXT: lw s8, 168(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a4, a4, s7
-; RV32I-NEXT: lw s7, 164(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a4, a4, s8
+; RV32I-NEXT: lw s8, 164(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
+; RV32I-NEXT: and s8, s8, ra
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: xor a1, a4, s7
+; RV32I-NEXT: xor a1, a4, s8
; RV32I-NEXT: lw a4, 160(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, s7
-; RV32I-NEXT: lw s7, 156(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, s8
+; RV32I-NEXT: lw s8, 156(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a4, a4, s7
-; RV32I-NEXT: lw s7, 152(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a4, a4, s8
+; RV32I-NEXT: lw s8, 152(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a4, a4, s7
-; RV32I-NEXT: lw s7, 144(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a4, a4, s8
+; RV32I-NEXT: lw s8, 144(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
+; RV32I-NEXT: and s8, s8, ra
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a1, a4, s7
+; RV32I-NEXT: xor a1, a4, s8
; RV32I-NEXT: lw a4, 136(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, s7
-; RV32I-NEXT: lw s7, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, s8
+; RV32I-NEXT: lw s8, 132(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a4, a4, s7
-; RV32I-NEXT: lw s7, 128(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, s11
-; RV32I-NEXT: xor a4, a4, s7
-; RV32I-NEXT: lw s7, 120(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, s10
-; RV32I-NEXT: xor a4, a4, s7
-; RV32I-NEXT: lw s7, 116(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, s9
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a4, a4, s8
+; RV32I-NEXT: lw s8, 128(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, s11
+; RV32I-NEXT: xor a4, a4, s8
+; RV32I-NEXT: lw s8, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, s10
+; RV32I-NEXT: xor a4, a4, s8
+; RV32I-NEXT: lw s8, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s7, s8, s7
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a1, a4, s7
; RV32I-NEXT: lw a4, 112(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, s8
+; RV32I-NEXT: and a4, a4, s9
; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s5, s7, s5
; RV32I-NEXT: xor a4, a4, s5
@@ -37342,14 +37372,14 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: lw t3, 4(a0)
-; RV32I-NEXT: lw s7, 8(a0)
+; RV32I-NEXT: lw s8, 8(a0)
; RV32I-NEXT: lw a6, 12(a0)
-; RV32I-NEXT: addi s9, a2, -256
+; RV32I-NEXT: addi s10, a2, -256
; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: srli a0, a4, 8
; RV32I-NEXT: srli a2, a4, 24
-; RV32I-NEXT: and a5, a4, s9
-; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a5, a4, s10
+; RV32I-NEXT: and a0, a0, s10
; RV32I-NEXT: slli a5, a5, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: slli a2, a4, 24
@@ -37357,10 +37387,10 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: or a2, a2, a5
; RV32I-NEXT: lui a5, 61681
; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: addi s8, a5, -241
+; RV32I-NEXT: addi s9, a5, -241
; RV32I-NEXT: srli a5, a0, 4
-; RV32I-NEXT: and a0, a0, s8
-; RV32I-NEXT: and a5, a5, s8
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a5, a5, s9
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: lui a5, 209715
@@ -37373,261 +37403,260 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
-; RV32I-NEXT: or t5, t0, t4
-; RV32I-NEXT: srli t6, t5, 1
+; RV32I-NEXT: or t6, t0, t4
+; RV32I-NEXT: srli t5, t6, 1
; RV32I-NEXT: lui t4, 349525
-; RV32I-NEXT: addi t0, t4, 1365
+; RV32I-NEXT: addi ra, t4, 1365
; RV32I-NEXT: srli s0, t2, 8
-; RV32I-NEXT: and t6, t6, t0
+; RV32I-NEXT: and s1, t5, ra
+; RV32I-NEXT: and s0, s0, s10
+; RV32I-NEXT: srli s2, t2, 24
+; RV32I-NEXT: and s3, t2, s10
+; RV32I-NEXT: slli s3, s3, 8
+; RV32I-NEXT: slli s4, t2, 24
+; RV32I-NEXT: or s0, s0, s2
+; RV32I-NEXT: or s2, s4, s3
+; RV32I-NEXT: and t6, t6, ra
+; RV32I-NEXT: or s0, s2, s0
+; RV32I-NEXT: srli s2, s0, 4
; RV32I-NEXT: and s0, s0, s9
-; RV32I-NEXT: srli s1, t2, 24
-; RV32I-NEXT: and s2, t2, s9
-; RV32I-NEXT: slli s2, s2, 8
-; RV32I-NEXT: slli s3, t2, 24
-; RV32I-NEXT: or s0, s0, s1
-; RV32I-NEXT: or s1, s3, s2
-; RV32I-NEXT: and t5, t5, t0
-; RV32I-NEXT: or s0, s1, s0
-; RV32I-NEXT: srli s1, s0, 4
-; RV32I-NEXT: and s0, s0, s8
-; RV32I-NEXT: and s1, s1, s8
+; RV32I-NEXT: and s2, s2, s9
; RV32I-NEXT: slli s0, s0, 4
-; RV32I-NEXT: slli t5, t5, 1
-; RV32I-NEXT: or s0, s1, s0
-; RV32I-NEXT: srli s1, s0, 2
+; RV32I-NEXT: slli t6, t6, 1
+; RV32I-NEXT: or s0, s2, s0
+; RV32I-NEXT: srli s2, s0, 2
; RV32I-NEXT: and s0, s0, a5
-; RV32I-NEXT: and s1, s1, a5
+; RV32I-NEXT: and s2, s2, a5
; RV32I-NEXT: slli s0, s0, 2
-; RV32I-NEXT: or t5, t6, t5
-; RV32I-NEXT: or s0, s1, s0
-; RV32I-NEXT: srli t6, s0, 1
-; RV32I-NEXT: and s0, s0, t0
-; RV32I-NEXT: and s1, t6, t0
-; RV32I-NEXT: slli t6, s0, 1
-; RV32I-NEXT: slli s2, t5, 1
-; RV32I-NEXT: or s0, s1, t6
-; RV32I-NEXT: andi s1, s0, 2
-; RV32I-NEXT: andi s3, s0, 1
-; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: or t6, s1, t6
+; RV32I-NEXT: or s0, s2, s0
+; RV32I-NEXT: srli s1, s0, 1
+; RV32I-NEXT: and s0, s0, ra
+; RV32I-NEXT: and s1, s1, ra
+; RV32I-NEXT: slli s0, s0, 1
+; RV32I-NEXT: slli s2, t6, 1
+; RV32I-NEXT: or s1, s1, s0
+; RV32I-NEXT: andi s3, s1, 2
+; RV32I-NEXT: andi s4, s1, 1
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, s3, t5
-; RV32I-NEXT: xor s1, s2, s1
-; RV32I-NEXT: andi s2, s0, 4
-; RV32I-NEXT: slli s3, t5, 2
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: andi s4, s0, 8
-; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 3
+; RV32I-NEXT: seqz s4, s4
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 16
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 4
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and s2, s3, s2
+; RV32I-NEXT: and s3, s4, t6
+; RV32I-NEXT: xor s2, s3, s2
+; RV32I-NEXT: andi s3, s1, 4
+; RV32I-NEXT: slli s4, t6, 2
+; RV32I-NEXT: seqz s3, s3
; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: andi s5, s1, 8
; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 32
-; RV32I-NEXT: slli s5, t5, 5
-; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: andi s6, s0, 64
; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: slli s6, t5, 6
-; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: andi s5, s1, 16
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: xor s2, s3, s4
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: andi s2, s0, 128
-; RV32I-NEXT: slli s3, t5, 7
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: andi s4, s0, 256
-; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 8
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 512
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 4
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: andi s5, s1, 32
+; RV32I-NEXT: slli s6, t6, 5
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: andi s7, s1, 64
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: slli s7, t6, 6
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 9
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 1024
+; RV32I-NEXT: xor s3, s4, s5
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t5, 10
+; RV32I-NEXT: andi s3, s1, 128
+; RV32I-NEXT: slli s4, t6, 7
+; RV32I-NEXT: seqz s3, s3
; RV32I-NEXT: addi s3, s3, -1
+; RV32I-NEXT: andi s5, s1, 256
; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: li s4, 1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: slli s11, s4, 11
-; RV32I-NEXT: slli s3, t5, 11
-; RV32I-NEXT: and s4, s0, s11
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: lui t1, 1
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: and s5, s0, t1
-; RV32I-NEXT: and s3, s4, s3
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: slli s5, t5, 12
+; RV32I-NEXT: slli s5, t6, 8
; RV32I-NEXT: addi s4, s4, -1
; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: lui t1, 2
+; RV32I-NEXT: andi s5, s1, 512
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s0, t1
-; RV32I-NEXT: lui s10, 2
-; RV32I-NEXT: slli s5, t5, 13
-; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 9
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lui s6, 4
; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: and s5, s0, s6
+; RV32I-NEXT: andi s5, s1, 1024
; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: slli s5, t6, 10
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lui s6, 8
-; RV32I-NEXT: slli s5, t5, 14
-; RV32I-NEXT: and s6, s0, s6
; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: li s5, 1
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: slli t0, s5, 11
+; RV32I-NEXT: slli s4, t6, 11
+; RV32I-NEXT: and s5, s1, t0
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: lui t1, 1
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: and s6, s1, t1
+; RV32I-NEXT: and s4, s5, s4
; RV32I-NEXT: seqz s5, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t5, 15
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: xor s2, s3, s4
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: and s2, s0, a3
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: lui a3, 32
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, a3
+; RV32I-NEXT: lui s7, 2
+; RV32I-NEXT: slli s6, t6, 12
+; RV32I-NEXT: and s7, s1, s7
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, t6, 13
+; RV32I-NEXT: lui s7, 4
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and s6, s1, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui s7, 8
+; RV32I-NEXT: slli s6, t6, 14
+; RV32I-NEXT: and s7, s1, s7
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, t6, 15
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: xor s3, s4, s5
+; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: and s3, s1, a3
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: slli s4, t5, 16
-; RV32I-NEXT: and s2, s2, s4
+; RV32I-NEXT: lui a3, 32
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t5, 17
+; RV32I-NEXT: and s4, s1, a3
+; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: slli s5, t6, 16
+; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: slli s5, t6, 17
; RV32I-NEXT: lui a3, 64
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: and s4, s0, a3
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a3, 128
-; RV32I-NEXT: slli s4, t5, 18
-; RV32I-NEXT: and s5, s0, a3
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: and s5, s1, a3
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t5, 19
+; RV32I-NEXT: lui a3, 128
+; RV32I-NEXT: slli s5, t6, 18
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 19
; RV32I-NEXT: lui a3, 256
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a3
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a3, 512
-; RV32I-NEXT: slli s4, t5, 20
-; RV32I-NEXT: and s5, s0, a3
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s5, s1, a3
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t5, 21
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: and s3, s4, s5
-; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: lui a3, 512
+; RV32I-NEXT: slli s5, t6, 20
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s6, t6, 21
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: and s4, s5, s6
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: lui a3, 1024
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: and s2, s0, a3
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: lui a3, 2048
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, a3
+; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: and s3, s1, a3
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: slli s4, t5, 22
-; RV32I-NEXT: and s2, s2, s4
+; RV32I-NEXT: lui a3, 2048
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t5, 23
+; RV32I-NEXT: and s4, s1, a3
+; RV32I-NEXT: seqz s4, s4
+; RV32I-NEXT: slli s5, t6, 22
+; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: slli s5, t6, 23
; RV32I-NEXT: lui a3, 4096
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: and s4, s0, a3
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a3, 8192
-; RV32I-NEXT: slli s4, t5, 24
-; RV32I-NEXT: and s5, s0, a3
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: and s5, s1, a3
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t5, 25
+; RV32I-NEXT: lui a3, 8192
+; RV32I-NEXT: slli s5, t6, 24
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 25
; RV32I-NEXT: lui a3, 16384
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a3
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a3, 32768
-; RV32I-NEXT: slli s4, t5, 26
-; RV32I-NEXT: and s5, s0, a3
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s5, s1, a3
+; RV32I-NEXT: xor s3, s3, s4
; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t5, 27
+; RV32I-NEXT: lui a3, 32768
+; RV32I-NEXT: slli s5, t6, 26
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 27
; RV32I-NEXT: lui a3, 65536
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a3
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t5, 28
-; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s5, s1, a3
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
; RV32I-NEXT: lui a3, 131072
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: and s3, s0, a3
-; RV32I-NEXT: seqz s3, s3
+; RV32I-NEXT: slli s5, t6, 28
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s4, t6, 29
; RV32I-NEXT: lui a3, 262144
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s0, s0, a3
+; RV32I-NEXT: and s4, s5, s4
+; RV32I-NEXT: and s1, s1, a3
+; RV32I-NEXT: slli t6, t6, 30
+; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: srli s0, s0, 31
+; RV32I-NEXT: and t6, s1, t6
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli s4, t5, 29
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: srli t6, t6, 31
-; RV32I-NEXT: slli s4, t5, 30
-; RV32I-NEXT: and s0, s0, s4
-; RV32I-NEXT: seqz t6, t6
; RV32I-NEXT: slli t5, t5, 31
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: xor s0, s3, s0
-; RV32I-NEXT: and t5, t6, t5
-; RV32I-NEXT: xor t6, s1, s2
-; RV32I-NEXT: xor t5, s0, t5
+; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: xor t6, s4, t6
+; RV32I-NEXT: and t5, s0, t5
+; RV32I-NEXT: xor s0, s2, s3
; RV32I-NEXT: xor t5, t6, t5
+; RV32I-NEXT: xor t5, s0, t5
; RV32I-NEXT: srli t6, t5, 8
-; RV32I-NEXT: and t6, t6, s9
+; RV32I-NEXT: and t6, t6, s10
; RV32I-NEXT: srli s0, t5, 24
-; RV32I-NEXT: and s1, t5, s9
+; RV32I-NEXT: and s1, t5, s10
; RV32I-NEXT: slli t5, t5, 24
; RV32I-NEXT: slli s1, s1, 8
; RV32I-NEXT: or t6, t6, s0
; RV32I-NEXT: or t5, t5, s1
; RV32I-NEXT: or t5, t5, t6
; RV32I-NEXT: srli t6, t5, 4
-; RV32I-NEXT: and t5, t5, s8
-; RV32I-NEXT: and t6, t6, s8
+; RV32I-NEXT: and t5, t5, s9
+; RV32I-NEXT: and t6, t6, s9
; RV32I-NEXT: slli t5, t5, 4
; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: srli t6, t5, 2
@@ -37639,7 +37668,7 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: sw a0, 216(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli t4, t5, 1
; RV32I-NEXT: and t4, t4, a0
-; RV32I-NEXT: and t5, t5, t0
+; RV32I-NEXT: and t5, t5, ra
; RV32I-NEXT: slli t5, t5, 1
; RV32I-NEXT: andi t6, t2, 2
; RV32I-NEXT: seqz t6, t6
@@ -37717,7 +37746,7 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: and t6, a3, s1
; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: and t6, t2, s11
+; RV32I-NEXT: and t6, t2, t0
; RV32I-NEXT: xor t4, t4, t5
; RV32I-NEXT: seqz t5, t6
; RV32I-NEXT: addi a3, t5, -1
@@ -37730,23 +37759,24 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: addi a3, t5, -1
; RV32I-NEXT: sw a3, 396(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t5, t3, 12
-; RV32I-NEXT: and s1, t2, s10
+; RV32I-NEXT: lui s2, 2
+; RV32I-NEXT: and s1, t2, s2
; RV32I-NEXT: and t5, a3, t5
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t5, t6, t5
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 392(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 13
-; RV32I-NEXT: lui s2, 4
-; RV32I-NEXT: and s1, t2, s2
+; RV32I-NEXT: lui s3, 4
+; RV32I-NEXT: and s1, t2, s3
; RV32I-NEXT: and t6, a3, t6
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 388(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 14
-; RV32I-NEXT: lui s3, 8
-; RV32I-NEXT: and s1, t2, s3
+; RV32I-NEXT: lui s4, 8
+; RV32I-NEXT: and s1, t2, s4
; RV32I-NEXT: and t6, a3, t6
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: addi a3, s1, -1
@@ -37755,46 +37785,46 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: and t6, a3, s1
; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: lui s10, 16
-; RV32I-NEXT: and t6, t2, s10
+; RV32I-NEXT: lui s11, 16
+; RV32I-NEXT: and t6, t2, s11
; RV32I-NEXT: xor t4, t4, t5
; RV32I-NEXT: seqz t5, t6
; RV32I-NEXT: addi a3, t5, -1
; RV32I-NEXT: sw a3, 380(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s4, 32
-; RV32I-NEXT: and t5, t2, s4
+; RV32I-NEXT: lui s5, 32
+; RV32I-NEXT: and t5, t2, s5
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: slli t6, t3, 16
; RV32I-NEXT: and t6, a3, t6
; RV32I-NEXT: addi a3, t5, -1
; RV32I-NEXT: sw a3, 376(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t5, t3, 17
-; RV32I-NEXT: lui s5, 64
-; RV32I-NEXT: and s1, t2, s5
+; RV32I-NEXT: lui s6, 64
+; RV32I-NEXT: and s1, t2, s6
; RV32I-NEXT: and t5, a3, t5
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t5, t6, t5
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 372(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 18
-; RV32I-NEXT: lui s6, 128
-; RV32I-NEXT: and s1, t2, s6
+; RV32I-NEXT: lui s7, 128
+; RV32I-NEXT: and s1, t2, s7
; RV32I-NEXT: and t6, a3, t6
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 368(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 19
-; RV32I-NEXT: lui ra, 256
-; RV32I-NEXT: and s1, t2, ra
+; RV32I-NEXT: lui a0, 256
+; RV32I-NEXT: and s1, t2, a0
; RV32I-NEXT: and t6, a3, t6
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 364(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 20
-; RV32I-NEXT: lui a0, 512
-; RV32I-NEXT: and s1, t2, a0
+; RV32I-NEXT: lui t1, 512
+; RV32I-NEXT: and s1, t2, t1
; RV32I-NEXT: and t6, a3, t6
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: addi a3, s1, -1
@@ -37822,23 +37852,23 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: and t5, a3, t5
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t5, t6, t5
-; RV32I-NEXT: addi t1, s1, -1
-; RV32I-NEXT: sw t1, 348(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: sw s1, 348(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 24
; RV32I-NEXT: lui a3, 8192
-; RV32I-NEXT: and s1, t2, a3
-; RV32I-NEXT: and t6, t1, t6
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: xor t5, t5, t6
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: sw s1, 344(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t6, t3, 25
-; RV32I-NEXT: lui t1, 16384
-; RV32I-NEXT: and a0, t2, t1
+; RV32I-NEXT: and a0, t2, a3
; RV32I-NEXT: and t6, s1, t6
; RV32I-NEXT: seqz s1, a0
; RV32I-NEXT: xor t5, t5, t6
; RV32I-NEXT: addi a0, s1, -1
+; RV32I-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t6, t3, 25
+; RV32I-NEXT: lui s1, 16384
+; RV32I-NEXT: and s1, t2, s1
+; RV32I-NEXT: and t6, a0, t6
+; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: xor t5, t5, t6
+; RV32I-NEXT: addi a0, s1, -1
; RV32I-NEXT: sw a0, 340(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t6, t3, 26
; RV32I-NEXT: lui s1, 32768
@@ -37956,103 +37986,101 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: xor t3, t3, t5
; RV32I-NEXT: and t4, t4, a0
; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: mv a0, s11
-; RV32I-NEXT: and t4, a2, s11
+; RV32I-NEXT: and t4, a2, t0
; RV32I-NEXT: xor t2, t2, t3
; RV32I-NEXT: seqz t3, t4
; RV32I-NEXT: addi t3, t3, -1
; RV32I-NEXT: and t4, a2, s0
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: slli t5, a4, 11
-; RV32I-NEXT: sw t5, 276(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t3, t3, t5
+; RV32I-NEXT: slli a0, a4, 11
+; RV32I-NEXT: sw a0, 276(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t3, t3, a0
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t6, a4, 12
-; RV32I-NEXT: sw t6, 272(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s0, 2
-; RV32I-NEXT: and t5, a2, s0
-; RV32I-NEXT: and t4, t4, t6
+; RV32I-NEXT: slli a0, a4, 12
+; RV32I-NEXT: sw a0, 272(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t5, a2, s2
+; RV32I-NEXT: and t4, t4, a0
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: xor t3, t3, t4
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: slli t6, a4, 13
-; RV32I-NEXT: sw t6, 268(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t4, a2, s2
-; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: slli a0, a4, 13
+; RV32I-NEXT: sw a0, 268(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, a2, s3
+; RV32I-NEXT: and t5, t5, a0
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: xor t3, t3, t5
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t6, a4, 14
-; RV32I-NEXT: sw t6, 264(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t5, a2, s3
-; RV32I-NEXT: and t4, t4, t6
+; RV32I-NEXT: slli a0, a4, 14
+; RV32I-NEXT: sw a0, 264(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t5, a2, s4
+; RV32I-NEXT: and t4, t4, a0
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: slli t6, a4, 15
-; RV32I-NEXT: sw t6, 260(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a4, 15
+; RV32I-NEXT: sw a0, 260(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: and t4, t5, t6
+; RV32I-NEXT: and t4, t5, a0
; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: and t4, a2, s10
+; RV32I-NEXT: and t4, a2, s11
; RV32I-NEXT: xor t2, t2, t3
; RV32I-NEXT: seqz t3, t4
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t4, a2, s4
-; RV32I-NEXT: lui s10, 32
+; RV32I-NEXT: and t4, a2, s5
+; RV32I-NEXT: lui s11, 32
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: slli t5, a4, 16
-; RV32I-NEXT: sw t5, 256(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t3, t3, t5
+; RV32I-NEXT: slli a0, a4, 16
+; RV32I-NEXT: sw a0, 256(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t3, t3, a0
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t6, a4, 17
-; RV32I-NEXT: sw t6, 252(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t5, a2, s5
-; RV32I-NEXT: and t4, t4, t6
+; RV32I-NEXT: slli a0, a4, 17
+; RV32I-NEXT: sw a0, 252(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t5, a2, s6
+; RV32I-NEXT: and t4, t4, a0
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: xor t3, t3, t4
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: slli t6, a4, 18
-; RV32I-NEXT: sw t6, 248(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t4, a2, s6
-; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: slli a0, a4, 18
+; RV32I-NEXT: sw a0, 248(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, a2, s7
+; RV32I-NEXT: and t5, t5, a0
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: xor t3, t3, t5
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t6, a4, 19
-; RV32I-NEXT: sw t6, 244(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t5, a2, ra
-; RV32I-NEXT: and t4, t4, t6
+; RV32I-NEXT: slli a0, a4, 19
+; RV32I-NEXT: sw a0, 244(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t5, 256
+; RV32I-NEXT: and t5, a2, t5
+; RV32I-NEXT: and t4, t4, a0
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: xor t3, t3, t4
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: slli t6, a4, 20
-; RV32I-NEXT: sw t6, 240(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui t4, 512
-; RV32I-NEXT: and t4, a2, t4
-; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: slli a0, a4, 20
+; RV32I-NEXT: sw a0, 240(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, a2, t1
+; RV32I-NEXT: and t5, t5, a0
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: xor t3, t3, t5
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t6, a4, 21
-; RV32I-NEXT: sw t6, 236(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui t5, 1024
-; RV32I-NEXT: and t5, a2, t5
-; RV32I-NEXT: and t4, t4, t6
+; RV32I-NEXT: slli a0, a4, 21
+; RV32I-NEXT: sw a0, 236(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t1, 1024
+; RV32I-NEXT: and t5, a2, t1
+; RV32I-NEXT: and t4, t4, a0
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: xor t3, t3, t4
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: slli t6, a4, 22
-; RV32I-NEXT: sw t6, 232(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui t4, 2048
-; RV32I-NEXT: and t4, a2, t4
-; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: slli a0, a4, 22
+; RV32I-NEXT: sw a0, 232(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t1, 2048
+; RV32I-NEXT: and t4, a2, t1
+; RV32I-NEXT: and t5, t5, a0
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t6, a4, 23
-; RV32I-NEXT: sw t6, 228(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t4, t4, t6
-; RV32I-NEXT: lui t6, 4096
-; RV32I-NEXT: and t6, a2, t6
+; RV32I-NEXT: slli a0, a4, 23
+; RV32I-NEXT: sw a0, 228(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: lui a0, 4096
+; RV32I-NEXT: and t6, a2, a0
; RV32I-NEXT: xor t4, t5, t4
; RV32I-NEXT: seqz t5, t6
; RV32I-NEXT: addi t5, t5, -1
@@ -38062,45 +38090,46 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: seqz t6, t6
; RV32I-NEXT: xor t4, t4, t5
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: slli a3, a4, 25
-; RV32I-NEXT: sw a3, 224(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t5, a2, t1
-; RV32I-NEXT: and t6, t6, a3
+; RV32I-NEXT: slli a0, a4, 25
+; RV32I-NEXT: sw a0, 224(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a3, 16384
+; RV32I-NEXT: and t5, a2, a3
+; RV32I-NEXT: and t6, t6, a0
; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: slli a3, a4, 26
-; RV32I-NEXT: sw a3, 220(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a4, 26
+; RV32I-NEXT: sw a0, 220(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor t4, t4, t6
-; RV32I-NEXT: and t5, t5, a3
+; RV32I-NEXT: and t5, t5, a0
; RV32I-NEXT: xor t2, t2, t3
; RV32I-NEXT: xor t5, t4, t5
-; RV32I-NEXT: srli t3, s7, 8
+; RV32I-NEXT: srli t3, s8, 8
; RV32I-NEXT: srli t4, a7, 8
-; RV32I-NEXT: and t3, t3, s9
-; RV32I-NEXT: and t4, t4, s9
-; RV32I-NEXT: srli t6, s7, 24
+; RV32I-NEXT: and t3, t3, s10
+; RV32I-NEXT: and t4, t4, s10
+; RV32I-NEXT: srli t6, s8, 24
; RV32I-NEXT: srli s2, a7, 24
; RV32I-NEXT: or t3, t3, t6
; RV32I-NEXT: or t4, t4, s2
-; RV32I-NEXT: and t6, s7, s9
-; RV32I-NEXT: and s2, a7, s9
-; RV32I-NEXT: mv s11, s9
+; RV32I-NEXT: and t6, s8, s10
+; RV32I-NEXT: and s2, a7, s10
+; RV32I-NEXT: mv a0, s10
; RV32I-NEXT: slli t6, t6, 8
; RV32I-NEXT: slli s2, s2, 8
-; RV32I-NEXT: slli a3, s7, 24
-; RV32I-NEXT: sw a3, 208(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t1, s8, 24
+; RV32I-NEXT: sw t1, 208(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli s3, a7, 24
; RV32I-NEXT: or s2, s3, s2
-; RV32I-NEXT: or t6, a3, t6
+; RV32I-NEXT: or t6, t1, t6
; RV32I-NEXT: or t3, t6, t3
; RV32I-NEXT: or t4, s2, t4
; RV32I-NEXT: srli t6, t3, 4
-; RV32I-NEXT: and t3, t3, s8
-; RV32I-NEXT: and t6, t6, s8
+; RV32I-NEXT: and t3, t3, s9
+; RV32I-NEXT: and t6, t6, s9
; RV32I-NEXT: slli t3, t3, 4
; RV32I-NEXT: srli s2, t4, 4
-; RV32I-NEXT: and t4, t4, s8
-; RV32I-NEXT: and s2, s2, s8
+; RV32I-NEXT: and t4, t4, s9
+; RV32I-NEXT: and s2, s2, s9
; RV32I-NEXT: slli t4, t4, 4
; RV32I-NEXT: or t3, t6, t3
; RV32I-NEXT: or t4, s2, t4
@@ -38108,246 +38137,246 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: and t3, t3, a5
; RV32I-NEXT: and t6, t6, a5
; RV32I-NEXT: slli t3, t3, 2
-; RV32I-NEXT: or t6, t6, t3
-; RV32I-NEXT: srli t3, t4, 2
-; RV32I-NEXT: and t3, t3, a5
+; RV32I-NEXT: srli s2, t4, 2
; RV32I-NEXT: and t4, t4, a5
+; RV32I-NEXT: and s2, s2, a5
; RV32I-NEXT: slli t4, t4, 2
-; RV32I-NEXT: srli s2, t6, 1
-; RV32I-NEXT: or t3, t3, t4
-; RV32I-NEXT: and t4, s2, t0
-; RV32I-NEXT: srli s2, t3, 1
-; RV32I-NEXT: and t3, t3, t0
-; RV32I-NEXT: and s2, s2, t0
-; RV32I-NEXT: slli t3, t3, 1
-; RV32I-NEXT: and s3, t6, t0
-; RV32I-NEXT: or t6, s2, t3
-; RV32I-NEXT: slli s3, s3, 1
-; RV32I-NEXT: andi s2, t6, 2
-; RV32I-NEXT: or t4, t4, s3
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: slli s3, t4, 1
-; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: lui a3, 32768
-; RV32I-NEXT: and s3, a2, a3
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: andi s4, t6, 1
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, a4, 27
-; RV32I-NEXT: sw s5, 212(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s3, s3, s5
-; RV32I-NEXT: and s4, s4, t4
-; RV32I-NEXT: xor t5, t5, s3
-; RV32I-NEXT: xor s2, s4, s2
-; RV32I-NEXT: andi s3, t6, 4
-; RV32I-NEXT: andi s4, t6, 8
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 2
-; RV32I-NEXT: slli s6, t4, 3
-; RV32I-NEXT: and s3, s3, s5
-; RV32I-NEXT: and s4, s4, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: andi s4, t6, 16
-; RV32I-NEXT: xor s2, s2, s3
+; RV32I-NEXT: or t6, t6, t3
+; RV32I-NEXT: or t4, s2, t4
+; RV32I-NEXT: srli t3, t6, 1
+; RV32I-NEXT: and t6, t6, ra
+; RV32I-NEXT: srli s2, t4, 1
+; RV32I-NEXT: and t4, t4, ra
+; RV32I-NEXT: and s2, s2, ra
+; RV32I-NEXT: slli t4, t4, 1
+; RV32I-NEXT: slli s3, t6, 1
+; RV32I-NEXT: or t6, s2, t4
+; RV32I-NEXT: and s2, t3, ra
+; RV32I-NEXT: andi s4, t6, 2
+; RV32I-NEXT: or s2, s2, s3
; RV32I-NEXT: seqz s3, s4
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: andi s4, t6, 32
+; RV32I-NEXT: slli s4, s2, 1
+; RV32I-NEXT: and s3, s3, s4
+; RV32I-NEXT: lui t1, 32768
+; RV32I-NEXT: and s4, a2, t1
; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 4
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: andi s5, t6, 1
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 5
-; RV32I-NEXT: andi s6, t6, 64
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: andi s4, t6, 128
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: andi s4, t6, 256
+; RV32I-NEXT: slli s6, a4, 27
+; RV32I-NEXT: sw s6, 212(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: and s5, s5, s2
+; RV32I-NEXT: xor t5, t5, s4
+; RV32I-NEXT: xor s3, s5, s3
+; RV32I-NEXT: andi s4, t6, 4
+; RV32I-NEXT: andi s5, t6, 8
; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 7
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: seqz s5, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 8
-; RV32I-NEXT: andi s6, t6, 512
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 9
-; RV32I-NEXT: andi s6, t6, 1024
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 10
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
+; RV32I-NEXT: slli s6, s2, 2
+; RV32I-NEXT: slli s7, s2, 3
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: and s5, s5, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: andi s5, t6, 16
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, t6, a0
-; RV32I-NEXT: mv s9, a0
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: and s4, t6, a0
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 11
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 12
-; RV32I-NEXT: and s6, t6, s0
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 13
-; RV32I-NEXT: lui a0, 4
-; RV32I-NEXT: and s6, t6, a0
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 14
-; RV32I-NEXT: lui a0, 8
-; RV32I-NEXT: and s6, t6, a0
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: andi s5, t6, 32
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 4
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 15
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
+; RV32I-NEXT: slli s6, s2, 5
+; RV32I-NEXT: andi s7, t6, 64
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 6
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: andi s5, t6, 128
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: lui a0, 16
-; RV32I-NEXT: and s4, t6, a0
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s4, t6, s10
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 16
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 17
-; RV32I-NEXT: lui a0, 64
-; RV32I-NEXT: and s6, t6, a0
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 18
-; RV32I-NEXT: lui a0, 128
-; RV32I-NEXT: and s6, t6, a0
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 19
-; RV32I-NEXT: and s6, t6, ra
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 20
-; RV32I-NEXT: lui a0, 512
-; RV32I-NEXT: and s6, t6, a0
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: andi s5, t6, 256
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 7
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 21
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
+; RV32I-NEXT: slli s6, s2, 8
+; RV32I-NEXT: andi s7, t6, 512
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 9
+; RV32I-NEXT: andi s7, t6, 1024
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 10
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: mv s10, t0
+; RV32I-NEXT: and s5, t6, t0
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: lui a0, 1024
-; RV32I-NEXT: and s4, t6, a0
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a0, 2048
-; RV32I-NEXT: and s4, t6, a0
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: slli s5, t4, 22
-; RV32I-NEXT: and s3, s3, s5
+; RV32I-NEXT: seqz s4, s5
; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t4, 23
-; RV32I-NEXT: lui a0, 4096
-; RV32I-NEXT: and s6, t6, a0
-; RV32I-NEXT: and s4, s4, s5
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 24
-; RV32I-NEXT: lui a0, 8192
-; RV32I-NEXT: and s6, t6, a0
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: and s5, t6, s0
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 11
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 25
-; RV32I-NEXT: and s6, t6, t1
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: slli s6, s2, 12
+; RV32I-NEXT: lui t0, 2
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 13
+; RV32I-NEXT: lui t0, 4
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 14
+; RV32I-NEXT: lui t0, 8
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 15
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lui t0, 16
+; RV32I-NEXT: and s5, t6, t0
; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: and s5, t6, s11
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 16
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 26
-; RV32I-NEXT: and s6, t6, a3
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: slli s6, s2, 17
+; RV32I-NEXT: lui t0, 64
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 18
+; RV32I-NEXT: lui t0, 128
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 19
+; RV32I-NEXT: lui t0, 256
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 20
+; RV32I-NEXT: lui t0, 512
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 21
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lui t0, 1024
+; RV32I-NEXT: and s5, t6, t0
; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: lui t0, 2048
+; RV32I-NEXT: and s5, t6, t0
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s2, 22
+; RV32I-NEXT: and s4, s4, s6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t4, 27
+; RV32I-NEXT: slli s6, s2, 23
+; RV32I-NEXT: lui t0, 4096
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 24
+; RV32I-NEXT: lui t0, 8192
+; RV32I-NEXT: and s7, t6, t0
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 25
+; RV32I-NEXT: and s7, t6, a3
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 26
+; RV32I-NEXT: and s7, t6, t1
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s2, 27
; RV32I-NEXT: lui a3, 65536
-; RV32I-NEXT: and s6, t6, a3
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t4, 28
+; RV32I-NEXT: and s7, t6, a3
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s2, 28
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s4, s4, s5
+; RV32I-NEXT: lui s6, 131072
+; RV32I-NEXT: and s5, t6, s6
; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: lui s5, 131072
-; RV32I-NEXT: and s4, t6, s5
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui s6, 262144
-; RV32I-NEXT: and t6, t6, s6
+; RV32I-NEXT: seqz s4, s5
+; RV32I-NEXT: addi s4, s4, -1
+; RV32I-NEXT: slli s5, s2, 29
+; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: lui s5, 262144
+; RV32I-NEXT: and t6, t6, s5
+; RV32I-NEXT: slli s2, s2, 30
; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: slli s4, t4, 29
-; RV32I-NEXT: and s3, s3, s4
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: srli t3, t3, 31
-; RV32I-NEXT: slli s4, t4, 30
-; RV32I-NEXT: and t6, t6, s4
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: slli t4, t4, 31
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: xor t6, s3, t6
-; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: srli t4, t4, 31
+; RV32I-NEXT: and t6, t6, s2
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: slli t3, t3, 31
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: xor t6, s4, t6
+; RV32I-NEXT: and t3, t4, t3
; RV32I-NEXT: xor t3, t6, t3
; RV32I-NEXT: and t4, a2, a3
-; RV32I-NEXT: lui ra, 65536
-; RV32I-NEXT: xor t3, s2, t3
+; RV32I-NEXT: xor t3, s3, t3
; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli a0, a4, 28
-; RV32I-NEXT: sw a0, 204(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t4, t4, a0
+; RV32I-NEXT: slli a3, a4, 28
+; RV32I-NEXT: sw a3, 204(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a3
; RV32I-NEXT: srli t6, t3, 8
; RV32I-NEXT: xor t4, t5, t4
-; RV32I-NEXT: and t5, t6, s11
-; RV32I-NEXT: and t1, t3, s11
+; RV32I-NEXT: and t5, t6, a0
+; RV32I-NEXT: and t1, t3, a0
; RV32I-NEXT: srli t6, t3, 24
; RV32I-NEXT: slli t3, t3, 24
; RV32I-NEXT: slli t1, t1, 8
@@ -38355,9 +38384,9 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: xor t2, t2, t4
; RV32I-NEXT: or t1, t1, t5
-; RV32I-NEXT: and t3, a2, s5
-; RV32I-NEXT: lui s10, 131072
-; RV32I-NEXT: and t4, a2, s6
+; RV32I-NEXT: and t3, a2, s6
+; RV32I-NEXT: lui s7, 131072
+; RV32I-NEXT: and t4, a2, s5
; RV32I-NEXT: lui s11, 262144
; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: seqz t4, t4
@@ -38372,8 +38401,8 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: xor t3, t3, t4
; RV32I-NEXT: srli t4, t1, 4
; RV32I-NEXT: srli a0, a2, 31
-; RV32I-NEXT: and t4, t4, s8
-; RV32I-NEXT: and a2, t1, s8
+; RV32I-NEXT: and t4, t4, s9
+; RV32I-NEXT: and a2, t1, s9
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: slli t1, a4, 31
@@ -38405,7 +38434,7 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: slli a0, a6, 1
; RV32I-NEXT: and a0, t1, a0
; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: and a2, a2, t0
+; RV32I-NEXT: and a2, a2, ra
; RV32I-NEXT: sw a2, 128(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a0, a5, a0
; RV32I-NEXT: andi a2, a7, 4
@@ -38470,7 +38499,7 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: and a5, a3, t0
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, a7, s9
+; RV32I-NEXT: and a5, a7, s10
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a3, a2, -1
@@ -38483,24 +38512,24 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: sw a3, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a2, a6, 12
-; RV32I-NEXT: lui t1, 2
-; RV32I-NEXT: and t0, a7, t1
+; RV32I-NEXT: lui s5, 2
+; RV32I-NEXT: and t0, a7, s5
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a5, a2
; RV32I-NEXT: addi a3, t0, -1
; RV32I-NEXT: sw a3, 132(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 13
-; RV32I-NEXT: lui s5, 4
-; RV32I-NEXT: and t0, a7, s5
+; RV32I-NEXT: lui s4, 4
+; RV32I-NEXT: and t0, a7, s4
; RV32I-NEXT: and a5, a3, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a3, t0, -1
; RV32I-NEXT: sw a3, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 14
-; RV32I-NEXT: lui s4, 8
-; RV32I-NEXT: and t0, a7, s4
+; RV32I-NEXT: lui s3, 8
+; RV32I-NEXT: and t0, a7, s3
; RV32I-NEXT: and a5, a3, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: addi a3, t0, -1
@@ -38509,46 +38538,46 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: and a5, a3, t0
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: lui s1, 16
-; RV32I-NEXT: and a5, a7, s1
+; RV32I-NEXT: lui s0, 16
+; RV32I-NEXT: and a5, a7, s0
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: sw a3, 116(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s2, 32
-; RV32I-NEXT: and a2, a7, s2
+; RV32I-NEXT: lui s1, 32
+; RV32I-NEXT: and a2, a7, s1
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: slli a5, a6, 16
; RV32I-NEXT: and a5, a3, a5
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: sw a3, 112(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a2, a6, 17
-; RV32I-NEXT: lui s3, 64
-; RV32I-NEXT: and t0, a7, s3
+; RV32I-NEXT: lui s2, 64
+; RV32I-NEXT: and t0, a7, s2
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a5, a2
; RV32I-NEXT: addi a3, t0, -1
; RV32I-NEXT: sw a3, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 18
-; RV32I-NEXT: lui s0, 128
-; RV32I-NEXT: and t0, a7, s0
+; RV32I-NEXT: lui t6, 128
+; RV32I-NEXT: and t0, a7, t6
; RV32I-NEXT: and a5, a3, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a3, t0, -1
; RV32I-NEXT: sw a3, 104(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 19
-; RV32I-NEXT: lui t6, 256
-; RV32I-NEXT: and t0, a7, t6
+; RV32I-NEXT: lui t5, 256
+; RV32I-NEXT: and t0, a7, t5
; RV32I-NEXT: and a5, a3, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a3, t0, -1
; RV32I-NEXT: sw a3, 100(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 20
-; RV32I-NEXT: lui t5, 512
-; RV32I-NEXT: and t0, a7, t5
+; RV32I-NEXT: lui t4, 512
+; RV32I-NEXT: and t0, a7, t4
; RV32I-NEXT: and a5, a3, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: addi a3, t0, -1
@@ -38557,62 +38586,64 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: and a5, a3, t0
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: lui t2, 1024
-; RV32I-NEXT: and a5, a7, t2
+; RV32I-NEXT: lui t1, 1024
+; RV32I-NEXT: and a5, a7, t1
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: sw a3, 92(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui t3, 2048
-; RV32I-NEXT: and a2, a7, t3
+; RV32I-NEXT: lui t2, 2048
+; RV32I-NEXT: and a2, a7, t2
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: slli a5, a6, 22
; RV32I-NEXT: and a5, a3, a5
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: sw a3, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a2, a6, 23
-; RV32I-NEXT: lui t4, 4096
-; RV32I-NEXT: and t0, a7, t4
+; RV32I-NEXT: lui t3, 4096
+; RV32I-NEXT: and t0, a7, t3
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a5, a2
-; RV32I-NEXT: addi s8, t0, -1
-; RV32I-NEXT: sw s8, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, t0, -1
+; RV32I-NEXT: sw s9, 84(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 24
; RV32I-NEXT: lui a3, 8192
; RV32I-NEXT: and t0, a7, a3
-; RV32I-NEXT: and a5, s8, a5
+; RV32I-NEXT: lui ra, 8192
+; RV32I-NEXT: and a5, s9, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: addi s8, t0, -1
-; RV32I-NEXT: sw s8, 80(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, t0, -1
+; RV32I-NEXT: sw s9, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 25
; RV32I-NEXT: lui a3, 16384
; RV32I-NEXT: and t0, a7, a3
-; RV32I-NEXT: and a5, s8, a5
+; RV32I-NEXT: and a5, s9, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: addi s8, t0, -1
-; RV32I-NEXT: sw s8, 76(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, t0, -1
+; RV32I-NEXT: sw s9, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 26
-; RV32I-NEXT: lui a3, 32768
-; RV32I-NEXT: and t0, a7, a3
-; RV32I-NEXT: and a5, s8, a5
+; RV32I-NEXT: lui t0, 32768
+; RV32I-NEXT: and t0, a7, t0
+; RV32I-NEXT: and a5, s9, a5
; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: addi s8, t0, -1
-; RV32I-NEXT: sw s8, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, t0, -1
+; RV32I-NEXT: sw s9, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, a6, 27
-; RV32I-NEXT: and t0, a7, ra
-; RV32I-NEXT: and a5, s8, a5
+; RV32I-NEXT: lui t0, 65536
+; RV32I-NEXT: and t0, a7, t0
+; RV32I-NEXT: and a5, s9, a5
; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: addi s8, t0, -1
-; RV32I-NEXT: sw s8, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s9, t0, -1
+; RV32I-NEXT: sw s9, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli t0, a6, 28
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, s8, t0
+; RV32I-NEXT: and a5, s9, t0
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, a7, s10
+; RV32I-NEXT: and a5, a7, s7
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi t0, a2, -1
@@ -38639,10 +38670,10 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, s7, 1
+; RV32I-NEXT: slli a7, s8, 1
; RV32I-NEXT: sw a7, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: and a6, a6, s7
+; RV32I-NEXT: and a6, a6, s8
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a0, a6, a5
@@ -38652,9 +38683,9 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a6, s7, 2
+; RV32I-NEXT: slli a6, s8, 2
; RV32I-NEXT: sw a6, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, s7, 3
+; RV32I-NEXT: slli a7, s8, 3
; RV32I-NEXT: sw a7, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: and a5, a5, a7
@@ -38665,17 +38696,17 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: andi a5, a1, 32
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli a6, s7, 4
+; RV32I-NEXT: slli a6, s8, 4
; RV32I-NEXT: sw a6, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a7, s7, 5
+; RV32I-NEXT: slli a7, s8, 5
; RV32I-NEXT: sw a7, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a6, a1, 64
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, s7, 6
+; RV32I-NEXT: slli a7, s8, 6
; RV32I-NEXT: sw a7, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: and a5, a6, a7
@@ -38686,138 +38717,138 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: andi a5, a1, 256
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli a6, s7, 7
+; RV32I-NEXT: slli a6, s8, 7
; RV32I-NEXT: sw a6, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a7, s7, 8
+; RV32I-NEXT: slli a7, s8, 8
; RV32I-NEXT: sw a7, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a6, a1, 512
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, s7, 9
+; RV32I-NEXT: slli a7, s8, 9
; RV32I-NEXT: sw a7, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a5, a1, 1024
; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a7, s7, 10
+; RV32I-NEXT: slli a7, s8, 10
; RV32I-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, a1, s9
+; RV32I-NEXT: and a5, a1, s10
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a5, a1, s6
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli a6, s7, 11
+; RV32I-NEXT: slli a6, s8, 11
; RV32I-NEXT: sw a6, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, a1, t1
-; RV32I-NEXT: slli a7, s7, 12
+; RV32I-NEXT: and a6, a1, s5
+; RV32I-NEXT: slli a7, s8, 12
; RV32I-NEXT: sw a7, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a5, a1, s5
-; RV32I-NEXT: slli s11, s7, 13
+; RV32I-NEXT: and a5, a1, s4
+; RV32I-NEXT: slli s11, s8, 13
; RV32I-NEXT: and a6, a6, s11
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, a1, s4
-; RV32I-NEXT: slli s10, s7, 14
+; RV32I-NEXT: and a6, a1, s3
+; RV32I-NEXT: slli s10, s8, 14
; RV32I-NEXT: and a5, a5, s10
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli s9, s7, 15
+; RV32I-NEXT: slli s7, s8, 15
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, a6, s9
+; RV32I-NEXT: and a5, a6, s7
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, a1, s1
+; RV32I-NEXT: and a5, a1, s0
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a5, a1, s2
+; RV32I-NEXT: and a5, a1, s1
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli s8, s7, 16
-; RV32I-NEXT: and a2, a2, s8
+; RV32I-NEXT: slli s9, s8, 16
+; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, a1, s3
-; RV32I-NEXT: slli s5, s7, 17
+; RV32I-NEXT: and a6, a1, s2
+; RV32I-NEXT: slli s5, s8, 17
; RV32I-NEXT: and a5, a5, s5
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a5, a1, s0
-; RV32I-NEXT: slli s4, s7, 18
+; RV32I-NEXT: and a5, a1, t6
+; RV32I-NEXT: slli s4, s8, 18
; RV32I-NEXT: and a6, a6, s4
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, a1, t6
-; RV32I-NEXT: slli s3, s7, 19
+; RV32I-NEXT: and a6, a1, t5
+; RV32I-NEXT: slli s3, s8, 19
; RV32I-NEXT: and a5, a5, s3
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a5, a1, t5
-; RV32I-NEXT: slli s2, s7, 20
+; RV32I-NEXT: and a5, a1, t4
+; RV32I-NEXT: slli s2, s8, 20
; RV32I-NEXT: and a6, a6, s2
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli t6, s7, 21
+; RV32I-NEXT: slli t6, s8, 21
; RV32I-NEXT: xor a2, a2, a6
; RV32I-NEXT: and a5, a5, t6
; RV32I-NEXT: xor a2, a2, a5
-; RV32I-NEXT: and a5, a1, t2
+; RV32I-NEXT: and a5, a1, t1
; RV32I-NEXT: xor s0, a0, a2
; RV32I-NEXT: seqz a0, a5
; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: and a2, a1, t3
+; RV32I-NEXT: and a2, a1, t2
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: slli s6, s7, 22
+; RV32I-NEXT: slli s6, s8, 22
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a5, a1, t4
-; RV32I-NEXT: slli t4, s7, 23
+; RV32I-NEXT: and a5, a1, t3
+; RV32I-NEXT: slli t4, s8, 23
; RV32I-NEXT: and a2, a2, t4
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: lw t5, 208(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a5, t5
-; RV32I-NEXT: lui a5, 8192
-; RV32I-NEXT: and a5, a1, a5
+; RV32I-NEXT: and a5, a1, ra
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli t3, s7, 25
+; RV32I-NEXT: slli t3, s8, 25
; RV32I-NEXT: and a2, a2, t3
-; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and a5, a1, a5
+; RV32I-NEXT: and a5, a1, a3
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli t2, s7, 26
+; RV32I-NEXT: slli t2, s8, 26
; RV32I-NEXT: and a2, a2, t2
-; RV32I-NEXT: and a5, a1, a3
+; RV32I-NEXT: lui a5, 32768
+; RV32I-NEXT: and a5, a1, a5
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli t1, s7, 27
+; RV32I-NEXT: slli t1, s8, 27
; RV32I-NEXT: and a2, a2, t1
-; RV32I-NEXT: and a5, a1, ra
+; RV32I-NEXT: lui a5, 65536
+; RV32I-NEXT: and a5, a1, a5
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: seqz a2, a5
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: slli t0, s7, 28
+; RV32I-NEXT: slli t0, s8, 28
; RV32I-NEXT: and a2, a2, t0
; RV32I-NEXT: lui a5, 131072
; RV32I-NEXT: and a5, a1, a5
@@ -38827,15 +38858,15 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: lui a5, 262144
; RV32I-NEXT: and a5, a1, a5
; RV32I-NEXT: seqz s1, a5
-; RV32I-NEXT: slli a7, s7, 29
+; RV32I-NEXT: slli a7, s8, 29
; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: srli a1, a1, 31
-; RV32I-NEXT: slli a6, s7, 30
+; RV32I-NEXT: slli a6, s8, 30
; RV32I-NEXT: and s1, s1, a6
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slli a5, s7, 31
+; RV32I-NEXT: slli a5, s8, 31
; RV32I-NEXT: xor a2, a2, s1
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: xor a0, s0, a0
@@ -38982,62 +39013,62 @@ define void @mul_use_commutative_clmul_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0
; RV32I-NEXT: lw a2, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lw a2, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a2, a2, s7
+; RV32I-NEXT: and a2, a2, s8
; RV32I-NEXT: lw a3, 184(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, s7
-; RV32I-NEXT: lw s7, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 48(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, s8
+; RV32I-NEXT: lw s8, 180(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
+; RV32I-NEXT: and s8, s8, ra
; RV32I-NEXT: xor a1, a2, a1
-; RV32I-NEXT: xor a2, a3, s7
+; RV32I-NEXT: xor a2, a3, s8
; RV32I-NEXT: lw a3, 176(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 40(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, s7
-; RV32I-NEXT: lw s7, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, s8
+; RV32I-NEXT: lw s8, 172(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a3, a3, s7
-; RV32I-NEXT: lw s7, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a3, a3, s8
+; RV32I-NEXT: lw s8, 168(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
+; RV32I-NEXT: and s8, s8, ra
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, a3, s7
+; RV32I-NEXT: xor a2, a3, s8
; RV32I-NEXT: lw a3, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, s7
-; RV32I-NEXT: lw s7, 160(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, s8
+; RV32I-NEXT: lw s8, 160(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a3, a3, s7
-; RV32I-NEXT: lw s7, 156(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a3, a3, s8
+; RV32I-NEXT: lw s8, 156(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a3, a3, s7
-; RV32I-NEXT: lw s7, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a3, a3, s8
+; RV32I-NEXT: lw s8, 148(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
+; RV32I-NEXT: and s8, s8, ra
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a2, a3, s7
+; RV32I-NEXT: xor a2, a3, s8
; RV32I-NEXT: lw a3, 140(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, s7
-; RV32I-NEXT: lw s7, 136(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s8, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, s8
+; RV32I-NEXT: lw s8, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, ra
-; RV32I-NEXT: xor a3, a3, s7
-; RV32I-NEXT: lw s7, 132(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, s11
-; RV32I-NEXT: xor a3, a3, s7
-; RV32I-NEXT: lw s7, 124(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, s10
-; RV32I-NEXT: xor a3, a3, s7
-; RV32I-NEXT: lw s7, 120(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s7, s7, s9
+; RV32I-NEXT: and s8, s8, ra
+; RV32I-NEXT: xor a3, a3, s8
+; RV32I-NEXT: lw s8, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, s11
+; RV32I-NEXT: xor a3, a3, s8
+; RV32I-NEXT: lw s8, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s8, s8, s10
+; RV32I-NEXT: xor a3, a3, s8
+; RV32I-NEXT: lw s8, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s7, s8, s7
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: xor a2, a3, s7
; RV32I-NEXT: lw a3, 116(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, s8
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: lw s7, 112(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s5, s7, s5
; RV32I-NEXT: xor a3, a3, s5
diff --git a/llvm/test/CodeGen/RISCV/clmulh.ll b/llvm/test/CodeGen/RISCV/clmulh.ll
index 256fd68a9dc35..75d32b7f7ed63 100644
--- a/llvm/test/CodeGen/RISCV/clmulh.ll
+++ b/llvm/test/CodeGen/RISCV/clmulh.ll
@@ -1300,9 +1300,11 @@ define i16 @clmulh_i16(i16 %a, i16 %b) nounwind {
define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: clmulh_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui t0, 16
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t1, 16
; RV32I-NEXT: srli a3, a0, 8
-; RV32I-NEXT: addi a2, t0, -256
+; RV32I-NEXT: addi a2, t1, -256
; RV32I-NEXT: and a3, a3, a2
; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: and a5, a0, a2
@@ -1324,248 +1326,248 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: and a4, a4, a3
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a4, a4, 2
-; RV32I-NEXT: or a6, a5, a4
-; RV32I-NEXT: srli a7, a6, 1
+; RV32I-NEXT: or a7, a5, a4
+; RV32I-NEXT: srli a6, a7, 1
; RV32I-NEXT: lui a5, 349525
; RV32I-NEXT: addi a4, a5, 1365
-; RV32I-NEXT: srli t1, a1, 8
-; RV32I-NEXT: and a7, a7, a4
-; RV32I-NEXT: and t1, t1, a2
-; RV32I-NEXT: srli t2, a1, 24
-; RV32I-NEXT: and t3, a1, a2
-; RV32I-NEXT: slli t3, t3, 8
+; RV32I-NEXT: srli t0, a1, 8
+; RV32I-NEXT: and t2, a6, a4
+; RV32I-NEXT: and t0, t0, a2
+; RV32I-NEXT: srli t3, a1, 24
+; RV32I-NEXT: and t4, a1, a2
+; RV32I-NEXT: slli t4, t4, 8
; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or t1, t1, t2
-; RV32I-NEXT: or a1, a1, t3
-; RV32I-NEXT: and a6, a6, a4
-; RV32I-NEXT: or a1, a1, t1
-; RV32I-NEXT: srli t1, a1, 4
+; RV32I-NEXT: or t0, t0, t3
+; RV32I-NEXT: or a1, a1, t4
+; RV32I-NEXT: and a7, a7, a4
+; RV32I-NEXT: or a1, a1, t0
+; RV32I-NEXT: srli t0, a1, 4
; RV32I-NEXT: and a1, a1, a0
-; RV32I-NEXT: and t1, t1, a0
+; RV32I-NEXT: and t0, t0, a0
; RV32I-NEXT: slli a1, a1, 4
-; RV32I-NEXT: slli a6, a6, 1
-; RV32I-NEXT: or a1, t1, a1
-; RV32I-NEXT: srli t1, a1, 2
+; RV32I-NEXT: slli a7, a7, 1
+; RV32I-NEXT: or a1, t0, a1
+; RV32I-NEXT: srli t0, a1, 2
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: and t1, t1, a3
-; RV32I-NEXT: slli t2, a1, 2
-; RV32I-NEXT: or a1, a7, a6
-; RV32I-NEXT: or a6, t1, t2
-; RV32I-NEXT: srli a7, a6, 1
-; RV32I-NEXT: and a6, a6, a4
+; RV32I-NEXT: and t0, t0, a3
+; RV32I-NEXT: slli t3, a1, 2
+; RV32I-NEXT: or a1, t2, a7
+; RV32I-NEXT: or a7, t0, t3
+; RV32I-NEXT: srli t0, a7, 1
; RV32I-NEXT: and a7, a7, a4
-; RV32I-NEXT: slli a6, a6, 1
-; RV32I-NEXT: slli t1, a1, 1
-; RV32I-NEXT: or a7, a7, a6
-; RV32I-NEXT: andi t2, a7, 2
-; RV32I-NEXT: andi t3, a7, 1
-; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: and t0, t0, a4
+; RV32I-NEXT: slli a7, a7, 1
+; RV32I-NEXT: slli t2, a1, 1
+; RV32I-NEXT: or t0, t0, a7
+; RV32I-NEXT: andi t3, t0, 2
+; RV32I-NEXT: andi t4, t0, 1
; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t1, t2, t1
-; RV32I-NEXT: and t2, t3, a1
-; RV32I-NEXT: slli t3, a1, 2
-; RV32I-NEXT: andi t4, a7, 4
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: andi t5, a7, 8
+; RV32I-NEXT: addi t3, t3, -1
; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: and t2, t3, t2
+; RV32I-NEXT: and t3, t4, a1
+; RV32I-NEXT: slli t4, a1, 2
+; RV32I-NEXT: andi t5, t0, 4
; RV32I-NEXT: seqz t5, t5
-; RV32I-NEXT: slli t6, a1, 3
+; RV32I-NEXT: andi t6, t0, 8
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: and t4, t5, t6
-; RV32I-NEXT: xor t1, t2, t1
-; RV32I-NEXT: xor t2, t3, t4
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: andi t2, a7, 16
-; RV32I-NEXT: slli t3, a1, 4
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: andi t4, a7, 32
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, a1, 5
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: andi t4, a7, 64
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, a1, 6
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: andi t4, a7, 128
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: slli s0, a1, 3
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: and t4, t5, t4
+; RV32I-NEXT: and t5, t6, s0
+; RV32I-NEXT: xor t2, t3, t2
+; RV32I-NEXT: xor t3, t4, t5
; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, a1, 7
+; RV32I-NEXT: andi t3, t0, 16
+; RV32I-NEXT: slli t4, a1, 4
+; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: andi t5, t0, 32
; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: andi t4, a7, 256
-; RV32I-NEXT: slli t5, a1, 8
-; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: seqz t4, t5
+; RV32I-NEXT: slli t5, a1, 5
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: andi t6, a7, 512
; RV32I-NEXT: and t4, t4, t5
-; RV32I-NEXT: seqz t5, t6
-; RV32I-NEXT: slli t6, a1, 9
-; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: andi t5, t0, 64
; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: and t4, t5, t6
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: xor t2, t3, t4
-; RV32I-NEXT: slli t3, a1, 10
-; RV32I-NEXT: andi t4, a7, 1024
-; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: li t5, 1
+; RV32I-NEXT: seqz t4, t5
+; RV32I-NEXT: slli t5, a1, 6
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: slli t5, t5, 11
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: and t4, a7, t5
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, a1, 11
-; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: lui t4, 1
-; RV32I-NEXT: slli t5, a1, 12
-; RV32I-NEXT: and t4, a7, t4
-; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: lui t6, 2
+; RV32I-NEXT: and t4, t4, t5
+; RV32I-NEXT: andi t5, t0, 128
+; RV32I-NEXT: xor t3, t3, t4
+; RV32I-NEXT: seqz t4, t5
+; RV32I-NEXT: slli t5, a1, 7
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: and t6, a7, t6
; RV32I-NEXT: and t4, t4, t5
-; RV32I-NEXT: seqz t5, t6
-; RV32I-NEXT: slli t6, a1, 13
+; RV32I-NEXT: andi t5, t0, 256
+; RV32I-NEXT: slli t6, a1, 8
+; RV32I-NEXT: seqz t5, t5
; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: andi s0, t0, 512
+; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: slli s0, a1, 9
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: xor t4, t4, t5
+; RV32I-NEXT: and t5, t6, s0
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: xor t3, t4, t5
+; RV32I-NEXT: slli t4, a1, 10
+; RV32I-NEXT: andi t5, t0, 1024
+; RV32I-NEXT: seqz t5, t5
+; RV32I-NEXT: li t6, 1
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: slli t6, t6, 11
+; RV32I-NEXT: and t4, t5, t4
+; RV32I-NEXT: and t5, t0, t6
; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: and t4, t5, t6
-; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: lui t4, 4
-; RV32I-NEXT: slli t5, a1, 14
-; RV32I-NEXT: and t4, a7, t4
-; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: lui t6, 8
+; RV32I-NEXT: seqz t4, t5
+; RV32I-NEXT: slli t5, a1, 11
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: and t6, a7, t6
; RV32I-NEXT: and t4, t4, t5
-; RV32I-NEXT: seqz t5, t6
-; RV32I-NEXT: slli t6, a1, 15
+; RV32I-NEXT: lui t5, 1
+; RV32I-NEXT: slli t6, a1, 12
+; RV32I-NEXT: and t5, t0, t5
+; RV32I-NEXT: seqz t5, t5
+; RV32I-NEXT: lui s0, 2
; RV32I-NEXT: addi t5, t5, -1
-; RV32I-NEXT: xor t3, t3, t4
-; RV32I-NEXT: and t4, t5, t6
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: xor t2, t3, t4
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: slli t2, a1, 16
-; RV32I-NEXT: and t0, a7, t0
-; RV32I-NEXT: lui t3, 32
-; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: and t3, a7, t3
-; RV32I-NEXT: addi t0, t0, -1
+; RV32I-NEXT: and s0, t0, s0
+; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: slli s0, a1, 13
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: xor t4, t4, t5
+; RV32I-NEXT: and t5, t6, s0
+; RV32I-NEXT: xor t4, t4, t5
+; RV32I-NEXT: lui t5, 4
+; RV32I-NEXT: slli t6, a1, 14
+; RV32I-NEXT: and t5, t0, t5
+; RV32I-NEXT: seqz t5, t5
+; RV32I-NEXT: lui s0, 8
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: and s0, t0, s0
+; RV32I-NEXT: and t5, t5, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: slli s0, a1, 15
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: xor t4, t4, t5
+; RV32I-NEXT: and t5, t6, s0
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: xor t3, t4, t5
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: slli t3, a1, 16
+; RV32I-NEXT: and t1, t0, t1
+; RV32I-NEXT: lui t4, 32
+; RV32I-NEXT: seqz t1, t1
+; RV32I-NEXT: and t4, t0, t4
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: slli t5, a1, 17
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: and t1, t1, t3
+; RV32I-NEXT: and t3, t4, t5
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lui t3, 64
+; RV32I-NEXT: slli t4, a1, 18
+; RV32I-NEXT: and t3, t0, t3
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: lui t5, 128
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: and t5, t0, t5
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: seqz t4, t5
+; RV32I-NEXT: slli t5, a1, 19
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: and t3, t4, t5
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lui t3, 256
+; RV32I-NEXT: slli t4, a1, 20
+; RV32I-NEXT: and t3, t0, t3
; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: slli t4, a1, 17
+; RV32I-NEXT: lui t5, 512
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t0, t0, t2
-; RV32I-NEXT: and t2, t3, t4
-; RV32I-NEXT: xor t0, t0, t2
-; RV32I-NEXT: lui t2, 64
-; RV32I-NEXT: slli t3, a1, 18
-; RV32I-NEXT: and t2, a7, t2
+; RV32I-NEXT: and t5, t0, t5
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: seqz t4, t5
+; RV32I-NEXT: slli t5, a1, 21
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: and t3, t4, t5
+; RV32I-NEXT: xor t1, t1, t3
+; RV32I-NEXT: lui t3, 1024
+; RV32I-NEXT: xor t1, t2, t1
+; RV32I-NEXT: and t2, t0, t3
+; RV32I-NEXT: slli t3, a1, 22
; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: lui t4, 128
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t4, a7, t4
+; RV32I-NEXT: lui t4, 2048
; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: and t3, t0, t4
+; RV32I-NEXT: slli t4, a1, 23
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: lui t5, 4096
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: and t4, t0, t5
+; RV32I-NEXT: xor t2, t2, t3
; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, a1, 19
+; RV32I-NEXT: slli t4, a1, 24
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: xor t0, t0, t2
-; RV32I-NEXT: and t2, t3, t4
-; RV32I-NEXT: xor t0, t0, t2
-; RV32I-NEXT: lui t2, 256
-; RV32I-NEXT: slli t3, a1, 20
-; RV32I-NEXT: and t2, a7, t2
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: lui t4, 512
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t4, a7, t4
-; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: lui t4, 8192
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: and t3, t0, t4
+; RV32I-NEXT: slli t4, a1, 25
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: lui t5, 16384
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: and t4, t0, t5
+; RV32I-NEXT: xor t2, t2, t3
; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: slli t4, a1, 21
+; RV32I-NEXT: slli t4, a1, 26
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: xor t0, t0, t2
-; RV32I-NEXT: and t2, t3, t4
-; RV32I-NEXT: xor t0, t0, t2
-; RV32I-NEXT: lui t2, 1024
-; RV32I-NEXT: xor t0, t1, t0
-; RV32I-NEXT: and t1, a7, t2
-; RV32I-NEXT: slli t2, a1, 22
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: lui t3, 2048
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: and t2, a7, t3
-; RV32I-NEXT: slli t3, a1, 23
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: lui t4, 4096
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: and t3, a7, t4
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 24
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: lui t3, 8192
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: and t2, a7, t3
-; RV32I-NEXT: slli t3, a1, 25
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: lui t4, 16384
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: and t3, a7, t4
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 26
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: lui t3, 32768
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: and t2, a7, t3
-; RV32I-NEXT: slli t3, a1, 27
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: lui t4, 65536
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: and t3, a7, t4
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 28
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: lui t3, 131072
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: and t2, a7, t3
-; RV32I-NEXT: slli t3, a1, 29
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: lui t4, 262144
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: and a7, a7, t4
-; RV32I-NEXT: slli t3, a1, 30
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: lui t4, 32768
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: and t3, t0, t4
+; RV32I-NEXT: slli t4, a1, 27
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: lui t5, 65536
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: and t4, t0, t5
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: slli t4, a1, 28
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: lui t4, 131072
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: and t3, t0, t4
+; RV32I-NEXT: slli t4, a1, 29
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: lui t5, 262144
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: and t0, t0, t5
+; RV32I-NEXT: slli a1, a1, 30
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: addi t0, t0, -1
+; RV32I-NEXT: srli a7, a7, 31
+; RV32I-NEXT: and a1, t0, a1
; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: slli a6, a6, 31
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: srli a6, a6, 31
-; RV32I-NEXT: and a7, a7, t3
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: slli a1, a1, 31
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: xor a7, t2, a7
-; RV32I-NEXT: and a1, a6, a1
-; RV32I-NEXT: xor a6, t0, t1
+; RV32I-NEXT: xor a1, t3, a1
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: xor a7, t1, t2
+; RV32I-NEXT: xor a1, a1, a6
; RV32I-NEXT: xor a1, a7, a1
-; RV32I-NEXT: xor a1, a6, a1
; RV32I-NEXT: srli a6, a1, 8
; RV32I-NEXT: and a6, a6, a2
; RV32I-NEXT: srli a7, a1, 24
@@ -1592,6 +1594,8 @@ define i32 @clmulh_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a0, a0, 1
+; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: clmulh_i32:
@@ -2922,7 +2926,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: sw s11, 236(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a3, 228(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a2, 224(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv t1, a0
+; RV32I-NEXT: mv t5, a0
; RV32I-NEXT: lw a0, 4(a1)
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: lw a3, 8(a1)
@@ -2930,7 +2934,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: lw a3, 12(a1)
; RV32I-NEXT: sw a3, 208(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s4, a2, -256
-; RV32I-NEXT: lui t4, 16
+; RV32I-NEXT: lui t6, 16
; RV32I-NEXT: srli a2, a0, 8
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: and a4, a0, s4
@@ -2957,6 +2961,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: addi s9, a3, 1365
; RV32I-NEXT: srli a2, a0, 1
+; RV32I-NEXT: sw a2, 212(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, s9
; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: slli a0, a0, 1
@@ -2970,10 +2975,10 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a2, a5, a4
-; RV32I-NEXT: lw a4, 4(t1)
-; RV32I-NEXT: lw a5, 8(t1)
+; RV32I-NEXT: lw a4, 4(t5)
+; RV32I-NEXT: lw a5, 8(t5)
; RV32I-NEXT: sw a5, 220(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a5, 12(t1)
+; RV32I-NEXT: lw a5, 12(t5)
; RV32I-NEXT: sw a5, 204(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: srli a2, a0, 4
@@ -3007,255 +3012,255 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: srli a4, a2, 1
; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: and a4, a4, s9
-; RV32I-NEXT: slli s11, a2, 1
+; RV32I-NEXT: slli s10, a2, 1
; RV32I-NEXT: or a5, a5, a0
-; RV32I-NEXT: or a0, a4, s11
-; RV32I-NEXT: srli a2, a5, 1
-; RV32I-NEXT: srli a4, a0, 8
-; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: and a4, a4, s4
-; RV32I-NEXT: srli a6, a0, 24
-; RV32I-NEXT: and a7, a0, s4
+; RV32I-NEXT: or a0, a4, s10
+; RV32I-NEXT: srli a4, a5, 1
+; RV32I-NEXT: srli a2, a0, 8
+; RV32I-NEXT: and a6, a4, s9
+; RV32I-NEXT: and a2, a2, s4
+; RV32I-NEXT: srli a7, a0, 24
+; RV32I-NEXT: and t1, a0, s4
; RV32I-NEXT: slli t2, a0, 24
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: or a4, a4, a6
-; RV32I-NEXT: or a6, t2, a7
+; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: or a2, a2, a7
+; RV32I-NEXT: or a7, t2, t1
; RV32I-NEXT: and a5, a5, s9
-; RV32I-NEXT: or a4, a6, a4
-; RV32I-NEXT: srli a6, a4, 4
-; RV32I-NEXT: and a4, a4, s3
-; RV32I-NEXT: and a6, a6, s3
-; RV32I-NEXT: slli a4, a4, 4
+; RV32I-NEXT: or a2, a7, a2
+; RV32I-NEXT: srli a7, a2, 4
+; RV32I-NEXT: and a2, a2, s3
+; RV32I-NEXT: and a7, a7, s3
+; RV32I-NEXT: slli a2, a2, 4
; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: or a4, a6, a4
-; RV32I-NEXT: srli a6, a4, 2
-; RV32I-NEXT: and a4, a4, s2
-; RV32I-NEXT: and a6, a6, s2
-; RV32I-NEXT: slli a4, a4, 2
-; RV32I-NEXT: or a2, a2, a5
-; RV32I-NEXT: or a4, a6, a4
-; RV32I-NEXT: srli a5, a4, 1
-; RV32I-NEXT: and t2, a4, s9
-; RV32I-NEXT: and a4, a5, s9
+; RV32I-NEXT: or a2, a7, a2
+; RV32I-NEXT: srli a7, a2, 2
+; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: and a7, a7, s2
+; RV32I-NEXT: slli t1, a2, 2
+; RV32I-NEXT: or a2, a6, a5
+; RV32I-NEXT: or a5, a7, t1
+; RV32I-NEXT: srli a6, a5, 1
+; RV32I-NEXT: and t2, a5, s9
+; RV32I-NEXT: and a5, a6, s9
; RV32I-NEXT: slli t2, t2, 1
-; RV32I-NEXT: slli a5, a2, 1
-; RV32I-NEXT: or t3, a4, t2
-; RV32I-NEXT: andi a4, t3, 2
-; RV32I-NEXT: andi a6, t3, 1
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: and a5, a6, a2
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: andi a5, t3, 4
-; RV32I-NEXT: slli a6, a2, 2
+; RV32I-NEXT: slli a6, a2, 1
+; RV32I-NEXT: or t3, a5, t2
+; RV32I-NEXT: andi a5, t3, 2
+; RV32I-NEXT: andi a7, t3, 1
; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: seqz a7, a7
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: andi a7, t3, 8
+; RV32I-NEXT: addi a7, a7, -1
; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, a2, 3
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 16
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, a2, 4
+; RV32I-NEXT: and a6, a7, a2
+; RV32I-NEXT: xor a5, a6, a5
+; RV32I-NEXT: andi a6, t3, 4
+; RV32I-NEXT: slli a7, a2, 2
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: andi t1, t3, 8
; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 32
-; RV32I-NEXT: slli s0, a2, 5
-; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: slli t1, a2, 3
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: andi t1, t3, 16
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: slli t1, a2, 4
; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: andi t1, t3, 32
+; RV32I-NEXT: slli t4, a2, 5
+; RV32I-NEXT: seqz t1, t1
+; RV32I-NEXT: addi t1, t1, -1
; RV32I-NEXT: andi s1, t3, 64
-; RV32I-NEXT: and a7, a7, s0
-; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: and t1, t1, t4
+; RV32I-NEXT: seqz t4, s1
+; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: slli s1, a2, 6
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: xor a7, a7, t1
+; RV32I-NEXT: and t1, t4, s1
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: xor a6, a7, t1
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: slli a6, a2, 7
+; RV32I-NEXT: andi a7, t3, 128
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: andi t1, t3, 256
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: seqz t1, t1
+; RV32I-NEXT: slli t4, a2, 8
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a7, t1, t4
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and s0, s0, s1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: xor a5, a6, s0
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: slli a5, a2, 7
-; RV32I-NEXT: andi a6, t3, 128
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: andi a7, t3, 256
-; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: andi a7, t3, 512
+; RV32I-NEXT: slli t1, a2, 9
; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: slli s0, a2, 8
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: and a6, a7, s0
+; RV32I-NEXT: andi t4, t3, 1024
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: slli t4, a2, 10
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: and a7, t1, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: li a7, 1
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: andi a6, t3, 512
-; RV32I-NEXT: slli a7, a2, 9
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: andi s0, t3, 1024
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, s0
-; RV32I-NEXT: slli s0, a2, 10
+; RV32I-NEXT: slli s1, a7, 11
+; RV32I-NEXT: slli a6, a2, 11
+; RV32I-NEXT: and a7, t3, s1
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: lui t1, 1
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, s0
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: li a6, 1
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: slli t5, a6, 11
-; RV32I-NEXT: slli a5, a2, 11
-; RV32I-NEXT: and a6, t3, t5
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: lui a7, 1
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: slli a7, a2, 12
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 2
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, t3, a7
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui t4, 2
+; RV32I-NEXT: slli t1, a2, 12
+; RV32I-NEXT: and t4, t3, t4
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t1, t1, -1
; RV32I-NEXT: slli a7, a2, 13
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui t6, 4
-; RV32I-NEXT: and a6, a6, a7
+; RV32I-NEXT: lui t4, 4
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: and t1, t3, t4
+; RV32I-NEXT: lui s5, 4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui t4, 8
+; RV32I-NEXT: slli t1, a2, 14
+; RV32I-NEXT: and t4, t3, t4
+; RV32I-NEXT: lui s8, 8
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: slli t4, a2, 15
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: and a7, t1, t4
+; RV32I-NEXT: xor a6, a6, a7
; RV32I-NEXT: and a7, t3, t6
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui t6, 8
-; RV32I-NEXT: slli a7, a2, 14
-; RV32I-NEXT: and s0, t3, t6
+; RV32I-NEXT: lui t1, 32
+; RV32I-NEXT: slli a7, a2, 16
+; RV32I-NEXT: and t1, t3, t1
; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, s0
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli s0, a2, 15
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, s0
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, t3, t4
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: lui a7, 32
-; RV32I-NEXT: slli a6, a2, 16
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: lui s8, 32
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
; RV32I-NEXT: lui t4, 64
-; RV32I-NEXT: slli a7, a2, 17
-; RV32I-NEXT: and s0, t3, t4
-; RV32I-NEXT: lui s5, 64
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, s0
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, a2, 18
+; RV32I-NEXT: slli t1, a2, 17
+; RV32I-NEXT: and t4, t3, t4
+; RV32I-NEXT: lui s6, 64
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: slli a7, a2, 18
; RV32I-NEXT: lui t4, 128
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, t3, t4
-; RV32I-NEXT: lui s1, 128
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui t4, 256
-; RV32I-NEXT: slli a7, a2, 19
-; RV32I-NEXT: and s0, t3, t4
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, s0
-; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: and t1, t3, t4
+; RV32I-NEXT: lui s0, 128
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, a2, 20
+; RV32I-NEXT: lui t4, 256
+; RV32I-NEXT: slli t1, a2, 19
+; RV32I-NEXT: and t4, t3, t4
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: slli a7, a2, 20
; RV32I-NEXT: lui t4, 512
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, t3, t4
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, a2, 21
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 1024
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, t3, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: lui a7, 2048
-; RV32I-NEXT: slli a6, a2, 22
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui t4, 4096
-; RV32I-NEXT: slli a7, a2, 23
-; RV32I-NEXT: and s0, t3, t4
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, s0
-; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: and t1, t3, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, a2, 24
-; RV32I-NEXT: lui t4, 8192
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, t3, t4
+; RV32I-NEXT: slli t1, a2, 21
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 1024
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: and a7, t3, t1
; RV32I-NEXT: xor a5, a5, a6
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui t4, 16384
-; RV32I-NEXT: slli a7, a2, 25
-; RV32I-NEXT: and s0, t3, t4
-; RV32I-NEXT: lui ra, 16384
+; RV32I-NEXT: lui t1, 2048
+; RV32I-NEXT: slli a7, a2, 22
+; RV32I-NEXT: and t1, t3, t1
; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, s0
-; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli a6, a2, 26
-; RV32I-NEXT: lui t4, 32768
-; RV32I-NEXT: and a6, a7, a6
-; RV32I-NEXT: and a7, t3, t4
-; RV32I-NEXT: lui s6, 32768
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui t4, 65536
-; RV32I-NEXT: slli a7, a2, 27
-; RV32I-NEXT: and s0, t3, t4
-; RV32I-NEXT: lui s7, 65536
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: seqz a7, s0
+; RV32I-NEXT: lui t4, 4096
+; RV32I-NEXT: slli t1, a2, 23
+; RV32I-NEXT: and t4, t3, t4
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: slli a7, a2, 24
+; RV32I-NEXT: lui t4, 8192
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: and t1, t3, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: slli s0, a2, 28
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: and a6, a7, s0
+; RV32I-NEXT: lui t4, 16384
+; RV32I-NEXT: slli t1, a2, 25
+; RV32I-NEXT: and t4, t3, t4
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: slli a7, a2, 26
+; RV32I-NEXT: lui t4, 32768
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: and t1, t3, t4
+; RV32I-NEXT: lui ra, 32768
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: lui t4, 65536
+; RV32I-NEXT: slli t1, a2, 27
+; RV32I-NEXT: and t4, t3, t4
+; RV32I-NEXT: lui s11, 65536
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: seqz t1, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: slli a7, a2, 28
+; RV32I-NEXT: lui t4, 131072
+; RV32I-NEXT: and a7, t1, a7
+; RV32I-NEXT: and t1, t3, t4
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: lui a6, 131072
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, t3, a6
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: lui a6, 262144
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, t3, a6
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: slli a7, a2, 29
-; RV32I-NEXT: and a5, a5, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: srli a7, t2, 31
-; RV32I-NEXT: slli t2, a2, 30
-; RV32I-NEXT: and a6, a6, t2
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli a6, a2, 29
+; RV32I-NEXT: lui t1, 262144
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a7, t3, t1
+; RV32I-NEXT: slli a2, a2, 30
; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: slli a2, a2, 31
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: srli t1, t2, 31
; RV32I-NEXT: and a2, a7, a2
-; RV32I-NEXT: xor a2, a5, a2
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: slli a4, a4, 31
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: xor a2, a6, a2
+; RV32I-NEXT: and a4, a7, a4
+; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: xor a2, a4, a2
+; RV32I-NEXT: xor a2, a5, a2
; RV32I-NEXT: srli a4, a2, 8
; RV32I-NEXT: and a4, a4, s4
; RV32I-NEXT: srli a5, a2, 24
@@ -3292,272 +3297,272 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: srli a4, a2, 2
; RV32I-NEXT: and a2, a2, s2
; RV32I-NEXT: and a4, a4, s2
-; RV32I-NEXT: slli a2, a2, 2
-; RV32I-NEXT: srli a5, a1, 1
+; RV32I-NEXT: slli a5, a2, 2
+; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: and a1, a1, s9
-; RV32I-NEXT: and a5, a5, s9
; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: or a4, a4, a2
-; RV32I-NEXT: or a2, a5, a1
-; RV32I-NEXT: addi a3, a3, 1364
-; RV32I-NEXT: sw a3, 232(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a1, a4, 1
-; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: and a3, a4, s9
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: andi a4, a0, 2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: andi a5, a0, 1
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 196(sp) # 4-byte Folded Spill
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 192(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 1
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: and a5, a5, a2
-; RV32I-NEXT: or a1, a1, a3
-; RV32I-NEXT: sw a1, 212(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: andi a1, a0, 4
-; RV32I-NEXT: andi a3, a0, 8
-; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a5, a1, -1
-; RV32I-NEXT: sw a5, 188(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 184(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a2, 2
-; RV32I-NEXT: slli a3, a2, 3
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: and a3, a6, a3
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: andi a3, a0, 16
-; RV32I-NEXT: xor a1, a4, a1
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 180(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a3, a0, 32
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, a2, 4
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 176(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, a2, 5
-; RV32I-NEXT: andi a5, a0, 64
-; RV32I-NEXT: and a3, a6, a3
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 172(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 6
-; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: and a4, a6, a5
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: andi a4, a0, 128
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: seqz a3, a4
-; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 168(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a3, a0, 256
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, a2, 7
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 164(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, a2, 8
-; RV32I-NEXT: andi a5, a0, 512
-; RV32I-NEXT: and a3, a6, a3
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 160(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 9
-; RV32I-NEXT: andi a5, a0, 1024
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 156(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 10
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, a6, a5
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: sw t5, 136(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a0, t5
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: seqz a3, a4
-; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 152(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s10, 1
-; RV32I-NEXT: and a3, a0, s10
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, a2, 11
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 148(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, a2, 12
-; RV32I-NEXT: lui t4, 2
-; RV32I-NEXT: and a5, a0, t4
-; RV32I-NEXT: and a3, a6, a3
+; RV32I-NEXT: and a6, a2, s9
+; RV32I-NEXT: or a4, a4, a5
+; RV32I-NEXT: or a1, a6, a1
+; RV32I-NEXT: addi a5, a3, 1364
+; RV32I-NEXT: sw a5, 232(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a3, a4, 1
+; RV32I-NEXT: and a3, a3, a5
+; RV32I-NEXT: and a4, a4, s9
+; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: andi a5, a0, 2
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: xor a3, a4, a3
+; RV32I-NEXT: andi a6, a0, 1
+; RV32I-NEXT: addi a7, a5, -1
+; RV32I-NEXT: sw a7, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 144(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 13
-; RV32I-NEXT: lui t6, 4
-; RV32I-NEXT: and a5, a0, t6
-; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: sw a6, 192(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 1
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: and a6, a6, a1
+; RV32I-NEXT: or a3, a3, a4
+; RV32I-NEXT: sw a3, 168(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a3, a6, a5
+; RV32I-NEXT: andi a4, a0, 4
+; RV32I-NEXT: andi a5, a0, 8
+; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 140(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 14
-; RV32I-NEXT: lui s0, 8
-; RV32I-NEXT: and a5, a0, s0
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a7, a5, -1
+; RV32I-NEXT: sw a7, 184(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 2
+; RV32I-NEXT: slli a5, a1, 3
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 132(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 15
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: andi a5, a0, 16
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a4, a0, 32
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: slli a5, a1, 4
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: addi a7, a4, -1
+; RV32I-NEXT: sw a7, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 5
+; RV32I-NEXT: andi a6, a0, 64
+; RV32I-NEXT: and a4, a7, a4
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 172(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 6
+; RV32I-NEXT: xor a4, a5, a4
+; RV32I-NEXT: and a5, a7, a6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: andi a5, a0, 128
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lui t2, 16
-; RV32I-NEXT: and a4, a0, t2
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: seqz a3, a4
-; RV32I-NEXT: addi a5, a3, -1
-; RV32I-NEXT: sw a5, 128(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a0, s8
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, a2, 16
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: addi a6, a3, -1
-; RV32I-NEXT: sw a6, 124(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a3, a2, 17
-; RV32I-NEXT: and a5, a0, s5
-; RV32I-NEXT: and a3, a6, a3
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: xor a3, a4, a3
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 120(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 18
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a4, a0, 256
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: slli a5, a1, 7
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: addi a7, a4, -1
+; RV32I-NEXT: sw a7, 160(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 8
+; RV32I-NEXT: andi a6, a0, 512
+; RV32I-NEXT: and a4, a7, a4
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: xor a4, a5, a4
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 156(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 9
+; RV32I-NEXT: andi a6, a0, 1024
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 10
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, a7, a6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: sw s1, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a5, a0, s1
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 116(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 19
-; RV32I-NEXT: lui a5, 256
-; RV32I-NEXT: and a5, a0, a5
-; RV32I-NEXT: lui s1, 256
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 112(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 20
-; RV32I-NEXT: lui a5, 512
-; RV32I-NEXT: and a5, a0, a5
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 108(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 21
-; RV32I-NEXT: lui a5, 1024
-; RV32I-NEXT: and a5, a0, a5
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 104(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a2, 22
-; RV32I-NEXT: lui a5, 2048
-; RV32I-NEXT: and a5, a0, a5
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 100(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 23
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 148(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui t6, 1
+; RV32I-NEXT: and a4, a0, t6
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: slli a5, a1, 11
; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: lui a6, 4096
-; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: addi a7, a4, -1
+; RV32I-NEXT: sw a7, 144(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 12
+; RV32I-NEXT: lui t4, 2
+; RV32I-NEXT: and a6, a0, t4
+; RV32I-NEXT: and a4, a7, a4
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: xor a4, a5, a4
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 13
+; RV32I-NEXT: and a6, a0, s5
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 96(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 24
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: lui a6, 8192
-; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 132(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 14
+; RV32I-NEXT: and a6, a0, s8
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 15
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 92(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 25
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: and a6, a0, ra
+; RV32I-NEXT: and a5, a7, a6
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: addi a6, a5, -1
-; RV32I-NEXT: sw a6, 88(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 26
+; RV32I-NEXT: lui t2, 16
+; RV32I-NEXT: and a5, a0, t2
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 124(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 32
+; RV32I-NEXT: and a4, a0, a4
+; RV32I-NEXT: lui s7, 32
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: slli a5, a1, 16
; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: addi a7, a4, -1
+; RV32I-NEXT: sw a7, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 17
; RV32I-NEXT: and a6, a0, s6
+; RV32I-NEXT: and a4, a7, a4
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: xor a4, a5, a4
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 116(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 18
+; RV32I-NEXT: and a6, a0, s0
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: seqz a5, a6
-; RV32I-NEXT: lw a6, 0(t1)
-; RV32I-NEXT: addi t1, a5, -1
-; RV32I-NEXT: sw t1, 84(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a2, 27
-; RV32I-NEXT: and a7, a0, s7
-; RV32I-NEXT: and a5, t1, a5
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: addi t1, a7, -1
-; RV32I-NEXT: sw t1, 80(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a7, a2, 28
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 19
+; RV32I-NEXT: lui a6, 256
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, t1, a7
-; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 108(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 20
+; RV32I-NEXT: lui a6, 512
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: srli a3, a6, 8
-; RV32I-NEXT: and a5, a6, s4
-; RV32I-NEXT: and a3, a3, s4
-; RV32I-NEXT: slli a5, a5, 8
-; RV32I-NEXT: srli a7, a6, 24
-; RV32I-NEXT: slli a6, a6, 24
-; RV32I-NEXT: or a3, a3, a7
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: sw a1, 64(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a3, a5, a3
-; RV32I-NEXT: lui t3, 131072
-; RV32I-NEXT: and a1, a0, t3
-; RV32I-NEXT: lui a4, 262144
-; RV32I-NEXT: and a0, a0, a4
-; RV32I-NEXT: seqz a1, a1
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: addi a4, a1, -1
-; RV32I-NEXT: sw a4, 72(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a5, a0, -1
-; RV32I-NEXT: sw a5, 68(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, a2, 29
-; RV32I-NEXT: slli a1, a2, 30
-; RV32I-NEXT: and a0, a4, a0
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: srli a4, a3, 4
-; RV32I-NEXT: and a3, a3, s3
-; RV32I-NEXT: and a4, a4, s3
-; RV32I-NEXT: slli a3, a3, 4
-; RV32I-NEXT: xor a1, a0, a1
-; RV32I-NEXT: or a3, a4, a3
-; RV32I-NEXT: srli a0, a3, 2
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 21
+; RV32I-NEXT: lui a6, 1024
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 22
+; RV32I-NEXT: lui a6, 2048
+; RV32I-NEXT: and a6, a0, a6
+; RV32I-NEXT: and a5, a7, a5
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 96(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 23
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: lui a7, 4096
+; RV32I-NEXT: and a7, a0, a7
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 24
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: lui a7, 8192
+; RV32I-NEXT: and a7, a0, a7
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 88(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 25
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: lui a7, 16384
+; RV32I-NEXT: and a7, a0, a7
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: addi a7, a6, -1
+; RV32I-NEXT: sw a7, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 26
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: and a7, a0, ra
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: seqz a6, a7
+; RV32I-NEXT: lw a7, 0(t5)
+; RV32I-NEXT: addi t3, a6, -1
+; RV32I-NEXT: sw t3, 80(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 27
+; RV32I-NEXT: and t1, a0, s11
+; RV32I-NEXT: and a6, t3, a6
+; RV32I-NEXT: seqz t1, t1
+; RV32I-NEXT: addi t3, t1, -1
+; RV32I-NEXT: sw t3, 76(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t1, a1, 28
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: and a6, t3, t1
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: xor a4, a5, a6
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: sw a3, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli a3, a7, 8
+; RV32I-NEXT: and a3, a3, s4
+; RV32I-NEXT: srli a4, a7, 24
+; RV32I-NEXT: or a3, a3, a4
+; RV32I-NEXT: and a4, a7, s4
+; RV32I-NEXT: slli a4, a4, 8
+; RV32I-NEXT: slli a7, a7, 24
+; RV32I-NEXT: or a4, a7, a4
+; RV32I-NEXT: lui t3, 131072
+; RV32I-NEXT: and a5, a0, t3
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a5, a4, -1
+; RV32I-NEXT: sw a5, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 262144
+; RV32I-NEXT: and a0, a0, a4
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: slli a4, a1, 29
+; RV32I-NEXT: slli a1, a1, 30
+; RV32I-NEXT: addi a6, a0, -1
+; RV32I-NEXT: sw a6, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, a5, a4
+; RV32I-NEXT: and a1, a6, a1
+; RV32I-NEXT: srli a4, a3, 4
+; RV32I-NEXT: and a3, a3, s3
+; RV32I-NEXT: and a4, a4, s3
+; RV32I-NEXT: slli a3, a3, 4
+; RV32I-NEXT: xor a1, a0, a1
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: srli a0, a3, 2
; RV32I-NEXT: and a3, a3, s2
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: slli a3, a3, 2
; RV32I-NEXT: or a0, a0, a3
-; RV32I-NEXT: srli a3, s11, 31
+; RV32I-NEXT: srli a3, s10, 31
; RV32I-NEXT: slli a2, a2, 31
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: srli a4, a0, 1
@@ -3565,7 +3570,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a0, a4, s9
; RV32I-NEXT: slli ra, ra, 1
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: sw a3, 76(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a3, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a0, a0, ra
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: andi a3, a0, 2
@@ -3575,11 +3580,11 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli a5, t0, 1
-; RV32I-NEXT: sw a5, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: and a4, a4, t0
; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: sw a1, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: andi a1, a0, 4
; RV32I-NEXT: andi a2, a0, 8
@@ -3588,9 +3593,9 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: slli a4, t0, 2
-; RV32I-NEXT: sw a4, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a5, t0, 3
-; RV32I-NEXT: sw a5, 52(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: xor a1, a1, a2
@@ -3601,17 +3606,17 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: andi a3, a0, 32
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli a4, t0, 4
-; RV32I-NEXT: sw a4, 48(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli a5, t0, 5
-; RV32I-NEXT: sw a5, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a4, a0, 64
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli a5, t0, 6
-; RV32I-NEXT: sw a5, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: and a3, a4, a5
; RV32I-NEXT: xor a2, a2, a3
@@ -3622,53 +3627,53 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: andi a3, a0, 256
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli a4, t0, 7
-; RV32I-NEXT: sw a4, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli a5, t0, 8
-; RV32I-NEXT: sw a5, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a4, a0, 512
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli a5, t0, 9
-; RV32I-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a3, a0, 1024
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli a5, t0, 10
-; RV32I-NEXT: sw a5, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, a0, t5
+; RV32I-NEXT: and a3, a0, s1
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, a0, s10
+; RV32I-NEXT: and a3, a0, t6
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli a4, t0, 11
-; RV32I-NEXT: sw a4, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a4, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli a5, t0, 12
-; RV32I-NEXT: sw a5, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a0, t4
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli a5, t0, 13
-; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a0, t6
+; RV32I-NEXT: sw a5, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a0, s5
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli s11, t0, 14
-; RV32I-NEXT: and a4, a0, s0
+; RV32I-NEXT: and a4, a0, s8
; RV32I-NEXT: and a3, a3, s11
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a4, a4, -1
@@ -3680,26 +3685,26 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, a0, s8
+; RV32I-NEXT: and a3, a0, s7
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli s8, t0, 16
; RV32I-NEXT: and a2, a2, s8
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli s7, t0, 17
-; RV32I-NEXT: and a4, a0, s5
+; RV32I-NEXT: and a4, a0, s6
; RV32I-NEXT: and a3, a3, s7
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi a4, a4, -1
; RV32I-NEXT: slli s6, t0, 18
-; RV32I-NEXT: lui a3, 128
-; RV32I-NEXT: and a3, a0, a3
+; RV32I-NEXT: and a3, a0, s0
; RV32I-NEXT: and a4, a4, s6
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli s5, t0, 19
-; RV32I-NEXT: and a4, a0, s1
+; RV32I-NEXT: lui a4, 256
+; RV32I-NEXT: and a4, a0, a4
; RV32I-NEXT: and a3, a3, s5
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: xor a2, a2, a3
@@ -3776,18 +3781,19 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli ra, t0, 30
; RV32I-NEXT: and a1, a1, ra
; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: lw t3, 212(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli t3, t3, 31
; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: slli t3, t0, 31
; RV32I-NEXT: xor a1, a3, a1
; RV32I-NEXT: and a0, a0, t3
; RV32I-NEXT: xor a2, a6, a2
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: lw a1, 64(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a0, a2, a0
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw a1, 212(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 168(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: xor a0, a1, a0
; RV32I-NEXT: srli a1, a0, 8
@@ -3817,37 +3823,33 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: sw a0, 212(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 196(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lw a1, 192(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, t0
; RV32I-NEXT: lw a2, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: lw a3, 184(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 52(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: xor a0, a1, a0
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: lw a1, 180(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 48(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: lw a3, 176(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: lw a3, 172(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a2, 168(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 164(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: lw a3, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, a6
-; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: lw a3, 160(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a6
@@ -3855,70 +3857,74 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: lw a3, 156(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a6
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: lw a3, 152(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a6, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a1, 152(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a3, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: lw a3, 148(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a6, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, a6
-; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: lw a3, 144(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a6, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: lw a3, 140(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a3, a3, s11
+; RV32I-NEXT: lw a6, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: lw a3, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a3, a3, s11
+; RV32I-NEXT: xor a1, a1, a3
+; RV32I-NEXT: lw a3, 128(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, s10
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a2, 128(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 124(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, s8
-; RV32I-NEXT: lw a3, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 120(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, s7
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a3, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 116(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, s6
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a3, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 112(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, s5
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a3, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, s1
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a3, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, s0
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lw a1, 104(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 100(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, t6
-; RV32I-NEXT: lw a3, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 96(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, t5
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 96(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 92(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, t4
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 88(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, t2
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 84(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, t1
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 80(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a3, 80(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: lw a2, 72(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 68(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: lw a3, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 64(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, ra
-; RV32I-NEXT: xor t4, a0, a1
+; RV32I-NEXT: xor t5, a0, a1
; RV32I-NEXT: xor a1, a2, a3
; RV32I-NEXT: lw a4, 208(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a0, a4, 8
@@ -3929,7 +3935,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli a4, a4, 24
; RV32I-NEXT: or a3, a0, a3
; RV32I-NEXT: or a2, a4, a2
-; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a0, a0, t3
; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: lw a6, 204(sp) # 4-byte Folded Reload
@@ -3958,37 +3964,38 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a2, a4, a2
; RV32I-NEXT: or a5, a5, a3
; RV32I-NEXT: srli a3, a2, 1
+; RV32I-NEXT: sw a3, 208(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: slli a2, a2, 1
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: or a3, a3, a2
; RV32I-NEXT: srli a2, a5, 2
; RV32I-NEXT: and a2, a2, s2
-; RV32I-NEXT: and a4, a5, s2
-; RV32I-NEXT: slli a4, a4, 2
-; RV32I-NEXT: srli a5, a3, 8
-; RV32I-NEXT: or a2, a2, a4
-; RV32I-NEXT: and a4, a5, s4
+; RV32I-NEXT: and a5, a5, s2
+; RV32I-NEXT: slli a5, a5, 2
+; RV32I-NEXT: srli a4, a3, 8
+; RV32I-NEXT: or a2, a2, a5
+; RV32I-NEXT: and a4, a4, s4
; RV32I-NEXT: srli a5, a2, 1
; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: and a5, a5, s9
; RV32I-NEXT: slli a2, a2, 1
-; RV32I-NEXT: sw a2, 204(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or t1, a5, a2
+; RV32I-NEXT: sw a2, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or t2, a5, a2
; RV32I-NEXT: srli a2, a3, 24
; RV32I-NEXT: or a2, a4, a2
-; RV32I-NEXT: srli a4, t1, 8
+; RV32I-NEXT: srli a4, t2, 8
; RV32I-NEXT: and a4, a4, s4
-; RV32I-NEXT: srli a5, t1, 24
+; RV32I-NEXT: srli a5, t2, 24
; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: and a5, t1, s4
+; RV32I-NEXT: and a5, t2, s4
; RV32I-NEXT: slli a5, a5, 8
-; RV32I-NEXT: slli a6, t1, 24
+; RV32I-NEXT: slli a6, t2, 24
; RV32I-NEXT: or a5, a6, a5
; RV32I-NEXT: and a6, a3, s4
; RV32I-NEXT: slli a6, a6, 8
; RV32I-NEXT: slli a7, a3, 24
-; RV32I-NEXT: sw a7, 208(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a7, 204(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a4, a5, a4
; RV32I-NEXT: or a5, a7, a6
; RV32I-NEXT: srli a6, a4, 4
@@ -4014,227 +4021,227 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a5, a5, a2
; RV32I-NEXT: srli a2, a4, 1
; RV32I-NEXT: and a6, a2, s9
-; RV32I-NEXT: and a2, a4, s9
-; RV32I-NEXT: slli a2, a2, 1
-; RV32I-NEXT: srli a4, a5, 1
; RV32I-NEXT: and a4, a4, s9
-; RV32I-NEXT: or t3, a6, a2
+; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: srli a2, a5, 1
; RV32I-NEXT: and a5, a5, s9
-; RV32I-NEXT: andi a6, t3, 2
+; RV32I-NEXT: or t3, a6, a4
; RV32I-NEXT: slli a5, a5, 1
+; RV32I-NEXT: andi a6, t3, 2
; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: or t2, a4, a5
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a4, t2, 1
-; RV32I-NEXT: andi a5, t3, 1
-; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: andi a6, t3, 4
-; RV32I-NEXT: and a5, a5, t2
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 2
-; RV32I-NEXT: andi a7, t3, 8
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 3
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 16
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 4
-; RV32I-NEXT: andi a7, t3, 32
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 5
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 64
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 6
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 128
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a7, a2, s9
+; RV32I-NEXT: or t4, a7, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 7
-; RV32I-NEXT: andi a7, t3, 256
+; RV32I-NEXT: slli a5, t4, 1
+; RV32I-NEXT: andi a7, t3, 1
; RV32I-NEXT: and a5, a6, a5
; RV32I-NEXT: seqz a6, a7
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 8
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 512
+; RV32I-NEXT: andi a7, t3, 4
+; RV32I-NEXT: and a6, a6, t4
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: xor a5, a6, a5
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli a6, t4, 2
+; RV32I-NEXT: andi t1, t3, 8
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 3
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: andi t1, t3, 16
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 9
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: andi a7, t3, 1024
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli a6, t4, 4
+; RV32I-NEXT: andi t1, t3, 32
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 5
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: andi t1, t3, 64
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 6
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: andi t1, t3, 128
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 10
-; RV32I-NEXT: and a6, a6, a7
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli a6, t4, 7
+; RV32I-NEXT: andi t1, t3, 256
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 8
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: andi t1, t3, 512
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 9
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: andi t1, t3, 1024
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 10
+; RV32I-NEXT: and a7, a7, t1
; RV32I-NEXT: lw t0, 136(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a7, t3, t0
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 11
-; RV32I-NEXT: lui ra, 1
-; RV32I-NEXT: and a7, t3, ra
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 12
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 2
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 13
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 4
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 14
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 8
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 15
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui s10, 16
-; RV32I-NEXT: and a7, t3, s10
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 16
-; RV32I-NEXT: lui s11, 32
-; RV32I-NEXT: and a7, t3, s11
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 17
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui t5, 64
-; RV32I-NEXT: and a7, t3, t5
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 18
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui t6, 128
-; RV32I-NEXT: and a7, t3, t6
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 19
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui s0, 256
-; RV32I-NEXT: and a7, t3, s0
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 20
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui s1, 512
-; RV32I-NEXT: and a7, t3, s1
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 21
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui s5, 1024
-; RV32I-NEXT: and a7, t3, s5
+; RV32I-NEXT: and t1, t3, t0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a5, t2, 22
-; RV32I-NEXT: lui s6, 2048
-; RV32I-NEXT: and a7, t3, s6
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 23
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui s7, 4096
-; RV32I-NEXT: and a7, t3, s7
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli a6, t4, 11
+; RV32I-NEXT: lui t1, 1
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 12
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 2
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 13
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 4
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 14
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t6, 8
+; RV32I-NEXT: and t1, t3, t6
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 15
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 16
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 24
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui s8, 8192
-; RV32I-NEXT: and a7, t3, s8
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli a6, t4, 16
+; RV32I-NEXT: lui s1, 32
+; RV32I-NEXT: and t1, t3, s1
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 17
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui s0, 64
+; RV32I-NEXT: and t1, t3, s0
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 18
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui s5, 128
+; RV32I-NEXT: and t1, t3, s5
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 19
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui s6, 256
+; RV32I-NEXT: and t1, t3, s6
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 20
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui s7, 512
+; RV32I-NEXT: and t1, t3, s7
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 21
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui s8, 1024
+; RV32I-NEXT: and t1, t3, s8
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 25
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 16384
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 26
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 32768
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 27
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 65536
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a7, t2, 28
-; RV32I-NEXT: and a6, a6, a7
-; RV32I-NEXT: lui a7, 131072
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: xor a5, a5, a6
-; RV32I-NEXT: seqz a6, a7
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: lui a7, 262144
-; RV32I-NEXT: and a7, t3, a7
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: slli t3, t2, 29
-; RV32I-NEXT: and a6, a6, t3
; RV32I-NEXT: addi a7, a7, -1
-; RV32I-NEXT: srli a2, a2, 31
-; RV32I-NEXT: slli t3, t2, 30
-; RV32I-NEXT: and a7, a7, t3
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: slli t2, t2, 31
-; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: slli a6, t4, 22
+; RV32I-NEXT: lui s11, 2048
+; RV32I-NEXT: and t1, t3, s11
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 23
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui ra, 4096
+; RV32I-NEXT: and t1, t3, ra
; RV32I-NEXT: xor a6, a6, a7
-; RV32I-NEXT: and a2, a2, t2
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: xor a2, a6, a2
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 24
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui s10, 8192
+; RV32I-NEXT: and t1, t3, s10
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 25
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 16384
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 26
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 32768
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 27
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 65536
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 28
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 131072
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: xor a6, a6, a7
+; RV32I-NEXT: seqz a7, t1
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: slli t1, t4, 29
+; RV32I-NEXT: and a7, a7, t1
+; RV32I-NEXT: lui t1, 262144
+; RV32I-NEXT: and t1, t3, t1
+; RV32I-NEXT: slli t4, t4, 30
+; RV32I-NEXT: seqz t1, t1
+; RV32I-NEXT: addi t1, t1, -1
+; RV32I-NEXT: srli a4, a4, 31
+; RV32I-NEXT: and t1, t1, t4
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: slli a2, a2, 31
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: xor a7, a7, t1
+; RV32I-NEXT: and a2, a4, a2
+; RV32I-NEXT: xor a4, a5, a6
+; RV32I-NEXT: xor a2, a7, a2
; RV32I-NEXT: xor a0, a1, a0
; RV32I-NEXT: xor a2, a4, a2
-; RV32I-NEXT: xor a4, t4, a0
-; RV32I-NEXT: sw a4, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a4, t5, a0
+; RV32I-NEXT: sw a4, 192(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a0, a2, 8
; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: srli a1, a2, 24
@@ -4247,7 +4254,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a2, a2, s4
; RV32I-NEXT: srli a4, a4, 24
; RV32I-NEXT: or a2, a2, a4
-; RV32I-NEXT: sw a2, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a2, 196(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: lw a5, 216(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a1, a5, 8
@@ -4274,354 +4281,356 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a4, a1
-; RV32I-NEXT: srli a2, a1, 2
-; RV32I-NEXT: and a1, a1, s2
-; RV32I-NEXT: and a2, a2, s2
-; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a0, 1
+; RV32I-NEXT: and a0, a0, s9
; RV32I-NEXT: lw a4, 232(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: and a0, a0, s9
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: srli a4, a1, 1
+; RV32I-NEXT: srli a4, a1, 2
+; RV32I-NEXT: and a1, a1, s2
+; RV32I-NEXT: and a4, a4, s2
+; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a0, a2, a0
-; RV32I-NEXT: sw a0, 172(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a0, a4, s9
+; RV32I-NEXT: sw a0, 168(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a1, a4, a1
+; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: and a1, a1, s9
-; RV32I-NEXT: andi a2, t1, 2
; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: andi a2, t2, 2
; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 216(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a0, 1
-; RV32I-NEXT: andi a2, t1, 1
-; RV32I-NEXT: and a1, a4, a1
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: sw a4, 192(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a2, t1, 4
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: and a4, a4, a0
-; RV32I-NEXT: xor a1, a4, a1
+; RV32I-NEXT: and a4, a0, s9
+; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: addi a5, a2, -1
-; RV32I-NEXT: sw a5, 188(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, a0, 2
-; RV32I-NEXT: andi a4, t1, 8
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 184(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 3
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: andi a5, t1, 16
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 180(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, a0, 4
-; RV32I-NEXT: andi a4, t1, 32
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 176(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 5
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: andi a5, t1, 64
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 168(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 6
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: andi a5, t1, 128
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 164(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, a0, 7
-; RV32I-NEXT: andi a4, t1, 256
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 160(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 8
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: andi a5, t1, 512
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 156(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 9
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: andi a5, t1, 1024
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 152(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 10
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, t1, t0
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 148(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, a0, 11
-; RV32I-NEXT: and a4, t1, ra
-; RV32I-NEXT: lui t3, 1
-; RV32I-NEXT: and a2, a5, a2
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 144(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 12
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: lui a5, 2
-; RV32I-NEXT: and a5, t1, a5
-; RV32I-NEXT: lui t2, 2
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 140(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 13
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: lui a5, 4
-; RV32I-NEXT: and a5, t1, a5
-; RV32I-NEXT: lui t4, 4
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 132(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 14
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: lui a5, 8
-; RV32I-NEXT: and a5, t1, a5
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 128(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 15
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, t1, s10
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 124(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, a0, 16
-; RV32I-NEXT: and a4, t1, s11
-; RV32I-NEXT: lui s10, 32
+; RV32I-NEXT: sw a5, 216(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a2, a1, 1
+; RV32I-NEXT: andi a4, t2, 1
; RV32I-NEXT: and a2, a5, a2
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 120(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 17
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, t1, t5
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 116(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 18
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, t1, t6
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 112(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 19
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, t1, s0
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 108(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 20
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, t1, s1
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a5, a4, -1
-; RV32I-NEXT: sw a5, 104(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 21
-; RV32I-NEXT: and a4, a5, a4
-; RV32I-NEXT: and a5, t1, s5
-; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 100(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, t1, s6
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: slli a5, a0, 22
-; RV32I-NEXT: and a5, a6, a5
-; RV32I-NEXT: addi a7, a4, -1
-; RV32I-NEXT: sw a7, 96(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a4, a0, 23
-; RV32I-NEXT: and a6, t1, s7
-; RV32I-NEXT: and a4, a7, a4
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 92(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a0, 24
-; RV32I-NEXT: and a6, t1, s8
-; RV32I-NEXT: and a5, a7, a5
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 88(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a0, 25
-; RV32I-NEXT: lui a6, 16384
-; RV32I-NEXT: and a6, t1, a6
-; RV32I-NEXT: and a5, a7, a5
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 84(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a0, 26
-; RV32I-NEXT: lui a6, 32768
-; RV32I-NEXT: and a6, t1, a6
-; RV32I-NEXT: and a5, a7, a5
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 80(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a5, a0, 27
-; RV32I-NEXT: lui a6, 65536
-; RV32I-NEXT: and a6, t1, a6
-; RV32I-NEXT: and a5, a7, a5
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a7, a6, -1
-; RV32I-NEXT: sw a7, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a0, 28
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, a7, a6
-; RV32I-NEXT: xor a1, a1, a2
-; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a7, 220(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a2, a7, 8
-; RV32I-NEXT: and a5, a7, s4
-; RV32I-NEXT: and a2, a2, s4
-; RV32I-NEXT: slli a5, a5, 8
-; RV32I-NEXT: srli a6, a7, 24
-; RV32I-NEXT: slli a7, a7, 24
-; RV32I-NEXT: or a2, a2, a6
-; RV32I-NEXT: or a5, a7, a5
-; RV32I-NEXT: xor a1, a1, a4
-; RV32I-NEXT: sw a1, 64(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a2, a5, a2
-; RV32I-NEXT: lui a7, 131072
-; RV32I-NEXT: and a1, t1, a7
-; RV32I-NEXT: lui a4, 262144
-; RV32I-NEXT: and a4, t1, a4
-; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: sw a5, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a4, t2, 4
; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a5, a1, -1
-; RV32I-NEXT: sw a5, 220(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a5, a1
+; RV32I-NEXT: xor a2, a5, a2
; RV32I-NEXT: addi a6, a4, -1
-; RV32I-NEXT: sw a6, 72(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, a0, 29
-; RV32I-NEXT: slli a4, a0, 30
-; RV32I-NEXT: and a1, a5, a1
+; RV32I-NEXT: sw a6, 184(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 2
+; RV32I-NEXT: andi a5, t2, 8
; RV32I-NEXT: and a4, a6, a4
-; RV32I-NEXT: srli a5, a2, 4
-; RV32I-NEXT: and a2, a2, s3
-; RV32I-NEXT: and a5, a5, s3
-; RV32I-NEXT: slli a2, a2, 4
-; RV32I-NEXT: xor a4, a1, a4
-; RV32I-NEXT: or a2, a5, a2
-; RV32I-NEXT: srli a1, a2, 2
-; RV32I-NEXT: and a2, a2, s2
-; RV32I-NEXT: and a1, a1, s2
-; RV32I-NEXT: slli a2, a2, 2
-; RV32I-NEXT: or a1, a1, a2
-; RV32I-NEXT: lw a2, 204(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a2, a2, 31
-; RV32I-NEXT: slli a5, a0, 31
-; RV32I-NEXT: seqz a0, a2
-; RV32I-NEXT: srli a2, a1, 1
-; RV32I-NEXT: and a1, a1, s9
-; RV32I-NEXT: and a2, a2, s9
-; RV32I-NEXT: slli ra, a1, 1
-; RV32I-NEXT: addi a1, a0, -1
-; RV32I-NEXT: sw a1, 204(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a0, a2, ra
-; RV32I-NEXT: and a2, a1, a5
-; RV32I-NEXT: andi a5, a0, 2
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: andi a6, a0, 1
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a1, a3, 1
-; RV32I-NEXT: sw a1, 68(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: and a6, a6, a3
-; RV32I-NEXT: xor a2, a4, a2
-; RV32I-NEXT: sw a2, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a2, a6, a5
-; RV32I-NEXT: andi a4, a0, 4
-; RV32I-NEXT: andi a5, a0, 8
-; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a1, a3, 2
-; RV32I-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a6, a3, 3
-; RV32I-NEXT: sw a6, 56(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a1
-; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 3
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: andi a6, t2, 16
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: andi a5, a0, 16
+; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: andi a5, a0, 32
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 4
+; RV32I-NEXT: andi a5, t2, 32
+; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli a1, a3, 4
-; RV32I-NEXT: sw a1, 52(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a4, a4, a1
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: slli a1, a3, 5
-; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi a6, a0, 64
-; RV32I-NEXT: and a5, a5, a1
-; RV32I-NEXT: seqz a6, a6
-; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: slli a1, a3, 6
-; RV32I-NEXT: sw a1, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 172(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 5
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: andi a6, t2, 64
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: and a5, a6, a1
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 6
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: andi a6, t2, 128
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: andi a5, a0, 128
+; RV32I-NEXT: seqz a5, a6
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: seqz a4, a5
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: andi a5, a0, 256
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 160(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 7
+; RV32I-NEXT: andi a5, t2, 256
+; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli a1, a3, 7
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 156(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 8
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: andi a6, t2, 512
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 9
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: andi a6, t2, 1024
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 148(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 10
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t2, t0
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 144(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 11
+; RV32I-NEXT: lui a5, 1
+; RV32I-NEXT: and a5, t2, a5
+; RV32I-NEXT: lui t1, 1
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 12
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: lui a6, 2
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: lui t3, 2
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 132(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 13
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: lui a6, 4
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: lui t5, 4
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 14
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t2, t6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 124(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 15
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: lui a6, 16
+; RV32I-NEXT: and a6, t2, a6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a4, a1, 16
+; RV32I-NEXT: and a5, t2, s1
+; RV32I-NEXT: and a4, a6, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 116(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 17
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t2, s0
+; RV32I-NEXT: lui t4, 64
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 18
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t2, s5
+; RV32I-NEXT: lui s0, 128
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 108(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 19
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t2, s6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 20
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t2, s7
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a6, a5, -1
+; RV32I-NEXT: sw a6, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 21
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: and a6, t2, s8
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: seqz a5, a6
+; RV32I-NEXT: addi a7, a5, -1
+; RV32I-NEXT: sw a7, 96(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, t2, s11
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: slli a6, a1, 22
+; RV32I-NEXT: and a6, a7, a6
+; RV32I-NEXT: addi s5, a5, -1
+; RV32I-NEXT: sw s5, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a5, a1, 23
+; RV32I-NEXT: and a7, t2, ra
+; RV32I-NEXT: and a5, s5, a5
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: xor a5, a6, a5
+; RV32I-NEXT: addi s5, a7, -1
+; RV32I-NEXT: sw s5, 88(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 24
+; RV32I-NEXT: and a7, t2, s10
+; RV32I-NEXT: and a6, s5, a6
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: addi s5, a7, -1
+; RV32I-NEXT: sw s5, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 25
+; RV32I-NEXT: lui a7, 16384
+; RV32I-NEXT: and a7, t2, a7
+; RV32I-NEXT: and a6, s5, a6
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: addi s5, a7, -1
+; RV32I-NEXT: sw s5, 80(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 26
+; RV32I-NEXT: lui a7, 32768
+; RV32I-NEXT: and a7, t2, a7
+; RV32I-NEXT: and a6, s5, a6
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: addi s5, a7, -1
+; RV32I-NEXT: sw s5, 76(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a1, 27
+; RV32I-NEXT: lui a7, 65536
+; RV32I-NEXT: and a7, t2, a7
+; RV32I-NEXT: and a6, s5, a6
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: addi s5, a7, -1
+; RV32I-NEXT: sw s5, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a7, a1, 28
+; RV32I-NEXT: xor a5, a5, a6
+; RV32I-NEXT: and a6, s5, a7
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: xor a4, a5, a6
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: sw a2, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a5, 220(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a2, a5, 8
+; RV32I-NEXT: and a2, a2, s4
+; RV32I-NEXT: srli a4, a5, 24
+; RV32I-NEXT: or a2, a2, a4
+; RV32I-NEXT: and a4, a5, s4
+; RV32I-NEXT: slli a4, a4, 8
+; RV32I-NEXT: slli a5, a5, 24
+; RV32I-NEXT: or a4, a5, a4
+; RV32I-NEXT: lui a7, 131072
+; RV32I-NEXT: and a5, t2, a7
+; RV32I-NEXT: or a2, a4, a2
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a6, a4, -1
+; RV32I-NEXT: sw a6, 220(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a4, 262144
+; RV32I-NEXT: and a4, t2, a4
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: slli a5, a1, 29
+; RV32I-NEXT: slli a1, a1, 30
+; RV32I-NEXT: addi t2, a4, -1
+; RV32I-NEXT: sw t2, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a6, a5
+; RV32I-NEXT: and a1, t2, a1
+; RV32I-NEXT: srli a5, a2, 4
+; RV32I-NEXT: and a2, a2, s3
+; RV32I-NEXT: and a5, a5, s3
+; RV32I-NEXT: slli a2, a2, 4
+; RV32I-NEXT: xor a4, a4, a1
+; RV32I-NEXT: or a2, a5, a2
+; RV32I-NEXT: srli a1, a2, 2
+; RV32I-NEXT: and a2, a2, s2
+; RV32I-NEXT: and a1, a1, s2
+; RV32I-NEXT: slli a2, a2, 2
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: lw a2, 200(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a2, a2, 31
+; RV32I-NEXT: slli a5, a0, 31
+; RV32I-NEXT: seqz a0, a2
+; RV32I-NEXT: srli a2, a1, 1
+; RV32I-NEXT: and a1, a1, s9
+; RV32I-NEXT: and a2, a2, s9
+; RV32I-NEXT: slli ra, a1, 1
+; RV32I-NEXT: addi a1, a0, -1
+; RV32I-NEXT: sw a1, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a0, a2, ra
+; RV32I-NEXT: and a2, a1, a5
+; RV32I-NEXT: andi a5, a0, 2
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: andi a6, a0, 1
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a1, a3, 1
+; RV32I-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a5, a5, a1
+; RV32I-NEXT: and a6, a6, a3
+; RV32I-NEXT: xor a2, a4, a2
+; RV32I-NEXT: sw a2, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a2, a6, a5
+; RV32I-NEXT: andi a4, a0, 4
+; RV32I-NEXT: andi a5, a0, 8
+; RV32I-NEXT: seqz a4, a4
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: slli a1, a3, 2
+; RV32I-NEXT: sw a1, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a6, a3, 3
+; RV32I-NEXT: sw a6, 52(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a4, a1
+; RV32I-NEXT: and a5, a5, a6
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: andi a5, a0, 16
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a5, a0, 32
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: slli a1, a3, 4
+; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a4, a4, a1
+; RV32I-NEXT: addi a5, a5, -1
+; RV32I-NEXT: slli a1, a3, 5
+; RV32I-NEXT: sw a1, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a6, a0, 64
+; RV32I-NEXT: and a5, a5, a1
+; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: addi a6, a6, -1
+; RV32I-NEXT: slli a1, a3, 6
; RV32I-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: and a5, a6, a1
+; RV32I-NEXT: xor a4, a4, a5
+; RV32I-NEXT: andi a5, a0, 128
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: seqz a4, a5
+; RV32I-NEXT: addi a4, a4, -1
+; RV32I-NEXT: andi a5, a0, 256
+; RV32I-NEXT: seqz a5, a5
+; RV32I-NEXT: slli a1, a3, 7
+; RV32I-NEXT: sw a1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a4, a1
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: slli a1, a3, 8
-; RV32I-NEXT: sw a1, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a6, a0, 512
; RV32I-NEXT: and a5, a5, a1
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: addi a6, a6, -1
; RV32I-NEXT: slli a1, a3, 9
-; RV32I-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a5, a0, 1024
; RV32I-NEXT: and a6, a6, a1
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: addi a5, a5, -1
; RV32I-NEXT: slli a1, a3, 10
-; RV32I-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a4, a4, a6
; RV32I-NEXT: and a5, a5, a1
; RV32I-NEXT: xor a4, a4, a5
@@ -4629,30 +4638,29 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a5, a0, t3
+; RV32I-NEXT: and a5, a0, t1
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: slli a1, a3, 11
; RV32I-NEXT: sw a1, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a4, a4, a1
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, a0, t2
+; RV32I-NEXT: and a6, a0, t3
; RV32I-NEXT: slli a1, a3, 12
-; RV32I-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a5, a5, a1
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a5, a0, t4
+; RV32I-NEXT: and a5, a0, t5
; RV32I-NEXT: slli a1, a3, 13
-; RV32I-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a6, a6, a1
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a4, a4, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: lui a1, 8
-; RV32I-NEXT: and a6, a0, a1
+; RV32I-NEXT: and a6, a0, t6
; RV32I-NEXT: slli a1, a3, 14
-; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a5, a5, a1
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: addi a6, a6, -1
@@ -4665,30 +4673,32 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: seqz a4, a5
; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: and a5, a0, s10
+; RV32I-NEXT: and a5, a0, s1
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: slli s8, a3, 16
; RV32I-NEXT: and a4, a4, s8
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, a0, t5
+; RV32I-NEXT: and a6, a0, t4
; RV32I-NEXT: slli s7, a3, 17
; RV32I-NEXT: and a5, a5, s7
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a5, a0, t6
+; RV32I-NEXT: and a5, a0, s0
; RV32I-NEXT: slli s6, a3, 18
; RV32I-NEXT: and a6, a6, s6
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a4, a4, a6
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: and a6, a0, s0
+; RV32I-NEXT: lui a1, 256
+; RV32I-NEXT: and a6, a0, a1
; RV32I-NEXT: slli s5, a3, 19
; RV32I-NEXT: and a5, a5, s5
; RV32I-NEXT: seqz a6, a6
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: and a5, a0, s1
+; RV32I-NEXT: lui a5, 512
+; RV32I-NEXT: and a5, a0, a5
; RV32I-NEXT: slli s1, a3, 20
; RV32I-NEXT: and a6, a6, s1
; RV32I-NEXT: seqz a5, a5
@@ -4715,7 +4725,7 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: lw t4, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t4, 204(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a5, t4
; RV32I-NEXT: lui a5, 8192
; RV32I-NEXT: and a5, a0, a5
@@ -4755,31 +4765,32 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: slli a7, a3, 29
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: srli a4, ra, 31
+; RV32I-NEXT: srli a5, ra, 31
; RV32I-NEXT: slli a6, a3, 30
-; RV32I-NEXT: and a0, a0, a6
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: addi a4, a4, -1
-; RV32I-NEXT: slli a5, a3, 31
-; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: xor a1, s10, a2
-; RV32I-NEXT: xor a0, a0, a4
-; RV32I-NEXT: lw a2, 64(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: and a4, a0, a6
+; RV32I-NEXT: seqz a0, a5
+; RV32I-NEXT: lw a5, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli a5, a5, 31
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: xor a2, s10, a2
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: lw a1, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a1, 64(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a1, a1, a4
+; RV32I-NEXT: xor a0, a2, a0
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: lw a1, 168(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: lw a2, 196(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 192(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a2, s4
; RV32I-NEXT: slli a2, a2, 24
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a0, 8
-; RV32I-NEXT: lw a4, 200(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 196(sp) # 4-byte Folded Reload
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: and a2, a2, s4
; RV32I-NEXT: srli a4, a0, 24
@@ -4805,53 +4816,49 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or s10, a2, a1
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: lw a1, 216(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a2, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: lw a2, 192(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 188(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: lw a3, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
-; RV32I-NEXT: lw a4, 184(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, ra
; RV32I-NEXT: xor a1, a2, a1
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a2, 180(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 52(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 176(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: lw a4, 176(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 48(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, ra
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 168(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 164(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, ra
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a3, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 160(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
-; RV32I-NEXT: lw a4, 160(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, ra
-; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: lw a4, 156(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, ra
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: lw a4, 152(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, ra
+; RV32I-NEXT: xor a3, a3, a4
+; RV32I-NEXT: lw a4, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, ra
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a2, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 144(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw a4, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: lw a4, 144(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and a4, a4, ra
-; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: lw a4, 140(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, ra
@@ -4861,64 +4868,68 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a4, a4, ra
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: lw a4, 128(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a4, a4, ra
+; RV32I-NEXT: xor a2, a2, a4
+; RV32I-NEXT: lw a4, 124(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s11
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a3, 124(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 120(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, s8
-; RV32I-NEXT: lw a4, 120(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 116(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s7
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 116(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 112(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s6
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s5
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s1
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 104(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 100(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s0
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a2, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 96(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, t6
-; RV32I-NEXT: lw a4, 96(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 92(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t5
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 88(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t4
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 84(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t3
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 80(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t2
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 80(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t1
; RV32I-NEXT: xor a2, a2, a4
-; RV32I-NEXT: lw a4, 76(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t0
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: xor a2, a2, a4
; RV32I-NEXT: lw a3, 220(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a7
-; RV32I-NEXT: lw a4, 72(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 68(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a2, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a2, 200(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: xor a2, a3, a2
-; RV32I-NEXT: and a3, a4, s2
+; RV32I-NEXT: and a4, a4, s2
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: srli a2, a1, 8
-; RV32I-NEXT: or a0, a3, a0
+; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: and a2, a2, s4
; RV32I-NEXT: srli a3, a1, 24
; RV32I-NEXT: and a4, a1, s4
@@ -5009,26 +5020,26 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: mv a7, a3
; RV64I-NEXT: mv t5, a1
; RV64I-NEXT: srli a1, a2, 24
-; RV64I-NEXT: lui s4, 4080
-; RV64I-NEXT: and a1, a1, s4
+; RV64I-NEXT: lui s5, 4080
+; RV64I-NEXT: and a1, a1, s5
; RV64I-NEXT: li t0, 255
; RV64I-NEXT: srli a5, a2, 8
-; RV64I-NEXT: slli s3, t0, 24
-; RV64I-NEXT: and a5, a5, s3
+; RV64I-NEXT: slli s4, t0, 24
+; RV64I-NEXT: and a5, a5, s4
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: srli a6, a2, 40
-; RV64I-NEXT: addi t0, a3, -256
-; RV64I-NEXT: and a6, a6, t0
+; RV64I-NEXT: addi t6, a3, -256
+; RV64I-NEXT: and a6, a6, t6
; RV64I-NEXT: srli t1, a2, 56
; RV64I-NEXT: or a1, a5, a1
; RV64I-NEXT: or a5, a6, t1
; RV64I-NEXT: or a1, a1, a5
-; RV64I-NEXT: and a5, a2, s4
+; RV64I-NEXT: and a5, a2, s5
; RV64I-NEXT: srliw a6, a2, 24
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: slli a6, a6, 32
; RV64I-NEXT: or a5, a5, a6
-; RV64I-NEXT: and a6, a2, t0
+; RV64I-NEXT: and a6, a2, t6
; RV64I-NEXT: slli a6, a6, 40
; RV64I-NEXT: slli a2, a2, 56
; RV64I-NEXT: or a2, a2, a6
@@ -5038,9 +5049,9 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, a6, 32
; RV64I-NEXT: srli a5, a1, 4
-; RV64I-NEXT: add a6, a6, a2
-; RV64I-NEXT: and a2, a5, a6
-; RV64I-NEXT: and a1, a1, a6
+; RV64I-NEXT: add t0, a6, a2
+; RV64I-NEXT: and a2, a5, t0
+; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: lui a5, 209715
; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: addi t1, a5, 819
@@ -5055,34 +5066,34 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: addi t2, a5, 1365
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, t2, 32
-; RV64I-NEXT: srli a5, a1, 1
+; RV64I-NEXT: srli s6, a1, 1
; RV64I-NEXT: add t2, t2, a2
-; RV64I-NEXT: and a2, a5, t2
+; RV64I-NEXT: and a2, s6, t2
; RV64I-NEXT: srli a5, a0, 24
; RV64I-NEXT: srli t3, a0, 8
-; RV64I-NEXT: and a5, a5, s4
-; RV64I-NEXT: and t3, t3, s3
+; RV64I-NEXT: and a5, a5, s5
+; RV64I-NEXT: and t3, t3, s4
; RV64I-NEXT: or a5, t3, a5
; RV64I-NEXT: srli t3, a0, 40
-; RV64I-NEXT: and t3, t3, t0
+; RV64I-NEXT: and t3, t3, t6
; RV64I-NEXT: srli t4, a0, 56
; RV64I-NEXT: or t3, t3, t4
-; RV64I-NEXT: and t4, a0, s4
+; RV64I-NEXT: and t4, a0, s5
; RV64I-NEXT: slli t4, t4, 24
-; RV64I-NEXT: srliw t6, a0, 24
-; RV64I-NEXT: slli t6, t6, 32
-; RV64I-NEXT: and s0, a0, t0
-; RV64I-NEXT: slli s0, s0, 40
+; RV64I-NEXT: srliw s0, a0, 24
+; RV64I-NEXT: slli s0, s0, 32
+; RV64I-NEXT: and s1, a0, t6
+; RV64I-NEXT: slli s1, s1, 40
; RV64I-NEXT: slli a0, a0, 56
-; RV64I-NEXT: or t4, t4, t6
-; RV64I-NEXT: or a0, a0, s0
+; RV64I-NEXT: or t4, t4, s0
+; RV64I-NEXT: or a0, a0, s1
; RV64I-NEXT: or a5, a5, t3
; RV64I-NEXT: or a0, a0, t4
; RV64I-NEXT: and a1, a1, t2
; RV64I-NEXT: or a0, a0, a5
; RV64I-NEXT: srli a5, a0, 4
-; RV64I-NEXT: and a0, a0, a6
-; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: and a0, a0, t0
+; RV64I-NEXT: and a5, a5, t0
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: slli a1, a1, 1
; RV64I-NEXT: or a0, a5, a0
@@ -5093,1040 +5104,1042 @@ define void @commutative_clmulh_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a0, a5, a0
; RV64I-NEXT: srli a2, a0, 1
-; RV64I-NEXT: and t4, a0, t2
+; RV64I-NEXT: and t3, a0, t2
; RV64I-NEXT: and a0, a2, t2
-; RV64I-NEXT: slli t4, t4, 1
+; RV64I-NEXT: slli t3, t3, 1
; RV64I-NEXT: slli a2, a1, 1
-; RV64I-NEXT: or a0, a0, t4
+; RV64I-NEXT: or a0, a0, t3
; RV64I-NEXT: andi a5, a0, 2
-; RV64I-NEXT: andi t3, a0, 1
+; RV64I-NEXT: andi t4, a0, 1
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: seqz t4, t4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: addi t4, t4, -1
; RV64I-NEXT: and a2, a5, a2
-; RV64I-NEXT: and a5, t3, a1
-; RV64I-NEXT: slli t3, a1, 2
-; RV64I-NEXT: andi t6, a0, 4
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: andi s0, a0, 8
-; RV64I-NEXT: addi t6, t6, -1
+; RV64I-NEXT: and a5, t4, a1
+; RV64I-NEXT: slli t4, a1, 2
+; RV64I-NEXT: andi s0, a0, 4
; RV64I-NEXT: seqz s0, s0
-; RV64I-NEXT: slli s1, a1, 3
+; RV64I-NEXT: andi s1, a0, 8
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: and t3, t6, t3
-; RV64I-NEXT: and s0, s0, s1
-; RV64I-NEXT: xor a2, a5, a2
-; RV64I-NEXT: xor a5, t3, s0
-; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: seqz s1, s1
+; RV64I-NEXT: slli s2, a1, 3
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: and t4, s0, t4
+; RV64I-NEXT: and s0, s1, s2
+; RV64I-NEXT: xor a2, a5, a2
+; RV64I-NEXT: xor a5, t4, s0
+; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: andi a5, a0, 16
-; RV64I-NEXT: slli t3, a1, 4
+; RV64I-NEXT: slli t4, a1, 4
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: andi t6, a0, 32
-; RV64I-NEXT: and a5, a5, t3
-; RV64I-NEXT: seqz t3, t6
-; RV64I-NEXT: slli t6, a1, 5
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: and t3, t3, t6
-; RV64I-NEXT: andi t6, a0, 64
-; RV64I-NEXT: xor a5, a5, t3
-; RV64I-NEXT: seqz t3, t6
-; RV64I-NEXT: slli t6, a1, 6
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: and t3, t3, t6
-; RV64I-NEXT: andi t6, a0, 128
-; RV64I-NEXT: xor a5, a5, t3
-; RV64I-NEXT: seqz t3, t6
-; RV64I-NEXT: slli t6, a1, 7
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: and t3, t3, t6
-; RV64I-NEXT: andi t6, a0, 256
-; RV64I-NEXT: slli s0, a1, 8
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: andi s1, a0, 512
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: slli s1, a1, 9
+; RV64I-NEXT: andi s0, a0, 32
+; RV64I-NEXT: and a5, a5, t4
+; RV64I-NEXT: seqz t4, s0
+; RV64I-NEXT: slli s0, a1, 5
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: and t4, t4, s0
+; RV64I-NEXT: andi s0, a0, 64
+; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: seqz t4, s0
+; RV64I-NEXT: slli s0, a1, 6
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: and t4, t4, s0
+; RV64I-NEXT: andi s0, a0, 128
+; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: seqz t4, s0
+; RV64I-NEXT: slli s0, a1, 7
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: and t4, t4, s0
+; RV64I-NEXT: andi s0, a0, 256
+; RV64I-NEXT: slli s1, a1, 8
+; RV64I-NEXT: seqz s0, s0
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: xor t3, t3, t6
+; RV64I-NEXT: andi s2, a0, 512
; RV64I-NEXT: and s0, s0, s1
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: xor a5, t3, s0
-; RV64I-NEXT: slli t6, a1, 10
-; RV64I-NEXT: andi t3, a0, 1024
-; RV64I-NEXT: seqz s0, t3
-; RV64I-NEXT: li t3, 1
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli a4, t3, 11
-; RV64I-NEXT: sd a4, 176(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a4
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: slli s0, a1, 11
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: lui s1, 1
-; RV64I-NEXT: slli s0, a1, 12
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: lui a4, 2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: and s2, a0, a4
-; RV64I-NEXT: and s0, s1, s0
; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: slli s2, a1, 13
+; RV64I-NEXT: slli s2, a1, 9
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: xor t6, t6, s0
+; RV64I-NEXT: xor t4, t4, s0
; RV64I-NEXT: and s0, s1, s2
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: lui s1, 4
-; RV64I-NEXT: slli s0, a1, 14
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: lui a4, 8
+; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: xor a5, t4, s0
+; RV64I-NEXT: slli s0, a1, 10
+; RV64I-NEXT: andi t4, a0, 1024
+; RV64I-NEXT: seqz s1, t4
+; RV64I-NEXT: li t4, 1
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: and s2, a0, a4
+; RV64I-NEXT: slli a4, t4, 11
+; RV64I-NEXT: sd a4, 176(sp) # 8-byte Folded Spill
; RV64I-NEXT: and s0, s1, s0
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: slli s2, a1, 15
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: and s0, s1, s2
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: xor a5, t6, s0
+; RV64I-NEXT: and s1, a0, a4
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: slli s1, a1, 11
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: lui a4, 1
+; RV64I-NEXT: slli s1, a1, 12
+; RV64I-NEXT: and s2, a0, a4
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: lui a4, 2
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: and s3, a0, a4
+; RV64I-NEXT: and s1, s2, s1
+; RV64I-NEXT: seqz s2, s3
+; RV64I-NEXT: slli s3, a1, 13
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: and s1, s2, s3
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: lui a4, 4
+; RV64I-NEXT: slli s1, a1, 14
+; RV64I-NEXT: and s2, a0, a4
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: lui a4, 8
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: and s3, a0, a4
+; RV64I-NEXT: and s1, s2, s1
+; RV64I-NEXT: seqz s2, s3
+; RV64I-NEXT: slli s3, a1, 15
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: and s1, s2, s3
; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: slli a5, a1, 16
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: lui s0, 32
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and s0, a0, s0
-; RV64I-NEXT: and a5, t6, a5
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: slli s0, a1, 17
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, a0, a3
+; RV64I-NEXT: seqz s0, s0
+; RV64I-NEXT: lui s1, 32
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: and s1, a0, s1
+; RV64I-NEXT: and a5, s0, a5
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: slli s1, a1, 17
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: and s0, s0, s1
; RV64I-NEXT: lui a3, 64
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: slli s0, a1, 18
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui a3, 128
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: slli s0, a1, 19
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: slli s1, a1, 18
+; RV64I-NEXT: seqz s0, s0
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: lui a3, 128
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
; RV64I-NEXT: lui a3, 256
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
+; RV64I-NEXT: slli s1, a1, 19
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: slli s0, a1, 20
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: addi t6, t6, -1
; RV64I-NEXT: lui a3, 512
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 21
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s1, a1, 21
+; RV64I-NEXT: and s0, s0, s1
; RV64I-NEXT: lui a3, 1024
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: and s0, a0, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: seqz a5, t6
+; RV64I-NEXT: seqz a5, s0
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui s0, 2048
-; RV64I-NEXT: slli t6, a1, 22
-; RV64I-NEXT: and s0, a0, s0
-; RV64I-NEXT: and a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui s1, 4096
-; RV64I-NEXT: slli s0, a1, 23
+; RV64I-NEXT: lui s1, 2048
+; RV64I-NEXT: slli s0, a1, 22
; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 24
+; RV64I-NEXT: lui a3, 4096
+; RV64I-NEXT: slli s1, a1, 23
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 24
; RV64I-NEXT: lui a3, 8192
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui s1, 16384
-; RV64I-NEXT: slli s0, a1, 25
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 26
+; RV64I-NEXT: lui a3, 16384
+; RV64I-NEXT: slli s1, a1, 25
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 26
; RV64I-NEXT: lui a3, 32768
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui s1, 65536
-; RV64I-NEXT: slli s0, a1, 27
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli s1, a1, 28
-; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: lui a3, 65536
+; RV64I-NEXT: slli s1, a1, 27
+; RV64I-NEXT: and s2, a0, a3
; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s2, a1, 28
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: and s0, s1, s2
; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: lui a3, 131072
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: and a5, a0, a3
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: lui a3, 262144
+; RV64I-NEXT: lui s0, 262144
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: slli s0, a1, 29
-; RV64I-NEXT: and a5, a5, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 30
-; RV64I-NEXT: sraiw s1, a0, 31
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: and s0, a0, s0
+; RV64I-NEXT: seqz s0, s0
+; RV64I-NEXT: slli s1, a1, 29
+; RV64I-NEXT: and a5, a5, s1
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 31
-; RV64I-NEXT: slli a3, t3, 32
+; RV64I-NEXT: slli s1, a1, 30
+; RV64I-NEXT: sraiw s2, a0, 31
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 31
+; RV64I-NEXT: slli a3, t4, 32
; RV64I-NEXT: sd a3, 168(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 33
-; RV64I-NEXT: sd s1, 160(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 32
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 33
-; RV64I-NEXT: slli a3, t3, 34
+; RV64I-NEXT: slli a3, t4, 33
+; RV64I-NEXT: sd a3, 160(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 32
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 33
+; RV64I-NEXT: slli a3, t4, 34
; RV64I-NEXT: sd a3, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 35
-; RV64I-NEXT: sd s1, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 34
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 35
-; RV64I-NEXT: slli a3, t3, 36
+; RV64I-NEXT: slli a3, t4, 35
+; RV64I-NEXT: sd a3, 144(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 34
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 35
+; RV64I-NEXT: slli a3, t4, 36
; RV64I-NEXT: sd a3, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 36
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: slli a3, t3, 37
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s1, a1, 36
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: slli a3, t4, 37
; RV64I-NEXT: sd a3, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: and s0, a0, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: seqz a5, t6
+; RV64I-NEXT: seqz a5, s0
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli s0, t3, 38
-; RV64I-NEXT: sd s0, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t6, a1, 37
-; RV64I-NEXT: and s0, a0, s0
-; RV64I-NEXT: and a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 39
-; RV64I-NEXT: sd s1, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 38
+; RV64I-NEXT: slli s1, t4, 38
+; RV64I-NEXT: sd s1, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s0, a1, 37
; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 39
-; RV64I-NEXT: slli a3, t3, 40
+; RV64I-NEXT: slli a3, t4, 39
+; RV64I-NEXT: sd a3, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 38
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 39
+; RV64I-NEXT: slli a3, t4, 40
; RV64I-NEXT: sd a3, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 41
-; RV64I-NEXT: sd s1, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 40
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 41
-; RV64I-NEXT: slli a3, t3, 42
+; RV64I-NEXT: slli a3, t4, 41
+; RV64I-NEXT: sd a3, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 40
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 41
+; RV64I-NEXT: slli a3, t4, 42
; RV64I-NEXT: sd a3, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 43
-; RV64I-NEXT: sd s1, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 42
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 43
-; RV64I-NEXT: slli a3, t3, 44
+; RV64I-NEXT: slli a3, t4, 43
+; RV64I-NEXT: sd a3, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 42
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 43
+; RV64I-NEXT: slli a3, t4, 44
; RV64I-NEXT: sd a3, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 45
-; RV64I-NEXT: sd s1, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 44
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli s1, a1, 45
-; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: slli a3, t4, 45
+; RV64I-NEXT: sd a3, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 44
+; RV64I-NEXT: and s2, a0, a3
; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s2, a1, 45
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: and s0, s1, s2
; RV64I-NEXT: xor a5, a5, s0
-; RV64I-NEXT: slli a3, t3, 46
+; RV64I-NEXT: slli a3, t4, 46
; RV64I-NEXT: sd a3, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor a5, a2, a5
+; RV64I-NEXT: xor a6, a2, a5
; RV64I-NEXT: and a2, a0, a3
; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: slli a3, t3, 47
-; RV64I-NEXT: sd a3, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s0, t4, 47
+; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: slli s0, a1, 46
-; RV64I-NEXT: and a2, a2, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 47
-; RV64I-NEXT: slli a3, t3, 48
+; RV64I-NEXT: and s0, a0, s0
+; RV64I-NEXT: seqz s0, s0
+; RV64I-NEXT: slli s1, a1, 46
+; RV64I-NEXT: and a2, a2, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s1, a1, 47
+; RV64I-NEXT: slli a3, t4, 48
; RV64I-NEXT: sd a3, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 49
-; RV64I-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 48
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 49
-; RV64I-NEXT: slli a3, t3, 50
+; RV64I-NEXT: slli a3, t4, 49
+; RV64I-NEXT: sd a3, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 48
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 49
+; RV64I-NEXT: slli a3, t4, 50
; RV64I-NEXT: sd a3, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli ra, t3, 51
-; RV64I-NEXT: slli s0, a1, 50
-; RV64I-NEXT: and s1, a0, ra
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 51
-; RV64I-NEXT: slli s11, t3, 52
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, s11
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s10, t3, 53
-; RV64I-NEXT: slli s0, a1, 52
-; RV64I-NEXT: and s1, a0, s10
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: slli a3, t4, 51
+; RV64I-NEXT: sd a3, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 50
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 51
+; RV64I-NEXT: slli s11, t4, 52
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, s11
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 53
-; RV64I-NEXT: slli s9, t3, 54
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, s9
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s8, t3, 55
-; RV64I-NEXT: slli s0, a1, 54
-; RV64I-NEXT: and s1, a0, s8
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: slli ra, t4, 53
+; RV64I-NEXT: slli s1, a1, 52
+; RV64I-NEXT: and s2, a0, ra
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 53
+; RV64I-NEXT: slli s10, t4, 54
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, s10
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 55
-; RV64I-NEXT: slli s7, t3, 56
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, s7
-; RV64I-NEXT: xor a4, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s5, t3, 57
-; RV64I-NEXT: slli s0, a1, 56
-; RV64I-NEXT: and s1, a0, s5
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: slli s9, t4, 55
+; RV64I-NEXT: slli s1, a1, 54
+; RV64I-NEXT: and s2, a0, s9
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 55
+; RV64I-NEXT: slli s8, t4, 56
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, s8
+; RV64I-NEXT: xor a5, a2, s0
; RV64I-NEXT: seqz s0, s1
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli s6, t3, 58
-; RV64I-NEXT: slli s1, a1, 57
-; RV64I-NEXT: and a2, a0, s6
+; RV64I-NEXT: slli s3, t4, 57
+; RV64I-NEXT: slli s1, a1, 56
+; RV64I-NEXT: and s2, a0, s3
; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s7, t4, 58
+; RV64I-NEXT: slli s2, a1, 57
+; RV64I-NEXT: and a2, a0, s7
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: xor t6, t6, s0
+; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli s0, a1, 58
-; RV64I-NEXT: slli s1, t3, 59
-; RV64I-NEXT: and a2, a2, s0
-; RV64I-NEXT: and s0, a0, s1
-; RV64I-NEXT: xor a3, t6, a2
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s2, t3, 60
+; RV64I-NEXT: slli s2, a1, 58
+; RV64I-NEXT: slli s1, t4, 59
+; RV64I-NEXT: and a2, a2, s2
+; RV64I-NEXT: and s2, a0, s1
+; RV64I-NEXT: xor a4, s0, a2
+; RV64I-NEXT: seqz s0, s2
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s2, t4, 60
; RV64I-NEXT: slli a2, a1, 59
-; RV64I-NEXT: and s0, a0, s2
-; RV64I-NEXT: and a2, t6, a2
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: xor a2, a3, a2
-; RV64I-NEXT: addi a3, t6, -1
-; RV64I-NEXT: slli s0, a1, 60
-; RV64I-NEXT: slli t6, t3, 61
-; RV64I-NEXT: and a3, a3, s0
-; RV64I-NEXT: and s0, a0, t6
+; RV64I-NEXT: and a3, a0, s2
+; RV64I-NEXT: and a2, s0, a2
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: xor a2, a4, a2
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a4, a1, 60
+; RV64I-NEXT: slli s0, t4, 61
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: and a4, a0, s0
; RV64I-NEXT: xor a2, a2, a3
-; RV64I-NEXT: seqz a3, s0
+; RV64I-NEXT: seqz a3, a4
; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: slli t3, t3, 62
-; RV64I-NEXT: and a0, a0, t3
-; RV64I-NEXT: slli s0, a1, 61
-; RV64I-NEXT: and a3, a3, s0
-; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: slli a4, a1, 61
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slli t4, t4, 62
; RV64I-NEXT: xor a2, a2, a3
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: srli a3, t4, 63
-; RV64I-NEXT: slli t4, a1, 62
; RV64I-NEXT: and a0, a0, t4
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: slli a1, a1, 63
-; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a1, a1, 62
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: srli a3, t3, 63
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: seqz a1, a3
+; RV64I-NEXT: slli s6, s6, 63
+; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: and a1, a3, a1
-; RV64I-NEXT: xor a4, a5, a4
+; RV64I-NEXT: and a1, a1, s6
+; RV64I-NEXT: xor a2, a6, a5
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: xor a0, a4, a0
+; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: srli a1, a0, 40
-; RV64I-NEXT: and a1, a1, t0
+; RV64I-NEXT: and a1, a1, t6
; RV64I-NEXT: srli a2, a0, 24
-; RV64I-NEXT: and a2, a2, s4
+; RV64I-NEXT: and a2, a2, s5
; RV64I-NEXT: srli a3, a0, 8
-; RV64I-NEXT: and a3, a3, s3
+; RV64I-NEXT: and a3, a3, s4
; RV64I-NEXT: srli a4, a0, 56
; RV64I-NEXT: or a1, a1, a4
; RV64I-NEXT: or a2, a3, a2
-; RV64I-NEXT: or s0, a2, a1
+; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 24
-; RV64I-NEXT: and a2, a0, s4
+; RV64I-NEXT: and a2, a0, s5
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: slli a2, a2, 24
; RV64I-NEXT: or a1, a2, a1
-; RV64I-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a1, a0, t0
+; RV64I-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a1, a0, t6
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: slli a1, a1, 40
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: srli a0, a7, 24
-; RV64I-NEXT: and a0, a0, s4
-; RV64I-NEXT: srli a1, a7, 8
-; RV64I-NEXT: and a1, a1, s3
-; RV64I-NEXT: srli a2, a7, 40
-; RV64I-NEXT: and a2, a2, t0
-; RV64I-NEXT: srli a3, a7, 56
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: or a2, a2, a3
-; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: and a1, a7, s4
-; RV64I-NEXT: slli a1, a1, 24
-; RV64I-NEXT: srliw a2, a7, 24
-; RV64I-NEXT: slli a2, a2, 32
-; RV64I-NEXT: and a3, a7, t0
-; RV64I-NEXT: slli a3, a3, 40
+; RV64I-NEXT: srli a1, a7, 24
+; RV64I-NEXT: and a1, a1, s5
+; RV64I-NEXT: srli a2, a7, 8
+; RV64I-NEXT: and a2, a2, s4
+; RV64I-NEXT: srli a3, a7, 40
+; RV64I-NEXT: and a3, a3, t6
+; RV64I-NEXT: srli a4, a7, 56
+; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: or a3, a3, a4
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: and a2, a7, s5
+; RV64I-NEXT: slli a2, a2, 24
+; RV64I-NEXT: srliw a3, a7, 24
+; RV64I-NEXT: slli a3, a3, 32
+; RV64I-NEXT: and a4, a7, t6
+; RV64I-NEXT: slli a4, a4, 40
; RV64I-NEXT: slli a7, a7, 56
-; RV64I-NEXT: or a1, a1, a2
-; RV64I-NEXT: or a2, a7, a3
-; RV64I-NEXT: srli a3, t5, 24
-; RV64I-NEXT: srli a4, t5, 8
-; RV64I-NEXT: and a3, a3, s4
-; RV64I-NEXT: and a4, a4, s3
-; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a4, t5, 40
-; RV64I-NEXT: and a4, a4, t0
-; RV64I-NEXT: srli a5, t5, 56
-; RV64I-NEXT: or a4, a4, a5
-; RV64I-NEXT: and a5, t5, s4
-; RV64I-NEXT: slli a5, a5, 24
+; RV64I-NEXT: or a2, a2, a3
+; RV64I-NEXT: or a3, a7, a4
+; RV64I-NEXT: srli a4, t5, 24
+; RV64I-NEXT: srli a5, t5, 8
+; RV64I-NEXT: and a4, a4, s5
+; RV64I-NEXT: and a5, a5, s4
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a5, t5, 40
+; RV64I-NEXT: and a5, a5, t6
+; RV64I-NEXT: srli a6, t5, 56
+; RV64I-NEXT: or a5, a5, a6
+; RV64I-NEXT: and a6, t5, s5
+; RV64I-NEXT: slli a6, a6, 24
; RV64I-NEXT: srliw a7, t5, 24
; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: and t4, t5, t0
-; RV64I-NEXT: slli t4, t4, 40
+; RV64I-NEXT: and t3, t5, t6
+; RV64I-NEXT: slli t3, t3, 40
; RV64I-NEXT: slli t5, t5, 56
-; RV64I-NEXT: or a5, a5, a7
-; RV64I-NEXT: or a7, t5, t4
+; RV64I-NEXT: or a6, a6, a7
+; RV64I-NEXT: or a7, t5, t3
+; RV64I-NEXT: or a4, a4, a5
+; RV64I-NEXT: or a5, a7, a6
+; RV64I-NEXT: or a2, a3, a2
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a3, a4, 4
+; RV64I-NEXT: and a4, a4, t0
+; RV64I-NEXT: and a3, a3, t0
+; RV64I-NEXT: slli a4, a4, 4
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a3, a3, a4
-; RV64I-NEXT: or a4, a7, a5
+; RV64I-NEXT: srli a2, a1, 4
+; RV64I-NEXT: and a1, a1, t0
+; RV64I-NEXT: and a2, a2, t0
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: srli a4, a3, 2
+; RV64I-NEXT: and a3, a3, t1
+; RV64I-NEXT: and a4, a4, t1
+; RV64I-NEXT: slli a3, a3, 2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a2, a3, 4
-; RV64I-NEXT: and a3, a3, a6
-; RV64I-NEXT: and a2, a2, a6
-; RV64I-NEXT: slli a3, a3, 4
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: or a2, a2, a3
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: and a0, a0, a6
-; RV64I-NEXT: and a1, a1, a6
-; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: srli a3, a2, 2
-; RV64I-NEXT: and a2, a2, t1
-; RV64I-NEXT: and a3, a3, t1
-; RV64I-NEXT: slli a2, a2, 2
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: or a2, a3, a2
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: and a0, a0, t1
+; RV64I-NEXT: srli a2, a1, 2
; RV64I-NEXT: and a1, a1, t1
-; RV64I-NEXT: slli a0, a0, 2
-; RV64I-NEXT: or a1, a1, a0
-; RV64I-NEXT: srli a0, a2, 1
-; RV64I-NEXT: and a3, a0, t2
-; RV64I-NEXT: and a0, a2, t2
-; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: srli a2, a1, 1
+; RV64I-NEXT: and a2, a2, t1
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: or a2, a2, a1
+; RV64I-NEXT: srli a1, a3, 1
+; RV64I-NEXT: and a4, a1, t2
+; RV64I-NEXT: and a3, a3, t2
+; RV64I-NEXT: slli a3, a3, 1
+; RV64I-NEXT: srli a1, a2, 1
; RV64I-NEXT: and a2, a2, t2
-; RV64I-NEXT: or a3, a3, a0
-; RV64I-NEXT: and a1, a1, t2
-; RV64I-NEXT: andi a4, a3, 2
-; RV64I-NEXT: slli a1, a1, 1
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: or a1, a2, a1
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a2, a1, 1
-; RV64I-NEXT: andi a5, a3, 1
-; RV64I-NEXT: and a2, a4, a2
-; RV64I-NEXT: seqz a4, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: andi a5, a3, 4
-; RV64I-NEXT: and a4, a4, a1
-; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a4, a2
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, a1, 2
-; RV64I-NEXT: andi a7, a3, 8
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 3
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 16
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, a1, 4
-; RV64I-NEXT: andi a7, a3, 32
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 5
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 64
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 6
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 128
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, a1, 7
-; RV64I-NEXT: andi a7, a3, 256
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 8
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 512
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 9
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 1024
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 10
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 176(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 1
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 11
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 12
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: lui a7, 2
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 13
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 4
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 14
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 8
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 15
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 16
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 32
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 16
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 17
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: lui a7, 64
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 18
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 128
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 19
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 256
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 20
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 512
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 21
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 1024
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 2048
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 22
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 23
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: lui a7, 4096
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 24
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 8192
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 25
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 16384
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 26
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 32768
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 27
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 65536
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 28
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 131072
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 262144
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 29
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 30
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: sraiw a7, a3, 31
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 31
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 168(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 32
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 160(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 33
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 34
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 35
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 36
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: ld a4, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 37
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 38
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: ld a7, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 39
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 40
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 41
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 42
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 43
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 44
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 45
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: or a4, a4, a3
+; RV64I-NEXT: slli a2, a2, 1
+; RV64I-NEXT: andi a5, a4, 2
+; RV64I-NEXT: seqz a6, a5
+; RV64I-NEXT: and a5, a1, t2
+; RV64I-NEXT: or a5, a5, a2
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli a2, a5, 1
+; RV64I-NEXT: andi a7, a4, 1
+; RV64I-NEXT: and a2, a6, a2
+; RV64I-NEXT: seqz a6, a7
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: andi a7, a4, 4
+; RV64I-NEXT: and a6, a6, a5
+; RV64I-NEXT: seqz a7, a7
+; RV64I-NEXT: xor a2, a6, a2
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli a6, a5, 2
+; RV64I-NEXT: andi t3, a4, 8
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 3
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 16
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli a6, a5, 4
+; RV64I-NEXT: andi t3, a4, 32
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 5
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 64
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 6
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 128
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli a6, a5, 7
+; RV64I-NEXT: andi t3, a4, 256
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 8
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 512
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 9
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 1024
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 10
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 176(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 1
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 11
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 12
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: lui t3, 2
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 13
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 4
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 14
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 8
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 15
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 16
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 32
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 16
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 17
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: lui t3, 64
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 18
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 128
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 19
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 256
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 20
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 512
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 21
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 1024
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 2048
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 22
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 23
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: lui t3, 4096
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 24
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 8192
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 25
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 16384
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 26
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 32768
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 27
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 65536
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 28
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 131072
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 262144
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 29
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 30
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: sraiw t3, a4, 31
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 31
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 168(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 32
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 160(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 33
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 152(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 34
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 144(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 35
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 36
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: ld a6, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 37
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 38
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: ld t3, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 39
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 40
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 41
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 42
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 43
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 44
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 45
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor t5, a6, a7
+; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: addi a6, a6, -1
; RV64I-NEXT: ld a7, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
+; RV64I-NEXT: and a7, a4, a7
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: slli t4, a1, 46
-; RV64I-NEXT: and a5, a5, t4
+; RV64I-NEXT: slli t3, a5, 46
+; RV64I-NEXT: and a6, a6, t3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: ld t4, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and t4, a3, t4
-; RV64I-NEXT: slli t5, a1, 47
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: ld t3, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: slli s6, a5, 47
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: addi t3, t3, -1
; RV64I-NEXT: ld a7, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: slli t5, a1, 48
-; RV64I-NEXT: and t4, t4, t5
+; RV64I-NEXT: and a7, a4, a7
+; RV64I-NEXT: slli s6, a5, 48
+; RV64I-NEXT: and t3, t3, s6
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: ld t4, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and t4, a3, t4
-; RV64I-NEXT: slli t5, a1, 49
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and a7, a3, ra
-; RV64I-NEXT: slli t5, a1, 50
-; RV64I-NEXT: and t4, t4, t5
+; RV64I-NEXT: ld t3, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: slli s6, a5, 49
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: ld a7, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a4, a7
+; RV64I-NEXT: slli s6, a5, 50
+; RV64I-NEXT: and t3, t3, s6
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and t4, a3, s11
-; RV64I-NEXT: slli t5, a1, 51
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and a7, a3, s10
-; RV64I-NEXT: slli t5, a1, 52
-; RV64I-NEXT: and t4, t4, t5
+; RV64I-NEXT: and t3, a4, s11
+; RV64I-NEXT: slli s6, a5, 51
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: and a7, a4, ra
+; RV64I-NEXT: slli s6, a5, 52
+; RV64I-NEXT: and t3, t3, s6
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: slli t5, a1, 53
-; RV64I-NEXT: xor a5, a5, t4
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, a3, s9
-; RV64I-NEXT: slli t4, a1, 54
+; RV64I-NEXT: slli s6, a5, 53
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, a4, s10
+; RV64I-NEXT: slli t3, a5, 54
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and t5, a3, s8
-; RV64I-NEXT: and a7, a7, t4
-; RV64I-NEXT: seqz t4, t5
-; RV64I-NEXT: slli t5, a1, 55
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: xor a4, a5, a7
-; RV64I-NEXT: slli a5, a1, 56
-; RV64I-NEXT: and a7, a3, s7
+; RV64I-NEXT: and s6, a4, s9
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz t3, s6
+; RV64I-NEXT: slli s6, a5, 55
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, t3, s6
+; RV64I-NEXT: xor a2, a2, t5
+; RV64I-NEXT: xor t3, a6, a7
+; RV64I-NEXT: slli a6, a5, 56
+; RV64I-NEXT: and a7, a4, s8
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: and t4, a3, s5
+; RV64I-NEXT: and t5, a4, s3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: slli t5, a1, 57
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and a5, a7, a5
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, a3, s6
-; RV64I-NEXT: slli t4, a1, 58
+; RV64I-NEXT: seqz t5, t5
+; RV64I-NEXT: slli s3, a5, 57
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: and a7, t5, s3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, a4, s7
+; RV64I-NEXT: slli t5, a5, 58
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and s1, a3, s1
-; RV64I-NEXT: and a7, a7, t4
-; RV64I-NEXT: seqz t4, s1
-; RV64I-NEXT: slli t5, a1, 59
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, a3, s2
-; RV64I-NEXT: slli t4, a1, 60
+; RV64I-NEXT: and s1, a4, s1
+; RV64I-NEXT: and a7, a7, t5
+; RV64I-NEXT: seqz t5, s1
+; RV64I-NEXT: slli s1, a5, 59
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, t5, s1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, a4, s2
+; RV64I-NEXT: slli t5, a5, 60
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and t5, a3, t6
-; RV64I-NEXT: and a7, a7, t4
-; RV64I-NEXT: seqz t4, t5
-; RV64I-NEXT: slli t5, a1, 61
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a3, a3, t3
-; RV64I-NEXT: slli a7, a1, 62
+; RV64I-NEXT: and s0, a4, s0
+; RV64I-NEXT: and a7, a7, t5
+; RV64I-NEXT: seqz t5, s0
+; RV64I-NEXT: slli s0, a5, 61
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, t5, s0
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a4, a4, t4
+; RV64I-NEXT: slli a5, a5, 62
+; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: srli a3, a3, 63
+; RV64I-NEXT: and a4, a4, a5
; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: srli a0, a0, 63
-; RV64I-NEXT: and a3, a3, a7
-; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: slli a1, a1, 63
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: xor a3, a5, a3
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: xor a0, a3, a0
-; RV64I-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: or a1, a3, a1
-; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: or a1, a1, s0
-; RV64I-NEXT: srli a2, a0, 40
-; RV64I-NEXT: and a2, a2, t0
-; RV64I-NEXT: srli a3, a0, 8
-; RV64I-NEXT: srli a4, a0, 24
-; RV64I-NEXT: and a3, a3, s3
-; RV64I-NEXT: srli a5, a0, 56
-; RV64I-NEXT: and a4, a4, s4
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: xor a4, a6, a4
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: xor a2, a2, t3
+; RV64I-NEXT: xor a1, a4, a1
+; RV64I-NEXT: ld a3, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: xor a1, a2, a1
+; RV64I-NEXT: ld a2, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: srli a2, a1, 40
+; RV64I-NEXT: and a2, a2, t6
+; RV64I-NEXT: srli a3, a1, 8
+; RV64I-NEXT: srli a4, a1, 24
+; RV64I-NEXT: and a3, a3, s4
+; RV64I-NEXT: srli a5, a1, 56
+; RV64I-NEXT: and a4, a4, s5
; RV64I-NEXT: or a2, a2, a5
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: or a2, a3, a2
-; RV64I-NEXT: srliw a3, a0, 24
+; RV64I-NEXT: srliw a3, a1, 24
; RV64I-NEXT: slli a3, a3, 32
-; RV64I-NEXT: and a4, a0, s4
+; RV64I-NEXT: and a4, a1, s5
; RV64I-NEXT: slli a4, a4, 24
-; RV64I-NEXT: and a5, a0, t0
-; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: and a5, a1, t6
+; RV64I-NEXT: slli a1, a1, 56
; RV64I-NEXT: slli a5, a5, 40
; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: or a0, a0, a5
-; RV64I-NEXT: or a0, a0, a3
-; RV64I-NEXT: srli a3, a1, 4
-; RV64I-NEXT: and a3, a3, a6
-; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: and a1, a1, a6
-; RV64I-NEXT: srli a2, a0, 4
-; RV64I-NEXT: and a2, a2, a6
-; RV64I-NEXT: and a0, a0, a6
-; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: or a1, a1, a5
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: srli a3, a0, 4
+; RV64I-NEXT: and a3, a3, t0
+; RV64I-NEXT: or a1, a1, a2
+; RV64I-NEXT: and a0, a0, t0
+; RV64I-NEXT: srli a2, a1, 4
+; RV64I-NEXT: and a2, a2, t0
+; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: or a1, a3, a1
-; RV64I-NEXT: or a0, a2, a0
-; RV64I-NEXT: srli a2, a1, 2
-; RV64I-NEXT: and a1, a1, t1
-; RV64I-NEXT: and a2, a2, t1
-; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a2, a0, 2
-; RV64I-NEXT: and a2, a2, t1
; RV64I-NEXT: and a0, a0, t1
-; RV64I-NEXT: srli a3, a1, 1
+; RV64I-NEXT: and a2, a2, t1
; RV64I-NEXT: slli a0, a0, 2
-; RV64I-NEXT: and a3, a3, t2
; RV64I-NEXT: or a0, a2, a0
-; RV64I-NEXT: and a1, a1, t2
-; RV64I-NEXT: srli a2, a0, 1
-; RV64I-NEXT: and a2, a2, t2
+; RV64I-NEXT: srli a2, a1, 2
+; RV64I-NEXT: and a2, a2, t1
+; RV64I-NEXT: and a1, a1, t1
+; RV64I-NEXT: srli a3, a0, 1
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: and a3, a3, t2
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: and a0, a0, t2
-; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: srli a2, a1, 1
+; RV64I-NEXT: and a2, a2, t2
+; RV64I-NEXT: and a1, a1, t2
; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: or a1, a3, a1
-; RV64I-NEXT: or a0, a2, a0
-; RV64I-NEXT: srli a1, a1, 1
+; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: or a0, a3, a0
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: srli a1, a1, 1
; RV64I-NEXT: ld a2, 184(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sd a1, 0(a2)
-; RV64I-NEXT: sd a0, 8(a2)
+; RV64I-NEXT: sd a0, 0(a2)
+; RV64I-NEXT: sd a1, 8(a2)
; RV64I-NEXT: ld a2, 192(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sd a1, 0(a2)
-; RV64I-NEXT: sd a0, 8(a2)
+; RV64I-NEXT: sd a0, 0(a2)
+; RV64I-NEXT: sd a1, 8(a2)
; RV64I-NEXT: ld ra, 296(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 288(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 280(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/clmulr.ll b/llvm/test/CodeGen/RISCV/clmulr.ll
index 0d2463507aed7..bf07cf4ddcbcf 100644
--- a/llvm/test/CodeGen/RISCV/clmulr.ll
+++ b/llvm/test/CodeGen/RISCV/clmulr.ll
@@ -1256,9 +1256,9 @@ define i16 @clmulr_i16(i16 %a, i16 %b) nounwind {
define i32 @clmulr_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: clmulr_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a7, 16
+; RV32I-NEXT: lui t0, 16
; RV32I-NEXT: srli a3, a0, 8
-; RV32I-NEXT: addi a2, a7, -256
+; RV32I-NEXT: addi a2, t0, -256
; RV32I-NEXT: and a3, a3, a2
; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: and a5, a0, a2
@@ -1280,248 +1280,248 @@ define i32 @clmulr_i32(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: and a4, a4, a3
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a4, a4, 2
-; RV32I-NEXT: or a5, a5, a4
-; RV32I-NEXT: srli a6, a5, 1
+; RV32I-NEXT: or a6, a5, a4
+; RV32I-NEXT: srli a5, a6, 1
; RV32I-NEXT: lui a4, 349525
; RV32I-NEXT: addi a4, a4, 1365
-; RV32I-NEXT: srli t0, a1, 8
-; RV32I-NEXT: and a6, a6, a4
-; RV32I-NEXT: and t0, t0, a2
-; RV32I-NEXT: srli t1, a1, 24
-; RV32I-NEXT: and t2, a1, a2
-; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: srli a7, a1, 8
+; RV32I-NEXT: and t1, a5, a4
+; RV32I-NEXT: and a7, a7, a2
+; RV32I-NEXT: srli t2, a1, 24
+; RV32I-NEXT: and t3, a1, a2
+; RV32I-NEXT: slli t3, t3, 8
; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or t0, t0, t1
-; RV32I-NEXT: or a1, a1, t2
-; RV32I-NEXT: and a5, a5, a4
-; RV32I-NEXT: or a1, a1, t0
-; RV32I-NEXT: srli t0, a1, 4
+; RV32I-NEXT: or a7, a7, t2
+; RV32I-NEXT: or a1, a1, t3
+; RV32I-NEXT: and a6, a6, a4
+; RV32I-NEXT: or a1, a1, a7
+; RV32I-NEXT: srli a7, a1, 4
; RV32I-NEXT: and a1, a1, a0
-; RV32I-NEXT: and t0, t0, a0
+; RV32I-NEXT: and a7, a7, a0
; RV32I-NEXT: slli a1, a1, 4
-; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: or a1, t0, a1
-; RV32I-NEXT: srli t0, a1, 2
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: or a1, a7, a1
+; RV32I-NEXT: srli a7, a1, 2
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: and t0, t0, a3
-; RV32I-NEXT: slli t1, a1, 2
-; RV32I-NEXT: or a1, a6, a5
-; RV32I-NEXT: or a5, t0, t1
-; RV32I-NEXT: srli a6, a5, 1
-; RV32I-NEXT: and a5, a5, a4
+; RV32I-NEXT: and a7, a7, a3
+; RV32I-NEXT: slli t2, a1, 2
+; RV32I-NEXT: or a1, t1, a6
+; RV32I-NEXT: or a6, a7, t2
+; RV32I-NEXT: srli a7, a6, 1
; RV32I-NEXT: and a6, a6, a4
-; RV32I-NEXT: slli a5, a5, 1
-; RV32I-NEXT: slli t0, a1, 1
-; RV32I-NEXT: or a6, a6, a5
-; RV32I-NEXT: andi t1, a6, 2
-; RV32I-NEXT: andi t2, a6, 1
-; RV32I-NEXT: seqz t1, t1
+; RV32I-NEXT: and a7, a7, a4
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: slli t1, a1, 1
+; RV32I-NEXT: or a7, a7, a6
+; RV32I-NEXT: andi t2, a7, 2
+; RV32I-NEXT: andi t3, a7, 1
; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t0, t1, t0
-; RV32I-NEXT: and t1, t2, a1
-; RV32I-NEXT: slli t2, a1, 2
-; RV32I-NEXT: andi t3, a6, 4
; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: andi t4, a6, 8
+; RV32I-NEXT: addi t2, t2, -1
; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: and t1, t2, t1
+; RV32I-NEXT: and t2, t3, a1
+; RV32I-NEXT: slli t3, a1, 2
+; RV32I-NEXT: andi t4, a7, 4
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: slli t5, a1, 3
+; RV32I-NEXT: andi t5, a7, 8
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: and t2, t3, t2
-; RV32I-NEXT: and t3, t4, t5
-; RV32I-NEXT: xor t0, t1, t0
-; RV32I-NEXT: xor t1, t2, t3
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: andi t1, a6, 16
-; RV32I-NEXT: slli t2, a1, 4
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: andi t3, a6, 32
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 5
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: andi t3, a6, 64
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 6
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: andi t3, a6, 128
+; RV32I-NEXT: seqz t5, t5
+; RV32I-NEXT: slli t6, a1, 3
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: and t3, t4, t3
+; RV32I-NEXT: and t4, t5, t6
+; RV32I-NEXT: xor t1, t2, t1
+; RV32I-NEXT: xor t2, t3, t4
; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 7
+; RV32I-NEXT: andi t2, a7, 16
+; RV32I-NEXT: slli t3, a1, 4
+; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: andi t4, a7, 32
; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: andi t3, a6, 256
-; RV32I-NEXT: slli t4, a1, 8
-; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: slli t4, a1, 5
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: andi t5, a6, 512
; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: seqz t4, t5
-; RV32I-NEXT: slli t5, a1, 9
-; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: andi t4, a7, 64
; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: and t3, t4, t5
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: xor t1, t2, t3
-; RV32I-NEXT: slli t2, a1, 10
-; RV32I-NEXT: andi t3, a6, 1024
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: li t4, 1
+; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: slli t4, a1, 6
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: slli t4, t4, 11
-; RV32I-NEXT: and t2, t3, t2
-; RV32I-NEXT: and t3, a6, t4
-; RV32I-NEXT: xor t1, t1, t2
-; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 11
-; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and t2, t2, t3
-; RV32I-NEXT: lui t3, 1
-; RV32I-NEXT: slli t4, a1, 12
-; RV32I-NEXT: and t3, a6, t3
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: lui t5, 2
+; RV32I-NEXT: and t3, t3, t4
+; RV32I-NEXT: andi t4, a7, 128
+; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: slli t4, a1, 7
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t5, a6, t5
; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: seqz t4, t5
-; RV32I-NEXT: slli t5, a1, 13
+; RV32I-NEXT: andi t4, a7, 256
+; RV32I-NEXT: slli t5, a1, 8
+; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: andi t6, a7, 512
+; RV32I-NEXT: and t4, t4, t5
+; RV32I-NEXT: seqz t5, t6
+; RV32I-NEXT: slli t6, a1, 9
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: xor t3, t3, t4
+; RV32I-NEXT: and t4, t5, t6
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: xor t2, t3, t4
+; RV32I-NEXT: slli t3, a1, 10
+; RV32I-NEXT: andi t4, a7, 1024
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: li t5, 1
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: slli t5, t5, 11
+; RV32I-NEXT: and t3, t4, t3
+; RV32I-NEXT: and t4, a7, t5
; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: and t3, t4, t5
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: lui t3, 4
-; RV32I-NEXT: slli t4, a1, 14
-; RV32I-NEXT: and t3, a6, t3
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: lui t5, 8
+; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: slli t4, a1, 11
; RV32I-NEXT: addi t3, t3, -1
-; RV32I-NEXT: and t5, a6, t5
; RV32I-NEXT: and t3, t3, t4
-; RV32I-NEXT: seqz t4, t5
-; RV32I-NEXT: slli t5, a1, 15
+; RV32I-NEXT: lui t4, 1
+; RV32I-NEXT: slli t5, a1, 12
+; RV32I-NEXT: and t4, a7, t4
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: lui t6, 2
; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: and t3, t4, t5
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: xor t1, t2, t3
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: slli t1, a1, 16
-; RV32I-NEXT: and a7, a6, a7
-; RV32I-NEXT: lui t2, 32
-; RV32I-NEXT: seqz a7, a7
-; RV32I-NEXT: and t2, a6, t2
-; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: and t6, a7, t6
+; RV32I-NEXT: and t4, t4, t5
+; RV32I-NEXT: seqz t5, t6
+; RV32I-NEXT: slli t6, a1, 13
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: xor t3, t3, t4
+; RV32I-NEXT: and t4, t5, t6
+; RV32I-NEXT: xor t3, t3, t4
+; RV32I-NEXT: lui t4, 4
+; RV32I-NEXT: slli t5, a1, 14
+; RV32I-NEXT: and t4, a7, t4
+; RV32I-NEXT: seqz t4, t4
+; RV32I-NEXT: lui t6, 8
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: and t6, a7, t6
+; RV32I-NEXT: and t4, t4, t5
+; RV32I-NEXT: seqz t5, t6
+; RV32I-NEXT: slli t6, a1, 15
+; RV32I-NEXT: addi t5, t5, -1
+; RV32I-NEXT: xor t3, t3, t4
+; RV32I-NEXT: and t4, t5, t6
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: xor t2, t3, t4
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: slli t2, a1, 16
+; RV32I-NEXT: and t0, a7, t0
+; RV32I-NEXT: lui t3, 32
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: and t3, a7, t3
+; RV32I-NEXT: addi t0, t0, -1
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: slli t4, a1, 17
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: and t0, t0, t2
+; RV32I-NEXT: and t2, t3, t4
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lui t2, 64
+; RV32I-NEXT: slli t3, a1, 18
+; RV32I-NEXT: and t2, a7, t2
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: lui t4, 128
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: and t4, a7, t4
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: slli t4, a1, 19
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: and t2, t3, t4
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lui t2, 256
+; RV32I-NEXT: slli t3, a1, 20
+; RV32I-NEXT: and t2, a7, t2
; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: slli t3, a1, 17
+; RV32I-NEXT: lui t4, 512
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and a7, a7, t1
-; RV32I-NEXT: and t1, t2, t3
-; RV32I-NEXT: xor a7, a7, t1
-; RV32I-NEXT: lui t1, 64
-; RV32I-NEXT: slli t2, a1, 18
-; RV32I-NEXT: and t1, a6, t1
+; RV32I-NEXT: and t4, a7, t4
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: slli t4, a1, 21
+; RV32I-NEXT: addi t3, t3, -1
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: and t2, t3, t4
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lui t2, 1024
+; RV32I-NEXT: xor t0, t1, t0
+; RV32I-NEXT: and t1, a7, t2
+; RV32I-NEXT: slli t2, a1, 22
; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: lui t3, 128
; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: and t3, a6, t3
+; RV32I-NEXT: lui t3, 2048
; RV32I-NEXT: and t1, t1, t2
+; RV32I-NEXT: and t2, a7, t3
+; RV32I-NEXT: slli t3, a1, 23
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: lui t4, 4096
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: and t3, a7, t4
+; RV32I-NEXT: xor t1, t1, t2
; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 19
+; RV32I-NEXT: slli t3, a1, 24
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: xor a7, a7, t1
-; RV32I-NEXT: and t1, t2, t3
-; RV32I-NEXT: xor a7, a7, t1
-; RV32I-NEXT: lui t1, 256
-; RV32I-NEXT: slli t2, a1, 20
-; RV32I-NEXT: and t1, a6, t1
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: lui t3, 512
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: and t3, a6, t3
-; RV32I-NEXT: and t1, t1, t2
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: lui t3, 8192
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: and t2, a7, t3
+; RV32I-NEXT: slli t3, a1, 25
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: lui t4, 16384
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: and t3, a7, t4
+; RV32I-NEXT: xor t1, t1, t2
; RV32I-NEXT: seqz t2, t3
-; RV32I-NEXT: slli t3, a1, 21
+; RV32I-NEXT: slli t3, a1, 26
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: xor a7, a7, t1
-; RV32I-NEXT: and t1, t2, t3
-; RV32I-NEXT: xor a7, a7, t1
-; RV32I-NEXT: lui t1, 1024
-; RV32I-NEXT: xor a7, t0, a7
-; RV32I-NEXT: and t0, a6, t1
-; RV32I-NEXT: slli t1, a1, 22
-; RV32I-NEXT: seqz t0, t0
-; RV32I-NEXT: addi t0, t0, -1
-; RV32I-NEXT: lui t2, 2048
-; RV32I-NEXT: and t0, t0, t1
-; RV32I-NEXT: and t1, a6, t2
-; RV32I-NEXT: slli t2, a1, 23
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: lui t3, 4096
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: and t2, a6, t3
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: seqz t1, t2
-; RV32I-NEXT: slli t2, a1, 24
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: lui t2, 8192
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: and t1, a6, t2
-; RV32I-NEXT: slli t2, a1, 25
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: lui t3, 16384
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: and t2, a6, t3
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: seqz t1, t2
-; RV32I-NEXT: slli t2, a1, 26
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: lui t2, 32768
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: and t1, a6, t2
-; RV32I-NEXT: slli t2, a1, 27
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: lui t3, 65536
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: and t2, a6, t3
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: seqz t1, t2
-; RV32I-NEXT: slli t2, a1, 28
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: lui t2, 131072
-; RV32I-NEXT: xor t0, t0, t1
-; RV32I-NEXT: and t1, a6, t2
-; RV32I-NEXT: slli t2, a1, 29
-; RV32I-NEXT: seqz t1, t1
-; RV32I-NEXT: addi t1, t1, -1
-; RV32I-NEXT: lui t3, 262144
-; RV32I-NEXT: and t1, t1, t2
-; RV32I-NEXT: and a6, a6, t3
-; RV32I-NEXT: slli t2, a1, 30
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: lui t3, 32768
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: and t2, a7, t3
+; RV32I-NEXT: slli t3, a1, 27
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: lui t4, 65536
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: and t3, a7, t4
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: seqz t2, t3
+; RV32I-NEXT: slli t3, a1, 28
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: lui t3, 131072
+; RV32I-NEXT: xor t1, t1, t2
+; RV32I-NEXT: and t2, a7, t3
+; RV32I-NEXT: slli t3, a1, 29
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: lui t4, 262144
+; RV32I-NEXT: and t2, t2, t3
+; RV32I-NEXT: and a7, a7, t4
+; RV32I-NEXT: slli a1, a1, 30
+; RV32I-NEXT: seqz a7, a7
+; RV32I-NEXT: addi a7, a7, -1
+; RV32I-NEXT: srli a6, a6, 31
+; RV32I-NEXT: and a1, a7, a1
; RV32I-NEXT: seqz a6, a6
+; RV32I-NEXT: slli a5, a5, 31
; RV32I-NEXT: addi a6, a6, -1
-; RV32I-NEXT: srli a5, a5, 31
-; RV32I-NEXT: and a6, a6, t2
-; RV32I-NEXT: seqz a5, a5
-; RV32I-NEXT: slli a1, a1, 31
-; RV32I-NEXT: addi a5, a5, -1
-; RV32I-NEXT: xor a6, t1, a6
-; RV32I-NEXT: and a1, a5, a1
-; RV32I-NEXT: xor a5, a7, t0
+; RV32I-NEXT: xor a1, t2, a1
+; RV32I-NEXT: and a5, a6, a5
+; RV32I-NEXT: xor a6, t0, t1
+; RV32I-NEXT: xor a1, a1, a5
; RV32I-NEXT: xor a1, a6, a1
-; RV32I-NEXT: xor a1, a5, a1
; RV32I-NEXT: srli a5, a1, 8
; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: srli a6, a1, 24
@@ -2921,18 +2921,18 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: sw s11, 476(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a3, 468(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a2, 464(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv t2, a0
; RV32I-NEXT: lw a2, 4(a1)
-; RV32I-NEXT: lui a4, 16
-; RV32I-NEXT: lw a0, 8(a1)
-; RV32I-NEXT: sw a0, 340(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s10, 12(a1)
-; RV32I-NEXT: addi s8, a4, -256
+; RV32I-NEXT: lui a3, 16
+; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: sw a4, 344(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a4, 12(a1)
+; RV32I-NEXT: sw a4, 204(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi s10, a3, -256
; RV32I-NEXT: srli a5, a2, 8
; RV32I-NEXT: srli a6, a2, 24
-; RV32I-NEXT: and a7, a2, s8
+; RV32I-NEXT: and a7, a2, s10
; RV32I-NEXT: slli a2, a2, 24
-; RV32I-NEXT: and a5, a5, s8
+; RV32I-NEXT: and a5, a5, s10
; RV32I-NEXT: slli a7, a7, 8
; RV32I-NEXT: or a5, a5, a6
; RV32I-NEXT: or a2, a2, a7
@@ -2946,1178 +2946,1179 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a2, a5, a2
; RV32I-NEXT: lui a5, 209715
; RV32I-NEXT: srli a6, a2, 2
-; RV32I-NEXT: addi s7, a5, 819
-; RV32I-NEXT: and a6, a6, s7
-; RV32I-NEXT: and a2, a2, s7
+; RV32I-NEXT: addi s9, a5, 819
+; RV32I-NEXT: and a6, a6, s9
+; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: slli a2, a2, 2
-; RV32I-NEXT: lui a0, 349525
+; RV32I-NEXT: lui t2, 349525
; RV32I-NEXT: or a2, a6, a2
-; RV32I-NEXT: addi a6, a0, 1365
-; RV32I-NEXT: srli t0, a2, 1
+; RV32I-NEXT: addi a6, t2, 1365
+; RV32I-NEXT: srli a3, a2, 1
+; RV32I-NEXT: sw a3, 208(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a2, a2, a6
-; RV32I-NEXT: and t0, t0, a6
+; RV32I-NEXT: and t0, a3, a6
; RV32I-NEXT: slli a2, a2, 1
; RV32I-NEXT: or t1, t0, a2
; RV32I-NEXT: srli a2, t1, 8
-; RV32I-NEXT: and a2, a2, s8
-; RV32I-NEXT: srli t0, t1, 24
-; RV32I-NEXT: and t3, t1, s8
+; RV32I-NEXT: lw t0, 4(a0)
+; RV32I-NEXT: and a2, a2, s10
+; RV32I-NEXT: srli t3, t1, 24
+; RV32I-NEXT: and t4, t1, s10
; RV32I-NEXT: slli a3, t1, 24
; RV32I-NEXT: sw a3, 472(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, t3, 8
-; RV32I-NEXT: or t0, a2, t0
-; RV32I-NEXT: or t3, a3, t3
-; RV32I-NEXT: lw t4, 4(t2)
-; RV32I-NEXT: lw a2, 8(t2)
+; RV32I-NEXT: slli t4, t4, 8
+; RV32I-NEXT: or a2, a2, t3
+; RV32I-NEXT: or t3, a3, t4
+; RV32I-NEXT: or t3, t3, a2
+; RV32I-NEXT: srli t4, t3, 4
+; RV32I-NEXT: lw a2, 8(a0)
; RV32I-NEXT: sw a2, 460(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s9, 12(t2)
-; RV32I-NEXT: or t0, t3, t0
+; RV32I-NEXT: lw a2, 12(a0)
+; RV32I-NEXT: sw a2, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a7
+; RV32I-NEXT: and t3, t3, a7
+; RV32I-NEXT: srli t6, t0, 8
+; RV32I-NEXT: slli t3, t3, 4
+; RV32I-NEXT: and t6, t6, s10
+; RV32I-NEXT: srli s0, t0, 24
+; RV32I-NEXT: and s1, t0, s10
+; RV32I-NEXT: slli s1, s1, 8
+; RV32I-NEXT: slli t0, t0, 24
+; RV32I-NEXT: or t6, t6, s0
+; RV32I-NEXT: or t0, t0, s1
+; RV32I-NEXT: or t4, t4, t3
+; RV32I-NEXT: or t0, t0, t6
; RV32I-NEXT: srli t3, t0, 4
; RV32I-NEXT: and t0, t0, a7
; RV32I-NEXT: and t3, t3, a7
; RV32I-NEXT: slli t0, t0, 4
+; RV32I-NEXT: srli t6, t4, 2
; RV32I-NEXT: or t0, t3, t0
-; RV32I-NEXT: srli t3, t4, 8
-; RV32I-NEXT: srli t6, t0, 2
-; RV32I-NEXT: and t3, t3, s8
-; RV32I-NEXT: srli s0, t4, 24
-; RV32I-NEXT: and s1, t4, s8
-; RV32I-NEXT: slli s1, s1, 8
-; RV32I-NEXT: slli t4, t4, 24
-; RV32I-NEXT: or t3, t3, s0
-; RV32I-NEXT: or t4, t4, s1
-; RV32I-NEXT: and t6, t6, s7
-; RV32I-NEXT: or t3, t4, t3
-; RV32I-NEXT: srli t4, t3, 4
-; RV32I-NEXT: and t3, t3, a7
-; RV32I-NEXT: and t4, t4, a7
-; RV32I-NEXT: slli t3, t3, 4
-; RV32I-NEXT: and t0, t0, s7
-; RV32I-NEXT: or t3, t4, t3
-; RV32I-NEXT: srli t4, t3, 2
-; RV32I-NEXT: and t3, t3, s7
-; RV32I-NEXT: and t4, t4, s7
-; RV32I-NEXT: slli t3, t3, 2
+; RV32I-NEXT: srli t3, t0, 2
+; RV32I-NEXT: and t0, t0, s9
+; RV32I-NEXT: and t3, t3, s9
; RV32I-NEXT: slli t0, t0, 2
-; RV32I-NEXT: or t3, t4, t3
-; RV32I-NEXT: srli t4, t3, 1
-; RV32I-NEXT: and t3, t3, a6
-; RV32I-NEXT: and t4, t4, a6
-; RV32I-NEXT: slli t3, t3, 1
-; RV32I-NEXT: or t0, t6, t0
-; RV32I-NEXT: or t4, t4, t3
-; RV32I-NEXT: srli t6, t0, 1
-; RV32I-NEXT: srli s0, t4, 8
-; RV32I-NEXT: and t6, t6, a6
-; RV32I-NEXT: and s0, s0, s8
-; RV32I-NEXT: srli s1, t4, 24
-; RV32I-NEXT: and s2, t4, s8
-; RV32I-NEXT: slli s3, t4, 24
-; RV32I-NEXT: slli s2, s2, 8
-; RV32I-NEXT: or s0, s0, s1
-; RV32I-NEXT: or s1, s3, s2
+; RV32I-NEXT: and t6, t6, s9
+; RV32I-NEXT: or t0, t3, t0
+; RV32I-NEXT: srli t3, t0, 1
; RV32I-NEXT: and t0, t0, a6
+; RV32I-NEXT: and s0, t3, a6
+; RV32I-NEXT: slli t3, t0, 1
+; RV32I-NEXT: and t0, t4, s9
+; RV32I-NEXT: or t4, s0, t3
+; RV32I-NEXT: slli t0, t0, 2
+; RV32I-NEXT: srli s0, t4, 8
+; RV32I-NEXT: or t6, t6, t0
+; RV32I-NEXT: and s0, s0, s10
+; RV32I-NEXT: srli t0, t4, 24
+; RV32I-NEXT: and s1, t4, s10
+; RV32I-NEXT: slli s2, t4, 24
+; RV32I-NEXT: slli s1, s1, 8
+; RV32I-NEXT: or s0, s0, t0
+; RV32I-NEXT: or s1, s2, s1
+; RV32I-NEXT: srli t0, t6, 1
; RV32I-NEXT: or s0, s1, s0
; RV32I-NEXT: srli s1, s0, 4
; RV32I-NEXT: and s0, s0, a7
; RV32I-NEXT: and s1, s1, a7
; RV32I-NEXT: slli s0, s0, 4
-; RV32I-NEXT: slli t0, t0, 1
+; RV32I-NEXT: and s2, t0, a6
; RV32I-NEXT: or s0, s1, s0
; RV32I-NEXT: srli s1, s0, 2
-; RV32I-NEXT: and s0, s0, s7
-; RV32I-NEXT: and s1, s1, s7
+; RV32I-NEXT: and s0, s0, s9
+; RV32I-NEXT: and s1, s1, s9
; RV32I-NEXT: slli s0, s0, 2
-; RV32I-NEXT: or t0, t6, t0
+; RV32I-NEXT: and s3, t6, a6
; RV32I-NEXT: or s0, s1, s0
; RV32I-NEXT: srli t6, s0, 1
; RV32I-NEXT: and s0, s0, a6
; RV32I-NEXT: and s1, t6, a6
; RV32I-NEXT: slli t6, s0, 1
-; RV32I-NEXT: slli s2, t0, 1
-; RV32I-NEXT: or s0, s1, t6
-; RV32I-NEXT: andi s1, s0, 2
-; RV32I-NEXT: andi s3, s0, 1
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, s3, t0
-; RV32I-NEXT: xor s1, s2, s1
-; RV32I-NEXT: andi s2, s0, 4
-; RV32I-NEXT: slli s3, t0, 2
+; RV32I-NEXT: slli s3, s3, 1
+; RV32I-NEXT: or s1, s1, t6
+; RV32I-NEXT: or s0, s2, s3
+; RV32I-NEXT: andi s2, s1, 2
+; RV32I-NEXT: slli s3, s0, 1
; RV32I-NEXT: seqz s2, s2
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: andi s4, s0, 8
+; RV32I-NEXT: andi s5, s1, 1
; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t0, 3
+; RV32I-NEXT: seqz s3, s5
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 16
+; RV32I-NEXT: andi s5, s1, 4
+; RV32I-NEXT: slli s6, s0, 2
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: andi s7, s1, 8
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: slli s7, s0, 3
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: and s3, s3, s0
+; RV32I-NEXT: and s6, s6, s7
+; RV32I-NEXT: xor s2, s3, s2
+; RV32I-NEXT: xor s3, s5, s6
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t0, 4
+; RV32I-NEXT: andi s3, s1, 16
+; RV32I-NEXT: slli s5, s0, 4
+; RV32I-NEXT: seqz s3, s3
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 32
-; RV32I-NEXT: slli s5, t0, 5
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: andi s6, s0, 64
-; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: andi s6, s1, 32
+; RV32I-NEXT: and s3, s3, s5
; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: slli s6, t0, 6
+; RV32I-NEXT: slli s6, s0, 5
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: xor s2, s3, s4
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: andi s2, s0, 128
-; RV32I-NEXT: slli s3, t0, 7
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: andi s4, s0, 256
-; RV32I-NEXT: and s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t0, 8
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 512
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t0, 9
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: andi s4, s0, 1024
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: slli s4, t0, 10
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: li s4, 1
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: slli s11, s4, 11
-; RV32I-NEXT: slli s3, t0, 11
-; RV32I-NEXT: and s4, s0, s11
-; RV32I-NEXT: seqz s4, s4
-; RV32I-NEXT: lui a4, 1
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: and s5, s0, a4
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lui a2, 2
-; RV32I-NEXT: slli s5, t0, 12
-; RV32I-NEXT: and s6, s0, a2
-; RV32I-NEXT: lui a3, 2
-; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: andi s6, s1, 64
+; RV32I-NEXT: xor s3, s3, s5
; RV32I-NEXT: seqz s5, s6
-; RV32I-NEXT: xor s3, s3, s4
+; RV32I-NEXT: slli s6, s0, 6
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s4, t0, 13
-; RV32I-NEXT: lui s6, 4
-; RV32I-NEXT: and s4, s5, s4
-; RV32I-NEXT: and s5, s0, s6
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: lui s6, 8
-; RV32I-NEXT: slli s5, t0, 14
-; RV32I-NEXT: and s6, s0, s6
-; RV32I-NEXT: and s4, s4, s5
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: andi s6, s1, 128
+; RV32I-NEXT: xor s3, s3, s5
; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: slli s6, s0, 7
; RV32I-NEXT: addi s5, s5, -1
-; RV32I-NEXT: slli s6, t0, 15
-; RV32I-NEXT: xor s3, s3, s4
-; RV32I-NEXT: and s4, s5, s6
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: xor s2, s3, s4
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: lui a0, 16
-; RV32I-NEXT: and s2, s0, a0
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: lui a2, 32
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, a2
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: slli s4, t0, 16
-; RV32I-NEXT: and s2, s2, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t0, 17
-; RV32I-NEXT: lui s5, 64
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: and s4, s0, s5
-; RV32I-NEXT: lui s6, 64
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui s5, 128
-; RV32I-NEXT: slli s4, t0, 18
-; RV32I-NEXT: and s5, s0, s5
-; RV32I-NEXT: lui t5, 128
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t0, 19
-; RV32I-NEXT: lui s5, 256
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, s5
-; RV32I-NEXT: lui ra, 256
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: andi s6, s1, 256
+; RV32I-NEXT: slli s7, s0, 8
+; RV32I-NEXT: seqz s6, s6
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: andi s8, s1, 512
+; RV32I-NEXT: and s6, s6, s7
+; RV32I-NEXT: seqz s7, s8
+; RV32I-NEXT: addi s7, s7, -1
+; RV32I-NEXT: slli s8, s0, 9
+; RV32I-NEXT: xor s5, s5, s6
+; RV32I-NEXT: and s6, s7, s8
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui s5, 512
-; RV32I-NEXT: slli s4, t0, 20
-; RV32I-NEXT: and s5, s0, s5
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s5, t0, 21
+; RV32I-NEXT: xor s3, s5, s6
+; RV32I-NEXT: slli s5, s0, 10
+; RV32I-NEXT: andi s6, s1, 1024
+; RV32I-NEXT: seqz s6, s6
+; RV32I-NEXT: li s7, 1
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli a4, s7, 11
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and s6, s1, a4
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui s7, 1
+; RV32I-NEXT: slli s6, s0, 11
+; RV32I-NEXT: and s7, s1, s7
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: lui s8, 2
+; RV32I-NEXT: slli s7, s0, 12
+; RV32I-NEXT: and s8, s1, s8
+; RV32I-NEXT: and s6, s6, s7
+; RV32I-NEXT: seqz s7, s8
+; RV32I-NEXT: xor s5, s5, s6
+; RV32I-NEXT: addi s7, s7, -1
+; RV32I-NEXT: slli s6, s0, 13
+; RV32I-NEXT: lui s8, 4
+; RV32I-NEXT: and s6, s7, s6
+; RV32I-NEXT: and s7, s1, s8
+; RV32I-NEXT: xor s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: lui s8, 8
+; RV32I-NEXT: slli s7, s0, 14
+; RV32I-NEXT: and s8, s1, s8
+; RV32I-NEXT: and s6, s6, s7
+; RV32I-NEXT: seqz s7, s8
+; RV32I-NEXT: addi s7, s7, -1
+; RV32I-NEXT: slli s8, s0, 15
+; RV32I-NEXT: xor s5, s5, s6
+; RV32I-NEXT: and s6, s7, s8
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: and s3, s4, s5
+; RV32I-NEXT: xor s3, s5, s6
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: lui s3, 1024
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: and s2, s0, s3
-; RV32I-NEXT: seqz s2, s2
-; RV32I-NEXT: lui s3, 2048
-; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s3
+; RV32I-NEXT: lui a2, 16
+; RV32I-NEXT: and s3, s1, a2
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: slli s4, t0, 22
-; RV32I-NEXT: and s2, s2, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t0, 23
-; RV32I-NEXT: lui s5, 4096
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: and s4, s0, s5
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui s5, 8192
-; RV32I-NEXT: slli s4, t0, 24
-; RV32I-NEXT: and s5, s0, s5
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t0, 25
-; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a5
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: lui a5, 32768
-; RV32I-NEXT: slli s4, t0, 26
-; RV32I-NEXT: and s5, s0, a5
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: seqz s4, s5
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: addi s4, s4, -1
-; RV32I-NEXT: slli s3, t0, 27
-; RV32I-NEXT: lui a2, 65536
-; RV32I-NEXT: and s3, s4, s3
-; RV32I-NEXT: and s4, s0, a2
-; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: seqz s3, s4
+; RV32I-NEXT: lui a3, 32
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: slli s4, t0, 28
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: lui a2, 131072
+; RV32I-NEXT: and s5, s1, a3
+; RV32I-NEXT: lui t5, 32
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s0, 16
+; RV32I-NEXT: and s3, s3, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s6, s0, 17
+; RV32I-NEXT: lui s7, 64
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: and s6, s1, s7
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui s7, 128
+; RV32I-NEXT: slli s6, s0, 18
+; RV32I-NEXT: and s7, s1, s7
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s0, 19
+; RV32I-NEXT: lui s7, 256
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and s6, s1, s7
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui s7, 512
+; RV32I-NEXT: slli s6, s0, 20
+; RV32I-NEXT: and s7, s1, s7
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s7, s0, 21
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: and s5, s6, s7
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: lui a3, 1024
; RV32I-NEXT: xor s2, s2, s3
-; RV32I-NEXT: and s3, s0, a2
+; RV32I-NEXT: and s3, s1, a3
; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: lui a2, 262144
+; RV32I-NEXT: lui a3, 2048
; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli s4, t0, 29
-; RV32I-NEXT: and s3, s3, s4
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and s5, s1, a3
+; RV32I-NEXT: lui s11, 2048
+; RV32I-NEXT: seqz s5, s5
+; RV32I-NEXT: slli s6, s0, 22
+; RV32I-NEXT: and s3, s3, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: slli s6, s0, 23
+; RV32I-NEXT: lui a3, 4096
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui a3, 8192
+; RV32I-NEXT: slli s6, s0, 24
+; RV32I-NEXT: and s7, s1, a3
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s0, 25
+; RV32I-NEXT: lui a3, 16384
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui a3, 32768
+; RV32I-NEXT: slli s6, s0, 26
+; RV32I-NEXT: and s7, s1, a3
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s0, 27
+; RV32I-NEXT: lui a3, 65536
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and s6, s1, a3
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: seqz s5, s6
+; RV32I-NEXT: addi s5, s5, -1
+; RV32I-NEXT: lui a3, 131072
+; RV32I-NEXT: slli s6, s0, 28
+; RV32I-NEXT: and s7, s1, a3
+; RV32I-NEXT: and s5, s5, s6
+; RV32I-NEXT: seqz s6, s7
+; RV32I-NEXT: xor s3, s3, s5
+; RV32I-NEXT: addi s6, s6, -1
+; RV32I-NEXT: slli s5, s0, 29
+; RV32I-NEXT: lui a3, 262144
+; RV32I-NEXT: and s5, s6, s5
+; RV32I-NEXT: and s1, s1, a3
+; RV32I-NEXT: slli s0, s0, 30
+; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: srli t6, t6, 31
-; RV32I-NEXT: slli s4, t0, 30
-; RV32I-NEXT: and s0, s0, s4
+; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz t6, t6
; RV32I-NEXT: slli t0, t0, 31
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: xor s0, s3, s0
+; RV32I-NEXT: xor s0, s5, s0
; RV32I-NEXT: and t0, t6, t0
-; RV32I-NEXT: xor t6, s1, s2
+; RV32I-NEXT: xor t6, s2, s3
; RV32I-NEXT: xor t0, s0, t0
; RV32I-NEXT: xor t0, t6, t0
; RV32I-NEXT: srli t6, t0, 8
-; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: and t6, t6, s8
+; RV32I-NEXT: and t6, t6, s10
; RV32I-NEXT: srli s0, t0, 24
-; RV32I-NEXT: and s1, t0, s8
+; RV32I-NEXT: and s1, t0, s10
; RV32I-NEXT: slli t0, t0, 24
; RV32I-NEXT: slli s1, s1, 8
; RV32I-NEXT: or t6, t6, s0
; RV32I-NEXT: or t0, t0, s1
-; RV32I-NEXT: srli s0, a1, 8
-; RV32I-NEXT: and s1, a1, s8
-; RV32I-NEXT: and s0, s0, s8
-; RV32I-NEXT: slli s1, s1, 8
-; RV32I-NEXT: srli s2, a1, 24
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or s0, s0, s2
-; RV32I-NEXT: or a1, a1, s1
; RV32I-NEXT: or t0, t0, t6
-; RV32I-NEXT: or a1, a1, s0
+; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: srli t6, t0, 4
; RV32I-NEXT: and t0, t0, a7
; RV32I-NEXT: and t6, t6, a7
; RV32I-NEXT: slli t0, t0, 4
-; RV32I-NEXT: srli s0, a1, 4
-; RV32I-NEXT: and a1, a1, a7
-; RV32I-NEXT: and s0, s0, a7
-; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or t0, t6, t0
-; RV32I-NEXT: or a1, s0, a1
-; RV32I-NEXT: srli t6, a1, 2
-; RV32I-NEXT: and a1, a1, s7
-; RV32I-NEXT: and t6, t6, s7
-; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: or t6, t6, a1
-; RV32I-NEXT: srli a1, t0, 2
-; RV32I-NEXT: and a1, a1, s7
-; RV32I-NEXT: and t0, t0, s7
+; RV32I-NEXT: srli t6, a1, 8
+; RV32I-NEXT: and s0, a1, s10
+; RV32I-NEXT: and t6, t6, s10
+; RV32I-NEXT: slli s0, s0, 8
+; RV32I-NEXT: srli s1, a1, 24
+; RV32I-NEXT: slli a1, a1, 24
+; RV32I-NEXT: or t6, t6, s1
+; RV32I-NEXT: or a1, a1, s0
+; RV32I-NEXT: srli s0, t0, 2
+; RV32I-NEXT: and t0, t0, s9
+; RV32I-NEXT: and s0, s0, s9
; RV32I-NEXT: slli t0, t0, 2
-; RV32I-NEXT: srli s0, t6, 1
-; RV32I-NEXT: or a1, a1, t0
-; RV32I-NEXT: and t0, s0, a6
-; RV32I-NEXT: and t6, t6, a6
-; RV32I-NEXT: andi s0, t4, 2
+; RV32I-NEXT: or s0, s0, t0
+; RV32I-NEXT: or a1, a1, t6
+; RV32I-NEXT: srli t0, a1, 4
+; RV32I-NEXT: and a1, a1, a7
+; RV32I-NEXT: and t0, t0, a7
+; RV32I-NEXT: slli a1, a1, 4
+; RV32I-NEXT: or a1, t0, a1
+; RV32I-NEXT: addi a3, t2, 1364
+; RV32I-NEXT: sw a3, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli t2, s0, 1
+; RV32I-NEXT: and t6, s0, a6
+; RV32I-NEXT: and t2, t2, a3
; RV32I-NEXT: slli t6, t6, 1
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: or t6, t0, t6
-; RV32I-NEXT: addi a2, s0, -1
-; RV32I-NEXT: sw a2, 456(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, t6, 1
+; RV32I-NEXT: srli s0, a1, 2
+; RV32I-NEXT: and a1, a1, s9
+; RV32I-NEXT: and s0, s0, s9
+; RV32I-NEXT: slli a1, a1, 2
+; RV32I-NEXT: or a3, t2, t6
+; RV32I-NEXT: sw a3, 192(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or s0, s0, a1
+; RV32I-NEXT: srli a5, s0, 1
+; RV32I-NEXT: and t2, s0, a6
+; RV32I-NEXT: slli t2, t2, 1
+; RV32I-NEXT: andi t6, t4, 2
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: and s0, a5, a6
+; RV32I-NEXT: or t2, s0, t2
+; RV32I-NEXT: addi a3, t6, -1
+; RV32I-NEXT: sw a3, 456(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t6, t2, 1
; RV32I-NEXT: andi s0, t4, 1
-; RV32I-NEXT: and t0, a2, t0
+; RV32I-NEXT: and t6, a3, t6
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: addi a2, s0, -1
-; RV32I-NEXT: sw a2, 452(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a3, s0, -1
+; RV32I-NEXT: sw a3, 452(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi s0, t4, 4
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: and s1, a2, t6
-; RV32I-NEXT: xor t0, s1, t0
-; RV32I-NEXT: addi a2, s0, -1
-; RV32I-NEXT: sw a2, 448(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t6, 2
+; RV32I-NEXT: and s1, a3, t2
+; RV32I-NEXT: xor t6, s1, t6
+; RV32I-NEXT: addi a3, s0, -1
+; RV32I-NEXT: sw a3, 448(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t2, 2
; RV32I-NEXT: andi s1, t4, 8
-; RV32I-NEXT: and s0, a2, s0
+; RV32I-NEXT: and s0, a3, s0
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 444(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 3
-; RV32I-NEXT: and s1, a2, s1
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 444(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 3
+; RV32I-NEXT: and s1, a3, s1
; RV32I-NEXT: andi s2, t4, 16
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: xor t0, t0, s0
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 440(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t6, 4
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 440(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t2, 4
; RV32I-NEXT: andi s1, t4, 32
-; RV32I-NEXT: and s0, a2, s0
+; RV32I-NEXT: and s0, a3, s0
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 436(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 5
-; RV32I-NEXT: and s1, a2, s1
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 436(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 5
+; RV32I-NEXT: and s1, a3, s1
; RV32I-NEXT: andi s2, t4, 64
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 432(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 6
-; RV32I-NEXT: and s1, a2, s1
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 432(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 6
+; RV32I-NEXT: and s1, a3, s1
; RV32I-NEXT: andi s2, t4, 128
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: xor t0, t0, s0
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 428(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t6, 7
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 428(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t2, 7
; RV32I-NEXT: andi s1, t4, 256
-; RV32I-NEXT: and s0, a2, s0
+; RV32I-NEXT: and s0, a3, s0
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 424(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 8
-; RV32I-NEXT: and s1, a2, s1
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 424(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 8
+; RV32I-NEXT: and s1, a3, s1
; RV32I-NEXT: andi s2, t4, 512
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 420(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 9
-; RV32I-NEXT: and s1, a2, s1
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 420(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 9
+; RV32I-NEXT: and s1, a3, s1
; RV32I-NEXT: andi s2, t4, 1024
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: addi a2, s1, -1
-; RV32I-NEXT: sw a2, 416(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 10
-; RV32I-NEXT: and s1, a2, s1
-; RV32I-NEXT: and s2, t4, s11
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 416(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 10
+; RV32I-NEXT: and s1, a3, s1
+; RV32I-NEXT: mv s8, a4
+; RV32I-NEXT: and s2, t4, a4
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: xor t0, t0, s0
-; RV32I-NEXT: addi a5, s1, -1
-; RV32I-NEXT: sw a5, 412(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t6, 11
-; RV32I-NEXT: and s1, t4, a4
-; RV32I-NEXT: and s0, a5, s0
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 412(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t2, 11
+; RV32I-NEXT: lui s3, 1
+; RV32I-NEXT: and s1, t4, s3
+; RV32I-NEXT: and s0, a3, s0
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: addi a5, s1, -1
-; RV32I-NEXT: sw a5, 408(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 12
-; RV32I-NEXT: and s1, a5, s1
-; RV32I-NEXT: and s2, t4, a3
+; RV32I-NEXT: addi a3, s1, -1
+; RV32I-NEXT: sw a3, 408(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 12
+; RV32I-NEXT: and s1, a3, s1
+; RV32I-NEXT: lui s5, 2
+; RV32I-NEXT: and s2, t4, s5
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 404(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 13
+; RV32I-NEXT: slli s1, t2, 13
; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: lui s4, 4
-; RV32I-NEXT: and s2, t4, s4
+; RV32I-NEXT: lui s6, 4
+; RV32I-NEXT: and s2, t4, s6
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 400(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 14
+; RV32I-NEXT: slli s1, t2, 14
; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: lui s5, 8
-; RV32I-NEXT: and s2, t4, s5
+; RV32I-NEXT: lui s7, 8
+; RV32I-NEXT: and s2, t4, s7
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 396(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 15
+; RV32I-NEXT: slli s1, t2, 15
; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: and s2, t4, a0
+; RV32I-NEXT: and s2, t4, a2
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: xor t0, t0, s0
-; RV32I-NEXT: addi a3, s1, -1
-; RV32I-NEXT: sw a3, 392(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s0, t6, 16
-; RV32I-NEXT: lui a0, 32
-; RV32I-NEXT: and s1, t4, a0
-; RV32I-NEXT: and s0, a3, s0
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi a2, s1, -1
+; RV32I-NEXT: sw a2, 392(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t2, 16
+; RV32I-NEXT: and s1, t4, t5
+; RV32I-NEXT: and s0, a2, s0
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: addi a3, s1, -1
-; RV32I-NEXT: sw a3, 388(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 17
-; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: and s2, t4, s6
+; RV32I-NEXT: addi a2, s1, -1
+; RV32I-NEXT: sw a2, 388(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 17
+; RV32I-NEXT: and s1, a2, s1
+; RV32I-NEXT: lui a2, 64
+; RV32I-NEXT: and s2, t4, a2
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi a3, s1, -1
; RV32I-NEXT: sw a3, 384(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 18
+; RV32I-NEXT: slli s1, t2, 18
; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: and s2, t4, t5
+; RV32I-NEXT: lui t0, 128
+; RV32I-NEXT: and s2, t4, t0
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: addi a3, s1, -1
-; RV32I-NEXT: sw a3, 380(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 19
-; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: and s2, t4, ra
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 380(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 19
+; RV32I-NEXT: and s1, a4, s1
+; RV32I-NEXT: lui s4, 256
+; RV32I-NEXT: and s2, t4, s4
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: addi a3, s1, -1
-; RV32I-NEXT: sw a3, 376(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 20
-; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: lui a0, 512
-; RV32I-NEXT: and s2, t4, a0
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 376(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 20
+; RV32I-NEXT: and s1, a4, s1
+; RV32I-NEXT: lui a1, 512
+; RV32I-NEXT: and s2, t4, a1
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: addi a3, s1, -1
-; RV32I-NEXT: sw a3, 372(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 21
-; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: lui a0, 1024
-; RV32I-NEXT: and s2, t4, a0
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 372(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 21
+; RV32I-NEXT: and s1, a4, s1
+; RV32I-NEXT: lui a1, 1024
+; RV32I-NEXT: and s2, t4, a1
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
-; RV32I-NEXT: addi a3, s1, -1
-; RV32I-NEXT: sw a3, 368(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui a0, 2048
-; RV32I-NEXT: and s1, t4, a0
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 368(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t2, 22
+; RV32I-NEXT: and s1, t4, s11
+; RV32I-NEXT: and s0, a4, s0
; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: slli s2, t6, 22
-; RV32I-NEXT: and s2, a3, s2
-; RV32I-NEXT: addi a3, s1, -1
-; RV32I-NEXT: sw a3, 364(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s1, t6, 23
-; RV32I-NEXT: lui a0, 4096
-; RV32I-NEXT: and s3, t4, a0
-; RV32I-NEXT: and s1, a3, s1
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: xor s1, s2, s1
-; RV32I-NEXT: addi a3, s3, -1
-; RV32I-NEXT: sw a3, 360(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s2, t6, 24
-; RV32I-NEXT: lui ra, 8192
-; RV32I-NEXT: and s3, t4, ra
-; RV32I-NEXT: and s2, a3, s2
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: addi a3, s3, -1
-; RV32I-NEXT: sw a3, 356(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s2, t6, 25
-; RV32I-NEXT: lui s6, 16384
-; RV32I-NEXT: and s3, t4, s6
-; RV32I-NEXT: and s2, a3, s2
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: addi a3, s3, -1
-; RV32I-NEXT: sw a3, 352(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s2, t6, 26
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 364(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 23
+; RV32I-NEXT: and s1, a4, s1
+; RV32I-NEXT: lui ra, 4096
+; RV32I-NEXT: and s2, t4, ra
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 360(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 24
+; RV32I-NEXT: and s1, a4, s1
+; RV32I-NEXT: lui s11, 8192
+; RV32I-NEXT: and s2, t4, s11
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 356(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 25
+; RV32I-NEXT: and s1, a4, s1
+; RV32I-NEXT: lui a1, 16384
+; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: addi a4, s1, -1
+; RV32I-NEXT: sw a4, 352(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 26
+; RV32I-NEXT: and s1, a4, s1
; RV32I-NEXT: lui t5, 32768
-; RV32I-NEXT: and s3, t4, t5
-; RV32I-NEXT: and s2, a3, s2
-; RV32I-NEXT: seqz s3, s3
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: addi s3, s3, -1
-; RV32I-NEXT: sw s3, 348(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s2, t6, 27
-; RV32I-NEXT: lui a5, 65536
-; RV32I-NEXT: and a0, t4, a5
-; RV32I-NEXT: and s2, s3, s2
-; RV32I-NEXT: seqz s3, a0
-; RV32I-NEXT: addi a0, s3, -1
-; RV32I-NEXT: sw a0, 344(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli s3, t6, 28
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: and s2, a0, s3
-; RV32I-NEXT: xor s0, t0, s0
-; RV32I-NEXT: xor s1, s1, s2
-; RV32I-NEXT: lw a0, 0(t2)
-; RV32I-NEXT: lui t0, 349525
-; RV32I-NEXT: addi t0, t0, 1364
-; RV32I-NEXT: srli t2, a1, 1
-; RV32I-NEXT: and a1, a1, a6
-; RV32I-NEXT: and t2, t2, t0
-; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: or a1, t2, a1
-; RV32I-NEXT: sw a1, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s2, t4, t5
; RV32I-NEXT: xor s0, s0, s1
-; RV32I-NEXT: srli t2, a0, 8
-; RV32I-NEXT: and s1, a0, s8
-; RV32I-NEXT: and t2, t2, s8
-; RV32I-NEXT: slli s1, s1, 8
-; RV32I-NEXT: srli s2, a0, 24
+; RV32I-NEXT: seqz s1, s2
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: addi s1, s1, -1
+; RV32I-NEXT: sw s1, 348(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a1, t2, 27
+; RV32I-NEXT: lui a4, 65536
+; RV32I-NEXT: and s2, t4, a4
+; RV32I-NEXT: and a1, s1, a1
+; RV32I-NEXT: seqz s2, s2
+; RV32I-NEXT: addi s2, s2, -1
+; RV32I-NEXT: sw s2, 340(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 28
+; RV32I-NEXT: xor s0, s0, a1
+; RV32I-NEXT: and s1, s2, s1
+; RV32I-NEXT: xor s0, s0, s1
+; RV32I-NEXT: srli s1, a0, 8
+; RV32I-NEXT: xor t6, t6, s0
+; RV32I-NEXT: and s1, s1, s10
+; RV32I-NEXT: srli s0, a0, 24
+; RV32I-NEXT: and s2, a0, s10
+; RV32I-NEXT: or s0, s1, s0
+; RV32I-NEXT: slli s2, s2, 8
; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or t2, t2, s2
-; RV32I-NEXT: or a2, a0, s1
-; RV32I-NEXT: lui s2, 131072
-; RV32I-NEXT: and s1, t4, s2
-; RV32I-NEXT: lui a3, 262144
-; RV32I-NEXT: and t4, t4, a3
+; RV32I-NEXT: lui a3, 131072
+; RV32I-NEXT: and s1, t4, a3
+; RV32I-NEXT: or a0, a0, s2
; RV32I-NEXT: seqz s1, s1
+; RV32I-NEXT: addi a1, s1, -1
+; RV32I-NEXT: sw a1, 336(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s2, 262144
+; RV32I-NEXT: and t4, t4, s2
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: sw s1, 336(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s1, t2, 29
+; RV32I-NEXT: slli t2, t2, 30
; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: sw t4, 332(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a1, t6, 29
-; RV32I-NEXT: slli a0, t6, 30
-; RV32I-NEXT: and a1, s1, a1
-; RV32I-NEXT: and s1, t4, a0
-; RV32I-NEXT: xor t4, a1, s1
-; RV32I-NEXT: or a0, a2, t2
-; RV32I-NEXT: srli t2, a0, 4
+; RV32I-NEXT: and s1, a1, s1
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: xor t2, s1, t2
+; RV32I-NEXT: or a0, a0, s0
+; RV32I-NEXT: srli t4, a0, 4
; RV32I-NEXT: and a0, a0, a7
-; RV32I-NEXT: and t2, t2, a7
+; RV32I-NEXT: and t4, t4, a7
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: or a0, t2, a0
-; RV32I-NEXT: srli t2, t3, 31
-; RV32I-NEXT: srli t3, a0, 2
-; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and t3, t3, s7
+; RV32I-NEXT: or a0, t4, a0
+; RV32I-NEXT: srli t3, t3, 31
+; RV32I-NEXT: srli t4, a0, 2
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and t4, t4, s9
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: or a0, t3, a0
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: slli t6, t6, 31
-; RV32I-NEXT: addi a1, t2, -1
-; RV32I-NEXT: sw a1, 328(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli t2, a0, 1
+; RV32I-NEXT: or a0, t4, a0
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: slli a1, a5, 31
+; RV32I-NEXT: addi a5, t3, -1
+; RV32I-NEXT: sw a5, 328(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli t3, a0, 1
; RV32I-NEXT: and a0, a0, a6
-; RV32I-NEXT: and t2, t2, a6
+; RV32I-NEXT: and t3, t3, a6
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: and t3, a1, t6
-; RV32I-NEXT: or t2, t2, a0
-; RV32I-NEXT: xor t3, t4, t3
-; RV32I-NEXT: andi t4, t2, 2
+; RV32I-NEXT: and t4, a5, a1
+; RV32I-NEXT: or a1, t3, a0
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: andi t3, a1, 2
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: andi t4, a1, 1
+; RV32I-NEXT: addi t3, t3, -1
; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: andi t6, t2, 1
; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: slli a5, t1, 1
+; RV32I-NEXT: sw a5, 324(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s0, t3, a5
+; RV32I-NEXT: and t4, t4, t1
+; RV32I-NEXT: xor t3, t6, t2
+; RV32I-NEXT: xor t2, t4, s0
+; RV32I-NEXT: andi t4, a1, 4
+; RV32I-NEXT: andi t6, a1, 8
+; RV32I-NEXT: seqz t4, t4
; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: slli a1, t1, 1
-; RV32I-NEXT: sw a1, 324(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t4, t4, a1
-; RV32I-NEXT: and t6, t6, t1
-; RV32I-NEXT: xor s3, s0, t3
-; RV32I-NEXT: xor t4, t6, t4
-; RV32I-NEXT: andi t6, t2, 4
-; RV32I-NEXT: andi s0, t2, 8
-; RV32I-NEXT: seqz t6, t6
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli a1, t1, 2
-; RV32I-NEXT: sw a1, 320(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, t1, 3
-; RV32I-NEXT: sw a2, 316(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t6, t6, a1
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: andi s0, t2, 16
+; RV32I-NEXT: slli a5, t1, 2
+; RV32I-NEXT: sw a5, 320(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli s0, t1, 3
+; RV32I-NEXT: sw s0, 316(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a5
+; RV32I-NEXT: and t6, t6, s0
; RV32I-NEXT: xor t4, t4, t6
-; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: andi t6, a1, 16
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: seqz t4, t6
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: andi t6, a1, 32
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: slli a5, t1, 4
+; RV32I-NEXT: sw a5, 312(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a5
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: andi s0, t2, 32
+; RV32I-NEXT: slli a5, t1, 5
+; RV32I-NEXT: sw a5, 308(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi s0, a1, 64
+; RV32I-NEXT: and t6, t6, a5
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli a1, t1, 4
-; RV32I-NEXT: sw a1, 312(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t6, t6, a1
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli a1, t1, 5
-; RV32I-NEXT: sw a1, 308(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s1, t2, 64
-; RV32I-NEXT: and s0, s0, a1
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli a1, t1, 6
-; RV32I-NEXT: sw a1, 304(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: and s0, s1, a1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: andi s0, t2, 128
+; RV32I-NEXT: slli a5, t1, 6
+; RV32I-NEXT: sw a5, 304(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor t4, t4, t6
-; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: and t6, s0, a5
+; RV32I-NEXT: xor t4, t4, t6
+; RV32I-NEXT: andi t6, a1, 128
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: seqz t4, t6
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: andi t6, a1, 256
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: slli a5, t1, 7
+; RV32I-NEXT: sw a5, 300(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a5
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: andi s0, t2, 256
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli a1, t1, 7
-; RV32I-NEXT: sw a1, 300(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t6, t6, a1
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli a1, t1, 8
-; RV32I-NEXT: sw a1, 296(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s1, t2, 512
-; RV32I-NEXT: and s0, s0, a1
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli a1, t1, 9
-; RV32I-NEXT: sw a1, 292(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi s0, t2, 1024
-; RV32I-NEXT: and s1, s1, a1
+; RV32I-NEXT: slli a5, t1, 8
+; RV32I-NEXT: sw a5, 296(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi s0, a1, 512
+; RV32I-NEXT: and t6, t6, a5
; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: xor t4, t4, t6
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli a1, t1, 10
-; RV32I-NEXT: sw a1, 288(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor t6, t6, s1
-; RV32I-NEXT: and s0, s0, a1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: mv a1, s11
-; RV32I-NEXT: and s0, t2, s11
+; RV32I-NEXT: slli a5, t1, 9
+; RV32I-NEXT: sw a5, 292(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi t6, a1, 1024
+; RV32I-NEXT: and s0, s0, a5
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: slli a5, t1, 10
+; RV32I-NEXT: sw a5, 288(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor t4, t4, s0
+; RV32I-NEXT: and t6, t6, a5
; RV32I-NEXT: xor t4, t4, t6
-; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: and t6, a1, s8
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: seqz t4, t6
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: and t6, a1, s3
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: slli a5, t1, 11
+; RV32I-NEXT: sw a5, 284(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a5
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: and s0, t2, a4
+; RV32I-NEXT: slli a5, t1, 12
+; RV32I-NEXT: sw a5, 280(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s0, a1, s5
+; RV32I-NEXT: and t6, t6, a5
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli a2, t1, 11
-; RV32I-NEXT: sw a2, 284(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: xor t4, t4, t6
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli a2, t1, 12
-; RV32I-NEXT: sw a2, 280(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui t3, 2
-; RV32I-NEXT: and s1, t2, t3
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli a2, t1, 13
-; RV32I-NEXT: sw a2, 276(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s0, t2, s4
-; RV32I-NEXT: and s1, s1, a2
+; RV32I-NEXT: slli a5, t1, 13
+; RV32I-NEXT: sw a5, 276(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t6, a1, s6
+; RV32I-NEXT: and s0, s0, a5
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: xor t4, t4, s0
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: slli a5, t1, 14
+; RV32I-NEXT: sw a5, 272(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s0, a1, s7
+; RV32I-NEXT: and t6, t6, a5
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: xor t6, t6, s1
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli a2, t1, 14
-; RV32I-NEXT: sw a2, 272(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s1, t2, s5
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli a2, t1, 15
-; RV32I-NEXT: sw a2, 268(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: and s0, s1, a2
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: lui a2, 16
-; RV32I-NEXT: and s0, t2, a2
+; RV32I-NEXT: slli a5, t1, 15
+; RV32I-NEXT: sw a5, 268(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor t4, t4, t6
-; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: and t6, s0, a5
+; RV32I-NEXT: xor t4, t4, t6
+; RV32I-NEXT: lui a5, 16
+; RV32I-NEXT: and t6, a1, a5
+; RV32I-NEXT: lui s5, 16
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: seqz t4, t6
+; RV32I-NEXT: addi t4, t4, -1
+; RV32I-NEXT: lui a5, 32
+; RV32I-NEXT: and t6, a1, a5
+; RV32I-NEXT: lui s7, 32
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: slli a5, t1, 16
+; RV32I-NEXT: sw a5, 264(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t4, t4, a5
; RV32I-NEXT: addi t6, t6, -1
-; RV32I-NEXT: lui a4, 32
-; RV32I-NEXT: and s0, t2, a4
+; RV32I-NEXT: slli a5, t1, 17
+; RV32I-NEXT: sw a5, 260(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and s0, a1, a2
+; RV32I-NEXT: and t6, t6, a5
; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: slli a2, t1, 16
-; RV32I-NEXT: sw a2, 264(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: xor t4, t4, t6
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli a2, t1, 17
-; RV32I-NEXT: sw a2, 260(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s1, 64
-; RV32I-NEXT: and s1, t2, s1
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: slli a2, t1, 18
; RV32I-NEXT: sw a2, 256(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s0, 128
-; RV32I-NEXT: and s0, t2, s0
-; RV32I-NEXT: and s1, s1, a2
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: xor t6, t6, s1
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and t6, a1, t0
+; RV32I-NEXT: and s0, s0, a2
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: xor t4, t4, s0
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a2, t1, 19
; RV32I-NEXT: sw a2, 252(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s1, 256
-; RV32I-NEXT: and s1, t2, s1
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli a2, t1, 20
-; RV32I-NEXT: sw a2, 248(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s0, 512
-; RV32I-NEXT: and s0, t2, s0
-; RV32I-NEXT: and s1, s1, a2
+; RV32I-NEXT: and s0, a1, s4
+; RV32I-NEXT: and t6, t6, a2
; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: xor t4, t4, t6
; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: slli a2, t1, 20
+; RV32I-NEXT: sw a2, 248(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a5, 512
+; RV32I-NEXT: and t6, a1, a5
+; RV32I-NEXT: and s0, s0, a2
+; RV32I-NEXT: seqz t6, t6
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a2, t1, 21
; RV32I-NEXT: sw a2, 244(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor t6, t6, s1
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: lui a2, 1024
-; RV32I-NEXT: and s0, t2, a2
+; RV32I-NEXT: xor t4, t4, s0
+; RV32I-NEXT: and t6, t6, a2
; RV32I-NEXT: xor t4, t4, t6
-; RV32I-NEXT: seqz t6, s0
-; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: lui a2, 1024
+; RV32I-NEXT: and t6, a1, a2
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: seqz t4, t6
+; RV32I-NEXT: addi t4, t4, -1
; RV32I-NEXT: lui a2, 2048
-; RV32I-NEXT: and s0, t2, a2
-; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: and t6, a1, a2
+; RV32I-NEXT: seqz t6, t6
; RV32I-NEXT: slli a2, t1, 22
; RV32I-NEXT: sw a2, 240(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t6, t6, a2
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and t4, t4, a2
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a2, t1, 23
; RV32I-NEXT: sw a2, 236(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lui s1, 4096
-; RV32I-NEXT: and s1, t2, s1
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: seqz s1, s1
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: lw s0, 472(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s0, s1, s0
-; RV32I-NEXT: and s1, t2, ra
-; RV32I-NEXT: lui s11, 8192
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: seqz s0, s1
+; RV32I-NEXT: and s0, a1, ra
+; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: seqz s0, s0
+; RV32I-NEXT: xor t4, t4, t6
; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: lw a2, 472(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t6, s0, a2
+; RV32I-NEXT: and s0, a1, s11
+; RV32I-NEXT: xor t4, t4, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a2, t1, 25
; RV32I-NEXT: sw a2, 232(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: and s1, t2, s6
-; RV32I-NEXT: lui ra, 16384
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: lui s0, 16384
+; RV32I-NEXT: and s0, a1, s0
+; RV32I-NEXT: lui t0, 16384
+; RV32I-NEXT: xor t4, t4, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a2, t1, 26
; RV32I-NEXT: sw a2, 228(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: and s1, t2, t5
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: and s0, a1, t5
+; RV32I-NEXT: xor t4, t4, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a2, t1, 27
; RV32I-NEXT: sw a2, 224(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: and s1, t2, a5
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: addi s0, s0, -1
+; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: and s0, a1, a4
+; RV32I-NEXT: xor t4, t4, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: addi t6, t6, -1
; RV32I-NEXT: slli a2, t1, 28
; RV32I-NEXT: sw a2, 220(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: and s1, t2, s2
-; RV32I-NEXT: xor t6, t6, s0
-; RV32I-NEXT: seqz s0, s1
-; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: and t2, t2, a3
-; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: and s0, a1, a3
+; RV32I-NEXT: xor t4, t4, t6
+; RV32I-NEXT: seqz t6, s0
+; RV32I-NEXT: addi t6, t6, -1
+; RV32I-NEXT: and a1, a1, s2
+; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: slli a2, t1, 29
; RV32I-NEXT: sw a2, 216(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and s0, s0, a2
-; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: and t6, t6, a2
+; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: slli a2, t1, 30
; RV32I-NEXT: sw a2, 212(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t2, t2, a2
+; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: slli a2, t1, 31
+; RV32I-NEXT: lw a2, 208(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli a2, a2, 31
; RV32I-NEXT: sw a2, 208(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor t2, s0, t2
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: xor a1, t6, a1
; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: xor t4, t4, t6
-; RV32I-NEXT: xor a0, t2, a0
-; RV32I-NEXT: srli t2, s10, 8
-; RV32I-NEXT: and t6, s10, s8
-; RV32I-NEXT: and t2, t2, s8
-; RV32I-NEXT: slli t6, t6, 8
-; RV32I-NEXT: srli s0, s10, 24
-; RV32I-NEXT: slli a3, s10, 24
-; RV32I-NEXT: or t2, t2, s0
-; RV32I-NEXT: or t6, a3, t6
-; RV32I-NEXT: xor a3, t4, a0
-; RV32I-NEXT: or a0, t6, t2
-; RV32I-NEXT: srli t2, s9, 8
-; RV32I-NEXT: and t4, s9, s8
-; RV32I-NEXT: and t2, t2, s8
+; RV32I-NEXT: xor t2, t2, t4
+; RV32I-NEXT: xor a0, a1, a0
+; RV32I-NEXT: lw a3, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a1, a3, 8
+; RV32I-NEXT: and t4, a3, s10
+; RV32I-NEXT: and a1, a1, s10
; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: srli t6, s9, 24
-; RV32I-NEXT: slli a2, s9, 24
-; RV32I-NEXT: or t2, t2, t6
-; RV32I-NEXT: or a2, a2, t4
-; RV32I-NEXT: srli t4, a0, 4
+; RV32I-NEXT: srli t6, a3, 24
+; RV32I-NEXT: slli a3, a3, 24
+; RV32I-NEXT: or t6, a1, t6
+; RV32I-NEXT: or a3, a3, t4
+; RV32I-NEXT: xor a1, t2, a0
+; RV32I-NEXT: or a0, a3, t6
+; RV32I-NEXT: lw a2, 200(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a3, a2, 8
+; RV32I-NEXT: and t2, a2, s10
+; RV32I-NEXT: and a3, a3, s10
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: srli t4, a2, 24
+; RV32I-NEXT: slli a2, a2, 24
+; RV32I-NEXT: or a3, a3, t4
+; RV32I-NEXT: or a2, a2, t2
+; RV32I-NEXT: srli t2, a0, 4
; RV32I-NEXT: and a0, a0, a7
-; RV32I-NEXT: and t4, t4, a7
+; RV32I-NEXT: and t2, t2, a7
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: or a0, t4, a0
-; RV32I-NEXT: or a2, a2, t2
-; RV32I-NEXT: srli t2, a0, 2
-; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and t2, t2, s7
+; RV32I-NEXT: or a0, t2, a0
+; RV32I-NEXT: or a2, a2, a3
+; RV32I-NEXT: srli a3, a0, 2
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: slli a0, a0, 2
-; RV32I-NEXT: srli t4, a2, 4
+; RV32I-NEXT: srli t2, a2, 4
; RV32I-NEXT: and a2, a2, a7
-; RV32I-NEXT: and t4, t4, a7
+; RV32I-NEXT: and t2, t2, a7
; RV32I-NEXT: slli a2, a2, 4
-; RV32I-NEXT: or a0, t2, a0
-; RV32I-NEXT: or a2, t4, a2
-; RV32I-NEXT: srli t2, a0, 1
+; RV32I-NEXT: or a0, a3, a0
+; RV32I-NEXT: or a2, t2, a2
+; RV32I-NEXT: srli a3, a0, 1
+; RV32I-NEXT: sw a3, 204(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a6
-; RV32I-NEXT: and t2, t2, a6
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: or s4, t2, a0
+; RV32I-NEXT: and a3, a3, a6
+; RV32I-NEXT: or s4, a3, a0
; RV32I-NEXT: srli a0, a2, 2
-; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and a2, a2, s7
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: slli a2, a2, 2
-; RV32I-NEXT: srli t2, s4, 8
+; RV32I-NEXT: srli a3, s4, 8
; RV32I-NEXT: or a0, a0, a2
-; RV32I-NEXT: and a2, t2, s8
-; RV32I-NEXT: srli t2, a0, 1
+; RV32I-NEXT: and a3, a3, s10
+; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a0, a0, a6
-; RV32I-NEXT: and t2, t2, a6
+; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: sw a0, 148(sp) # 4-byte Folded Spill
-; RV32I-NEXT: or a0, t2, a0
-; RV32I-NEXT: srli t2, s4, 24
-; RV32I-NEXT: or a2, a2, t2
-; RV32I-NEXT: srli t2, a0, 8
-; RV32I-NEXT: and t2, t2, s8
-; RV32I-NEXT: srli t4, a0, 24
-; RV32I-NEXT: or t2, t2, t4
-; RV32I-NEXT: and t4, a0, s8
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: slli t6, a0, 24
-; RV32I-NEXT: or t4, t6, t4
-; RV32I-NEXT: and t6, s4, s8
-; RV32I-NEXT: slli t6, t6, 8
-; RV32I-NEXT: slli t5, s4, 24
-; RV32I-NEXT: sw t5, 204(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw a0, 168(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: srli a2, s4, 24
+; RV32I-NEXT: or a2, a3, a2
+; RV32I-NEXT: srli a3, a0, 8
+; RV32I-NEXT: and a3, a3, s10
+; RV32I-NEXT: srli t2, a0, 24
+; RV32I-NEXT: or a3, a3, t2
+; RV32I-NEXT: and t2, a0, s10
+; RV32I-NEXT: slli t2, t2, 8
+; RV32I-NEXT: slli t4, a0, 24
; RV32I-NEXT: or t2, t4, t2
-; RV32I-NEXT: or t4, t5, t6
-; RV32I-NEXT: srli t6, t2, 4
-; RV32I-NEXT: and t2, t2, a7
-; RV32I-NEXT: and t6, t6, a7
-; RV32I-NEXT: slli t2, t2, 4
-; RV32I-NEXT: or a2, t4, a2
-; RV32I-NEXT: or t2, t6, t2
-; RV32I-NEXT: srli t4, a2, 4
-; RV32I-NEXT: and a2, a2, a7
+; RV32I-NEXT: and t4, s4, s10
+; RV32I-NEXT: slli t4, t4, 8
+; RV32I-NEXT: slli a4, s4, 24
+; RV32I-NEXT: sw a4, 200(sp) # 4-byte Folded Spill
+; RV32I-NEXT: or a3, t2, a3
+; RV32I-NEXT: or t2, a4, t4
+; RV32I-NEXT: srli t4, a3, 4
+; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: and t4, t4, a7
+; RV32I-NEXT: slli a3, a3, 4
+; RV32I-NEXT: or a2, t2, a2
+; RV32I-NEXT: or a3, t4, a3
+; RV32I-NEXT: srli t2, a2, 4
+; RV32I-NEXT: and a2, a2, a7
+; RV32I-NEXT: and t2, t2, a7
; RV32I-NEXT: slli a2, a2, 4
-; RV32I-NEXT: srli t6, t2, 2
-; RV32I-NEXT: and t2, t2, s7
-; RV32I-NEXT: and t6, t6, s7
-; RV32I-NEXT: slli t2, t2, 2
-; RV32I-NEXT: or a2, t4, a2
-; RV32I-NEXT: or t2, t6, t2
-; RV32I-NEXT: srli t4, a2, 2
-; RV32I-NEXT: and a2, a2, s7
-; RV32I-NEXT: and t4, t4, s7
+; RV32I-NEXT: srli t4, a3, 2
+; RV32I-NEXT: and a3, a3, s9
+; RV32I-NEXT: and t4, t4, s9
+; RV32I-NEXT: slli a3, a3, 2
+; RV32I-NEXT: or a2, t2, a2
+; RV32I-NEXT: or a3, t4, a3
+; RV32I-NEXT: srli t2, a2, 2
+; RV32I-NEXT: and a2, a2, s9
+; RV32I-NEXT: and t2, t2, s9
; RV32I-NEXT: slli a2, a2, 2
-; RV32I-NEXT: or t6, t4, a2
-; RV32I-NEXT: srli a2, t2, 1
+; RV32I-NEXT: or t2, t2, a2
+; RV32I-NEXT: srli a2, a3, 1
; RV32I-NEXT: and t4, a2, a6
-; RV32I-NEXT: and a2, t2, a6
-; RV32I-NEXT: slli a2, a2, 1
-; RV32I-NEXT: srli t2, t6, 1
-; RV32I-NEXT: and t2, t2, a6
-; RV32I-NEXT: or t4, t4, a2
-; RV32I-NEXT: and t6, t6, a6
-; RV32I-NEXT: andi s0, t4, 2
+; RV32I-NEXT: and a3, a3, a6
+; RV32I-NEXT: slli a3, a3, 1
+; RV32I-NEXT: srli a2, t2, 1
+; RV32I-NEXT: and t6, t2, a6
+; RV32I-NEXT: or t2, t4, a3
; RV32I-NEXT: slli t6, t6, 1
-; RV32I-NEXT: seqz s0, s0
-; RV32I-NEXT: or t2, t2, t6
+; RV32I-NEXT: andi t4, t2, 2
+; RV32I-NEXT: seqz s0, t4
+; RV32I-NEXT: and t4, a2, a6
+; RV32I-NEXT: or t4, t4, t6
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: slli t6, t2, 1
-; RV32I-NEXT: andi s1, t4, 1
+; RV32I-NEXT: slli t6, t4, 1
+; RV32I-NEXT: andi s1, t2, 1
; RV32I-NEXT: and t6, s0, t6
; RV32I-NEXT: seqz s0, s1
; RV32I-NEXT: addi s0, s0, -1
-; RV32I-NEXT: andi s1, t4, 4
-; RV32I-NEXT: and s0, s0, t2
+; RV32I-NEXT: andi s1, t2, 4
+; RV32I-NEXT: and s0, s0, t4
; RV32I-NEXT: seqz s1, s1
; RV32I-NEXT: xor t6, s0, t6
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s0, t2, 2
-; RV32I-NEXT: andi s2, t4, 8
+; RV32I-NEXT: slli s0, t4, 2
+; RV32I-NEXT: andi s2, t2, 8
; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 3
+; RV32I-NEXT: slli s2, t4, 3
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: andi s2, t4, 16
+; RV32I-NEXT: andi s2, t2, 16
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s0, t2, 4
-; RV32I-NEXT: andi s2, t4, 32
+; RV32I-NEXT: slli s0, t4, 4
+; RV32I-NEXT: andi s2, t2, 32
; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 5
+; RV32I-NEXT: slli s2, t4, 5
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: andi s2, t4, 64
+; RV32I-NEXT: andi s2, t2, 64
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 6
+; RV32I-NEXT: slli s2, t4, 6
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: andi s2, t4, 128
+; RV32I-NEXT: andi s2, t2, 128
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s0, t2, 7
-; RV32I-NEXT: andi s2, t4, 256
+; RV32I-NEXT: slli s0, t4, 7
+; RV32I-NEXT: andi s2, t2, 256
; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 8
+; RV32I-NEXT: slli s2, t4, 8
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: andi s2, t4, 512
+; RV32I-NEXT: andi s2, t2, 512
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 9
+; RV32I-NEXT: slli s2, t4, 9
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: andi s2, t4, 1024
+; RV32I-NEXT: andi s2, t2, 1024
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 10
+; RV32I-NEXT: slli s2, t4, 10
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, t4, a1
-; RV32I-NEXT: mv s6, a1
+; RV32I-NEXT: and s2, t2, s8
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s0, t2, 11
-; RV32I-NEXT: lui a1, 1
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: slli s0, t4, 11
+; RV32I-NEXT: lui a4, 1
+; RV32I-NEXT: and s2, t2, a4
; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 12
+; RV32I-NEXT: slli s2, t4, 12
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, t4, t3
-; RV32I-NEXT: lui s10, 2
+; RV32I-NEXT: lui a5, 2
+; RV32I-NEXT: and s2, t2, a5
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 13
+; RV32I-NEXT: slli s2, t4, 13
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 4
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui s3, 4
+; RV32I-NEXT: and s2, t2, s3
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 14
+; RV32I-NEXT: slli s2, t4, 14
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, t4, s5
+; RV32I-NEXT: lui s6, 8
+; RV32I-NEXT: and s2, t2, s6
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 15
+; RV32I-NEXT: slli s2, t4, 15
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui s9, 16
-; RV32I-NEXT: and s2, t4, s9
+; RV32I-NEXT: and s2, t2, s5
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s0, t2, 16
-; RV32I-NEXT: and s2, t4, a4
-; RV32I-NEXT: lui s5, 32
+; RV32I-NEXT: slli s0, t4, 16
+; RV32I-NEXT: and s2, t2, s7
; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 17
+; RV32I-NEXT: slli s2, t4, 17
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 64
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui s5, 64
+; RV32I-NEXT: and s2, t2, s5
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 18
+; RV32I-NEXT: slli s2, t4, 18
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 128
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui s7, 128
+; RV32I-NEXT: and s2, t2, s7
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 19
+; RV32I-NEXT: slli s2, t4, 19
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 256
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui s11, 256
+; RV32I-NEXT: and s2, t2, s11
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 20
+; RV32I-NEXT: slli s2, t4, 20
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 512
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui ra, 512
+; RV32I-NEXT: and s2, t2, ra
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 21
+; RV32I-NEXT: slli s2, t4, 21
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 1024
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui s2, 1024
+; RV32I-NEXT: and s2, t2, s2
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: xor t6, t6, s0
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s0, t2, 22
-; RV32I-NEXT: lui a1, 2048
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: slli s0, t4, 22
+; RV32I-NEXT: lui s2, 2048
+; RV32I-NEXT: and s2, t2, s2
; RV32I-NEXT: and s0, s1, s0
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 23
+; RV32I-NEXT: slli s2, t4, 23
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 4096
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui s2, 4096
+; RV32I-NEXT: and s2, t2, s2
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 24
+; RV32I-NEXT: slli s2, t4, 24
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, t4, s11
-; RV32I-NEXT: lui a5, 8192
+; RV32I-NEXT: lui s2, 8192
+; RV32I-NEXT: and s2, t2, s2
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 25
+; RV32I-NEXT: slli s2, t4, 25
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: and s2, t4, ra
+; RV32I-NEXT: and s2, t2, t0
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 26
+; RV32I-NEXT: slli s2, t4, 26
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 32768
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: and s2, t2, t5
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 27
+; RV32I-NEXT: slli s2, t4, 27
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 65536
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui t0, 65536
+; RV32I-NEXT: and s2, t2, t0
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: slli s2, t2, 28
+; RV32I-NEXT: slli s2, t4, 28
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: lui a1, 131072
-; RV32I-NEXT: and s2, t4, a1
+; RV32I-NEXT: lui t0, 131072
+; RV32I-NEXT: and s2, t2, t0
; RV32I-NEXT: xor s0, s0, s1
; RV32I-NEXT: seqz s1, s2
; RV32I-NEXT: addi s1, s1, -1
-; RV32I-NEXT: lui a1, 262144
-; RV32I-NEXT: and t4, t4, a1
-; RV32I-NEXT: seqz t4, t4
-; RV32I-NEXT: slli s2, t2, 29
+; RV32I-NEXT: slli s2, t4, 29
; RV32I-NEXT: and s1, s1, s2
-; RV32I-NEXT: addi t4, t4, -1
-; RV32I-NEXT: srli a2, a2, 31
-; RV32I-NEXT: slli s2, t2, 30
-; RV32I-NEXT: and t4, t4, s2
-; RV32I-NEXT: seqz a2, a2
-; RV32I-NEXT: slli t2, t2, 31
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: xor t4, s1, t4
-; RV32I-NEXT: and a2, a2, t2
-; RV32I-NEXT: xor t2, t6, s0
-; RV32I-NEXT: xor a2, t4, a2
-; RV32I-NEXT: xor a3, a3, s3
+; RV32I-NEXT: lui t0, 262144
+; RV32I-NEXT: and t2, t2, t0
+; RV32I-NEXT: slli t4, t4, 30
+; RV32I-NEXT: seqz t2, t2
+; RV32I-NEXT: addi t2, t2, -1
+; RV32I-NEXT: srli a3, a3, 31
+; RV32I-NEXT: and t2, t2, t4
+; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: slli a2, a2, 31
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: xor t2, s1, t2
+; RV32I-NEXT: and a2, a3, a2
+; RV32I-NEXT: xor a3, t6, s0
; RV32I-NEXT: xor a2, t2, a2
-; RV32I-NEXT: lw a1, 200(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a1, a1, 1
+; RV32I-NEXT: xor a1, a1, t3
+; RV32I-NEXT: xor a2, a3, a2
+; RV32I-NEXT: lw a3, 192(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a3, a3, 1
; RV32I-NEXT: srli t2, a2, 8
-; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: sw a1, 152(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a1, t2, s8
+; RV32I-NEXT: xor a1, a3, a1
+; RV32I-NEXT: sw a1, 148(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a1, t2, s10
; RV32I-NEXT: srli a3, a2, 24
-; RV32I-NEXT: and t2, a2, s8
+; RV32I-NEXT: and t2, a2, s10
; RV32I-NEXT: slli a2, a2, 24
; RV32I-NEXT: slli t2, t2, 8
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a2, a2, t2
-; RV32I-NEXT: lw t5, 340(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t5, 344(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a3, t5, 8
-; RV32I-NEXT: and t2, t5, s8
-; RV32I-NEXT: and a3, a3, s8
+; RV32I-NEXT: and t2, t5, s10
+; RV32I-NEXT: and a3, a3, s10
; RV32I-NEXT: slli t2, t2, 8
; RV32I-NEXT: srli t3, t5, 24
; RV32I-NEXT: slli t5, t5, 24
@@ -4136,314 +4137,312 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a2, t2, a2
; RV32I-NEXT: srli a3, a1, 2
-; RV32I-NEXT: and a1, a1, s7
-; RV32I-NEXT: and a3, a3, s7
+; RV32I-NEXT: and a1, a1, s9
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: slli a1, a1, 2
-; RV32I-NEXT: srli t2, a2, 2
-; RV32I-NEXT: and a2, a2, s7
-; RV32I-NEXT: and t2, t2, s7
-; RV32I-NEXT: slli t3, a2, 2
-; RV32I-NEXT: or a2, a3, a1
-; RV32I-NEXT: or a1, t2, t3
-; RV32I-NEXT: srli a3, a2, 1
-; RV32I-NEXT: srli t2, a1, 1
-; RV32I-NEXT: and a3, a3, t0
-; RV32I-NEXT: and t0, t2, a6
-; RV32I-NEXT: and a1, a1, a6
+; RV32I-NEXT: or a3, a3, a1
+; RV32I-NEXT: srli a1, a2, 2
+; RV32I-NEXT: and a1, a1, s9
+; RV32I-NEXT: and a2, a2, s9
+; RV32I-NEXT: slli a2, a2, 2
+; RV32I-NEXT: srli t2, a3, 1
+; RV32I-NEXT: lw t0, 196(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and t0, t2, t0
+; RV32I-NEXT: or a2, a1, a2
+; RV32I-NEXT: srli a1, a2, 1
+; RV32I-NEXT: and a2, a2, a6
+; RV32I-NEXT: slli a2, a2, 1
+; RV32I-NEXT: and t2, a1, a6
+; RV32I-NEXT: or a2, t2, a2
+; RV32I-NEXT: and a3, a3, a6
+; RV32I-NEXT: slli a3, a3, 1
; RV32I-NEXT: andi t2, a0, 2
-; RV32I-NEXT: slli a1, a1, 1
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: or a1, t0, a1
-; RV32I-NEXT: addi a4, t2, -1
-; RV32I-NEXT: sw a4, 340(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t0, a1, 1
-; RV32I-NEXT: andi t2, a0, 1
-; RV32I-NEXT: and t0, a4, t0
; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: addi a4, t2, -1
-; RV32I-NEXT: sw a4, 200(sp) # 4-byte Folded Spill
-; RV32I-NEXT: andi t2, a0, 4
+; RV32I-NEXT: andi t3, a0, 1
+; RV32I-NEXT: addi t4, t2, -1
+; RV32I-NEXT: sw t4, 344(sp) # 4-byte Folded Spill
+; RV32I-NEXT: seqz t2, t3
+; RV32I-NEXT: addi t3, t2, -1
+; RV32I-NEXT: sw t3, 196(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 1
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: and t3, t3, a2
+; RV32I-NEXT: or a3, t0, a3
+; RV32I-NEXT: sw a3, 96(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a3, t3, t2
+; RV32I-NEXT: andi t0, a0, 4
+; RV32I-NEXT: andi t2, a0, 8
+; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: and t3, a4, a1
-; RV32I-NEXT: xor t0, t3, t0
-; RV32I-NEXT: addi a4, t2, -1
-; RV32I-NEXT: sw a4, 196(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, a1, 2
-; RV32I-NEXT: andi t3, a0, 8
-; RV32I-NEXT: and t2, a4, t2
+; RV32I-NEXT: addi t3, t0, -1
+; RV32I-NEXT: sw t3, 192(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi t4, t2, -1
+; RV32I-NEXT: sw t4, 188(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, a2, 2
+; RV32I-NEXT: slli t2, a2, 3
+; RV32I-NEXT: and t0, t3, t0
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: andi t2, a0, 16
+; RV32I-NEXT: xor a3, a3, t0
+; RV32I-NEXT: seqz t0, t2
+; RV32I-NEXT: addi t3, t0, -1
+; RV32I-NEXT: sw t3, 184(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi t0, a0, 32
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: slli t2, a2, 4
+; RV32I-NEXT: and t2, t3, t2
+; RV32I-NEXT: addi t4, t0, -1
+; RV32I-NEXT: sw t4, 180(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, a2, 5
+; RV32I-NEXT: andi t3, a0, 64
+; RV32I-NEXT: and t0, t4, t0
; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 192(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 3
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: andi t4, a0, 16
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: addi t4, t3, -1
+; RV32I-NEXT: sw t4, 176(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, a2, 6
+; RV32I-NEXT: xor t0, t2, t0
+; RV32I-NEXT: and t2, t4, t3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: andi t2, a0, 128
+; RV32I-NEXT: xor a3, a3, t0
+; RV32I-NEXT: seqz t0, t2
+; RV32I-NEXT: addi t3, t0, -1
+; RV32I-NEXT: sw t3, 172(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi t0, a0, 256
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: slli t2, a2, 7
+; RV32I-NEXT: and t2, t3, t2
+; RV32I-NEXT: addi t4, t0, -1
+; RV32I-NEXT: sw t4, 164(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, a2, 8
+; RV32I-NEXT: andi t3, a0, 512
+; RV32I-NEXT: and t0, t4, t0
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: xor t0, t2, t0
+; RV32I-NEXT: addi t4, t3, -1
+; RV32I-NEXT: sw t4, 160(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 9
+; RV32I-NEXT: andi t3, a0, 1024
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: addi t4, t3, -1
+; RV32I-NEXT: sw t4, 156(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, a2, 10
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: and t2, t4, t3
; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: and t2, a0, s8
+; RV32I-NEXT: xor a3, a3, t0
+; RV32I-NEXT: seqz t0, t2
+; RV32I-NEXT: addi t3, t0, -1
+; RV32I-NEXT: sw t3, 152(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t0, a0, a4
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: slli t2, a2, 11
+; RV32I-NEXT: and t2, t3, t2
+; RV32I-NEXT: addi a4, t0, -1
+; RV32I-NEXT: sw a4, 144(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, a2, 12
+; RV32I-NEXT: and t3, a0, a5
+; RV32I-NEXT: and t0, a4, t0
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: xor t0, t2, t0
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 188(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, a1, 4
-; RV32I-NEXT: andi t3, a0, 32
+; RV32I-NEXT: sw a4, 140(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 13
+; RV32I-NEXT: and t3, a0, s3
; RV32I-NEXT: and t2, a4, t2
; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 184(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 5
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: andi t4, a0, 64
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 180(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 6
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: andi t4, a0, 128
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
; RV32I-NEXT: xor t0, t0, t2
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 176(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, a1, 7
-; RV32I-NEXT: andi t3, a0, 256
+; RV32I-NEXT: sw a4, 136(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 14
+; RV32I-NEXT: and t3, a0, s6
; RV32I-NEXT: and t2, a4, t2
; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 172(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 8
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: andi t4, a0, 512
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 168(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 9
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: andi t4, a0, 1024
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: sw a4, 132(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, a2, 15
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: and t2, a4, t3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lui a5, 16
+; RV32I-NEXT: and t2, a0, a5
+; RV32I-NEXT: xor a3, a3, t0
+; RV32I-NEXT: seqz t0, t2
+; RV32I-NEXT: addi a4, t0, -1
+; RV32I-NEXT: sw a4, 128(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s1, 32
+; RV32I-NEXT: and t0, a0, s1
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: slli t2, a2, 16
+; RV32I-NEXT: and t2, a4, t2
+; RV32I-NEXT: addi a4, t0, -1
+; RV32I-NEXT: sw a4, 124(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, a2, 17
+; RV32I-NEXT: and t3, a0, s5
+; RV32I-NEXT: lui s3, 64
+; RV32I-NEXT: and t0, a4, t0
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: xor t0, t2, t0
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 164(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 10
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: and t4, a0, s6
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: sw a4, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 18
+; RV32I-NEXT: and t3, a0, s7
+; RV32I-NEXT: and t2, a4, t2
+; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: xor t0, t0, t2
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 160(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, a1, 11
-; RV32I-NEXT: lui s11, 1
+; RV32I-NEXT: sw a4, 116(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 19
; RV32I-NEXT: and t3, a0, s11
+; RV32I-NEXT: lui s7, 256
; RV32I-NEXT: and t2, a4, t2
; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: xor t0, t0, t2
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 156(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 12
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: and t4, a0, s10
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 144(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 13
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: lui ra, 4
-; RV32I-NEXT: and t4, a0, ra
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 140(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 14
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: lui s3, 8
-; RV32I-NEXT: and t4, a0, s3
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: sw a4, 112(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 20
+; RV32I-NEXT: and t3, a0, ra
+; RV32I-NEXT: and t2, a4, t2
+; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 136(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 15
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: and t4, a0, s9
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: sw a4, 108(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, a2, 21
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: and t2, a4, t3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lui s2, 1024
+; RV32I-NEXT: and t2, a0, s2
+; RV32I-NEXT: xor a3, a3, t0
+; RV32I-NEXT: seqz t0, t2
+; RV32I-NEXT: addi a4, t0, -1
+; RV32I-NEXT: sw a4, 104(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui s5, 2048
+; RV32I-NEXT: and t0, a0, s5
+; RV32I-NEXT: seqz t0, t0
+; RV32I-NEXT: slli t2, a2, 22
+; RV32I-NEXT: and t2, a4, t2
+; RV32I-NEXT: addi a4, t0, -1
+; RV32I-NEXT: sw a4, 100(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t0, a2, 23
+; RV32I-NEXT: lui s0, 4096
+; RV32I-NEXT: and t3, a0, s0
+; RV32I-NEXT: and t0, a4, t0
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: xor t0, t2, t0
+; RV32I-NEXT: addi t4, t3, -1
+; RV32I-NEXT: sw t4, 92(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 24
+; RV32I-NEXT: lui a4, 8192
+; RV32I-NEXT: and t3, a0, a4
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: seqz t3, t3
; RV32I-NEXT: xor t0, t0, t2
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 132(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, a1, 16
-; RV32I-NEXT: and t3, a0, s5
-; RV32I-NEXT: lui s9, 32
+; RV32I-NEXT: sw a4, 88(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 25
+; RV32I-NEXT: lui t6, 16384
+; RV32I-NEXT: and t3, a0, t6
; RV32I-NEXT: and t2, a4, t2
; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: xor t0, t0, t2
; RV32I-NEXT: addi a4, t3, -1
-; RV32I-NEXT: sw a4, 128(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 17
-; RV32I-NEXT: and t3, a4, t3
-; RV32I-NEXT: lui t5, 64
-; RV32I-NEXT: and t4, a0, t5
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi t4, t3, -1
-; RV32I-NEXT: sw t4, 124(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 18
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: lui t6, 128
-; RV32I-NEXT: and t4, a0, t6
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
+; RV32I-NEXT: sw a4, 84(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 26
+; RV32I-NEXT: lui t5, 32768
+; RV32I-NEXT: and t3, a0, t5
+; RV32I-NEXT: and t2, a4, t2
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: xor t0, t0, t2
; RV32I-NEXT: addi t4, t3, -1
-; RV32I-NEXT: sw t4, 120(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 19
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: lui s1, 256
-; RV32I-NEXT: and t4, a0, s1
-; RV32I-NEXT: xor t2, t2, t3
+; RV32I-NEXT: sw t4, 80(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t2, a2, 27
+; RV32I-NEXT: lui a4, 65536
+; RV32I-NEXT: and t3, a0, a4
+; RV32I-NEXT: and t2, t4, t2
+; RV32I-NEXT: seqz t3, t3
+; RV32I-NEXT: addi a4, t3, -1
+; RV32I-NEXT: sw a4, 76(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, a2, 28
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: and t2, a4, t3
+; RV32I-NEXT: xor t0, t0, t2
+; RV32I-NEXT: lw a4, 460(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli t2, a4, 8
+; RV32I-NEXT: xor a3, a3, t0
+; RV32I-NEXT: and t0, t2, s10
+; RV32I-NEXT: srli t2, a4, 24
+; RV32I-NEXT: and t3, a4, s10
+; RV32I-NEXT: or t0, t0, t2
+; RV32I-NEXT: slli t3, t3, 8
+; RV32I-NEXT: slli t2, a4, 24
+; RV32I-NEXT: lui a4, 131072
+; RV32I-NEXT: and t4, a0, a4
+; RV32I-NEXT: or t2, t2, t3
; RV32I-NEXT: seqz t3, t4
; RV32I-NEXT: addi t4, t3, -1
-; RV32I-NEXT: sw t4, 116(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 20
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: lui s5, 512
-; RV32I-NEXT: and t4, a0, s5
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi t4, t3, -1
-; RV32I-NEXT: sw t4, 112(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 21
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: lui a4, 1024
-; RV32I-NEXT: and t4, a0, a4
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: xor t0, t0, t2
-; RV32I-NEXT: addi t4, t3, -1
-; RV32I-NEXT: sw t4, 108(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, a1, 22
-; RV32I-NEXT: lui s2, 2048
-; RV32I-NEXT: and t3, a0, s2
-; RV32I-NEXT: and t2, t4, t2
-; RV32I-NEXT: seqz t3, t3
-; RV32I-NEXT: addi t4, t3, -1
-; RV32I-NEXT: sw t4, 104(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 23
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: lui s0, 4096
-; RV32I-NEXT: and t4, a0, s0
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi t4, t3, -1
-; RV32I-NEXT: sw t4, 100(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 24
-; RV32I-NEXT: and t3, t4, t3
-; RV32I-NEXT: and t4, a0, a5
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a5, t3, -1
-; RV32I-NEXT: sw a5, 96(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 25
-; RV32I-NEXT: and t3, a5, t3
-; RV32I-NEXT: lui a5, 16384
-; RV32I-NEXT: and t4, a0, a5
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a5, t3, -1
-; RV32I-NEXT: sw a5, 92(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 26
-; RV32I-NEXT: and t3, a5, t3
-; RV32I-NEXT: lui a4, 32768
-; RV32I-NEXT: and t4, a0, a4
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a5, t3, -1
-; RV32I-NEXT: sw a5, 88(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 27
-; RV32I-NEXT: and t3, a5, t3
-; RV32I-NEXT: lui a5, 65536
-; RV32I-NEXT: and t4, a0, a5
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: seqz t3, t4
-; RV32I-NEXT: addi a5, t3, -1
-; RV32I-NEXT: sw a5, 84(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t3, a1, 28
-; RV32I-NEXT: and a2, a2, a6
-; RV32I-NEXT: and t3, a5, t3
-; RV32I-NEXT: xor t2, t2, t3
-; RV32I-NEXT: slli a2, a2, 1
-; RV32I-NEXT: or a2, a3, a2
-; RV32I-NEXT: sw a2, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a4, t0, t2
-; RV32I-NEXT: lw t3, 460(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a3, t3, 8
-; RV32I-NEXT: and t0, t3, s8
-; RV32I-NEXT: and a3, a3, s8
-; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: srli t2, t3, 24
-; RV32I-NEXT: slli t3, t3, 24
-; RV32I-NEXT: or a3, a3, t2
-; RV32I-NEXT: or t0, t3, t0
-; RV32I-NEXT: lui t3, 131072
-; RV32I-NEXT: and t2, a0, t3
-; RV32I-NEXT: lui a5, 262144
-; RV32I-NEXT: and a0, a0, a5
-; RV32I-NEXT: seqz t2, t2
-; RV32I-NEXT: seqz a0, a0
-; RV32I-NEXT: addi t4, t2, -1
; RV32I-NEXT: sw t4, 460(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a2, a1, 29
-; RV32I-NEXT: slli t2, a1, 30
-; RV32I-NEXT: and a2, t4, a2
-; RV32I-NEXT: and t2, a0, t2
-; RV32I-NEXT: xor t2, a2, t2
-; RV32I-NEXT: or a0, t0, a3
-; RV32I-NEXT: srli a3, a0, 4
+; RV32I-NEXT: lui t3, 262144
+; RV32I-NEXT: and a0, a0, t3
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: slli t3, a2, 29
+; RV32I-NEXT: slli a2, a2, 30
+; RV32I-NEXT: addi s11, a0, -1
+; RV32I-NEXT: sw s11, 72(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a0, t4, t3
+; RV32I-NEXT: and a2, s11, a2
+; RV32I-NEXT: xor a2, a0, a2
+; RV32I-NEXT: or a0, t2, t0
+; RV32I-NEXT: srli t0, a0, 4
; RV32I-NEXT: and a0, a0, a7
-; RV32I-NEXT: and a3, a3, a7
+; RV32I-NEXT: and t0, t0, a7
; RV32I-NEXT: slli a0, a0, 4
-; RV32I-NEXT: or a0, a3, a0
-; RV32I-NEXT: lw a3, 148(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a3, a3, 31
-; RV32I-NEXT: srli t0, a0, 2
-; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and t0, t0, s7
-; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, t0, a0
-; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: lw t0, 168(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli t0, t0, 31
+; RV32I-NEXT: srli t2, a0, 2
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and t2, t2, s9
+; RV32I-NEXT: slli a0, a0, 2
+; RV32I-NEXT: or a0, t2, a0
+; RV32I-NEXT: seqz t0, t0
; RV32I-NEXT: slli a1, a1, 31
-; RV32I-NEXT: addi a2, a3, -1
-; RV32I-NEXT: sw a2, 148(sp) # 4-byte Folded Spill
-; RV32I-NEXT: srli a3, a0, 1
-; RV32I-NEXT: and t0, a0, a6
-; RV32I-NEXT: and a0, a3, a6
-; RV32I-NEXT: slli t0, t0, 1
-; RV32I-NEXT: and a1, a2, a1
-; RV32I-NEXT: or a0, a0, t0
-; RV32I-NEXT: xor a1, t2, a1
-; RV32I-NEXT: andi a3, a0, 2
-; RV32I-NEXT: seqz a3, a3
+; RV32I-NEXT: addi t3, t0, -1
+; RV32I-NEXT: sw t3, 168(sp) # 4-byte Folded Spill
+; RV32I-NEXT: srli t0, a0, 1
+; RV32I-NEXT: and a0, a0, a6
+; RV32I-NEXT: and t2, t0, a6
+; RV32I-NEXT: slli t0, a0, 1
+; RV32I-NEXT: and a1, t3, a1
+; RV32I-NEXT: or a0, t2, t0
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: andi a2, a0, 2
+; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: andi t2, a0, 1
-; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: slli a2, s4, 1
-; RV32I-NEXT: sw a2, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a3, a2
+; RV32I-NEXT: slli t3, s4, 1
+; RV32I-NEXT: sw t3, 68(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, t3
; RV32I-NEXT: and t2, t2, s4
-; RV32I-NEXT: xor a1, a4, a1
-; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: xor a1, t2, a3
+; RV32I-NEXT: xor a1, a3, a1
+; RV32I-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: xor a1, t2, a2
; RV32I-NEXT: andi a2, a0, 4
; RV32I-NEXT: andi a3, a0, 8
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a4, s4, 2
-; RV32I-NEXT: sw a4, 72(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli t2, s4, 3
-; RV32I-NEXT: sw t2, 68(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a4
-; RV32I-NEXT: and a3, a3, t2
+; RV32I-NEXT: slli t2, s4, 2
+; RV32I-NEXT: sw t2, 64(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, s4, 3
+; RV32I-NEXT: sw t3, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, t2
+; RV32I-NEXT: and a3, a3, t3
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: andi a3, a0, 16
; RV32I-NEXT: xor a1, a1, a2
@@ -4451,20 +4450,20 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: andi a3, a0, 32
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, s4, 4
-; RV32I-NEXT: sw a4, 64(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: slli t2, s4, 4
+; RV32I-NEXT: sw t2, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, t2
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a4, s4, 5
-; RV32I-NEXT: sw a4, 60(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, s4, 5
+; RV32I-NEXT: sw t3, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi t2, a0, 64
-; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: and a3, a3, t3
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: slli a4, s4, 6
-; RV32I-NEXT: sw a4, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, s4, 6
+; RV32I-NEXT: sw t3, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, t2, a4
+; RV32I-NEXT: and a3, t2, t3
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: andi a3, a0, 128
; RV32I-NEXT: xor a1, a1, a2
@@ -4472,93 +4471,96 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: andi a3, a0, 256
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, s4, 7
-; RV32I-NEXT: sw a4, 52(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: slli t2, s4, 7
+; RV32I-NEXT: sw t2, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, t2
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a4, s4, 8
-; RV32I-NEXT: sw a4, 48(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, s4, 8
+; RV32I-NEXT: sw t3, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi t2, a0, 512
-; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: and a3, a3, t3
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: slli a4, s4, 9
-; RV32I-NEXT: sw a4, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, s4, 9
+; RV32I-NEXT: sw t3, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a3, a0, 1024
-; RV32I-NEXT: and t2, t2, a4
+; RV32I-NEXT: and t2, t2, t3
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli a4, s4, 10
-; RV32I-NEXT: sw a4, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, s4, 10
+; RV32I-NEXT: sw t3, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, t2
-; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: and a3, a3, t3
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, a0, s6
+; RV32I-NEXT: and a3, a0, s8
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, a0, s11
+; RV32I-NEXT: lui a3, 1
+; RV32I-NEXT: and a3, a0, a3
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, s4, 11
-; RV32I-NEXT: sw a4, 36(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: slli t2, s4, 11
+; RV32I-NEXT: sw t2, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, t2
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and t2, a0, s10
-; RV32I-NEXT: slli a4, s4, 12
-; RV32I-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: lui t2, 2
+; RV32I-NEXT: and t2, a0, t2
+; RV32I-NEXT: slli t3, s4, 12
+; RV32I-NEXT: sw t3, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a3, t3
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and a3, a0, ra
-; RV32I-NEXT: slli a4, s4, 13
-; RV32I-NEXT: sw a4, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and t2, t2, a4
+; RV32I-NEXT: lui a3, 4
+; RV32I-NEXT: and a3, a0, a3
+; RV32I-NEXT: slli t3, s4, 13
+; RV32I-NEXT: sw t3, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and t2, t2, t3
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a2, a2, t2
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and t2, a0, s3
-; RV32I-NEXT: slli a4, s4, 14
-; RV32I-NEXT: sw a4, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a3, a3, a4
+; RV32I-NEXT: and t2, a0, s6
+; RV32I-NEXT: slli t3, s4, 14
+; RV32I-NEXT: sw t3, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a3, a3, t3
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: slli a4, s4, 15
-; RV32I-NEXT: sw a4, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli t3, s4, 15
+; RV32I-NEXT: sw t3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: and a3, t2, a4
+; RV32I-NEXT: and a3, t2, t3
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lui a3, 16
-; RV32I-NEXT: and a3, a0, a3
+; RV32I-NEXT: and a3, a0, a5
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, a0, s9
+; RV32I-NEXT: and a3, a0, s1
; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: slli a4, s4, 16
-; RV32I-NEXT: sw a4, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: and a2, a2, a4
+; RV32I-NEXT: slli a5, s4, 16
+; RV32I-NEXT: sw a5, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and t2, a0, t5
+; RV32I-NEXT: and t2, a0, s3
; RV32I-NEXT: slli s11, s4, 17
; RV32I-NEXT: and a3, a3, s11
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and a3, a0, t6
-; RV32I-NEXT: slli s10, s4, 18
-; RV32I-NEXT: and t2, t2, s10
+; RV32I-NEXT: lui a3, 128
+; RV32I-NEXT: and a3, a0, a3
+; RV32I-NEXT: slli s8, s4, 18
+; RV32I-NEXT: and t2, t2, s8
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: xor a2, a2, t2
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and t2, a0, s1
-; RV32I-NEXT: slli s9, s4, 19
-; RV32I-NEXT: and a3, a3, s9
+; RV32I-NEXT: and t2, a0, s7
+; RV32I-NEXT: slli s7, s4, 19
+; RV32I-NEXT: and a3, a3, s7
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: and a3, a0, s5
+; RV32I-NEXT: and a3, a0, ra
; RV32I-NEXT: slli s6, s4, 20
; RV32I-NEXT: and t2, t2, s6
; RV32I-NEXT: seqz a3, a3
@@ -4567,12 +4569,11 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: xor a2, a2, t2
; RV32I-NEXT: and a3, a3, s3
; RV32I-NEXT: xor a2, a2, a3
-; RV32I-NEXT: lui a3, 1024
-; RV32I-NEXT: and a3, a0, a3
-; RV32I-NEXT: xor a4, a1, a2
+; RV32I-NEXT: and a3, a0, s2
+; RV32I-NEXT: xor a5, a1, a2
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a3, a0, s2
+; RV32I-NEXT: and a3, a0, s5
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: slli s5, s4, 22
; RV32I-NEXT: and a2, a2, s5
@@ -4583,7 +4584,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: seqz t2, t2
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: addi t2, t2, -1
-; RV32I-NEXT: lw s1, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 200(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, t2, s1
; RV32I-NEXT: lui a1, 8192
; RV32I-NEXT: and t2, a0, a1
@@ -4592,15 +4593,13 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli s0, s4, 25
; RV32I-NEXT: and a3, a3, s0
-; RV32I-NEXT: lui a1, 16384
-; RV32I-NEXT: and t2, a0, a1
+; RV32I-NEXT: and t2, a0, t6
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: seqz a3, t2
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli t6, s4, 26
; RV32I-NEXT: and a3, a3, t6
-; RV32I-NEXT: lui a1, 32768
-; RV32I-NEXT: and t2, a0, a1
+; RV32I-NEXT: and t2, a0, t5
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: seqz a3, t2
; RV32I-NEXT: addi a3, a3, -1
@@ -4613,50 +4612,52 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: slli t4, s4, 28
; RV32I-NEXT: and a3, a3, t4
-; RV32I-NEXT: and t2, a0, t3
-; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: and t2, a0, a4
+; RV32I-NEXT: xor a4, a2, a3
; RV32I-NEXT: seqz a3, t2
-; RV32I-NEXT: and a0, a0, a5
+; RV32I-NEXT: lui a1, 262144
+; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: slli t3, s4, 29
-; RV32I-NEXT: and a1, a3, t3
+; RV32I-NEXT: and a2, a3, t3
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: srli a3, t0, 31
; RV32I-NEXT: slli t2, s4, 30
-; RV32I-NEXT: and a0, a0, t2
-; RV32I-NEXT: seqz a3, a3
-; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: slli t0, s4, 31
+; RV32I-NEXT: and a1, a0, t2
+; RV32I-NEXT: seqz a0, a3
+; RV32I-NEXT: lw t0, 204(sp) # 4-byte Folded Reload
+; RV32I-NEXT: slli t0, t0, 31
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: xor a1, a2, a1
+; RV32I-NEXT: and a0, a0, t0
+; RV32I-NEXT: xor a4, a5, a4
; RV32I-NEXT: xor a0, a1, a0
-; RV32I-NEXT: and a1, a3, t0
-; RV32I-NEXT: xor a2, a4, a2
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: lw a4, 152(sp) # 4-byte Folded Reload
-; RV32I-NEXT: srli a1, a4, 8
-; RV32I-NEXT: lw a2, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: xor a0, a4, a0
+; RV32I-NEXT: lw a5, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: srli a1, a5, 8
+; RV32I-NEXT: lw a2, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: xor a0, a0, a2
-; RV32I-NEXT: and a1, a1, s8
-; RV32I-NEXT: lw a2, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and a1, a1, s10
+; RV32I-NEXT: lw a2, 96(sp) # 4-byte Folded Reload
; RV32I-NEXT: srli a2, a2, 1
-; RV32I-NEXT: srli a3, a4, 24
-; RV32I-NEXT: or a5, a1, a3
+; RV32I-NEXT: srli a4, a5, 24
+; RV32I-NEXT: or a3, a1, a4
; RV32I-NEXT: xor a0, a2, a0
-; RV32I-NEXT: slli a2, a4, 24
-; RV32I-NEXT: and a3, a4, s8
-; RV32I-NEXT: slli a3, a3, 8
-; RV32I-NEXT: srli a4, a0, 8
-; RV32I-NEXT: or a2, a2, a3
-; RV32I-NEXT: and a3, a4, s8
-; RV32I-NEXT: srli a4, a0, 24
-; RV32I-NEXT: and a1, a0, s8
+; RV32I-NEXT: slli a2, a5, 24
+; RV32I-NEXT: and a4, a5, s10
+; RV32I-NEXT: slli a4, a4, 8
+; RV32I-NEXT: srli a5, a0, 8
+; RV32I-NEXT: or a2, a2, a4
+; RV32I-NEXT: and a4, a5, s10
+; RV32I-NEXT: srli a5, a0, 24
+; RV32I-NEXT: and a1, a0, s10
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: slli a1, a1, 8
-; RV32I-NEXT: or a3, a3, a4
+; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: or a2, a2, a5
-; RV32I-NEXT: or a0, a0, a3
+; RV32I-NEXT: or a2, a2, a3
+; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a1, a2, 4
; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: and a1, a1, a7
@@ -4668,12 +4669,12 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srli a2, a1, 2
-; RV32I-NEXT: and a1, a1, s7
-; RV32I-NEXT: and a2, a2, s7
+; RV32I-NEXT: and a1, a1, s9
+; RV32I-NEXT: and a2, a2, s9
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: srli a3, a0, 2
-; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and a3, a3, s7
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a3, a0
@@ -4795,7 +4796,7 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: lw t1, 224(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, t1
; RV32I-NEXT: xor a3, a3, a5
-; RV32I-NEXT: lw a5, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 340(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw t1, 220(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, t1
; RV32I-NEXT: xor a0, a0, a4
@@ -4812,54 +4813,50 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: and a5, a5, t1
; RV32I-NEXT: xor t1, a0, a3
; RV32I-NEXT: xor a0, a4, a5
-; RV32I-NEXT: lw a3, 340(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw a4, 76(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a3, 344(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 68(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a3, a3, a4
-; RV32I-NEXT: lw a4, 200(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 196(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s4
-; RV32I-NEXT: lw a5, 196(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 72(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 192(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s4
-; RV32I-NEXT: lw s4, 192(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 68(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 188(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: xor a4, a5, s4
-; RV32I-NEXT: lw a5, 188(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 184(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s4
-; RV32I-NEXT: lw s4, 184(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 180(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a5, a5, s4
-; RV32I-NEXT: lw s4, 180(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 56(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 176(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a4, a5, s4
-; RV32I-NEXT: lw a5, 176(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 52(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 172(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s4
-; RV32I-NEXT: lw s4, 172(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 48(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 164(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a5, a5, s4
-; RV32I-NEXT: lw s4, 168(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 160(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a5, a5, s4
-; RV32I-NEXT: lw s4, 164(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 156(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a4, a5, s4
-; RV32I-NEXT: lw a5, 160(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 152(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s4
-; RV32I-NEXT: lw s4, 156(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, ra
-; RV32I-NEXT: xor a5, a5, s4
; RV32I-NEXT: lw s4, 144(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
@@ -4871,73 +4868,77 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: lw s4, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s4, s4, ra
+; RV32I-NEXT: xor a5, a5, s4
+; RV32I-NEXT: lw s4, 132(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, ra
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a4, a5, s4
-; RV32I-NEXT: lw a5, 132(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 128(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s4
-; RV32I-NEXT: lw s4, 128(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, s11
-; RV32I-NEXT: xor a5, a5, s4
; RV32I-NEXT: lw s4, 124(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, s10
+; RV32I-NEXT: and s4, s4, s11
; RV32I-NEXT: xor a5, a5, s4
; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, s9
+; RV32I-NEXT: and s4, s4, s8
; RV32I-NEXT: xor a5, a5, s4
; RV32I-NEXT: lw s4, 116(sp) # 4-byte Folded Reload
-; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: and s4, s4, s7
; RV32I-NEXT: xor a5, a5, s4
; RV32I-NEXT: lw s4, 112(sp) # 4-byte Folded Reload
+; RV32I-NEXT: and s4, s4, s6
+; RV32I-NEXT: xor a5, a5, s4
+; RV32I-NEXT: lw s4, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: and s3, s4, s3
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: xor a4, a5, s3
; RV32I-NEXT: xor a0, t1, a0
; RV32I-NEXT: xor a3, a3, a4
-; RV32I-NEXT: lw a4, 108(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a4, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, s5
-; RV32I-NEXT: lw a5, 104(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 100(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s2
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 100(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 92(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s1
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 96(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 88(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, s0
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 92(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 84(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, t6
; RV32I-NEXT: xor a4, a4, a5
-; RV32I-NEXT: lw a5, 88(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw a5, 80(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a5, a5, t5
; RV32I-NEXT: xor a4, a4, a5
; RV32I-NEXT: srli a5, a0, 8
-; RV32I-NEXT: lw t1, 84(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t1, t1, t4
-; RV32I-NEXT: and a5, a5, s8
+; RV32I-NEXT: and a5, a5, s10
; RV32I-NEXT: xor a4, a4, t1
; RV32I-NEXT: srli t1, a0, 24
; RV32I-NEXT: or a5, a5, t1
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: lw a4, 460(sp) # 4-byte Folded Reload
; RV32I-NEXT: and a4, a4, t3
-; RV32I-NEXT: lw t1, 80(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t1, t1, t2
; RV32I-NEXT: xor a4, a4, t1
-; RV32I-NEXT: lw t1, 148(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw t1, 168(sp) # 4-byte Folded Reload
; RV32I-NEXT: and t0, t1, t0
; RV32I-NEXT: xor a4, a4, t0
-; RV32I-NEXT: and t0, a0, s8
+; RV32I-NEXT: and t0, a0, s10
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: slli t0, t0, 8
; RV32I-NEXT: or a0, a0, t0
; RV32I-NEXT: xor a3, a3, a4
; RV32I-NEXT: or a0, a0, a5
; RV32I-NEXT: srli a4, a3, 8
-; RV32I-NEXT: and a4, a4, s8
+; RV32I-NEXT: and a4, a4, s10
; RV32I-NEXT: srli a5, a3, 24
; RV32I-NEXT: or a4, a4, a5
-; RV32I-NEXT: and a5, a3, s8
+; RV32I-NEXT: and a5, a3, s10
; RV32I-NEXT: slli a3, a3, 24
; RV32I-NEXT: slli a5, a5, 8
; RV32I-NEXT: or a3, a3, a5
@@ -4953,13 +4954,13 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: srli a4, a0, 2
-; RV32I-NEXT: and a0, a0, s7
-; RV32I-NEXT: and a4, a4, s7
+; RV32I-NEXT: and a0, a0, s9
+; RV32I-NEXT: and a4, a4, s9
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a4, a3, 2
-; RV32I-NEXT: and a4, a4, s7
-; RV32I-NEXT: and a3, a3, s7
+; RV32I-NEXT: and a4, a4, s9
+; RV32I-NEXT: and a3, a3, s9
; RV32I-NEXT: srli a5, a0, 1
; RV32I-NEXT: slli a3, a3, 2
; RV32I-NEXT: and a5, a5, a6
@@ -5019,26 +5020,26 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: mv a7, a3
; RV64I-NEXT: mv t5, a1
; RV64I-NEXT: srli a1, a2, 24
-; RV64I-NEXT: lui s4, 4080
-; RV64I-NEXT: and a1, a1, s4
+; RV64I-NEXT: lui s5, 4080
+; RV64I-NEXT: and a1, a1, s5
; RV64I-NEXT: li t0, 255
; RV64I-NEXT: srli a5, a2, 8
-; RV64I-NEXT: slli s3, t0, 24
-; RV64I-NEXT: and a5, a5, s3
+; RV64I-NEXT: slli s4, t0, 24
+; RV64I-NEXT: and a5, a5, s4
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: srli a6, a2, 40
-; RV64I-NEXT: addi t0, a3, -256
-; RV64I-NEXT: and a6, a6, t0
+; RV64I-NEXT: addi t6, a3, -256
+; RV64I-NEXT: and a6, a6, t6
; RV64I-NEXT: srli t1, a2, 56
; RV64I-NEXT: or a1, a5, a1
; RV64I-NEXT: or a5, a6, t1
; RV64I-NEXT: or a1, a1, a5
-; RV64I-NEXT: and a5, a2, s4
+; RV64I-NEXT: and a5, a2, s5
; RV64I-NEXT: srliw a6, a2, 24
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: slli a6, a6, 32
; RV64I-NEXT: or a5, a5, a6
-; RV64I-NEXT: and a6, a2, t0
+; RV64I-NEXT: and a6, a2, t6
; RV64I-NEXT: slli a6, a6, 40
; RV64I-NEXT: slli a2, a2, 56
; RV64I-NEXT: or a2, a2, a6
@@ -5048,9 +5049,9 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, a6, 32
; RV64I-NEXT: srli a5, a1, 4
-; RV64I-NEXT: add a6, a6, a2
-; RV64I-NEXT: and a2, a5, a6
-; RV64I-NEXT: and a1, a1, a6
+; RV64I-NEXT: add t0, a6, a2
+; RV64I-NEXT: and a2, a5, t0
+; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: lui a5, 209715
; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: addi t1, a5, 819
@@ -5065,34 +5066,34 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: addi t2, a5, 1365
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, t2, 32
-; RV64I-NEXT: srli a5, a1, 1
+; RV64I-NEXT: srli s6, a1, 1
; RV64I-NEXT: add t2, t2, a2
-; RV64I-NEXT: and a2, a5, t2
+; RV64I-NEXT: and a2, s6, t2
; RV64I-NEXT: srli a5, a0, 24
; RV64I-NEXT: srli t3, a0, 8
-; RV64I-NEXT: and a5, a5, s4
-; RV64I-NEXT: and t3, t3, s3
+; RV64I-NEXT: and a5, a5, s5
+; RV64I-NEXT: and t3, t3, s4
; RV64I-NEXT: or a5, t3, a5
; RV64I-NEXT: srli t3, a0, 40
-; RV64I-NEXT: and t3, t3, t0
+; RV64I-NEXT: and t3, t3, t6
; RV64I-NEXT: srli t4, a0, 56
; RV64I-NEXT: or t3, t3, t4
-; RV64I-NEXT: and t4, a0, s4
+; RV64I-NEXT: and t4, a0, s5
; RV64I-NEXT: slli t4, t4, 24
-; RV64I-NEXT: srliw t6, a0, 24
-; RV64I-NEXT: slli t6, t6, 32
-; RV64I-NEXT: and s0, a0, t0
-; RV64I-NEXT: slli s0, s0, 40
+; RV64I-NEXT: srliw s0, a0, 24
+; RV64I-NEXT: slli s0, s0, 32
+; RV64I-NEXT: and s1, a0, t6
+; RV64I-NEXT: slli s1, s1, 40
; RV64I-NEXT: slli a0, a0, 56
-; RV64I-NEXT: or t4, t4, t6
-; RV64I-NEXT: or a0, a0, s0
+; RV64I-NEXT: or t4, t4, s0
+; RV64I-NEXT: or a0, a0, s1
; RV64I-NEXT: or a5, a5, t3
; RV64I-NEXT: or a0, a0, t4
; RV64I-NEXT: and a1, a1, t2
; RV64I-NEXT: or a0, a0, a5
; RV64I-NEXT: srli a5, a0, 4
-; RV64I-NEXT: and a0, a0, a6
-; RV64I-NEXT: and a5, a5, a6
+; RV64I-NEXT: and a0, a0, t0
+; RV64I-NEXT: and a5, a5, t0
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: slli a1, a1, 1
; RV64I-NEXT: or a0, a5, a0
@@ -5103,1038 +5104,1040 @@ define void @commutative_clmulr_v2i64(<2 x i64> %x, <2 x i64> %y, ptr %p0, ptr %
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a0, a5, a0
; RV64I-NEXT: srli a2, a0, 1
-; RV64I-NEXT: and t4, a0, t2
+; RV64I-NEXT: and t3, a0, t2
; RV64I-NEXT: and a0, a2, t2
-; RV64I-NEXT: slli t4, t4, 1
+; RV64I-NEXT: slli t3, t3, 1
; RV64I-NEXT: slli a2, a1, 1
-; RV64I-NEXT: or a0, a0, t4
+; RV64I-NEXT: or a0, a0, t3
; RV64I-NEXT: andi a5, a0, 2
-; RV64I-NEXT: andi t3, a0, 1
+; RV64I-NEXT: andi t4, a0, 1
; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: seqz t4, t4
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: addi t4, t4, -1
; RV64I-NEXT: and a2, a5, a2
-; RV64I-NEXT: and a5, t3, a1
-; RV64I-NEXT: slli t3, a1, 2
-; RV64I-NEXT: andi t6, a0, 4
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: andi s0, a0, 8
-; RV64I-NEXT: addi t6, t6, -1
+; RV64I-NEXT: and a5, t4, a1
+; RV64I-NEXT: slli t4, a1, 2
+; RV64I-NEXT: andi s0, a0, 4
; RV64I-NEXT: seqz s0, s0
-; RV64I-NEXT: slli s1, a1, 3
+; RV64I-NEXT: andi s1, a0, 8
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: and t3, t6, t3
-; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s1
+; RV64I-NEXT: slli s2, a1, 3
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: and t4, s0, t4
+; RV64I-NEXT: and s0, s1, s2
; RV64I-NEXT: xor a2, a5, a2
-; RV64I-NEXT: xor a5, t3, s0
+; RV64I-NEXT: xor a5, t4, s0
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: andi a5, a0, 16
-; RV64I-NEXT: slli t3, a1, 4
+; RV64I-NEXT: slli t4, a1, 4
; RV64I-NEXT: seqz a5, a5
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: andi t6, a0, 32
-; RV64I-NEXT: and a5, a5, t3
-; RV64I-NEXT: seqz t3, t6
-; RV64I-NEXT: slli t6, a1, 5
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: and t3, t3, t6
-; RV64I-NEXT: andi t6, a0, 64
-; RV64I-NEXT: xor a5, a5, t3
-; RV64I-NEXT: seqz t3, t6
-; RV64I-NEXT: slli t6, a1, 6
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: and t3, t3, t6
-; RV64I-NEXT: andi t6, a0, 128
-; RV64I-NEXT: xor a5, a5, t3
-; RV64I-NEXT: seqz t3, t6
-; RV64I-NEXT: slli t6, a1, 7
-; RV64I-NEXT: addi t3, t3, -1
-; RV64I-NEXT: and t3, t3, t6
-; RV64I-NEXT: andi t6, a0, 256
-; RV64I-NEXT: slli s0, a1, 8
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: andi s1, a0, 512
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: slli s1, a1, 9
+; RV64I-NEXT: andi s0, a0, 32
+; RV64I-NEXT: and a5, a5, t4
+; RV64I-NEXT: seqz t4, s0
+; RV64I-NEXT: slli s0, a1, 5
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: and t4, t4, s0
+; RV64I-NEXT: andi s0, a0, 64
+; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: seqz t4, s0
+; RV64I-NEXT: slli s0, a1, 6
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: and t4, t4, s0
+; RV64I-NEXT: andi s0, a0, 128
+; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: seqz t4, s0
+; RV64I-NEXT: slli s0, a1, 7
+; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: and t4, t4, s0
+; RV64I-NEXT: andi s0, a0, 256
+; RV64I-NEXT: slli s1, a1, 8
+; RV64I-NEXT: seqz s0, s0
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: xor t3, t3, t6
+; RV64I-NEXT: andi s2, a0, 512
; RV64I-NEXT: and s0, s0, s1
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: xor a5, t3, s0
-; RV64I-NEXT: slli t6, a1, 10
-; RV64I-NEXT: andi t3, a0, 1024
-; RV64I-NEXT: seqz s0, t3
-; RV64I-NEXT: li t3, 1
-; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli a4, t3, 11
-; RV64I-NEXT: sd a4, 176(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a4
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: slli s0, a1, 11
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: lui s1, 1
-; RV64I-NEXT: slli s0, a1, 12
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: lui a4, 2
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: and s2, a0, a4
-; RV64I-NEXT: and s0, s1, s0
; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: slli s2, a1, 13
+; RV64I-NEXT: slli s2, a1, 9
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: xor t6, t6, s0
+; RV64I-NEXT: xor t4, t4, s0
; RV64I-NEXT: and s0, s1, s2
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: lui s1, 4
-; RV64I-NEXT: slli s0, a1, 14
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: seqz s1, s1
-; RV64I-NEXT: lui a4, 8
+; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: xor a5, t4, s0
+; RV64I-NEXT: slli s0, a1, 10
+; RV64I-NEXT: andi t4, a0, 1024
+; RV64I-NEXT: seqz s1, t4
+; RV64I-NEXT: li t4, 1
; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: and s2, a0, a4
+; RV64I-NEXT: slli a4, t4, 11
+; RV64I-NEXT: sd a4, 176(sp) # 8-byte Folded Spill
; RV64I-NEXT: and s0, s1, s0
-; RV64I-NEXT: seqz s1, s2
-; RV64I-NEXT: slli s2, a1, 15
-; RV64I-NEXT: addi s1, s1, -1
-; RV64I-NEXT: xor t6, t6, s0
-; RV64I-NEXT: and s0, s1, s2
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: xor a5, t6, s0
+; RV64I-NEXT: and s1, a0, a4
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: slli s1, a1, 11
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: lui a4, 1
+; RV64I-NEXT: slli s1, a1, 12
+; RV64I-NEXT: and s2, a0, a4
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: lui a4, 2
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: and s3, a0, a4
+; RV64I-NEXT: and s1, s2, s1
+; RV64I-NEXT: seqz s2, s3
+; RV64I-NEXT: slli s3, a1, 13
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: and s1, s2, s3
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: lui a4, 4
+; RV64I-NEXT: slli s1, a1, 14
+; RV64I-NEXT: and s2, a0, a4
+; RV64I-NEXT: seqz s2, s2
+; RV64I-NEXT: lui a4, 8
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: and s3, a0, a4
+; RV64I-NEXT: and s1, s2, s1
+; RV64I-NEXT: seqz s2, s3
+; RV64I-NEXT: slli s3, a1, 15
+; RV64I-NEXT: addi s2, s2, -1
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: and s1, s2, s3
; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: xor s0, s0, s1
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: slli a5, a1, 16
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: lui s0, 32
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and s0, a0, s0
-; RV64I-NEXT: and a5, t6, a5
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: slli s0, a1, 17
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: lui a3, 64
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: slli s0, a1, 18
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui a3, 128
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: slli s0, a1, 19
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: lui a3, 256
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: slli s0, a1, 20
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui a3, 512
-; RV64I-NEXT: and t6, t6, s0
; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 21
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: lui a3, 1024
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: seqz a5, t6
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui s0, 2048
-; RV64I-NEXT: slli t6, a1, 22
-; RV64I-NEXT: and s0, a0, s0
-; RV64I-NEXT: and a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui s1, 4096
-; RV64I-NEXT: slli s0, a1, 23
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: seqz s0, s0
+; RV64I-NEXT: lui s1, 32
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 24
-; RV64I-NEXT: lui a3, 8192
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui s1, 16384
-; RV64I-NEXT: slli s0, a1, 25
; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and a5, s0, a5
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: slli s1, a1, 17
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 26
-; RV64I-NEXT: lui a3, 32768
-; RV64I-NEXT: and t6, s0, t6
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: lui a3, 64
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: lui s1, 65536
-; RV64I-NEXT: slli s0, a1, 27
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: slli s1, a1, 18
+; RV64I-NEXT: seqz s0, s0
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli s1, a1, 28
-; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: lui a3, 128
; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: and s1, a0, a3
; RV64I-NEXT: xor a5, a5, s0
-; RV64I-NEXT: lui a3, 131072
-; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: and a5, a0, a3
-; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: lui a3, 262144
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: slli s0, a1, 29
-; RV64I-NEXT: and a5, a5, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 30
-; RV64I-NEXT: sraiw s1, a0, 31
-; RV64I-NEXT: and t6, t6, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 31
-; RV64I-NEXT: slli a3, t3, 32
-; RV64I-NEXT: sd a3, 168(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
+; RV64I-NEXT: lui a3, 256
+; RV64I-NEXT: slli s1, a1, 19
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 20
+; RV64I-NEXT: lui a3, 512
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s1, a1, 21
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: lui a3, 1024
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 33
-; RV64I-NEXT: sd s1, 160(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 32
+; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: seqz a5, s0
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: lui s1, 2048
+; RV64I-NEXT: slli s0, a1, 22
; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: lui a3, 4096
+; RV64I-NEXT: slli s1, a1, 23
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 24
+; RV64I-NEXT: lui a3, 8192
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: lui a3, 16384
+; RV64I-NEXT: slli s1, a1, 25
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 26
+; RV64I-NEXT: lui a3, 32768
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: lui a3, 65536
+; RV64I-NEXT: slli s1, a1, 27
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s2, a1, 28
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: and s0, s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: lui a3, 131072
+; RV64I-NEXT: xor a2, a2, a5
+; RV64I-NEXT: and a5, a0, a3
+; RV64I-NEXT: seqz a5, a5
+; RV64I-NEXT: lui s0, 262144
+; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: and s0, a0, s0
+; RV64I-NEXT: seqz s0, s0
+; RV64I-NEXT: slli s1, a1, 29
+; RV64I-NEXT: and a5, a5, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s1, a1, 30
+; RV64I-NEXT: sraiw s2, a0, 31
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 31
+; RV64I-NEXT: slli a3, t4, 32
+; RV64I-NEXT: sd a3, 168(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 33
-; RV64I-NEXT: slli a3, t3, 34
+; RV64I-NEXT: slli a3, t4, 33
+; RV64I-NEXT: sd a3, 160(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 32
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 33
+; RV64I-NEXT: slli a3, t4, 34
; RV64I-NEXT: sd a3, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 35
-; RV64I-NEXT: sd s1, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 34
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 35
-; RV64I-NEXT: slli a3, t3, 36
+; RV64I-NEXT: slli a3, t4, 35
+; RV64I-NEXT: sd a3, 144(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 34
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 35
+; RV64I-NEXT: slli a3, t4, 36
; RV64I-NEXT: sd a3, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 36
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: slli a3, t3, 37
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: seqz s0, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s1, a1, 36
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: slli a3, t4, 37
; RV64I-NEXT: sd a3, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: and t6, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: and s0, a0, a3
; RV64I-NEXT: xor a2, a2, a5
-; RV64I-NEXT: seqz a5, t6
+; RV64I-NEXT: seqz a5, s0
; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli s0, t3, 38
-; RV64I-NEXT: sd s0, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli t6, a1, 37
-; RV64I-NEXT: and s0, a0, s0
-; RV64I-NEXT: and a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 39
-; RV64I-NEXT: sd s1, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 38
+; RV64I-NEXT: slli s1, t4, 38
+; RV64I-NEXT: sd s1, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s0, a1, 37
; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 39
-; RV64I-NEXT: slli a3, t3, 40
+; RV64I-NEXT: slli a3, t4, 39
+; RV64I-NEXT: sd a3, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 38
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 39
+; RV64I-NEXT: slli a3, t4, 40
; RV64I-NEXT: sd a3, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 41
-; RV64I-NEXT: sd s1, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 40
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 41
-; RV64I-NEXT: slli a3, t3, 42
+; RV64I-NEXT: slli a3, t4, 41
+; RV64I-NEXT: sd a3, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 40
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 41
+; RV64I-NEXT: slli a3, t4, 42
; RV64I-NEXT: sd a3, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 43
-; RV64I-NEXT: sd s1, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 42
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a5, a5, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 43
-; RV64I-NEXT: slli a3, t3, 44
+; RV64I-NEXT: slli a3, t4, 43
+; RV64I-NEXT: sd a3, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 42
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 43
+; RV64I-NEXT: slli a3, t4, 44
; RV64I-NEXT: sd a3, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a5, a5, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 45
-; RV64I-NEXT: sd s1, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 44
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a5, a5, s0
; RV64I-NEXT: seqz s0, s1
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli s1, a1, 45
-; RV64I-NEXT: xor a5, a5, t6
+; RV64I-NEXT: slli a3, t4, 45
+; RV64I-NEXT: sd a3, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 44
+; RV64I-NEXT: and s2, a0, a3
; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s2, a1, 45
+; RV64I-NEXT: xor a5, a5, s0
+; RV64I-NEXT: and s0, s1, s2
; RV64I-NEXT: xor a5, a5, s0
-; RV64I-NEXT: slli a3, t3, 46
+; RV64I-NEXT: slli a3, t4, 46
; RV64I-NEXT: sd a3, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: xor a5, a2, a5
+; RV64I-NEXT: xor a6, a2, a5
; RV64I-NEXT: and a2, a0, a3
; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: slli a3, t3, 47
-; RV64I-NEXT: sd a3, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s0, t4, 47
+; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: and t6, a0, a3
-; RV64I-NEXT: seqz t6, t6
-; RV64I-NEXT: slli s0, a1, 46
-; RV64I-NEXT: and a2, a2, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s0, a1, 47
-; RV64I-NEXT: slli a3, t3, 48
+; RV64I-NEXT: and s0, a0, s0
+; RV64I-NEXT: seqz s0, s0
+; RV64I-NEXT: slli s1, a1, 46
+; RV64I-NEXT: and a2, a2, s1
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s1, a1, 47
+; RV64I-NEXT: slli a3, t4, 48
; RV64I-NEXT: sd a3, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, t6, s0
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s1, t3, 49
-; RV64I-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli s0, a1, 48
-; RV64I-NEXT: and s1, a0, s1
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 49
-; RV64I-NEXT: slli a3, t3, 50
+; RV64I-NEXT: slli a3, t4, 49
+; RV64I-NEXT: sd a3, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 48
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 49
+; RV64I-NEXT: slli a3, t4, 50
; RV64I-NEXT: sd a3, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, a3
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli ra, t3, 51
-; RV64I-NEXT: slli s0, a1, 50
-; RV64I-NEXT: and s1, a0, ra
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, a3
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 51
-; RV64I-NEXT: slli s11, t3, 52
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, s11
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s10, t3, 53
-; RV64I-NEXT: slli s0, a1, 52
-; RV64I-NEXT: and s1, a0, s10
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: slli a3, t4, 51
+; RV64I-NEXT: sd a3, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli s1, a1, 50
+; RV64I-NEXT: and s2, a0, a3
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 51
+; RV64I-NEXT: slli s11, t4, 52
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, s11
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 53
-; RV64I-NEXT: slli s9, t3, 54
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, s9
-; RV64I-NEXT: xor a2, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s8, t3, 55
-; RV64I-NEXT: slli s0, a1, 54
-; RV64I-NEXT: and s1, a0, s8
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: slli ra, t4, 53
+; RV64I-NEXT: slli s1, a1, 52
+; RV64I-NEXT: and s2, a0, ra
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 53
+; RV64I-NEXT: slli s10, t4, 54
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, s10
+; RV64I-NEXT: xor a2, a2, s0
; RV64I-NEXT: seqz s0, s1
-; RV64I-NEXT: xor a2, a2, t6
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli t6, a1, 55
-; RV64I-NEXT: slli s7, t3, 56
-; RV64I-NEXT: and t6, s0, t6
-; RV64I-NEXT: and s0, a0, s7
-; RV64I-NEXT: xor a4, a2, t6
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s5, t3, 57
-; RV64I-NEXT: slli s0, a1, 56
-; RV64I-NEXT: and s1, a0, s5
-; RV64I-NEXT: and t6, t6, s0
+; RV64I-NEXT: slli s9, t4, 55
+; RV64I-NEXT: slli s1, a1, 54
+; RV64I-NEXT: and s2, a0, s9
+; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: xor a2, a2, s0
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s0, a1, 55
+; RV64I-NEXT: slli s8, t4, 56
+; RV64I-NEXT: and s0, s1, s0
+; RV64I-NEXT: and s1, a0, s8
+; RV64I-NEXT: xor a5, a2, s0
; RV64I-NEXT: seqz s0, s1
; RV64I-NEXT: addi s0, s0, -1
-; RV64I-NEXT: slli s6, t3, 58
-; RV64I-NEXT: slli s1, a1, 57
-; RV64I-NEXT: and a2, a0, s6
+; RV64I-NEXT: slli s3, t4, 57
+; RV64I-NEXT: slli s1, a1, 56
+; RV64I-NEXT: and s2, a0, s3
; RV64I-NEXT: and s0, s0, s1
+; RV64I-NEXT: seqz s1, s2
+; RV64I-NEXT: addi s1, s1, -1
+; RV64I-NEXT: slli s7, t4, 58
+; RV64I-NEXT: slli s2, a1, 57
+; RV64I-NEXT: and a2, a0, s7
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: seqz a2, a2
-; RV64I-NEXT: xor t6, t6, s0
+; RV64I-NEXT: xor s0, s0, s1
; RV64I-NEXT: addi a2, a2, -1
-; RV64I-NEXT: slli s0, a1, 58
-; RV64I-NEXT: slli s1, t3, 59
-; RV64I-NEXT: and a2, a2, s0
-; RV64I-NEXT: and s0, a0, s1
-; RV64I-NEXT: xor a3, t6, a2
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: addi t6, t6, -1
-; RV64I-NEXT: slli s2, t3, 60
+; RV64I-NEXT: slli s2, a1, 58
+; RV64I-NEXT: slli s1, t4, 59
+; RV64I-NEXT: and a2, a2, s2
+; RV64I-NEXT: and s2, a0, s1
+; RV64I-NEXT: xor a4, s0, a2
+; RV64I-NEXT: seqz s0, s2
+; RV64I-NEXT: addi s0, s0, -1
+; RV64I-NEXT: slli s2, t4, 60
; RV64I-NEXT: slli a2, a1, 59
-; RV64I-NEXT: and s0, a0, s2
-; RV64I-NEXT: and a2, t6, a2
-; RV64I-NEXT: seqz t6, s0
-; RV64I-NEXT: xor a2, a3, a2
-; RV64I-NEXT: addi a3, t6, -1
-; RV64I-NEXT: slli s0, a1, 60
-; RV64I-NEXT: slli t6, t3, 61
-; RV64I-NEXT: and a3, a3, s0
-; RV64I-NEXT: and s0, a0, t6
+; RV64I-NEXT: and a3, a0, s2
+; RV64I-NEXT: and a2, s0, a2
+; RV64I-NEXT: seqz a3, a3
+; RV64I-NEXT: xor a2, a4, a2
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a4, a1, 60
+; RV64I-NEXT: slli s0, t4, 61
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: and a4, a0, s0
; RV64I-NEXT: xor a2, a2, a3
-; RV64I-NEXT: seqz a3, s0
+; RV64I-NEXT: seqz a3, a4
; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: slli t3, t3, 62
-; RV64I-NEXT: and a0, a0, t3
-; RV64I-NEXT: slli s0, a1, 61
-; RV64I-NEXT: and a3, a3, s0
-; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: slli a4, a1, 61
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slli t4, t4, 62
; RV64I-NEXT: xor a2, a2, a3
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: srli a3, t4, 63
-; RV64I-NEXT: slli t4, a1, 62
; RV64I-NEXT: and a0, a0, t4
-; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: slli a1, a1, 63
-; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: slli a1, a1, 62
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: srli a3, t3, 63
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: seqz a1, a3
+; RV64I-NEXT: slli s6, s6, 63
+; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: and a1, a3, a1
-; RV64I-NEXT: xor a4, a5, a4
+; RV64I-NEXT: and a1, a1, s6
+; RV64I-NEXT: xor a2, a6, a5
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: xor a0, a4, a0
+; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: srli a1, a0, 40
-; RV64I-NEXT: and a1, a1, t0
+; RV64I-NEXT: and a1, a1, t6
; RV64I-NEXT: srli a2, a0, 24
-; RV64I-NEXT: and a2, a2, s4
+; RV64I-NEXT: and a2, a2, s5
; RV64I-NEXT: srli a3, a0, 8
-; RV64I-NEXT: and a3, a3, s3
+; RV64I-NEXT: and a3, a3, s4
; RV64I-NEXT: srli a4, a0, 56
; RV64I-NEXT: or a1, a1, a4
; RV64I-NEXT: or a2, a3, a2
-; RV64I-NEXT: or s0, a2, a1
+; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 24
-; RV64I-NEXT: and a2, a0, s4
+; RV64I-NEXT: and a2, a0, s5
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: slli a2, a2, 24
; RV64I-NEXT: or a1, a2, a1
-; RV64I-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: and a1, a0, t0
+; RV64I-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: and a1, a0, t6
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: slli a1, a1, 40
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: srli a0, a7, 24
-; RV64I-NEXT: and a0, a0, s4
-; RV64I-NEXT: srli a1, a7, 8
-; RV64I-NEXT: and a1, a1, s3
-; RV64I-NEXT: srli a2, a7, 40
-; RV64I-NEXT: and a2, a2, t0
-; RV64I-NEXT: srli a3, a7, 56
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: or a2, a2, a3
-; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: and a1, a7, s4
-; RV64I-NEXT: slli a1, a1, 24
-; RV64I-NEXT: srliw a2, a7, 24
-; RV64I-NEXT: slli a2, a2, 32
-; RV64I-NEXT: and a3, a7, t0
-; RV64I-NEXT: slli a3, a3, 40
+; RV64I-NEXT: srli a1, a7, 24
+; RV64I-NEXT: and a1, a1, s5
+; RV64I-NEXT: srli a2, a7, 8
+; RV64I-NEXT: and a2, a2, s4
+; RV64I-NEXT: srli a3, a7, 40
+; RV64I-NEXT: and a3, a3, t6
+; RV64I-NEXT: srli a4, a7, 56
+; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: or a3, a3, a4
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: and a2, a7, s5
+; RV64I-NEXT: slli a2, a2, 24
+; RV64I-NEXT: srliw a3, a7, 24
+; RV64I-NEXT: slli a3, a3, 32
+; RV64I-NEXT: and a4, a7, t6
+; RV64I-NEXT: slli a4, a4, 40
; RV64I-NEXT: slli a7, a7, 56
-; RV64I-NEXT: or a1, a1, a2
-; RV64I-NEXT: or a2, a7, a3
-; RV64I-NEXT: srli a3, t5, 24
-; RV64I-NEXT: srli a4, t5, 8
-; RV64I-NEXT: and a3, a3, s4
-; RV64I-NEXT: and a4, a4, s3
-; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a4, t5, 40
-; RV64I-NEXT: and a4, a4, t0
-; RV64I-NEXT: srli a5, t5, 56
-; RV64I-NEXT: or a4, a4, a5
-; RV64I-NEXT: and a5, t5, s4
-; RV64I-NEXT: slli a5, a5, 24
+; RV64I-NEXT: or a2, a2, a3
+; RV64I-NEXT: or a3, a7, a4
+; RV64I-NEXT: srli a4, t5, 24
+; RV64I-NEXT: srli a5, t5, 8
+; RV64I-NEXT: and a4, a4, s5
+; RV64I-NEXT: and a5, a5, s4
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a5, t5, 40
+; RV64I-NEXT: and a5, a5, t6
+; RV64I-NEXT: srli a6, t5, 56
+; RV64I-NEXT: or a5, a5, a6
+; RV64I-NEXT: and a6, t5, s5
+; RV64I-NEXT: slli a6, a6, 24
; RV64I-NEXT: srliw a7, t5, 24
; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: and t4, t5, t0
-; RV64I-NEXT: slli t4, t4, 40
+; RV64I-NEXT: and t3, t5, t6
+; RV64I-NEXT: slli t3, t3, 40
; RV64I-NEXT: slli t5, t5, 56
-; RV64I-NEXT: or a5, a5, a7
-; RV64I-NEXT: or a7, t5, t4
+; RV64I-NEXT: or a6, a6, a7
+; RV64I-NEXT: or a7, t5, t3
+; RV64I-NEXT: or a4, a4, a5
+; RV64I-NEXT: or a5, a7, a6
+; RV64I-NEXT: or a2, a3, a2
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: srli a3, a4, 4
+; RV64I-NEXT: and a4, a4, t0
+; RV64I-NEXT: and a3, a3, t0
+; RV64I-NEXT: slli a4, a4, 4
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a3, a3, a4
-; RV64I-NEXT: or a4, a7, a5
+; RV64I-NEXT: srli a2, a1, 4
+; RV64I-NEXT: and a1, a1, t0
+; RV64I-NEXT: and a2, a2, t0
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: srli a4, a3, 2
+; RV64I-NEXT: and a3, a3, t1
+; RV64I-NEXT: and a4, a4, t1
+; RV64I-NEXT: slli a3, a3, 2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: srli a2, a3, 4
-; RV64I-NEXT: and a3, a3, a6
-; RV64I-NEXT: and a2, a2, a6
-; RV64I-NEXT: slli a3, a3, 4
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: or a2, a2, a3
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: and a0, a0, a6
-; RV64I-NEXT: and a1, a1, a6
-; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: srli a3, a2, 2
-; RV64I-NEXT: and a2, a2, t1
-; RV64I-NEXT: and a3, a3, t1
-; RV64I-NEXT: slli a2, a2, 2
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: or a2, a3, a2
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: and a0, a0, t1
+; RV64I-NEXT: srli a2, a1, 2
; RV64I-NEXT: and a1, a1, t1
-; RV64I-NEXT: slli a0, a0, 2
-; RV64I-NEXT: or a1, a1, a0
-; RV64I-NEXT: srli a0, a2, 1
-; RV64I-NEXT: and a3, a0, t2
-; RV64I-NEXT: and a0, a2, t2
-; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: srli a2, a1, 1
+; RV64I-NEXT: and a2, a2, t1
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: or a2, a2, a1
+; RV64I-NEXT: srli a1, a3, 1
+; RV64I-NEXT: and a4, a1, t2
+; RV64I-NEXT: and a3, a3, t2
+; RV64I-NEXT: slli a3, a3, 1
+; RV64I-NEXT: srli a1, a2, 1
; RV64I-NEXT: and a2, a2, t2
-; RV64I-NEXT: or a3, a3, a0
-; RV64I-NEXT: and a1, a1, t2
-; RV64I-NEXT: andi a4, a3, 2
-; RV64I-NEXT: slli a1, a1, 1
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: or a1, a2, a1
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a2, a1, 1
-; RV64I-NEXT: andi a5, a3, 1
-; RV64I-NEXT: and a2, a4, a2
-; RV64I-NEXT: seqz a4, a5
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: andi a5, a3, 4
-; RV64I-NEXT: and a4, a4, a1
-; RV64I-NEXT: seqz a5, a5
-; RV64I-NEXT: xor a2, a4, a2
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, a1, 2
-; RV64I-NEXT: andi a7, a3, 8
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 3
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 16
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, a1, 4
-; RV64I-NEXT: andi a7, a3, 32
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 5
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 64
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 6
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 128
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a4, a1, 7
-; RV64I-NEXT: andi a7, a3, 256
-; RV64I-NEXT: and a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 8
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 512
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 9
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: andi a7, a3, 1024
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 10
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 176(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 1
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 11
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 12
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: lui a7, 2
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 13
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 4
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 14
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 8
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 15
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 16
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 32
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 16
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 17
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: lui a7, 64
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 18
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 128
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 19
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 256
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 20
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 512
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 21
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 1024
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 2048
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 22
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 23
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: lui a7, 4096
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 24
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 8192
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 25
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 16384
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 26
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 32768
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 27
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 65536
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 28
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: lui a7, 131072
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: lui a4, 262144
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 29
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 30
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: sraiw a7, a3, 31
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 31
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 168(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 32
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 160(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 33
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 34
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 35
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 36
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: ld a4, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a4, a3, a4
-; RV64I-NEXT: slli a7, a1, 37
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: seqz a4, a4
-; RV64I-NEXT: addi a4, a4, -1
-; RV64I-NEXT: slli a7, a1, 38
-; RV64I-NEXT: and a4, a4, a7
-; RV64I-NEXT: ld a7, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a5, a4
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 39
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 40
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 41
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 42
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 43
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 44
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
-; RV64I-NEXT: slli a7, a1, 45
-; RV64I-NEXT: and a5, a5, a7
-; RV64I-NEXT: ld a7, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: xor a4, a4, a5
-; RV64I-NEXT: seqz a5, a7
-; RV64I-NEXT: addi a5, a5, -1
+; RV64I-NEXT: or a4, a4, a3
+; RV64I-NEXT: slli a2, a2, 1
+; RV64I-NEXT: andi a5, a4, 2
+; RV64I-NEXT: seqz a6, a5
+; RV64I-NEXT: and a5, a1, t2
+; RV64I-NEXT: or a5, a5, a2
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli a2, a5, 1
+; RV64I-NEXT: andi a7, a4, 1
+; RV64I-NEXT: and a2, a6, a2
+; RV64I-NEXT: seqz a6, a7
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: andi a7, a4, 4
+; RV64I-NEXT: and a6, a6, a5
+; RV64I-NEXT: seqz a7, a7
+; RV64I-NEXT: xor a2, a6, a2
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli a6, a5, 2
+; RV64I-NEXT: andi t3, a4, 8
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 3
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 16
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli a6, a5, 4
+; RV64I-NEXT: andi t3, a4, 32
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 5
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 64
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 6
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 128
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli a6, a5, 7
+; RV64I-NEXT: andi t3, a4, 256
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 8
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 512
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 9
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: andi t3, a4, 1024
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 10
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 176(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 1
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 11
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 12
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: lui t3, 2
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 13
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 4
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 14
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 8
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 15
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 16
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 32
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 16
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 17
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: lui t3, 64
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 18
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 128
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 19
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 256
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 20
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 512
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 21
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 1024
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 2048
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 22
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 23
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: lui t3, 4096
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 24
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 8192
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 25
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 16384
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 26
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 32768
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 27
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 65536
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 28
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: lui t3, 131072
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: lui a6, 262144
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 29
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 30
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: sraiw t3, a4, 31
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 31
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 168(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 32
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 160(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 33
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 152(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 34
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 144(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 35
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 36
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: xor a2, a2, a6
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: ld a6, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a6, a4, a6
+; RV64I-NEXT: slli t3, a5, 37
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz a6, a6
+; RV64I-NEXT: addi a6, a6, -1
+; RV64I-NEXT: slli t3, a5, 38
+; RV64I-NEXT: and a6, a6, t3
+; RV64I-NEXT: ld t3, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a7, a6
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 39
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 40
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 41
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 42
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 43
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 44
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: seqz a7, t3
+; RV64I-NEXT: addi a7, a7, -1
+; RV64I-NEXT: slli t3, a5, 45
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: ld t3, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: xor t5, a6, a7
+; RV64I-NEXT: seqz a6, t3
+; RV64I-NEXT: addi a6, a6, -1
; RV64I-NEXT: ld a7, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
+; RV64I-NEXT: and a7, a4, a7
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: slli t4, a1, 46
-; RV64I-NEXT: and a5, a5, t4
+; RV64I-NEXT: slli t3, a5, 46
+; RV64I-NEXT: and a6, a6, t3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: ld t4, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and t4, a3, t4
-; RV64I-NEXT: slli t5, a1, 47
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: addi t4, t4, -1
+; RV64I-NEXT: ld t3, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: slli s6, a5, 47
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: addi t3, t3, -1
; RV64I-NEXT: ld a7, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and a7, a3, a7
-; RV64I-NEXT: slli t5, a1, 48
-; RV64I-NEXT: and t4, t4, t5
+; RV64I-NEXT: and a7, a4, a7
+; RV64I-NEXT: slli s6, a5, 48
+; RV64I-NEXT: and t3, t3, s6
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: ld t4, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: and t4, a3, t4
-; RV64I-NEXT: slli t5, a1, 49
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and a7, a3, ra
-; RV64I-NEXT: slli t5, a1, 50
-; RV64I-NEXT: and t4, t4, t5
+; RV64I-NEXT: ld t3, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and t3, a4, t3
+; RV64I-NEXT: slli s6, a5, 49
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: ld a7, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: and a7, a4, a7
+; RV64I-NEXT: slli s6, a5, 50
+; RV64I-NEXT: and t3, t3, s6
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: xor a5, a5, t4
+; RV64I-NEXT: xor a6, a6, t3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and t4, a3, s11
-; RV64I-NEXT: slli t5, a1, 51
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and a7, a3, s10
-; RV64I-NEXT: slli t5, a1, 52
-; RV64I-NEXT: and t4, t4, t5
+; RV64I-NEXT: and t3, a4, s11
+; RV64I-NEXT: slli s6, a5, 51
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: seqz t3, t3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: and a7, a4, ra
+; RV64I-NEXT: slli s6, a5, 52
+; RV64I-NEXT: and t3, t3, s6
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: slli t5, a1, 53
-; RV64I-NEXT: xor a5, a5, t4
-; RV64I-NEXT: and a7, a7, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, a3, s9
-; RV64I-NEXT: slli t4, a1, 54
+; RV64I-NEXT: slli s6, a5, 53
+; RV64I-NEXT: xor a6, a6, t3
+; RV64I-NEXT: and a7, a7, s6
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, a4, s10
+; RV64I-NEXT: slli t3, a5, 54
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and t5, a3, s8
-; RV64I-NEXT: and a7, a7, t4
-; RV64I-NEXT: seqz t4, t5
-; RV64I-NEXT: slli t5, a1, 55
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: xor a4, a5, a7
-; RV64I-NEXT: slli a5, a1, 56
-; RV64I-NEXT: and a7, a3, s7
+; RV64I-NEXT: and s6, a4, s9
+; RV64I-NEXT: and a7, a7, t3
+; RV64I-NEXT: seqz t3, s6
+; RV64I-NEXT: slli s6, a5, 55
+; RV64I-NEXT: addi t3, t3, -1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, t3, s6
+; RV64I-NEXT: xor a2, a2, t5
+; RV64I-NEXT: xor t3, a6, a7
+; RV64I-NEXT: slli a6, a5, 56
+; RV64I-NEXT: and a7, a4, s8
; RV64I-NEXT: seqz a7, a7
-; RV64I-NEXT: and t4, a3, s5
+; RV64I-NEXT: and t5, a4, s3
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: seqz t4, t4
-; RV64I-NEXT: slli t5, a1, 57
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: and a5, a7, a5
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, a3, s6
-; RV64I-NEXT: slli t4, a1, 58
+; RV64I-NEXT: seqz t5, t5
+; RV64I-NEXT: slli s3, a5, 57
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: and a6, a7, a6
+; RV64I-NEXT: and a7, t5, s3
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, a4, s7
+; RV64I-NEXT: slli t5, a5, 58
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and s1, a3, s1
-; RV64I-NEXT: and a7, a7, t4
-; RV64I-NEXT: seqz t4, s1
-; RV64I-NEXT: slli t5, a1, 59
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, a3, s2
-; RV64I-NEXT: slli t4, a1, 60
+; RV64I-NEXT: and s1, a4, s1
+; RV64I-NEXT: and a7, a7, t5
+; RV64I-NEXT: seqz t5, s1
+; RV64I-NEXT: slli s1, a5, 59
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, t5, s1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, a4, s2
+; RV64I-NEXT: slli t5, a5, 60
; RV64I-NEXT: seqz a7, a7
; RV64I-NEXT: addi a7, a7, -1
-; RV64I-NEXT: and t5, a3, t6
-; RV64I-NEXT: and a7, a7, t4
-; RV64I-NEXT: seqz t4, t5
-; RV64I-NEXT: slli t5, a1, 61
-; RV64I-NEXT: addi t4, t4, -1
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a7, t4, t5
-; RV64I-NEXT: xor a5, a5, a7
-; RV64I-NEXT: and a3, a3, t3
-; RV64I-NEXT: slli a7, a1, 62
+; RV64I-NEXT: and s0, a4, s0
+; RV64I-NEXT: and a7, a7, t5
+; RV64I-NEXT: seqz t5, s0
+; RV64I-NEXT: slli s0, a5, 61
+; RV64I-NEXT: addi t5, t5, -1
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a7, t5, s0
+; RV64I-NEXT: xor a6, a6, a7
+; RV64I-NEXT: and a4, a4, t4
+; RV64I-NEXT: slli a5, a5, 62
+; RV64I-NEXT: seqz a4, a4
+; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: srli a3, a3, 63
+; RV64I-NEXT: and a4, a4, a5
; RV64I-NEXT: seqz a3, a3
-; RV64I-NEXT: addi a3, a3, -1
-; RV64I-NEXT: srli a0, a0, 63
-; RV64I-NEXT: and a3, a3, a7
-; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: slli a1, a1, 63
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: xor a3, a5, a3
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: xor a2, a2, a4
-; RV64I-NEXT: xor a0, a3, a0
-; RV64I-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld a3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: or a1, a3, a1
-; RV64I-NEXT: xor a0, a2, a0
-; RV64I-NEXT: or a1, a1, s0
-; RV64I-NEXT: srli a2, a0, 40
-; RV64I-NEXT: and a2, a2, t0
-; RV64I-NEXT: srli a3, a0, 8
-; RV64I-NEXT: srli a4, a0, 24
-; RV64I-NEXT: and a3, a3, s3
-; RV64I-NEXT: srli a5, a0, 56
-; RV64I-NEXT: and a4, a4, s4
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: xor a4, a6, a4
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: xor a2, a2, t3
+; RV64I-NEXT: xor a1, a4, a1
+; RV64I-NEXT: ld a3, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: xor a1, a2, a1
+; RV64I-NEXT: ld a2, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: srli a2, a1, 40
+; RV64I-NEXT: and a2, a2, t6
+; RV64I-NEXT: srli a3, a1, 8
+; RV64I-NEXT: srli a4, a1, 24
+; RV64I-NEXT: and a3, a3, s4
+; RV64I-NEXT: srli a5, a1, 56
+; RV64I-NEXT: and a4, a4, s5
; RV64I-NEXT: or a2, a2, a5
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: or a2, a3, a2
-; RV64I-NEXT: srliw a3, a0, 24
+; RV64I-NEXT: srliw a3, a1, 24
; RV64I-NEXT: slli a3, a3, 32
-; RV64I-NEXT: and a4, a0, s4
+; RV64I-NEXT: and a4, a1, s5
; RV64I-NEXT: slli a4, a4, 24
-; RV64I-NEXT: and a5, a0, t0
-; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: and a5, a1, t6
+; RV64I-NEXT: slli a1, a1, 56
; RV64I-NEXT: slli a5, a5, 40
; RV64I-NEXT: or a3, a4, a3
-; RV64I-NEXT: or a0, a0, a5
-; RV64I-NEXT: or a0, a0, a3
-; RV64I-NEXT: srli a3, a1, 4
-; RV64I-NEXT: and a3, a3, a6
-; RV64I-NEXT: or a0, a0, a2
-; RV64I-NEXT: and a1, a1, a6
-; RV64I-NEXT: srli a2, a0, 4
-; RV64I-NEXT: and a2, a2, a6
-; RV64I-NEXT: and a0, a0, a6
-; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: or a1, a1, a5
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: srli a3, a0, 4
+; RV64I-NEXT: and a3, a3, t0
+; RV64I-NEXT: or a1, a1, a2
+; RV64I-NEXT: and a0, a0, t0
+; RV64I-NEXT: srli a2, a1, 4
+; RV64I-NEXT: and a2, a2, t0
+; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: slli a0, a0, 4
-; RV64I-NEXT: or a1, a3, a1
-; RV64I-NEXT: or a0, a2, a0
-; RV64I-NEXT: srli a2, a1, 2
-; RV64I-NEXT: and a1, a1, t1
-; RV64I-NEXT: and a2, a2, t1
-; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a2, a0, 2
-; RV64I-NEXT: and a2, a2, t1
; RV64I-NEXT: and a0, a0, t1
-; RV64I-NEXT: srli a3, a1, 1
+; RV64I-NEXT: and a2, a2, t1
; RV64I-NEXT: slli a0, a0, 2
-; RV64I-NEXT: and a3, a3, t2
; RV64I-NEXT: or a0, a2, a0
-; RV64I-NEXT: and a1, a1, t2
-; RV64I-NEXT: srli a2, a0, 1
-; RV64I-NEXT: and a2, a2, t2
+; RV64I-NEXT: srli a2, a1, 2
+; RV64I-NEXT: and a2, a2, t1
+; RV64I-NEXT: and a1, a1, t1
+; RV64I-NEXT: srli a3, a0, 1
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: and a3, a3, t2
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: and a0, a0, t2
-; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: srli a2, a1, 1
+; RV64I-NEXT: and a2, a2, t2
+; RV64I-NEXT: and a1, a1, t2
; RV64I-NEXT: slli a0, a0, 1
-; RV64I-NEXT: or a1, a3, a1
-; RV64I-NEXT: or a0, a2, a0
+; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: or a0, a3, a0
+; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: ld a2, 184(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sd a1, 0(a2)
-; RV64I-NEXT: sd a0, 8(a2)
+; RV64I-NEXT: sd a0, 0(a2)
+; RV64I-NEXT: sd a1, 8(a2)
; RV64I-NEXT: ld a2, 192(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sd a1, 0(a2)
-; RV64I-NEXT: sd a0, 8(a2)
+; RV64I-NEXT: sd a0, 0(a2)
+; RV64I-NEXT: sd a1, 8(a2)
; RV64I-NEXT: ld ra, 296(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 288(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 280(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/idiv_large.ll b/llvm/test/CodeGen/RISCV/idiv_large.ll
index 27aefeaff7a91..55656ea7adbeb 100644
--- a/llvm/test/CodeGen/RISCV/idiv_large.ll
+++ b/llvm/test/CodeGen/RISCV/idiv_large.ll
@@ -23,14 +23,14 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-LABEL: udiv_i65:
; RV32: # %bb.0: # %_udiv-special-cases
; RV32-NEXT: lw a3, 4(a2)
-; RV32-NEXT: lw t1, 8(a2)
+; RV32-NEXT: lw t0, 8(a2)
; RV32-NEXT: lw a2, 0(a2)
; RV32-NEXT: lui a4, 349525
; RV32-NEXT: lui a5, 209715
; RV32-NEXT: lui a7, 61681
-; RV32-NEXT: addi t0, a4, 1365
+; RV32-NEXT: addi t1, a4, 1365
; RV32-NEXT: srli a4, a3, 1
-; RV32-NEXT: slli t2, t1, 31
+; RV32-NEXT: slli t2, t0, 31
; RV32-NEXT: addi a6, a5, 819
; RV32-NEXT: or t3, t2, a4
; RV32-NEXT: slli a4, a3, 31
@@ -51,7 +51,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: not a4, a4
; RV32-NEXT: srli a5, a4, 1
-; RV32-NEXT: and a5, a5, t0
+; RV32-NEXT: and a5, a5, t1
; RV32-NEXT: sub a4, a4, a5
; RV32-NEXT: srli a5, a4, 2
; RV32-NEXT: and a4, a4, a6
@@ -80,7 +80,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: not a4, a4
; RV32-NEXT: srli a5, a4, 1
-; RV32-NEXT: and a5, a5, t0
+; RV32-NEXT: and a5, a5, t1
; RV32-NEXT: sub a4, a4, a5
; RV32-NEXT: srli a5, a4, 2
; RV32-NEXT: and a4, a4, a6
@@ -122,7 +122,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: not a4, a4
; RV32-NEXT: srli a5, a4, 1
-; RV32-NEXT: and a5, a5, t0
+; RV32-NEXT: and a5, a5, t1
; RV32-NEXT: sub a4, a4, a5
; RV32-NEXT: srli a5, a4, 2
; RV32-NEXT: and a4, a4, a6
@@ -141,82 +141,82 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: lw a4, 4(a1)
; RV32-NEXT: lw a1, 8(a1)
; RV32-NEXT: or t3, t5, t3
-; RV32-NEXT: addi s2, s0, 64
+; RV32-NEXT: addi s1, s0, 64
; RV32-NEXT: bnez t3, .LBB1_8
; RV32-NEXT: # %bb.7: # %_udiv-special-cases
-; RV32-NEXT: mv t2, s2
+; RV32-NEXT: mv t2, s1
; RV32-NEXT: .LBB1_8: # %_udiv-special-cases
; RV32-NEXT: srli t5, a4, 1
; RV32-NEXT: slli t6, a1, 31
; RV32-NEXT: or t5, t6, t5
; RV32-NEXT: slli t6, a4, 31
-; RV32-NEXT: srli s1, a5, 1
+; RV32-NEXT: srli s2, a5, 1
; RV32-NEXT: snez s3, t3
-; RV32-NEXT: or t6, s1, t6
+; RV32-NEXT: or t6, s2, t6
; RV32-NEXT: bnez t5, .LBB1_10
; RV32-NEXT: # %bb.9: # %_udiv-special-cases
; RV32-NEXT: srli t3, t6, 1
; RV32-NEXT: or t3, t6, t3
-; RV32-NEXT: srli s1, t3, 2
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 8
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 16
-; RV32-NEXT: or t3, t3, s1
+; RV32-NEXT: srli s2, t3, 2
+; RV32-NEXT: or t3, t3, s2
+; RV32-NEXT: srli s2, t3, 4
+; RV32-NEXT: or t3, t3, s2
+; RV32-NEXT: srli s2, t3, 8
+; RV32-NEXT: or t3, t3, s2
+; RV32-NEXT: srli s2, t3, 16
+; RV32-NEXT: or t3, t3, s2
; RV32-NEXT: not t3, t3
-; RV32-NEXT: srli s1, t3, 1
-; RV32-NEXT: and s1, s1, t0
-; RV32-NEXT: sub t3, t3, s1
-; RV32-NEXT: srli s1, t3, 2
+; RV32-NEXT: srli s2, t3, 1
+; RV32-NEXT: and s2, s2, t1
+; RV32-NEXT: sub t3, t3, s2
+; RV32-NEXT: srli s2, t3, 2
; RV32-NEXT: and t3, t3, a6
-; RV32-NEXT: and s1, s1, a6
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: add t3, t3, s1
+; RV32-NEXT: and s2, s2, a6
+; RV32-NEXT: add t3, t3, s2
+; RV32-NEXT: srli s2, t3, 4
+; RV32-NEXT: add t3, t3, s2
; RV32-NEXT: and t3, t3, a7
-; RV32-NEXT: slli s1, t3, 8
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: slli s1, t3, 16
-; RV32-NEXT: add t3, t3, s1
+; RV32-NEXT: slli s2, t3, 8
+; RV32-NEXT: add t3, t3, s2
+; RV32-NEXT: slli s2, t3, 16
+; RV32-NEXT: add t3, t3, s2
; RV32-NEXT: srli t3, t3, 24
-; RV32-NEXT: addi s1, t3, 32
+; RV32-NEXT: addi s2, t3, 32
; RV32-NEXT: j .LBB1_11
; RV32-NEXT: .LBB1_10:
; RV32-NEXT: srli t3, t5, 1
; RV32-NEXT: or t3, t5, t3
-; RV32-NEXT: srli s1, t3, 2
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 8
-; RV32-NEXT: or t3, t3, s1
-; RV32-NEXT: srli s1, t3, 16
-; RV32-NEXT: or t3, t3, s1
+; RV32-NEXT: srli s2, t3, 2
+; RV32-NEXT: or t3, t3, s2
+; RV32-NEXT: srli s2, t3, 4
+; RV32-NEXT: or t3, t3, s2
+; RV32-NEXT: srli s2, t3, 8
+; RV32-NEXT: or t3, t3, s2
+; RV32-NEXT: srli s2, t3, 16
+; RV32-NEXT: or t3, t3, s2
; RV32-NEXT: not t3, t3
-; RV32-NEXT: srli s1, t3, 1
-; RV32-NEXT: and s1, s1, t0
-; RV32-NEXT: sub t3, t3, s1
-; RV32-NEXT: srli s1, t3, 2
+; RV32-NEXT: srli s2, t3, 1
+; RV32-NEXT: and s2, s2, t1
+; RV32-NEXT: sub t3, t3, s2
+; RV32-NEXT: srli s2, t3, 2
; RV32-NEXT: and t3, t3, a6
-; RV32-NEXT: and s1, s1, a6
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: srli s1, t3, 4
-; RV32-NEXT: add t3, t3, s1
+; RV32-NEXT: and s2, s2, a6
+; RV32-NEXT: add t3, t3, s2
+; RV32-NEXT: srli s2, t3, 4
+; RV32-NEXT: add t3, t3, s2
; RV32-NEXT: and t3, t3, a7
-; RV32-NEXT: slli s1, t3, 8
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: slli s1, t3, 16
-; RV32-NEXT: add t3, t3, s1
-; RV32-NEXT: srli s1, t3, 24
+; RV32-NEXT: slli s2, t3, 8
+; RV32-NEXT: add t3, t3, s2
+; RV32-NEXT: slli s2, t3, 16
+; RV32-NEXT: add t3, t3, s2
+; RV32-NEXT: srli s2, t3, 24
; RV32-NEXT: .LBB1_11: # %_udiv-special-cases
; RV32-NEXT: andi t3, a1, 1
-; RV32-NEXT: andi a1, t1, 1
-; RV32-NEXT: or t1, a2, a3
-; RV32-NEXT: sltu s0, s2, s0
+; RV32-NEXT: andi a1, t0, 1
+; RV32-NEXT: or t0, a2, a3
+; RV32-NEXT: sltu s0, s1, s0
; RV32-NEXT: slli s4, a5, 31
-; RV32-NEXT: or s2, a5, a4
+; RV32-NEXT: or s1, a5, a4
; RV32-NEXT: addi s3, s3, -1
; RV32-NEXT: beqz s4, .LBB1_13
; RV32-NEXT: # %bb.12:
@@ -232,14 +232,14 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: or t4, t4, s4
; RV32-NEXT: not t4, t4
; RV32-NEXT: srli s4, t4, 1
-; RV32-NEXT: and t0, s4, t0
-; RV32-NEXT: sub t0, t4, t0
-; RV32-NEXT: srli t4, t0, 2
-; RV32-NEXT: and t0, t0, a6
+; RV32-NEXT: and t1, s4, t1
+; RV32-NEXT: sub t1, t4, t1
+; RV32-NEXT: srli t4, t1, 2
+; RV32-NEXT: and t1, t1, a6
; RV32-NEXT: and a6, t4, a6
-; RV32-NEXT: add a6, t0, a6
-; RV32-NEXT: srli t0, a6, 4
-; RV32-NEXT: add a6, a6, t0
+; RV32-NEXT: add a6, t1, a6
+; RV32-NEXT: srli t1, a6, 4
+; RV32-NEXT: add a6, a6, t1
; RV32-NEXT: and a6, a6, a7
; RV32-NEXT: slli a7, a6, 8
; RV32-NEXT: add a6, a6, a7
@@ -247,40 +247,39 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: add a6, a6, a7
; RV32-NEXT: srli t4, a6, 24
; RV32-NEXT: .LBB1_13: # %_udiv-special-cases
-; RV32-NEXT: or t0, t1, a1
-; RV32-NEXT: or a7, s2, t3
+; RV32-NEXT: or t1, t0, a1
+; RV32-NEXT: or a7, s1, t3
; RV32-NEXT: or t5, t6, t5
; RV32-NEXT: and a6, s3, s0
; RV32-NEXT: addi t6, t4, 64
; RV32-NEXT: bnez t5, .LBB1_15
; RV32-NEXT: # %bb.14: # %_udiv-special-cases
-; RV32-NEXT: mv s1, t6
+; RV32-NEXT: mv s2, t6
; RV32-NEXT: .LBB1_15: # %_udiv-special-cases
-; RV32-NEXT: seqz t0, t0
+; RV32-NEXT: seqz t1, t1
; RV32-NEXT: snez t5, t5
; RV32-NEXT: sltu t4, t6, t4
; RV32-NEXT: addi t5, t5, -1
-; RV32-NEXT: and t6, t5, t4
-; RV32-NEXT: sltu s0, t2, s1
+; RV32-NEXT: and s0, t5, t4
+; RV32-NEXT: sltu t6, t2, s2
; RV32-NEXT: seqz a7, a7
-; RV32-NEXT: mv t4, s0
-; RV32-NEXT: beq a6, t6, .LBB1_17
+; RV32-NEXT: mv t4, t6
+; RV32-NEXT: beq a6, s0, .LBB1_17
; RV32-NEXT: # %bb.16: # %_udiv-special-cases
-; RV32-NEXT: sltu t4, a6, t6
+; RV32-NEXT: sltu t4, a6, s0
; RV32-NEXT: .LBB1_17: # %_udiv-special-cases
-; RV32-NEXT: or t5, t0, a7
-; RV32-NEXT: andi t4, t4, 1
-; RV32-NEXT: sub a6, a6, t6
-; RV32-NEXT: sub a7, a6, s0
-; RV32-NEXT: sub t0, t2, s1
+; RV32-NEXT: or t5, t1, a7
+; RV32-NEXT: sub a6, a6, s0
+; RV32-NEXT: sub t1, t2, s2
+; RV32-NEXT: sub a7, a6, t6
; RV32-NEXT: beqz t4, .LBB1_19
; RV32-NEXT: # %bb.18: # %_udiv-special-cases
; RV32-NEXT: mv a6, t4
; RV32-NEXT: j .LBB1_20
; RV32-NEXT: .LBB1_19:
-; RV32-NEXT: sltiu a6, t0, 65
-; RV32-NEXT: xori a6, a6, 1
+; RV32-NEXT: sltiu a6, t1, 65
; RV32-NEXT: snez t2, a7
+; RV32-NEXT: xori a6, a6, 1
; RV32-NEXT: or a6, a6, t2
; RV32-NEXT: .LBB1_20: # %_udiv-special-cases
; RV32-NEXT: or t6, t5, a6
@@ -290,15 +289,15 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: and t5, t5, a5
; RV32-NEXT: bnez t6, .LBB1_29
; RV32-NEXT: # %bb.21: # %_udiv-special-cases
-; RV32-NEXT: xori t6, t0, 64
+; RV32-NEXT: xori t6, t1, 64
; RV32-NEXT: or s0, t4, a7
; RV32-NEXT: or t6, t6, s0
; RV32-NEXT: beqz t6, .LBB1_29
; RV32-NEXT: # %bb.22: # %udiv-bb1
-; RV32-NEXT: addi a6, t0, 1
+; RV32-NEXT: addi a6, t1, 1
; RV32-NEXT: li t2, 64
; RV32-NEXT: seqz t5, a6
-; RV32-NEXT: sub t2, t2, t0
+; RV32-NEXT: sub t2, t2, t1
; RV32-NEXT: add a7, a7, t5
; RV32-NEXT: sw zero, 32(sp)
; RV32-NEXT: sw zero, 36(sp)
@@ -321,10 +320,10 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: xori s1, t2, 31
; RV32-NEXT: srli t2, t6, 1
; RV32-NEXT: srl t2, t2, s1
-; RV32-NEXT: neg s3, t0
-; RV32-NEXT: sll t0, s2, s3
+; RV32-NEXT: neg s3, t1
+; RV32-NEXT: sll t1, s2, s3
; RV32-NEXT: or t5, t5, t4
-; RV32-NEXT: or t0, t0, t2
+; RV32-NEXT: or t1, t1, t2
; RV32-NEXT: sll t2, t6, s3
; RV32-NEXT: beqz t5, .LBB1_28
; RV32-NEXT: # %bb.23: # %udiv-preheader
@@ -362,7 +361,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: andi s1, a5, 1
; RV32-NEXT: srl a5, s2, a6
; RV32-NEXT: or s2, a5, a4
-; RV32-NEXT: snez a4, t1
+; RV32-NEXT: snez a4, t0
; RV32-NEXT: seqz a5, a2
; RV32-NEXT: add a4, a1, a4
; RV32-NEXT: sub a1, a3, a5
@@ -372,7 +371,7 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: j .LBB1_26
; RV32-NEXT: .LBB1_24: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB1_26 Depth=1
-; RV32-NEXT: sltu s1, a1, t1
+; RV32-NEXT: sltu s1, a1, t0
; RV32-NEXT: .LBB1_25: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB1_26 Depth=1
; RV32-NEXT: srli t3, t3, 31
@@ -382,51 +381,51 @@ define i65 @udiv_i65(i65 %x, i65 %y) nounwind {
; RV32-NEXT: srai t3, t3, 31
; RV32-NEXT: and s3, t3, a3
; RV32-NEXT: srli s1, t2, 31
-; RV32-NEXT: slli s4, t0, 1
+; RV32-NEXT: slli s4, t1, 1
; RV32-NEXT: slli t2, t2, 1
; RV32-NEXT: or s1, s4, s1
-; RV32-NEXT: srli s4, t0, 31
+; RV32-NEXT: srli s4, t1, 31
; RV32-NEXT: or t2, t5, t2
-; RV32-NEXT: or t0, t6, s1
+; RV32-NEXT: or t1, t6, s1
; RV32-NEXT: or s1, s0, s4
; RV32-NEXT: andi s1, s1, 1
; RV32-NEXT: and t6, t3, a2
; RV32-NEXT: sltu s0, s2, t6
-; RV32-NEXT: sub t1, t1, s3
+; RV32-NEXT: sub t0, t0, s3
; RV32-NEXT: andi t5, t3, 1
-; RV32-NEXT: sub t3, t1, s0
+; RV32-NEXT: sub t3, t0, s0
; RV32-NEXT: sub s2, s2, t6
-; RV32-NEXT: or t1, a6, a7
+; RV32-NEXT: or t0, a6, a7
; RV32-NEXT: seqz t6, a6
-; RV32-NEXT: snez t1, t1
+; RV32-NEXT: snez t0, t0
; RV32-NEXT: sub a7, a7, t6
-; RV32-NEXT: add t1, t4, t1
-; RV32-NEXT: not t1, t1
+; RV32-NEXT: add t0, t4, t0
+; RV32-NEXT: not t0, t0
; RV32-NEXT: addi a6, a6, -1
-; RV32-NEXT: andi t4, t1, 1
-; RV32-NEXT: or t1, a6, a7
-; RV32-NEXT: or t1, t1, t4
+; RV32-NEXT: andi t4, t0, 1
+; RV32-NEXT: or t0, a6, a7
+; RV32-NEXT: or t0, t0, t4
; RV32-NEXT: li t6, 0
; RV32-NEXT: li s0, 0
-; RV32-NEXT: beqz t1, .LBB1_28
+; RV32-NEXT: beqz t0, .LBB1_28
; RV32-NEXT: .LBB1_26: # %udiv-do-while
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32-NEXT: srli t1, s2, 31
+; RV32-NEXT: srli t0, s2, 31
; RV32-NEXT: slli s3, t3, 1
-; RV32-NEXT: or t1, s3, t1
+; RV32-NEXT: or t0, s3, t0
; RV32-NEXT: slli s2, s2, 1
; RV32-NEXT: andi s1, s1, 1
; RV32-NEXT: or s2, s2, s1
-; RV32-NEXT: bne a1, t1, .LBB1_24
+; RV32-NEXT: bne a1, t0, .LBB1_24
; RV32-NEXT: # %bb.27: # in Loop: Header=BB1_26 Depth=1
; RV32-NEXT: sltu s1, a5, s2
; RV32-NEXT: j .LBB1_25
; RV32-NEXT: .LBB1_28: # %udiv-loop-exit
; RV32-NEXT: srli a1, t2, 31
-; RV32-NEXT: slli a2, t0, 1
+; RV32-NEXT: slli a2, t1, 1
; RV32-NEXT: slli a3, t2, 1
; RV32-NEXT: or t2, a2, a1
-; RV32-NEXT: srli a6, t0, 31
+; RV32-NEXT: srli a6, t1, 31
; RV32-NEXT: or t5, t5, a3
; RV32-NEXT: .LBB1_29: # %udiv-end
; RV32-NEXT: sw t5, 0(a0)
@@ -708,7 +707,7 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: slli t1, a0, 16
; RV32-NEXT: add a0, a0, t1
; RV32-NEXT: srli a0, a0, 24
-; RV32-NEXT: addi t1, a0, 32
+; RV32-NEXT: addi a0, a0, 32
; RV32-NEXT: j .LBB2_14
; RV32-NEXT: .LBB2_13:
; RV32-NEXT: srli a0, a7, 1
@@ -736,55 +735,52 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: add a0, a0, t1
; RV32-NEXT: slli t1, a0, 16
; RV32-NEXT: add a0, a0, t1
-; RV32-NEXT: srli t1, a0, 24
+; RV32-NEXT: srli a0, a0, 24
; RV32-NEXT: .LBB2_14: # %_udiv-special-cases
; RV32-NEXT: or s0, s1, s0
-; RV32-NEXT: or t2, s3, s2
-; RV32-NEXT: and t3, s4, t5
-; RV32-NEXT: and s1, s7, s6
+; RV32-NEXT: or t3, s3, s2
+; RV32-NEXT: and t1, s4, t5
+; RV32-NEXT: and t2, s7, s6
; RV32-NEXT: bnez s5, .LBB2_16
; RV32-NEXT: # %bb.15: # %_udiv-special-cases
-; RV32-NEXT: mv t1, t6
+; RV32-NEXT: mv a0, t6
; RV32-NEXT: .LBB2_16: # %_udiv-special-cases
-; RV32-NEXT: seqz a0, s0
-; RV32-NEXT: seqz t5, t2
-; RV32-NEXT: sltu t2, t4, t1
-; RV32-NEXT: sub s0, t3, s1
-; RV32-NEXT: mv t6, t2
-; RV32-NEXT: beq t3, s1, .LBB2_18
+; RV32-NEXT: seqz t6, s0
+; RV32-NEXT: sltu t5, t4, a0
+; RV32-NEXT: seqz t3, t3
+; RV32-NEXT: mv s0, t5
+; RV32-NEXT: beq t1, t2, .LBB2_18
; RV32-NEXT: # %bb.17: # %_udiv-special-cases
-; RV32-NEXT: sltu t6, t3, s1
+; RV32-NEXT: sltu s0, t1, t2
; RV32-NEXT: .LBB2_18: # %_udiv-special-cases
-; RV32-NEXT: seqz t3, t6
-; RV32-NEXT: neg t6, t6
-; RV32-NEXT: addi t3, t3, -1
-; RV32-NEXT: sub t2, s0, t2
-; RV32-NEXT: or s0, t6, t3
-; RV32-NEXT: or a0, a0, t5
-; RV32-NEXT: sub t5, t4, t1
-; RV32-NEXT: beqz s0, .LBB2_20
+; RV32-NEXT: or t6, t6, t3
+; RV32-NEXT: neg t3, s0
+; RV32-NEXT: sub t1, t1, t2
+; RV32-NEXT: sub t2, t1, t5
+; RV32-NEXT: sub t5, t4, a0
+; RV32-NEXT: beqz t3, .LBB2_20
; RV32-NEXT: # %bb.19: # %_udiv-special-cases
-; RV32-NEXT: snez t1, s0
+; RV32-NEXT: snez a0, t3
; RV32-NEXT: j .LBB2_21
; RV32-NEXT: .LBB2_20:
-; RV32-NEXT: sltiu t1, t5, 128
-; RV32-NEXT: snez t4, t2
-; RV32-NEXT: xori t1, t1, 1
-; RV32-NEXT: or t1, t1, t4
+; RV32-NEXT: sltiu a0, t5, 128
+; RV32-NEXT: snez t1, t2
+; RV32-NEXT: xori a0, a0, 1
+; RV32-NEXT: or a0, a0, t1
; RV32-NEXT: .LBB2_21: # %_udiv-special-cases
-; RV32-NEXT: or s1, a0, t1
-; RV32-NEXT: addi a0, s1, -1
-; RV32-NEXT: and s0, a0, a7
+; RV32-NEXT: or s0, t6, a0
+; RV32-NEXT: addi a0, s0, -1
+; RV32-NEXT: and t6, a0, a7
; RV32-NEXT: and t4, a0, a1
; RV32-NEXT: and t1, a0, a6
; RV32-NEXT: and a0, a0, t0
-; RV32-NEXT: bnez s1, .LBB2_32
+; RV32-NEXT: bnez s0, .LBB2_32
; RV32-NEXT: # %bb.22: # %_udiv-special-cases
-; RV32-NEXT: xori s1, t5, 127
-; RV32-NEXT: or s1, s1, t6
-; RV32-NEXT: or s2, t2, t3
-; RV32-NEXT: or s1, s1, s2
-; RV32-NEXT: beqz s1, .LBB2_32
+; RV32-NEXT: xori s0, t5, 127
+; RV32-NEXT: or s0, s0, t3
+; RV32-NEXT: or s1, t2, t3
+; RV32-NEXT: or s0, s0, s1
+; RV32-NEXT: beqz s0, .LBB2_32
; RV32-NEXT: # %bb.23: # %udiv-bb1
; RV32-NEXT: sw a3, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: addi t1, t5, 1
@@ -798,9 +794,9 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: li a3, 127
; RV32-NEXT: seqz t4, a0
; RV32-NEXT: sub a0, a3, t5
-; RV32-NEXT: add t4, t6, t4
+; RV32-NEXT: add t4, t3, t4
; RV32-NEXT: srli a3, a0, 3
-; RV32-NEXT: sltu a4, t4, t6
+; RV32-NEXT: sltu a4, t4, t3
; RV32-NEXT: andi a3, a3, 12
; RV32-NEXT: add t3, t3, a4
; RV32-NEXT: addi a4, sp, 72
@@ -981,14 +977,14 @@ define i128 @udiv_i128(i128 %x, i128 %y) nounwind {
; RV32-NEXT: srli s0, a3, 31
; RV32-NEXT: slli t6, t6, 1
; RV32-NEXT: slli t5, t5, 1
-; RV32-NEXT: or s0, t6, s0
+; RV32-NEXT: or t6, t6, s0
; RV32-NEXT: or a0, a0, t5
; RV32-NEXT: lw a3, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: .LBB2_32: # %udiv-end
; RV32-NEXT: sw a0, 0(a3)
; RV32-NEXT: sw t1, 4(a3)
; RV32-NEXT: sw t4, 8(a3)
-; RV32-NEXT: sw s0, 12(a3)
+; RV32-NEXT: sw t6, 12(a3)
; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
@@ -1039,7 +1035,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: lw a4, 8(a2)
; RV32-NEXT: lui a0, 349525
; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: lw t2, 16(a2)
+; RV32-NEXT: lw t1, 16(a2)
; RV32-NEXT: lw a6, 0(a2)
; RV32-NEXT: lw a2, 12(a2)
; RV32-NEXT: sw a2, 20(sp) # 4-byte Folded Spill
@@ -1116,7 +1112,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: .LBB3_3: # %_udiv-special-cases
; RV32-NEXT: lw a5, 20(sp) # 4-byte Folded Reload
; RV32-NEXT: srli a2, a5, 1
-; RV32-NEXT: slli a4, t2, 31
+; RV32-NEXT: slli a4, t1, 31
; RV32-NEXT: slli a5, a5, 31
; RV32-NEXT: lw a3, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: slli a3, a3, 31
@@ -1125,51 +1121,51 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: li s1, 64
; RV32-NEXT: bnez a3, .LBB3_5
; RV32-NEXT: # %bb.4: # %_udiv-special-cases
-; RV32-NEXT: li t1, 64
+; RV32-NEXT: li t2, 64
; RV32-NEXT: j .LBB3_6
; RV32-NEXT: .LBB3_5:
-; RV32-NEXT: srli t1, a3, 1
-; RV32-NEXT: or t1, a3, t1
-; RV32-NEXT: srli t6, t1, 2
-; RV32-NEXT: or t1, t1, t6
-; RV32-NEXT: srli t6, t1, 4
-; RV32-NEXT: or t1, t1, t6
-; RV32-NEXT: srli t6, t1, 8
-; RV32-NEXT: or t1, t1, t6
-; RV32-NEXT: srli t6, t1, 16
-; RV32-NEXT: or t1, t1, t6
-; RV32-NEXT: not t1, t1
-; RV32-NEXT: srli t6, t1, 1
+; RV32-NEXT: srli t2, a3, 1
+; RV32-NEXT: or t2, a3, t2
+; RV32-NEXT: srli t6, t2, 2
+; RV32-NEXT: or t2, t2, t6
+; RV32-NEXT: srli t6, t2, 4
+; RV32-NEXT: or t2, t2, t6
+; RV32-NEXT: srli t6, t2, 8
+; RV32-NEXT: or t2, t2, t6
+; RV32-NEXT: srli t6, t2, 16
+; RV32-NEXT: or t2, t2, t6
+; RV32-NEXT: not t2, t2
+; RV32-NEXT: srli t6, t2, 1
; RV32-NEXT: and t6, t6, t5
-; RV32-NEXT: sub t1, t1, t6
-; RV32-NEXT: srli t6, t1, 2
-; RV32-NEXT: and t1, t1, t4
+; RV32-NEXT: sub t2, t2, t6
+; RV32-NEXT: srli t6, t2, 2
+; RV32-NEXT: and t2, t2, t4
; RV32-NEXT: and t6, t6, t4
-; RV32-NEXT: add t1, t1, t6
-; RV32-NEXT: srli t6, t1, 4
-; RV32-NEXT: add t1, t1, t6
-; RV32-NEXT: and t1, t1, t3
-; RV32-NEXT: slli t6, t1, 8
-; RV32-NEXT: add t1, t1, t6
-; RV32-NEXT: slli t6, t1, 16
-; RV32-NEXT: add t1, t1, t6
-; RV32-NEXT: srli t1, t1, 24
+; RV32-NEXT: add t2, t2, t6
+; RV32-NEXT: srli t6, t2, 4
+; RV32-NEXT: add t2, t2, t6
+; RV32-NEXT: and t2, t2, t3
+; RV32-NEXT: slli t6, t2, 8
+; RV32-NEXT: add t2, t2, t6
+; RV32-NEXT: slli t6, t2, 16
+; RV32-NEXT: add t2, t2, t6
+; RV32-NEXT: srli t2, t2, 24
; RV32-NEXT: .LBB3_6: # %_udiv-special-cases
; RV32-NEXT: or a2, a4, a2
; RV32-NEXT: or a4, a7, a5
; RV32-NEXT: bnez a3, .LBB3_8
; RV32-NEXT: # %bb.7: # %_udiv-special-cases
-; RV32-NEXT: li t1, 128
+; RV32-NEXT: li t2, 128
; RV32-NEXT: .LBB3_8: # %_udiv-special-cases
; RV32-NEXT: or a0, a0, a2
; RV32-NEXT: or a3, a6, a4
; RV32-NEXT: or a7, a4, a2
; RV32-NEXT: or a3, a3, a0
; RV32-NEXT: addi a6, t0, 64
-; RV32-NEXT: addi a0, t1, 128
+; RV32-NEXT: addi a0, t2, 128
; RV32-NEXT: bnez a3, .LBB3_11
; RV32-NEXT: # %bb.9: # %_udiv-special-cases
-; RV32-NEXT: sltu t6, a0, t1
+; RV32-NEXT: sltu t6, a0, t2
; RV32-NEXT: beqz a2, .LBB3_12
; RV32-NEXT: .LBB3_10:
; RV32-NEXT: srli a4, a2, 1
@@ -1245,7 +1241,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: # %bb.15: # %_udiv-special-cases
; RV32-NEXT: mv s0, a0
; RV32-NEXT: .LBB3_16: # %_udiv-special-cases
-; RV32-NEXT: lw t1, 12(a1)
+; RV32-NEXT: lw t2, 12(a1)
; RV32-NEXT: lw a1, 16(a1)
; RV32-NEXT: slli a0, a6, 31
; RV32-NEXT: srli a2, t0, 1
@@ -1311,10 +1307,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: add a2, a2, a3
; RV32-NEXT: srli s4, a2, 24
; RV32-NEXT: .LBB3_19: # %_udiv-special-cases
-; RV32-NEXT: srli a2, t1, 1
+; RV32-NEXT: srli a2, t2, 1
; RV32-NEXT: slli a3, a1, 31
; RV32-NEXT: slli a4, a7, 31
-; RV32-NEXT: slli a5, t1, 31
+; RV32-NEXT: slli a5, t2, 31
; RV32-NEXT: srli s3, a6, 1
; RV32-NEXT: beqz a4, .LBB3_21
; RV32-NEXT: # %bb.20:
@@ -1387,7 +1383,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: add a2, a2, a4
; RV32-NEXT: slli a4, a2, 16
; RV32-NEXT: add a2, a2, a4
-; RV32-NEXT: srli a4, a2, 24
+; RV32-NEXT: srli a2, a2, 24
; RV32-NEXT: j .LBB3_28
; RV32-NEXT: .LBB3_26:
; RV32-NEXT: snez a0, s5
@@ -1422,46 +1418,45 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: slli a4, a2, 16
; RV32-NEXT: add a2, a2, a4
; RV32-NEXT: srli a2, a2, 24
-; RV32-NEXT: addi a4, a2, 32
+; RV32-NEXT: addi a2, a2, 32
; RV32-NEXT: .LBB3_28: # %_udiv-special-cases
; RV32-NEXT: andi s11, a1, 1
-; RV32-NEXT: andi s4, t2, 1
+; RV32-NEXT: andi s4, t1, 1
; RV32-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: or s1, s1, a1
; RV32-NEXT: or a1, a7, a6
; RV32-NEXT: bnez s5, .LBB3_30
; RV32-NEXT: # %bb.29: # %_udiv-special-cases
-; RV32-NEXT: mv a4, a3
+; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB3_30: # %_udiv-special-cases
-; RV32-NEXT: lw a2, 16(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw a3, 20(sp) # 4-byte Folded Reload
-; RV32-NEXT: or s6, a2, a3
-; RV32-NEXT: or a5, s1, s4
-; RV32-NEXT: or a2, t0, t1
-; RV32-NEXT: or a3, a1, s11
+; RV32-NEXT: lw a3, 16(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw a4, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: or s6, a3, a4
+; RV32-NEXT: or a3, s1, s4
+; RV32-NEXT: or a4, t0, t2
+; RV32-NEXT: or a5, a1, s11
; RV32-NEXT: bnez s3, .LBB3_32
; RV32-NEXT: # %bb.31: # %_udiv-special-cases
-; RV32-NEXT: mv a4, s2
+; RV32-NEXT: mv a2, s2
; RV32-NEXT: .LBB3_32: # %_udiv-special-cases
-; RV32-NEXT: or a1, a5, s6
-; RV32-NEXT: sltu a5, s0, a4
-; RV32-NEXT: or a2, a3, a2
-; RV32-NEXT: mv t4, a5
+; RV32-NEXT: or a1, a3, s6
+; RV32-NEXT: or a4, a5, a4
+; RV32-NEXT: sltu a3, s0, a2
+; RV32-NEXT: sub a5, t6, a0
+; RV32-NEXT: mv t5, a3
; RV32-NEXT: beq t6, a0, .LBB3_34
; RV32-NEXT: # %bb.33: # %_udiv-special-cases
-; RV32-NEXT: sltu t4, t6, a0
+; RV32-NEXT: sltu t5, t6, a0
; RV32-NEXT: .LBB3_34: # %_udiv-special-cases
-; RV32-NEXT: seqz a1, a1
-; RV32-NEXT: seqz a2, a2
-; RV32-NEXT: sub a0, t6, a0
-; RV32-NEXT: snez t2, t4
-; RV32-NEXT: neg a3, t4
-; RV32-NEXT: neg t3, t2
-; RV32-NEXT: sub t2, a0, a5
+; RV32-NEXT: sub t1, a5, a3
+; RV32-NEXT: snez a0, t5
+; RV32-NEXT: neg a3, t5
+; RV32-NEXT: neg t3, a0
+; RV32-NEXT: sub a0, s0, a2
; RV32-NEXT: or a5, a3, t3
-; RV32-NEXT: andi t5, t4, 1
-; RV32-NEXT: sub a0, s0, a4
+; RV32-NEXT: seqz a1, a1
+; RV32-NEXT: seqz a2, a4
; RV32-NEXT: beqz a5, .LBB3_36
; RV32-NEXT: # %bb.35: # %_udiv-special-cases
; RV32-NEXT: snez a4, a5
@@ -1470,7 +1465,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: j .LBB3_38
; RV32-NEXT: .LBB3_36:
; RV32-NEXT: sltiu a4, a0, 129
-; RV32-NEXT: snez a5, t2
+; RV32-NEXT: snez a5, t1
; RV32-NEXT: xori a4, a4, 1
; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: or a1, a1, a2
@@ -1481,7 +1476,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: or t6, a1, a4
; RV32-NEXT: addi t4, t6, -1
; RV32-NEXT: and a5, s11, t4
-; RV32-NEXT: and a4, t4, t1
+; RV32-NEXT: and a4, t4, t2
; RV32-NEXT: and a1, t4, a6
; RV32-NEXT: and a2, t4, t0
; RV32-NEXT: and t4, t4, a7
@@ -1489,7 +1484,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: # %bb.39: # %_udiv-special-cases
; RV32-NEXT: xori t6, a0, 128
; RV32-NEXT: or s0, t5, a3
-; RV32-NEXT: or s2, t2, t3
+; RV32-NEXT: or s2, t1, t3
; RV32-NEXT: or t6, t6, s0
; RV32-NEXT: or t6, t6, s2
; RV32-NEXT: beqz t6, .LBB3_55
@@ -1498,8 +1493,8 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw s7, 0(sp) # 4-byte Folded Spill
; RV32-NEXT: addi a1, a0, 1
; RV32-NEXT: seqz a2, a1
-; RV32-NEXT: add t2, t2, a2
-; RV32-NEXT: or a2, a1, t2
+; RV32-NEXT: add t1, t1, a2
+; RV32-NEXT: or a2, a1, t1
; RV32-NEXT: seqz t4, a2
; RV32-NEXT: sw zero, 120(sp)
; RV32-NEXT: sw zero, 124(sp)
@@ -1513,14 +1508,14 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw zero, 116(sp)
; RV32-NEXT: add t3, t3, a2
; RV32-NEXT: or a2, a1, t4
-; RV32-NEXT: or a3, t2, t3
+; RV32-NEXT: or a3, t1, t3
; RV32-NEXT: li a4, 128
; RV32-NEXT: or a5, a2, a3
; RV32-NEXT: sub a3, a4, a0
; RV32-NEXT: sw a7, 136(sp)
; RV32-NEXT: sw t0, 140(sp)
; RV32-NEXT: sw a6, 144(sp)
-; RV32-NEXT: sw t1, 148(sp)
+; RV32-NEXT: sw t2, 148(sp)
; RV32-NEXT: srli a2, a3, 3
; RV32-NEXT: andi a2, a2, 28
; RV32-NEXT: addi a4, sp, 136
@@ -1576,7 +1571,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sw a7, 40(sp)
; RV32-NEXT: sw t0, 44(sp)
; RV32-NEXT: sw a6, 48(sp)
-; RV32-NEXT: sw t1, 52(sp)
+; RV32-NEXT: sw t2, 52(sp)
; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: lw a4, 16(a2)
; RV32-NEXT: lw a5, 4(a2)
@@ -1588,10 +1583,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: andi t0, a1, 31
; RV32-NEXT: slli a4, a4, 1
; RV32-NEXT: xori t0, t0, 31
-; RV32-NEXT: srl t1, a7, a1
+; RV32-NEXT: srl t2, a7, a1
; RV32-NEXT: sll a4, a4, t0
; RV32-NEXT: or a3, a0, a3
-; RV32-NEXT: or s11, t1, a4
+; RV32-NEXT: or s11, t2, a4
; RV32-NEXT: srl a0, a6, a1
; RV32-NEXT: slli a7, a7, 1
; RV32-NEXT: sll a4, a7, t0
@@ -1628,7 +1623,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: sw a5, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: sw a6, 8(sp) # 4-byte Folded Spill
-; RV32-NEXT: mv t1, t5
+; RV32-NEXT: mv t2, t5
; RV32-NEXT: j .LBB3_43
; RV32-NEXT: .LBB3_42: # %udiv-do-while
; RV32-NEXT: # in Loop: Header=BB3_43 Depth=1
@@ -1639,12 +1634,12 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: xor t0, a0, a7
; RV32-NEXT: or t0, t0, ra
; RV32-NEXT: srli t0, s0, 31
-; RV32-NEXT: slli ra, t1, 1
-; RV32-NEXT: mv s7, t1
-; RV32-NEXT: srli t1, s2, 31
+; RV32-NEXT: slli ra, t2, 1
+; RV32-NEXT: mv s7, t2
+; RV32-NEXT: srli t2, s2, 31
; RV32-NEXT: slli s0, s0, 1
; RV32-NEXT: or t0, ra, t0
-; RV32-NEXT: or t1, s0, t1
+; RV32-NEXT: or t2, s0, t2
; RV32-NEXT: srli s0, t6, 31
; RV32-NEXT: slli s2, s2, 1
; RV32-NEXT: or s0, s2, s0
@@ -1652,8 +1647,8 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: srli ra, s7, 31
; RV32-NEXT: or t6, t5, t6
; RV32-NEXT: or s2, s8, s0
-; RV32-NEXT: or s0, s9, t1
-; RV32-NEXT: or t1, s10, t0
+; RV32-NEXT: or s0, s9, t2
+; RV32-NEXT: or t2, s10, t0
; RV32-NEXT: or t0, s3, ra
; RV32-NEXT: andi ra, t0, 1
; RV32-NEXT: andi s1, s1, 1
@@ -1667,22 +1662,22 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: sub a2, s5, a2
; RV32-NEXT: lw a7, 36(sp) # 4-byte Folded Reload
; RV32-NEXT: or a3, a1, a7
-; RV32-NEXT: or a5, t2, t3
+; RV32-NEXT: or a5, t1, t3
; RV32-NEXT: sub s5, a2, a6
; RV32-NEXT: or a3, a3, a5
; RV32-NEXT: sub s6, s6, a4
; RV32-NEXT: snez a2, a3
; RV32-NEXT: add a2, t4, a2
-; RV32-NEXT: or a3, a1, t2
+; RV32-NEXT: or a3, a1, t1
; RV32-NEXT: not a2, a2
; RV32-NEXT: seqz a3, a3
; RV32-NEXT: seqz a4, a1
; RV32-NEXT: sltu a5, a7, a3
; RV32-NEXT: sub t4, a7, a3
-; RV32-NEXT: sub t2, t2, a4
+; RV32-NEXT: sub t1, t1, a4
; RV32-NEXT: sub t3, t3, a5
; RV32-NEXT: addi a1, a1, -1
-; RV32-NEXT: or a3, t2, t3
+; RV32-NEXT: or a3, t1, t3
; RV32-NEXT: or a4, a1, t4
; RV32-NEXT: andi s3, a2, 1
; RV32-NEXT: or a3, a4, a3
@@ -1764,7 +1759,7 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: j .LBB3_42
; RV32-NEXT: .LBB3_53:
; RV32-NEXT: li s1, 0
-; RV32-NEXT: mv t1, t5
+; RV32-NEXT: mv t2, t5
; RV32-NEXT: .LBB3_54: # %udiv-loop-exit
; RV32-NEXT: srli a0, t6, 31
; RV32-NEXT: slli a2, s2, 1
@@ -1773,10 +1768,10 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV32-NEXT: or a2, a2, a0
; RV32-NEXT: or a1, a3, a1
; RV32-NEXT: srli s0, s0, 31
-; RV32-NEXT: slli a4, t1, 1
+; RV32-NEXT: slli a4, t2, 1
; RV32-NEXT: or a4, a4, s0
; RV32-NEXT: slli t6, t6, 1
-; RV32-NEXT: srli a5, t1, 31
+; RV32-NEXT: srli a5, t2, 31
; RV32-NEXT: or t4, s1, t6
; RV32-NEXT: lw s7, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: .LBB3_55: # %udiv-end
@@ -2071,27 +2066,26 @@ define i129 @udiv_i129(i129 %x, i129 %y) nounwind {
; RV64-NEXT: snez t5, t5
; RV64-NEXT: sltu t4, t6, t4
; RV64-NEXT: addi t5, t5, -1
-; RV64-NEXT: and t6, t5, t4
-; RV64-NEXT: sltu s0, t2, s2
+; RV64-NEXT: and s0, t5, t4
+; RV64-NEXT: sltu t6, t2, s2
; RV64-NEXT: seqz a7, a7
-; RV64-NEXT: mv t4, s0
-; RV64-NEXT: beq a6, t6, .LBB3_17
+; RV64-NEXT: mv t4, t6
+; RV64-NEXT: beq a6, s0, .LBB3_17
; RV64-NEXT: # %bb.16: # %_udiv-special-cases
-; RV64-NEXT: sltu t4, a6, t6
+; RV64-NEXT: sltu t4, a6, s0
; RV64-NEXT: .LBB3_17: # %_udiv-special-cases
; RV64-NEXT: or t5, t0, a7
-; RV64-NEXT: andi t4, t4, 1
-; RV64-NEXT: sub a6, a6, t6
-; RV64-NEXT: sub a7, a6, s0
+; RV64-NEXT: sub a6, a6, s0
; RV64-NEXT: sub t0, t2, s2
+; RV64-NEXT: sub a7, a6, t6
; RV64-NEXT: beqz t4, .LBB3_19
; RV64-NEXT: # %bb.18: # %_udiv-special-cases
; RV64-NEXT: mv a6, t4
; RV64-NEXT: j .LBB3_20
; RV64-NEXT: .LBB3_19:
; RV64-NEXT: sltiu a6, t0, 129
-; RV64-NEXT: xori a6, a6, 1
; RV64-NEXT: snez t2, a7
+; RV64-NEXT: xori a6, a6, 1
; RV64-NEXT: or a6, a6, t2
; RV64-NEXT: .LBB3_20: # %_udiv-special-cases
; RV64-NEXT: or t6, t5, a6
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
index 888a373bd3791..7e82eb3de9c3d 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
@@ -227,7 +227,8 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: srliw a1, a1, 24
+; RV64I-NEXT: slli a1, a1, 34
+; RV64I-NEXT: srli a1, a1, 58
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: xori a1, a1, 31
; RV64I-NEXT: addi a0, a0, -1
@@ -265,15 +266,17 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srliw a1, a0, 1
+; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 2
+; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 4
+; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 8
+; RV64I-NEXT: slli a1, a0, 33
+; RV64I-NEXT: srli a1, a1, 41
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 16
+; RV64I-NEXT: slli a1, a0, 33
+; RV64I-NEXT: srli a1, a1, 49
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: lui a1, 349525
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index b9a1fee5f0946..248a4991568c9 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -201,7 +201,8 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: srliw a1, a1, 24
+; RV64I-NEXT: slli a1, a1, 34
+; RV64I-NEXT: srli a1, a1, 58
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: xori a1, a1, 31
; RV64I-NEXT: addi a0, a0, -1
@@ -229,15 +230,17 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srliw a1, a0, 1
+; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 2
+; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 4
+; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 8
+; RV64I-NEXT: slli a1, a0, 33
+; RV64I-NEXT: srli a1, a1, 41
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srliw a1, a0, 16
+; RV64I-NEXT: slli a1, a0, 33
+; RV64I-NEXT: srli a1, a1, 49
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: lui a1, 349525
diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
index 96d0978223e5b..bbf0c4a6d1a51 100644
--- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
+++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
@@ -705,106 +705,97 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-LABEL: lshr_16bytes:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: lbu a3, 0(a1)
-; RV32I-NEXT: lbu a4, 1(a0)
-; RV32I-NEXT: lbu a5, 2(a0)
-; RV32I-NEXT: lbu a6, 3(a0)
-; RV32I-NEXT: lbu a7, 0(a0)
+; RV32I-NEXT: lbu a1, 0(a1)
+; RV32I-NEXT: lbu a3, 1(a0)
+; RV32I-NEXT: lbu a4, 2(a0)
+; RV32I-NEXT: lbu a5, 3(a0)
+; RV32I-NEXT: lbu a6, 0(a0)
+; RV32I-NEXT: slli a3, a3, 8
+; RV32I-NEXT: slli a4, a4, 16
+; RV32I-NEXT: slli a5, a5, 24
+; RV32I-NEXT: lbu a7, 4(a0)
; RV32I-NEXT: lbu t0, 5(a0)
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: slli a5, a5, 16
-; RV32I-NEXT: slli a6, a6, 24
; RV32I-NEXT: lbu t1, 6(a0)
-; RV32I-NEXT: lbu t2, 4(a0)
-; RV32I-NEXT: lbu t3, 7(a0)
-; RV32I-NEXT: or a4, a4, a7
-; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: lbu t2, 7(a0)
+; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: or a4, a5, a4
+; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: lbu a4, 9(a0)
; RV32I-NEXT: slli t1, t1, 16
-; RV32I-NEXT: lbu a6, 9(a0)
-; RV32I-NEXT: slli t3, t3, 24
+; RV32I-NEXT: slli t2, t2, 24
+; RV32I-NEXT: or a5, t0, a7
+; RV32I-NEXT: or a6, t2, t1
; RV32I-NEXT: lbu a7, 8(a0)
-; RV32I-NEXT: lbu t4, 10(a0)
-; RV32I-NEXT: lbu t5, 11(a0)
-; RV32I-NEXT: or a5, t0, t2
-; RV32I-NEXT: or t0, t3, t1
-; RV32I-NEXT: or a5, t0, a5
-; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: or a6, a6, a7
-; RV32I-NEXT: lbu a7, 13(a0)
-; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli t5, t5, 24
-; RV32I-NEXT: or t0, t5, t4
-; RV32I-NEXT: lbu t1, 12(a0)
-; RV32I-NEXT: lbu t2, 14(a0)
+; RV32I-NEXT: lbu t0, 10(a0)
+; RV32I-NEXT: lbu t1, 11(a0)
+; RV32I-NEXT: slli a4, a4, 8
+; RV32I-NEXT: lbu t2, 12(a0)
+; RV32I-NEXT: lbu t3, 13(a0)
+; RV32I-NEXT: lbu t4, 14(a0)
; RV32I-NEXT: lbu a0, 15(a0)
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: lbu t3, 1(a1)
-; RV32I-NEXT: lbu t4, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: or a6, t0, a6
-; RV32I-NEXT: or a7, a7, t1
-; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or a0, a0, t2
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a4, a4, a7
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t1, t1, 24
+; RV32I-NEXT: or a6, t1, t0
; RV32I-NEXT: slli t3, t3, 8
; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a3, t3, a3
-; RV32I-NEXT: or a1, a1, t4
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a7, t3, t2
+; RV32I-NEXT: or a0, a0, t4
+; RV32I-NEXT: or a4, a6, a4
; RV32I-NEXT: or a0, a0, a7
-; RV32I-NEXT: or a1, a1, a3
-; RV32I-NEXT: srli a3, a1, 3
+; RV32I-NEXT: srli a6, a1, 3
; RV32I-NEXT: sw zero, 16(sp)
; RV32I-NEXT: sw zero, 20(sp)
; RV32I-NEXT: sw zero, 24(sp)
; RV32I-NEXT: sw zero, 28(sp)
-; RV32I-NEXT: andi a3, a3, 12
+; RV32I-NEXT: andi a6, a6, 12
; RV32I-NEXT: mv a7, sp
-; RV32I-NEXT: sw a4, 0(sp)
+; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: sw a5, 4(sp)
-; RV32I-NEXT: sw a6, 8(sp)
+; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a0, 12(sp)
-; RV32I-NEXT: add a3, a7, a3
-; RV32I-NEXT: lw a0, 8(a3)
-; RV32I-NEXT: lw a4, 4(a3)
-; RV32I-NEXT: andi a5, a1, 31
-; RV32I-NEXT: xori a5, a5, 31
-; RV32I-NEXT: lw a6, 0(a3)
-; RV32I-NEXT: lw a3, 12(a3)
+; RV32I-NEXT: add a6, a7, a6
+; RV32I-NEXT: lw a0, 8(a6)
+; RV32I-NEXT: lw a3, 4(a6)
+; RV32I-NEXT: andi a4, a1, 31
+; RV32I-NEXT: lw a5, 0(a6)
+; RV32I-NEXT: lw a6, 12(a6)
; RV32I-NEXT: slli a7, a0, 1
-; RV32I-NEXT: srl t0, a4, a1
-; RV32I-NEXT: sll a7, a7, a5
+; RV32I-NEXT: xori a4, a4, 31
+; RV32I-NEXT: srl t0, a3, a1
+; RV32I-NEXT: sll a7, a7, a4
; RV32I-NEXT: or a7, t0, a7
-; RV32I-NEXT: slli a4, a4, 1
-; RV32I-NEXT: srl a6, a6, a1
-; RV32I-NEXT: sll a4, a4, a5
-; RV32I-NEXT: or a4, a6, a4
-; RV32I-NEXT: slli a6, a3, 1
+; RV32I-NEXT: slli a3, a3, 1
+; RV32I-NEXT: srl a5, a5, a1
+; RV32I-NEXT: sll a3, a3, a4
+; RV32I-NEXT: or a3, a5, a3
+; RV32I-NEXT: slli a5, a6, 1
; RV32I-NEXT: srl a0, a0, a1
-; RV32I-NEXT: sll a5, a6, a5
-; RV32I-NEXT: or a0, a0, a5
-; RV32I-NEXT: srl a1, a3, a1
-; RV32I-NEXT: srli a3, a1, 16
+; RV32I-NEXT: sll a4, a5, a4
+; RV32I-NEXT: or a0, a0, a4
+; RV32I-NEXT: srl a1, a6, a1
+; RV32I-NEXT: srli a4, a1, 16
; RV32I-NEXT: srli a5, a1, 24
; RV32I-NEXT: srli a6, a1, 8
; RV32I-NEXT: sb a1, 12(a2)
; RV32I-NEXT: sb a6, 13(a2)
-; RV32I-NEXT: sb a3, 14(a2)
+; RV32I-NEXT: sb a4, 14(a2)
; RV32I-NEXT: sb a5, 15(a2)
; RV32I-NEXT: srli a1, a0, 16
-; RV32I-NEXT: srli a3, a0, 24
+; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: srli a5, a0, 8
; RV32I-NEXT: sb a0, 8(a2)
; RV32I-NEXT: sb a5, 9(a2)
; RV32I-NEXT: sb a1, 10(a2)
-; RV32I-NEXT: sb a3, 11(a2)
-; RV32I-NEXT: srli a0, a4, 16
-; RV32I-NEXT: srli a1, a4, 24
-; RV32I-NEXT: srli a3, a4, 8
-; RV32I-NEXT: sb a4, 0(a2)
-; RV32I-NEXT: sb a3, 1(a2)
+; RV32I-NEXT: sb a4, 11(a2)
+; RV32I-NEXT: srli a0, a3, 16
+; RV32I-NEXT: srli a1, a3, 24
+; RV32I-NEXT: srli a4, a3, 8
+; RV32I-NEXT: sb a3, 0(a2)
+; RV32I-NEXT: sb a4, 1(a2)
; RV32I-NEXT: sb a0, 2(a2)
; RV32I-NEXT: sb a1, 3(a2)
; RV32I-NEXT: srli a0, a7, 16
@@ -941,75 +932,66 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-LABEL: shl_16bytes:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: lbu a3, 0(a1)
-; RV32I-NEXT: lbu a4, 1(a0)
-; RV32I-NEXT: lbu a5, 2(a0)
-; RV32I-NEXT: lbu a6, 3(a0)
-; RV32I-NEXT: lbu a7, 0(a0)
+; RV32I-NEXT: lbu a1, 0(a1)
+; RV32I-NEXT: lbu a3, 1(a0)
+; RV32I-NEXT: lbu a4, 2(a0)
+; RV32I-NEXT: lbu a5, 3(a0)
+; RV32I-NEXT: lbu a6, 0(a0)
+; RV32I-NEXT: slli a3, a3, 8
+; RV32I-NEXT: slli a4, a4, 16
+; RV32I-NEXT: slli a5, a5, 24
+; RV32I-NEXT: lbu a7, 4(a0)
; RV32I-NEXT: lbu t0, 5(a0)
-; RV32I-NEXT: slli a4, a4, 8
-; RV32I-NEXT: slli a5, a5, 16
-; RV32I-NEXT: slli a6, a6, 24
; RV32I-NEXT: lbu t1, 6(a0)
-; RV32I-NEXT: lbu t2, 4(a0)
-; RV32I-NEXT: lbu t3, 7(a0)
-; RV32I-NEXT: or a4, a4, a7
-; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: lbu t2, 7(a0)
+; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: or a4, a5, a4
+; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: lbu a4, 9(a0)
; RV32I-NEXT: slli t1, t1, 16
-; RV32I-NEXT: lbu a6, 9(a0)
-; RV32I-NEXT: slli t3, t3, 24
+; RV32I-NEXT: slli t2, t2, 24
+; RV32I-NEXT: or a5, t0, a7
+; RV32I-NEXT: or a6, t2, t1
; RV32I-NEXT: lbu a7, 8(a0)
-; RV32I-NEXT: lbu t4, 10(a0)
-; RV32I-NEXT: lbu t5, 11(a0)
-; RV32I-NEXT: or a5, t0, t2
-; RV32I-NEXT: or t0, t3, t1
-; RV32I-NEXT: or a5, t0, a5
-; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: or a6, a6, a7
-; RV32I-NEXT: lbu a7, 13(a0)
-; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli t5, t5, 24
-; RV32I-NEXT: or t0, t5, t4
-; RV32I-NEXT: lbu t1, 12(a0)
-; RV32I-NEXT: lbu t2, 14(a0)
+; RV32I-NEXT: lbu t0, 10(a0)
+; RV32I-NEXT: lbu t1, 11(a0)
+; RV32I-NEXT: slli a4, a4, 8
+; RV32I-NEXT: lbu t2, 12(a0)
+; RV32I-NEXT: lbu t3, 13(a0)
+; RV32I-NEXT: lbu t4, 14(a0)
; RV32I-NEXT: lbu a0, 15(a0)
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: lbu t3, 1(a1)
-; RV32I-NEXT: lbu t4, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: or a6, t0, a6
-; RV32I-NEXT: or a7, a7, t1
-; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or a0, a0, t2
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a4, a4, a7
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t1, t1, 24
+; RV32I-NEXT: or a6, t1, t0
; RV32I-NEXT: slli t3, t3, 8
; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a3, t3, a3
-; RV32I-NEXT: or a1, a1, t4
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or a7, t3, t2
+; RV32I-NEXT: or a0, a0, t4
+; RV32I-NEXT: or a4, a6, a4
; RV32I-NEXT: or a0, a0, a7
-; RV32I-NEXT: or a1, a1, a3
-; RV32I-NEXT: srli a3, a1, 3
+; RV32I-NEXT: srli a6, a1, 3
; RV32I-NEXT: sw zero, 0(sp)
; RV32I-NEXT: sw zero, 4(sp)
; RV32I-NEXT: sw zero, 8(sp)
; RV32I-NEXT: sw zero, 12(sp)
-; RV32I-NEXT: andi a3, a3, 12
+; RV32I-NEXT: andi a6, a6, 12
; RV32I-NEXT: addi a7, sp, 16
-; RV32I-NEXT: sw a4, 16(sp)
+; RV32I-NEXT: sw a3, 16(sp)
; RV32I-NEXT: sw a5, 20(sp)
-; RV32I-NEXT: sw a6, 24(sp)
+; RV32I-NEXT: sw a4, 24(sp)
; RV32I-NEXT: sw a0, 28(sp)
-; RV32I-NEXT: sub a0, a7, a3
+; RV32I-NEXT: sub a0, a7, a6
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a4, 4(a0)
; RV32I-NEXT: lw a5, 8(a0)
; RV32I-NEXT: andi a6, a1, 31
; RV32I-NEXT: lw a0, 12(a0)
-; RV32I-NEXT: xori a6, a6, 31
; RV32I-NEXT: srli a7, a3, 1
+; RV32I-NEXT: xori a6, a6, 31
; RV32I-NEXT: sll t0, a4, a1
; RV32I-NEXT: srl a7, a7, a6
; RV32I-NEXT: or a7, t0, a7
@@ -1177,76 +1159,67 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-LABEL: ashr_16bytes:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: lbu a4, 0(a1)
+; RV32I-NEXT: lbu a1, 0(a1)
; RV32I-NEXT: lbu a3, 1(a0)
-; RV32I-NEXT: lbu a5, 2(a0)
-; RV32I-NEXT: lbu a6, 3(a0)
-; RV32I-NEXT: lbu a7, 0(a0)
-; RV32I-NEXT: lbu t0, 5(a0)
+; RV32I-NEXT: lbu a4, 2(a0)
+; RV32I-NEXT: lbu a5, 3(a0)
+; RV32I-NEXT: lbu a6, 0(a0)
+; RV32I-NEXT: lbu a7, 5(a0)
; RV32I-NEXT: slli a3, a3, 8
-; RV32I-NEXT: slli a5, a5, 16
-; RV32I-NEXT: slli a6, a6, 24
-; RV32I-NEXT: or a3, a3, a7
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a3, a5, a3
-; RV32I-NEXT: lbu a5, 4(a0)
-; RV32I-NEXT: lbu a6, 6(a0)
-; RV32I-NEXT: lbu a7, 7(a0)
-; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: lbu t1, 9(a0)
-; RV32I-NEXT: lbu t2, 8(a0)
-; RV32I-NEXT: lbu t3, 10(a0)
-; RV32I-NEXT: or a5, t0, a5
-; RV32I-NEXT: lbu t0, 11(a0)
-; RV32I-NEXT: slli a6, a6, 16
-; RV32I-NEXT: slli a7, a7, 24
-; RV32I-NEXT: or a6, a7, a6
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: or a7, t1, t2
-; RV32I-NEXT: slli t3, t3, 16
-; RV32I-NEXT: slli t0, t0, 24
-; RV32I-NEXT: lbu t1, 13(a0)
-; RV32I-NEXT: or t0, t0, t3
-; RV32I-NEXT: lbu t2, 12(a0)
+; RV32I-NEXT: slli a4, a4, 16
+; RV32I-NEXT: slli a5, a5, 24
+; RV32I-NEXT: lbu t0, 4(a0)
+; RV32I-NEXT: lbu t1, 6(a0)
+; RV32I-NEXT: lbu t2, 7(a0)
+; RV32I-NEXT: or a3, a3, a6
+; RV32I-NEXT: or a4, a5, a4
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: or a4, a7, t0
+; RV32I-NEXT: lbu a5, 9(a0)
+; RV32I-NEXT: slli t1, t1, 16
+; RV32I-NEXT: slli t2, t2, 24
+; RV32I-NEXT: or a6, t2, t1
+; RV32I-NEXT: lbu a7, 8(a0)
+; RV32I-NEXT: lbu t0, 10(a0)
+; RV32I-NEXT: lbu t1, 11(a0)
+; RV32I-NEXT: or a4, a6, a4
+; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: lbu a6, 12(a0)
+; RV32I-NEXT: lbu t2, 13(a0)
; RV32I-NEXT: lbu t3, 14(a0)
; RV32I-NEXT: lbu a0, 15(a0)
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a6, t0, a7
-; RV32I-NEXT: slli t1, t1, 8
-; RV32I-NEXT: lbu a7, 1(a1)
-; RV32I-NEXT: lbu t0, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t1, t1, 24
+; RV32I-NEXT: or a5, a5, a7
+; RV32I-NEXT: or a7, t1, t0
+; RV32I-NEXT: or a5, a7, a5
+; RV32I-NEXT: slli t2, t2, 8
; RV32I-NEXT: slli t3, t3, 16
; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or t1, t1, t2
-; RV32I-NEXT: or t2, a0, t3
-; RV32I-NEXT: or t1, t2, t1
-; RV32I-NEXT: slli a7, a7, 8
-; RV32I-NEXT: slli t0, t0, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a4, a7, a4
-; RV32I-NEXT: or a1, a1, t0
-; RV32I-NEXT: or a1, a1, a4
+; RV32I-NEXT: or a6, t2, a6
+; RV32I-NEXT: or a7, a0, t3
+; RV32I-NEXT: or a6, a7, a6
; RV32I-NEXT: srai a0, a0, 31
-; RV32I-NEXT: srli a4, a1, 3
+; RV32I-NEXT: srli a7, a1, 3
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: sw a0, 28(sp)
-; RV32I-NEXT: andi a4, a4, 12
-; RV32I-NEXT: mv a0, sp
+; RV32I-NEXT: andi a0, a7, 12
+; RV32I-NEXT: mv a7, sp
; RV32I-NEXT: sw a3, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
-; RV32I-NEXT: sw a6, 8(sp)
-; RV32I-NEXT: sw t1, 12(sp)
-; RV32I-NEXT: add a0, a0, a4
+; RV32I-NEXT: sw a4, 4(sp)
+; RV32I-NEXT: sw a5, 8(sp)
+; RV32I-NEXT: sw a6, 12(sp)
+; RV32I-NEXT: add a0, a7, a0
; RV32I-NEXT: lw a3, 8(a0)
; RV32I-NEXT: lw a4, 4(a0)
; RV32I-NEXT: andi a5, a1, 31
-; RV32I-NEXT: xori a5, a5, 31
; RV32I-NEXT: lw a6, 0(a0)
; RV32I-NEXT: lw a0, 12(a0)
; RV32I-NEXT: slli a7, a3, 1
+; RV32I-NEXT: xori a5, a5, 31
; RV32I-NEXT: srl t0, a4, a1
; RV32I-NEXT: sll a7, a7, a5
; RV32I-NEXT: or a7, t0, a7
@@ -1300,192 +1273,171 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-LABEL: lshr_32bytes:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: lbu a3, 1(a1)
-; RV64I-NEXT: lbu a4, 1(a0)
+; RV64I-NEXT: lbu a1, 0(a1)
+; RV64I-NEXT: lbu a3, 1(a0)
+; RV64I-NEXT: lbu a4, 0(a0)
; RV64I-NEXT: lbu a5, 2(a0)
; RV64I-NEXT: lbu a6, 3(a0)
-; RV64I-NEXT: lbu a7, 0(a0)
-; RV64I-NEXT: slli a4, a4, 8
-; RV64I-NEXT: lbu t0, 5(a0)
+; RV64I-NEXT: lbu a7, 5(a0)
+; RV64I-NEXT: slli a3, a3, 8
+; RV64I-NEXT: lbu t0, 4(a0)
; RV64I-NEXT: lbu t1, 6(a0)
-; RV64I-NEXT: lbu t2, 4(a0)
-; RV64I-NEXT: lbu t3, 7(a0)
+; RV64I-NEXT: lbu t2, 7(a0)
+; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: slli a5, a5, 16
+; RV64I-NEXT: slli a7, a7, 8
; RV64I-NEXT: slli a6, a6, 24
-; RV64I-NEXT: or a4, a4, a7
+; RV64I-NEXT: or a4, a7, t0
+; RV64I-NEXT: slli t1, t1, 16
+; RV64I-NEXT: slli t2, t2, 24
+; RV64I-NEXT: or a7, t2, t1
+; RV64I-NEXT: lbu t0, 9(a0)
; RV64I-NEXT: or a5, a6, a5
+; RV64I-NEXT: or a4, a7, a4
+; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: slli a4, a4, 32
+; RV64I-NEXT: lbu a5, 8(a0)
+; RV64I-NEXT: lbu a6, 10(a0)
+; RV64I-NEXT: lbu a7, 11(a0)
; RV64I-NEXT: slli t0, t0, 8
-; RV64I-NEXT: slli t1, t1, 16
-; RV64I-NEXT: slli t3, t3, 24
-; RV64I-NEXT: lbu a6, 9(a0)
-; RV64I-NEXT: or a7, t0, t2
-; RV64I-NEXT: or t0, t3, t1
+; RV64I-NEXT: lbu t1, 12(a0)
+; RV64I-NEXT: lbu t2, 13(a0)
+; RV64I-NEXT: lbu t3, 14(a0)
+; RV64I-NEXT: lbu t4, 15(a0)
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: or a4, t0, a5
+; RV64I-NEXT: slli a6, a6, 16
+; RV64I-NEXT: slli a7, a7, 24
+; RV64I-NEXT: or a5, a7, a6
+; RV64I-NEXT: slli t2, t2, 8
+; RV64I-NEXT: slli t3, t3, 16
+; RV64I-NEXT: slli t4, t4, 24
+; RV64I-NEXT: lbu a6, 16(a0)
+; RV64I-NEXT: lbu a7, 17(a0)
+; RV64I-NEXT: lbu t0, 18(a0)
+; RV64I-NEXT: lbu t5, 19(a0)
+; RV64I-NEXT: or t1, t2, t1
+; RV64I-NEXT: or t2, t4, t3
; RV64I-NEXT: or a4, a5, a4
-; RV64I-NEXT: or a5, t0, a7
-; RV64I-NEXT: lbu a7, 8(a0)
-; RV64I-NEXT: lbu t0, 10(a0)
-; RV64I-NEXT: lbu t1, 11(a0)
-; RV64I-NEXT: slli a6, a6, 8
-; RV64I-NEXT: lbu t2, 12(a0)
-; RV64I-NEXT: lbu t3, 13(a0)
-; RV64I-NEXT: lbu t4, 14(a0)
-; RV64I-NEXT: lbu t5, 15(a0)
+; RV64I-NEXT: or a5, t2, t1
; RV64I-NEXT: slli a5, a5, 32
-; RV64I-NEXT: or a6, a6, a7
+; RV64I-NEXT: slli a7, a7, 8
; RV64I-NEXT: slli t0, t0, 16
-; RV64I-NEXT: slli t1, t1, 24
-; RV64I-NEXT: or a7, t1, t0
-; RV64I-NEXT: slli t3, t3, 8
-; RV64I-NEXT: slli t4, t4, 16
; RV64I-NEXT: slli t5, t5, 24
-; RV64I-NEXT: or t0, t3, t2
-; RV64I-NEXT: or t1, t5, t4
+; RV64I-NEXT: lbu t1, 20(a0)
+; RV64I-NEXT: lbu t2, 21(a0)
+; RV64I-NEXT: lbu t3, 22(a0)
+; RV64I-NEXT: lbu t4, 23(a0)
; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: or a7, t1, t0
-; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: lbu t0, 17(a0)
+; RV64I-NEXT: or a7, t5, t0
; RV64I-NEXT: or a4, a5, a4
; RV64I-NEXT: or a5, a7, a6
-; RV64I-NEXT: lbu a6, 16(a0)
-; RV64I-NEXT: lbu a7, 18(a0)
-; RV64I-NEXT: lbu t1, 19(a0)
-; RV64I-NEXT: lbu t2, 21(a0)
-; RV64I-NEXT: slli t0, t0, 8
-; RV64I-NEXT: lbu t3, 20(a0)
-; RV64I-NEXT: lbu t4, 22(a0)
-; RV64I-NEXT: lbu t5, 23(a0)
-; RV64I-NEXT: or a6, t0, a6
-; RV64I-NEXT: slli a7, a7, 16
-; RV64I-NEXT: slli t1, t1, 24
; RV64I-NEXT: slli t2, t2, 8
-; RV64I-NEXT: or a7, t1, a7
-; RV64I-NEXT: or t0, t2, t3
-; RV64I-NEXT: slli t4, t4, 16
-; RV64I-NEXT: slli t5, t5, 24
-; RV64I-NEXT: or t1, t5, t4
-; RV64I-NEXT: lbu t2, 25(a0)
-; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: or a7, t1, t0
-; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: lbu t0, 24(a0)
-; RV64I-NEXT: lbu t1, 26(a0)
+; RV64I-NEXT: lbu a6, 25(a0)
+; RV64I-NEXT: slli t3, t3, 16
+; RV64I-NEXT: slli t4, t4, 24
+; RV64I-NEXT: or a7, t2, t1
+; RV64I-NEXT: or t0, t4, t3
+; RV64I-NEXT: lbu t1, 24(a0)
+; RV64I-NEXT: lbu t2, 26(a0)
; RV64I-NEXT: lbu t3, 27(a0)
-; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: slli t2, t2, 8
-; RV64I-NEXT: lbu a7, 28(a0)
-; RV64I-NEXT: lbu t4, 29(a0)
-; RV64I-NEXT: lbu t5, 30(a0)
+; RV64I-NEXT: slli a6, a6, 8
+; RV64I-NEXT: lbu t4, 28(a0)
+; RV64I-NEXT: lbu t5, 29(a0)
+; RV64I-NEXT: lbu t6, 30(a0)
; RV64I-NEXT: lbu a0, 31(a0)
-; RV64I-NEXT: slli t1, t1, 16
-; RV64I-NEXT: slli t3, t3, 24
-; RV64I-NEXT: or t0, t2, t0
-; RV64I-NEXT: or t1, t3, t1
-; RV64I-NEXT: or t0, t1, t0
-; RV64I-NEXT: slli t4, t4, 8
-; RV64I-NEXT: slli t5, t5, 16
-; RV64I-NEXT: slli a0, a0, 24
-; RV64I-NEXT: or a7, t4, a7
-; RV64I-NEXT: or a0, a0, t5
-; RV64I-NEXT: lbu t1, 0(a1)
-; RV64I-NEXT: lbu t2, 2(a1)
-; RV64I-NEXT: lbu t3, 3(a1)
-; RV64I-NEXT: slli a3, a3, 8
-; RV64I-NEXT: lbu t4, 4(a1)
-; RV64I-NEXT: lbu t5, 5(a1)
-; RV64I-NEXT: lbu t6, 6(a1)
-; RV64I-NEXT: lbu a1, 7(a1)
-; RV64I-NEXT: or a0, a0, a7
-; RV64I-NEXT: or a3, a3, t1
+; RV64I-NEXT: or a7, t0, a7
+; RV64I-NEXT: or a6, a6, t1
; RV64I-NEXT: slli t2, t2, 16
; RV64I-NEXT: slli t3, t3, 24
-; RV64I-NEXT: or a7, t3, t2
+; RV64I-NEXT: or t0, t3, t2
; RV64I-NEXT: slli t5, t5, 8
; RV64I-NEXT: slli t6, t6, 16
-; RV64I-NEXT: slli a1, a1, 24
+; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or t1, t5, t4
-; RV64I-NEXT: or a1, a1, t6
-; RV64I-NEXT: or a1, a1, t1
+; RV64I-NEXT: or a0, a0, t6
+; RV64I-NEXT: or a0, a0, t1
+; RV64I-NEXT: slli a7, a7, 32
+; RV64I-NEXT: or a6, t0, a6
; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: or a3, a7, a3
-; RV64I-NEXT: slli a1, a1, 32
-; RV64I-NEXT: or a0, a0, t0
-; RV64I-NEXT: or a3, a1, a3
-; RV64I-NEXT: srli a1, a3, 3
+; RV64I-NEXT: or a5, a7, a5
+; RV64I-NEXT: or a0, a0, a6
+; RV64I-NEXT: srli a6, a1, 3
; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd zero, 48(sp)
; RV64I-NEXT: sd zero, 56(sp)
-; RV64I-NEXT: andi a1, a1, 24
+; RV64I-NEXT: andi a6, a6, 24
; RV64I-NEXT: mv a7, sp
-; RV64I-NEXT: sd a4, 0(sp)
-; RV64I-NEXT: sd a5, 8(sp)
-; RV64I-NEXT: sd a6, 16(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: sd a4, 8(sp)
+; RV64I-NEXT: sd a5, 16(sp)
; RV64I-NEXT: sd a0, 24(sp)
-; RV64I-NEXT: add a1, a7, a1
-; RV64I-NEXT: ld a4, 16(a1)
-; RV64I-NEXT: ld a5, 8(a1)
-; RV64I-NEXT: andi a0, a3, 63
-; RV64I-NEXT: xori a6, a0, 63
-; RV64I-NEXT: ld a7, 0(a1)
-; RV64I-NEXT: ld t0, 24(a1)
-; RV64I-NEXT: slli a0, a4, 1
-; RV64I-NEXT: srl a1, a5, a3
-; RV64I-NEXT: sll a0, a0, a6
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: slli a5, a5, 1
-; RV64I-NEXT: srl a1, a7, a3
-; RV64I-NEXT: sll a5, a5, a6
-; RV64I-NEXT: or a1, a1, a5
-; RV64I-NEXT: slli a5, t0, 1
-; RV64I-NEXT: srl a4, a4, a3
-; RV64I-NEXT: sll a5, a5, a6
+; RV64I-NEXT: add a6, a7, a6
+; RV64I-NEXT: ld a4, 16(a6)
+; RV64I-NEXT: ld a3, 8(a6)
+; RV64I-NEXT: andi a0, a1, 63
+; RV64I-NEXT: ld a5, 0(a6)
+; RV64I-NEXT: ld a6, 24(a6)
+; RV64I-NEXT: slli a7, a4, 1
+; RV64I-NEXT: xori t0, a0, 63
+; RV64I-NEXT: srl a0, a3, a1
+; RV64I-NEXT: sll a7, a7, t0
+; RV64I-NEXT: or a0, a0, a7
+; RV64I-NEXT: slli a3, a3, 1
+; RV64I-NEXT: srl a5, a5, a1
+; RV64I-NEXT: sll a3, a3, t0
+; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: slli a5, a6, 1
+; RV64I-NEXT: srl a4, a4, a1
+; RV64I-NEXT: sll a5, a5, t0
; RV64I-NEXT: or a4, a4, a5
-; RV64I-NEXT: srl a3, t0, a3
-; RV64I-NEXT: srli a5, a3, 56
-; RV64I-NEXT: srli a6, a3, 48
-; RV64I-NEXT: srli a7, a3, 40
-; RV64I-NEXT: srli t0, a3, 32
+; RV64I-NEXT: srl a1, a6, a1
+; RV64I-NEXT: srli a5, a1, 56
+; RV64I-NEXT: srli a6, a1, 48
+; RV64I-NEXT: srli a7, a1, 40
+; RV64I-NEXT: srli t0, a1, 32
; RV64I-NEXT: sb t0, 28(a2)
; RV64I-NEXT: sb a7, 29(a2)
; RV64I-NEXT: sb a6, 30(a2)
; RV64I-NEXT: sb a5, 31(a2)
-; RV64I-NEXT: srli a5, a3, 24
-; RV64I-NEXT: srli a6, a3, 16
-; RV64I-NEXT: srli a7, a3, 8
-; RV64I-NEXT: sb a3, 24(a2)
+; RV64I-NEXT: srli a5, a1, 24
+; RV64I-NEXT: srli a6, a1, 16
+; RV64I-NEXT: srli a7, a1, 8
+; RV64I-NEXT: sb a1, 24(a2)
; RV64I-NEXT: sb a7, 25(a2)
; RV64I-NEXT: sb a6, 26(a2)
; RV64I-NEXT: sb a5, 27(a2)
-; RV64I-NEXT: srli a3, a4, 56
+; RV64I-NEXT: srli a1, a4, 56
; RV64I-NEXT: srli a5, a4, 48
; RV64I-NEXT: srli a6, a4, 32
; RV64I-NEXT: srli a7, a4, 40
; RV64I-NEXT: sb a6, 20(a2)
; RV64I-NEXT: sb a7, 21(a2)
; RV64I-NEXT: sb a5, 22(a2)
-; RV64I-NEXT: sb a3, 23(a2)
-; RV64I-NEXT: srli a3, a4, 24
+; RV64I-NEXT: sb a1, 23(a2)
+; RV64I-NEXT: srli a1, a4, 24
; RV64I-NEXT: srli a5, a4, 16
; RV64I-NEXT: srli a6, a4, 8
; RV64I-NEXT: sb a4, 16(a2)
; RV64I-NEXT: sb a6, 17(a2)
; RV64I-NEXT: sb a5, 18(a2)
-; RV64I-NEXT: sb a3, 19(a2)
-; RV64I-NEXT: srli a3, a1, 56
-; RV64I-NEXT: srli a4, a1, 48
-; RV64I-NEXT: srli a5, a1, 40
-; RV64I-NEXT: srli a6, a1, 32
+; RV64I-NEXT: sb a1, 19(a2)
+; RV64I-NEXT: srli a1, a3, 56
+; RV64I-NEXT: srli a4, a3, 48
+; RV64I-NEXT: srli a5, a3, 40
+; RV64I-NEXT: srli a6, a3, 32
; RV64I-NEXT: sb a6, 4(a2)
; RV64I-NEXT: sb a5, 5(a2)
; RV64I-NEXT: sb a4, 6(a2)
-; RV64I-NEXT: sb a3, 7(a2)
-; RV64I-NEXT: srli a3, a1, 24
-; RV64I-NEXT: srli a4, a1, 16
-; RV64I-NEXT: srli a5, a1, 8
-; RV64I-NEXT: sb a1, 0(a2)
+; RV64I-NEXT: sb a1, 7(a2)
+; RV64I-NEXT: srli a1, a3, 24
+; RV64I-NEXT: srli a4, a3, 16
+; RV64I-NEXT: srli a5, a3, 8
+; RV64I-NEXT: sb a3, 0(a2)
; RV64I-NEXT: sb a5, 1(a2)
; RV64I-NEXT: sb a4, 2(a2)
-; RV64I-NEXT: sb a3, 3(a2)
+; RV64I-NEXT: sb a1, 3(a2)
; RV64I-NEXT: srli a1, a0, 56
; RV64I-NEXT: srli a3, a0, 48
; RV64I-NEXT: srli a4, a0, 32
@@ -1509,96 +1461,87 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw s0, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 72(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lbu a4, 0(a1)
+; RV32I-NEXT: lbu a1, 0(a1)
; RV32I-NEXT: lbu a3, 1(a0)
+; RV32I-NEXT: lbu a4, 0(a0)
; RV32I-NEXT: lbu a5, 2(a0)
; RV32I-NEXT: lbu a6, 3(a0)
-; RV32I-NEXT: lbu a7, 0(a0)
-; RV32I-NEXT: lbu t0, 5(a0)
; RV32I-NEXT: slli a3, a3, 8
+; RV32I-NEXT: lbu a7, 5(a0)
+; RV32I-NEXT: lbu t0, 6(a0)
+; RV32I-NEXT: lbu t1, 7(a0)
+; RV32I-NEXT: lbu t2, 4(a0)
+; RV32I-NEXT: or a3, a3, a4
; RV32I-NEXT: slli a5, a5, 16
; RV32I-NEXT: slli a6, a6, 24
-; RV32I-NEXT: lbu t1, 6(a0)
-; RV32I-NEXT: lbu t2, 4(a0)
-; RV32I-NEXT: lbu t3, 7(a0)
-; RV32I-NEXT: or a3, a3, a7
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a3, a5, a3
-; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
-; RV32I-NEXT: lbu a6, 9(a0)
-; RV32I-NEXT: slli t3, t3, 24
-; RV32I-NEXT: lbu a7, 10(a0)
-; RV32I-NEXT: lbu t4, 8(a0)
-; RV32I-NEXT: lbu t5, 11(a0)
-; RV32I-NEXT: or a5, t0, t2
-; RV32I-NEXT: or t0, t3, t1
-; RV32I-NEXT: or a5, t0, a5
-; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: slli a7, a7, 16
-; RV32I-NEXT: lbu t0, 13(a0)
-; RV32I-NEXT: slli t5, t5, 24
+; RV32I-NEXT: or a4, a6, a5
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t1, t1, 24
+; RV32I-NEXT: lbu a5, 8(a0)
+; RV32I-NEXT: lbu a6, 9(a0)
+; RV32I-NEXT: lbu t3, 10(a0)
+; RV32I-NEXT: lbu t4, 11(a0)
+; RV32I-NEXT: or a7, a7, t2
+; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: or a4, t0, a7
+; RV32I-NEXT: slli a6, a6, 8
+; RV32I-NEXT: lbu a7, 13(a0)
+; RV32I-NEXT: slli t3, t3, 16
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a6, t4, t3
+; RV32I-NEXT: lbu t0, 12(a0)
; RV32I-NEXT: lbu t1, 14(a0)
-; RV32I-NEXT: lbu t2, 12(a0)
-; RV32I-NEXT: lbu t3, 15(a0)
-; RV32I-NEXT: or a6, a6, t4
-; RV32I-NEXT: or a7, t5, a7
-; RV32I-NEXT: or a6, a7, a6
-; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
+; RV32I-NEXT: lbu t2, 15(a0)
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: lbu t3, 16(a0)
; RV32I-NEXT: lbu t4, 17(a0)
-; RV32I-NEXT: slli t3, t3, 24
; RV32I-NEXT: lbu t5, 18(a0)
-; RV32I-NEXT: lbu t6, 16(a0)
-; RV32I-NEXT: lbu s0, 19(a0)
-; RV32I-NEXT: or a7, t0, t2
-; RV32I-NEXT: or t0, t3, t1
-; RV32I-NEXT: or a7, t0, a7
+; RV32I-NEXT: lbu t6, 19(a0)
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a6, a7, t0
+; RV32I-NEXT: slli t1, t1, 16
+; RV32I-NEXT: slli t2, t2, 24
+; RV32I-NEXT: or a7, t2, t1
; RV32I-NEXT: slli t4, t4, 8
; RV32I-NEXT: slli t5, t5, 16
+; RV32I-NEXT: slli t6, t6, 24
+; RV32I-NEXT: lbu t0, 20(a0)
; RV32I-NEXT: lbu t1, 21(a0)
-; RV32I-NEXT: slli s0, s0, 24
; RV32I-NEXT: lbu t2, 22(a0)
-; RV32I-NEXT: lbu t3, 20(a0)
-; RV32I-NEXT: lbu s1, 23(a0)
-; RV32I-NEXT: or t0, t4, t6
-; RV32I-NEXT: or t4, s0, t5
-; RV32I-NEXT: or t0, t4, t0
+; RV32I-NEXT: lbu s0, 23(a0)
+; RV32I-NEXT: or t3, t4, t3
+; RV32I-NEXT: or t4, t6, t5
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a7, t4, t3
; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: lbu t3, 25(a0)
; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: lbu t4, 25(a0)
-; RV32I-NEXT: slli s1, s1, 24
-; RV32I-NEXT: lbu t5, 24(a0)
-; RV32I-NEXT: lbu t6, 26(a0)
-; RV32I-NEXT: lbu s0, 27(a0)
-; RV32I-NEXT: or t1, t1, t3
-; RV32I-NEXT: or t2, s1, t2
-; RV32I-NEXT: or t1, t2, t1
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: or t2, t4, t5
-; RV32I-NEXT: lbu t3, 29(a0)
-; RV32I-NEXT: slli t6, t6, 16
; RV32I-NEXT: slli s0, s0, 24
-; RV32I-NEXT: or t4, s0, t6
-; RV32I-NEXT: lbu t5, 28(a0)
-; RV32I-NEXT: lbu t6, 30(a0)
-; RV32I-NEXT: lbu a0, 31(a0)
+; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: or t1, s0, t2
+; RV32I-NEXT: lbu t2, 24(a0)
+; RV32I-NEXT: lbu t4, 26(a0)
+; RV32I-NEXT: lbu t5, 27(a0)
; RV32I-NEXT: slli t3, t3, 8
-; RV32I-NEXT: lbu s0, 1(a1)
-; RV32I-NEXT: lbu s1, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: or t2, t4, t2
-; RV32I-NEXT: or t3, t3, t5
-; RV32I-NEXT: slli t6, t6, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or a0, a0, t6
+; RV32I-NEXT: lbu t6, 28(a0)
+; RV32I-NEXT: lbu s0, 29(a0)
+; RV32I-NEXT: lbu s1, 30(a0)
+; RV32I-NEXT: lbu a0, 31(a0)
+; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: or t1, t3, t2
+; RV32I-NEXT: slli t4, t4, 16
+; RV32I-NEXT: slli t5, t5, 24
+; RV32I-NEXT: or t2, t5, t4
; RV32I-NEXT: slli s0, s0, 8
; RV32I-NEXT: slli s1, s1, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a4, s0, a4
-; RV32I-NEXT: or a1, a1, s1
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or t3, s0, t6
+; RV32I-NEXT: or a0, a0, s1
+; RV32I-NEXT: or t1, t2, t1
; RV32I-NEXT: or a0, a0, t3
-; RV32I-NEXT: or a4, a1, a4
; RV32I-NEXT: sw zero, 56(sp)
; RV32I-NEXT: sw zero, 60(sp)
; RV32I-NEXT: sw zero, 64(sp)
@@ -1607,106 +1550,106 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: sw zero, 44(sp)
; RV32I-NEXT: sw zero, 48(sp)
; RV32I-NEXT: sw zero, 52(sp)
-; RV32I-NEXT: srli a1, a4, 3
-; RV32I-NEXT: sw t0, 24(sp)
-; RV32I-NEXT: sw t1, 28(sp)
-; RV32I-NEXT: sw t2, 32(sp)
+; RV32I-NEXT: srli t2, a1, 3
+; RV32I-NEXT: sw a7, 24(sp)
+; RV32I-NEXT: sw t0, 28(sp)
+; RV32I-NEXT: sw t1, 32(sp)
; RV32I-NEXT: sw a0, 36(sp)
-; RV32I-NEXT: andi a1, a1, 28
-; RV32I-NEXT: addi a0, sp, 8
+; RV32I-NEXT: andi a0, t2, 28
+; RV32I-NEXT: addi a7, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
-; RV32I-NEXT: sw a5, 12(sp)
-; RV32I-NEXT: sw a6, 16(sp)
-; RV32I-NEXT: sw a7, 20(sp)
-; RV32I-NEXT: add a3, a0, a1
-; RV32I-NEXT: lw a5, 8(a3)
-; RV32I-NEXT: lw a0, 4(a3)
-; RV32I-NEXT: andi a1, a4, 31
-; RV32I-NEXT: xori a6, a1, 31
-; RV32I-NEXT: lw a1, 0(a3)
-; RV32I-NEXT: lw a7, 12(a3)
+; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: sw a5, 16(sp)
+; RV32I-NEXT: sw a6, 20(sp)
+; RV32I-NEXT: add a7, a7, a0
+; RV32I-NEXT: lw a5, 8(a7)
+; RV32I-NEXT: lw a0, 4(a7)
+; RV32I-NEXT: andi a3, a1, 31
+; RV32I-NEXT: lw a4, 0(a7)
+; RV32I-NEXT: lw a6, 12(a7)
; RV32I-NEXT: slli t0, a5, 1
-; RV32I-NEXT: srl t1, a0, a4
-; RV32I-NEXT: sll t0, t0, a6
+; RV32I-NEXT: xori t1, a3, 31
+; RV32I-NEXT: srl a3, a0, a1
+; RV32I-NEXT: sll t0, t0, t1
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: lw t2, 16(a3)
-; RV32I-NEXT: srl a1, a1, a4
-; RV32I-NEXT: sll t3, a0, a6
-; RV32I-NEXT: or a0, t1, t0
-; RV32I-NEXT: or a1, a1, t3
-; RV32I-NEXT: lw t0, 20(a3)
-; RV32I-NEXT: lw t1, 24(a3)
-; RV32I-NEXT: lw t3, 28(a3)
-; RV32I-NEXT: slli a3, t2, 1
-; RV32I-NEXT: srl t4, a7, a4
-; RV32I-NEXT: sll a3, a3, a6
-; RV32I-NEXT: or a3, t4, a3
-; RV32I-NEXT: slli a7, a7, 1
-; RV32I-NEXT: srl a5, a5, a4
-; RV32I-NEXT: sll a7, a7, a6
-; RV32I-NEXT: or a5, a5, a7
-; RV32I-NEXT: slli a7, t1, 1
-; RV32I-NEXT: srl t4, t0, a4
-; RV32I-NEXT: sll a7, a7, a6
-; RV32I-NEXT: or a7, t4, a7
+; RV32I-NEXT: lw t2, 16(a7)
+; RV32I-NEXT: srl a4, a4, a1
+; RV32I-NEXT: sll t3, a0, t1
+; RV32I-NEXT: or a0, a3, t0
+; RV32I-NEXT: or a3, a4, t3
+; RV32I-NEXT: lw t0, 20(a7)
+; RV32I-NEXT: lw t3, 24(a7)
+; RV32I-NEXT: lw a7, 28(a7)
+; RV32I-NEXT: slli a4, t2, 1
+; RV32I-NEXT: srl t4, a6, a1
+; RV32I-NEXT: sll a4, a4, t1
+; RV32I-NEXT: or a4, t4, a4
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: srl a5, a5, a1
+; RV32I-NEXT: sll a6, a6, t1
+; RV32I-NEXT: or a5, a5, a6
+; RV32I-NEXT: slli a6, t3, 1
+; RV32I-NEXT: srl t4, t0, a1
+; RV32I-NEXT: sll a6, a6, t1
+; RV32I-NEXT: or a6, t4, a6
; RV32I-NEXT: slli t0, t0, 1
-; RV32I-NEXT: srl t2, t2, a4
-; RV32I-NEXT: sll t0, t0, a6
+; RV32I-NEXT: srl t2, t2, a1
+; RV32I-NEXT: sll t0, t0, t1
; RV32I-NEXT: or t0, t2, t0
-; RV32I-NEXT: slli t2, t3, 1
-; RV32I-NEXT: srl t1, t1, a4
-; RV32I-NEXT: sll a6, t2, a6
-; RV32I-NEXT: or a6, t1, a6
-; RV32I-NEXT: srl a4, t3, a4
-; RV32I-NEXT: srli t1, a4, 24
-; RV32I-NEXT: srli t2, a4, 16
-; RV32I-NEXT: srli t3, a4, 8
-; RV32I-NEXT: sb a4, 28(a2)
+; RV32I-NEXT: slli t2, a7, 1
+; RV32I-NEXT: srl t3, t3, a1
+; RV32I-NEXT: sll t1, t2, t1
+; RV32I-NEXT: or t1, t3, t1
+; RV32I-NEXT: srl a1, a7, a1
+; RV32I-NEXT: srli a7, a1, 24
+; RV32I-NEXT: srli t2, a1, 16
+; RV32I-NEXT: srli t3, a1, 8
+; RV32I-NEXT: sb a1, 28(a2)
; RV32I-NEXT: sb t3, 29(a2)
; RV32I-NEXT: sb t2, 30(a2)
-; RV32I-NEXT: sb t1, 31(a2)
-; RV32I-NEXT: srli a4, a6, 24
-; RV32I-NEXT: srli t1, a6, 16
-; RV32I-NEXT: srli t2, a6, 8
-; RV32I-NEXT: sb a6, 24(a2)
+; RV32I-NEXT: sb a7, 31(a2)
+; RV32I-NEXT: srli a1, t1, 24
+; RV32I-NEXT: srli a7, t1, 16
+; RV32I-NEXT: srli t2, t1, 8
+; RV32I-NEXT: sb t1, 24(a2)
; RV32I-NEXT: sb t2, 25(a2)
-; RV32I-NEXT: sb t1, 26(a2)
-; RV32I-NEXT: sb a4, 27(a2)
-; RV32I-NEXT: srli a4, t0, 24
-; RV32I-NEXT: srli a6, t0, 16
+; RV32I-NEXT: sb a7, 26(a2)
+; RV32I-NEXT: sb a1, 27(a2)
+; RV32I-NEXT: srli a1, t0, 24
+; RV32I-NEXT: srli a7, t0, 16
; RV32I-NEXT: srli t1, t0, 8
; RV32I-NEXT: sb t0, 16(a2)
; RV32I-NEXT: sb t1, 17(a2)
-; RV32I-NEXT: sb a6, 18(a2)
-; RV32I-NEXT: sb a4, 19(a2)
-; RV32I-NEXT: srli a4, a7, 24
-; RV32I-NEXT: srli a6, a7, 16
-; RV32I-NEXT: srli t0, a7, 8
-; RV32I-NEXT: sb a7, 20(a2)
+; RV32I-NEXT: sb a7, 18(a2)
+; RV32I-NEXT: sb a1, 19(a2)
+; RV32I-NEXT: srli a1, a6, 24
+; RV32I-NEXT: srli a7, a6, 16
+; RV32I-NEXT: srli t0, a6, 8
+; RV32I-NEXT: sb a6, 20(a2)
; RV32I-NEXT: sb t0, 21(a2)
-; RV32I-NEXT: sb a6, 22(a2)
-; RV32I-NEXT: sb a4, 23(a2)
-; RV32I-NEXT: srli a4, a5, 24
+; RV32I-NEXT: sb a7, 22(a2)
+; RV32I-NEXT: sb a1, 23(a2)
+; RV32I-NEXT: srli a1, a5, 24
; RV32I-NEXT: srli a6, a5, 16
; RV32I-NEXT: srli a7, a5, 8
; RV32I-NEXT: sb a5, 8(a2)
; RV32I-NEXT: sb a7, 9(a2)
; RV32I-NEXT: sb a6, 10(a2)
-; RV32I-NEXT: sb a4, 11(a2)
-; RV32I-NEXT: srli a4, a3, 24
-; RV32I-NEXT: srli a5, a3, 16
-; RV32I-NEXT: srli a6, a3, 8
-; RV32I-NEXT: sb a3, 12(a2)
+; RV32I-NEXT: sb a1, 11(a2)
+; RV32I-NEXT: srli a1, a4, 24
+; RV32I-NEXT: srli a5, a4, 16
+; RV32I-NEXT: srli a6, a4, 8
+; RV32I-NEXT: sb a4, 12(a2)
; RV32I-NEXT: sb a6, 13(a2)
; RV32I-NEXT: sb a5, 14(a2)
-; RV32I-NEXT: sb a4, 15(a2)
-; RV32I-NEXT: srli a3, a1, 24
-; RV32I-NEXT: srli a4, a1, 16
-; RV32I-NEXT: srli a5, a1, 8
-; RV32I-NEXT: sb a1, 0(a2)
+; RV32I-NEXT: sb a1, 15(a2)
+; RV32I-NEXT: srli a1, a3, 24
+; RV32I-NEXT: srli a4, a3, 16
+; RV32I-NEXT: srli a5, a3, 8
+; RV32I-NEXT: sb a3, 0(a2)
; RV32I-NEXT: sb a5, 1(a2)
; RV32I-NEXT: sb a4, 2(a2)
-; RV32I-NEXT: sb a3, 3(a2)
+; RV32I-NEXT: sb a1, 3(a2)
; RV32I-NEXT: srli a1, a0, 24
; RV32I-NEXT: srli a3, a0, 16
; RV32I-NEXT: srli a4, a0, 8
@@ -1728,192 +1671,171 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-LABEL: shl_32bytes:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: lbu a3, 1(a1)
-; RV64I-NEXT: lbu a4, 1(a0)
+; RV64I-NEXT: lbu a1, 0(a1)
+; RV64I-NEXT: lbu a3, 1(a0)
+; RV64I-NEXT: lbu a4, 0(a0)
; RV64I-NEXT: lbu a5, 2(a0)
; RV64I-NEXT: lbu a6, 3(a0)
-; RV64I-NEXT: lbu a7, 0(a0)
-; RV64I-NEXT: slli a4, a4, 8
-; RV64I-NEXT: lbu t0, 5(a0)
+; RV64I-NEXT: lbu a7, 5(a0)
+; RV64I-NEXT: slli a3, a3, 8
+; RV64I-NEXT: lbu t0, 4(a0)
; RV64I-NEXT: lbu t1, 6(a0)
-; RV64I-NEXT: lbu t2, 4(a0)
-; RV64I-NEXT: lbu t3, 7(a0)
+; RV64I-NEXT: lbu t2, 7(a0)
+; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: slli a5, a5, 16
+; RV64I-NEXT: slli a7, a7, 8
; RV64I-NEXT: slli a6, a6, 24
-; RV64I-NEXT: or a4, a4, a7
+; RV64I-NEXT: or a4, a7, t0
+; RV64I-NEXT: slli t1, t1, 16
+; RV64I-NEXT: slli t2, t2, 24
+; RV64I-NEXT: or a7, t2, t1
+; RV64I-NEXT: lbu t0, 9(a0)
; RV64I-NEXT: or a5, a6, a5
+; RV64I-NEXT: or a4, a7, a4
+; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: slli a4, a4, 32
+; RV64I-NEXT: lbu a5, 8(a0)
+; RV64I-NEXT: lbu a6, 10(a0)
+; RV64I-NEXT: lbu a7, 11(a0)
; RV64I-NEXT: slli t0, t0, 8
-; RV64I-NEXT: slli t1, t1, 16
-; RV64I-NEXT: slli t3, t3, 24
-; RV64I-NEXT: lbu a6, 9(a0)
-; RV64I-NEXT: or a7, t0, t2
-; RV64I-NEXT: or t0, t3, t1
+; RV64I-NEXT: lbu t1, 12(a0)
+; RV64I-NEXT: lbu t2, 13(a0)
+; RV64I-NEXT: lbu t3, 14(a0)
+; RV64I-NEXT: lbu t4, 15(a0)
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: or a4, t0, a5
+; RV64I-NEXT: slli a6, a6, 16
+; RV64I-NEXT: slli a7, a7, 24
+; RV64I-NEXT: or a5, a7, a6
+; RV64I-NEXT: slli t2, t2, 8
+; RV64I-NEXT: slli t3, t3, 16
+; RV64I-NEXT: slli t4, t4, 24
+; RV64I-NEXT: lbu a6, 16(a0)
+; RV64I-NEXT: lbu a7, 17(a0)
+; RV64I-NEXT: lbu t0, 18(a0)
+; RV64I-NEXT: lbu t5, 19(a0)
+; RV64I-NEXT: or t1, t2, t1
+; RV64I-NEXT: or t2, t4, t3
; RV64I-NEXT: or a4, a5, a4
-; RV64I-NEXT: or a5, t0, a7
-; RV64I-NEXT: lbu a7, 8(a0)
-; RV64I-NEXT: lbu t0, 10(a0)
-; RV64I-NEXT: lbu t1, 11(a0)
-; RV64I-NEXT: slli a6, a6, 8
-; RV64I-NEXT: lbu t2, 12(a0)
-; RV64I-NEXT: lbu t3, 13(a0)
-; RV64I-NEXT: lbu t4, 14(a0)
-; RV64I-NEXT: lbu t5, 15(a0)
+; RV64I-NEXT: or a5, t2, t1
; RV64I-NEXT: slli a5, a5, 32
-; RV64I-NEXT: or a6, a6, a7
+; RV64I-NEXT: slli a7, a7, 8
; RV64I-NEXT: slli t0, t0, 16
-; RV64I-NEXT: slli t1, t1, 24
-; RV64I-NEXT: or a7, t1, t0
-; RV64I-NEXT: slli t3, t3, 8
-; RV64I-NEXT: slli t4, t4, 16
; RV64I-NEXT: slli t5, t5, 24
-; RV64I-NEXT: or t0, t3, t2
-; RV64I-NEXT: or t1, t5, t4
+; RV64I-NEXT: lbu t1, 20(a0)
+; RV64I-NEXT: lbu t2, 21(a0)
+; RV64I-NEXT: lbu t3, 22(a0)
+; RV64I-NEXT: lbu t4, 23(a0)
; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: or a7, t1, t0
-; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: lbu t0, 17(a0)
+; RV64I-NEXT: or a7, t5, t0
; RV64I-NEXT: or a4, a5, a4
; RV64I-NEXT: or a5, a7, a6
-; RV64I-NEXT: lbu a6, 16(a0)
-; RV64I-NEXT: lbu a7, 18(a0)
-; RV64I-NEXT: lbu t1, 19(a0)
-; RV64I-NEXT: lbu t2, 21(a0)
-; RV64I-NEXT: slli t0, t0, 8
-; RV64I-NEXT: lbu t3, 20(a0)
-; RV64I-NEXT: lbu t4, 22(a0)
-; RV64I-NEXT: lbu t5, 23(a0)
-; RV64I-NEXT: or a6, t0, a6
-; RV64I-NEXT: slli a7, a7, 16
-; RV64I-NEXT: slli t1, t1, 24
; RV64I-NEXT: slli t2, t2, 8
-; RV64I-NEXT: or a7, t1, a7
-; RV64I-NEXT: or t0, t2, t3
-; RV64I-NEXT: slli t4, t4, 16
-; RV64I-NEXT: slli t5, t5, 24
-; RV64I-NEXT: or t1, t5, t4
-; RV64I-NEXT: lbu t2, 25(a0)
-; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: or a7, t1, t0
-; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: lbu t0, 24(a0)
-; RV64I-NEXT: lbu t1, 26(a0)
+; RV64I-NEXT: lbu a6, 25(a0)
+; RV64I-NEXT: slli t3, t3, 16
+; RV64I-NEXT: slli t4, t4, 24
+; RV64I-NEXT: or a7, t2, t1
+; RV64I-NEXT: or t0, t4, t3
+; RV64I-NEXT: lbu t1, 24(a0)
+; RV64I-NEXT: lbu t2, 26(a0)
; RV64I-NEXT: lbu t3, 27(a0)
-; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: slli t2, t2, 8
-; RV64I-NEXT: lbu a7, 28(a0)
-; RV64I-NEXT: lbu t4, 29(a0)
-; RV64I-NEXT: lbu t5, 30(a0)
+; RV64I-NEXT: slli a6, a6, 8
+; RV64I-NEXT: lbu t4, 28(a0)
+; RV64I-NEXT: lbu t5, 29(a0)
+; RV64I-NEXT: lbu t6, 30(a0)
; RV64I-NEXT: lbu a0, 31(a0)
-; RV64I-NEXT: slli t1, t1, 16
-; RV64I-NEXT: slli t3, t3, 24
-; RV64I-NEXT: or t0, t2, t0
-; RV64I-NEXT: or t1, t3, t1
-; RV64I-NEXT: or t0, t1, t0
-; RV64I-NEXT: slli t4, t4, 8
-; RV64I-NEXT: slli t5, t5, 16
-; RV64I-NEXT: slli a0, a0, 24
-; RV64I-NEXT: or a7, t4, a7
-; RV64I-NEXT: or a0, a0, t5
-; RV64I-NEXT: lbu t1, 0(a1)
-; RV64I-NEXT: lbu t2, 2(a1)
-; RV64I-NEXT: lbu t3, 3(a1)
-; RV64I-NEXT: slli a3, a3, 8
-; RV64I-NEXT: lbu t4, 4(a1)
-; RV64I-NEXT: lbu t5, 5(a1)
-; RV64I-NEXT: lbu t6, 6(a1)
-; RV64I-NEXT: lbu a1, 7(a1)
-; RV64I-NEXT: or a0, a0, a7
-; RV64I-NEXT: or a3, a3, t1
+; RV64I-NEXT: or a7, t0, a7
+; RV64I-NEXT: or a6, a6, t1
; RV64I-NEXT: slli t2, t2, 16
; RV64I-NEXT: slli t3, t3, 24
-; RV64I-NEXT: or a7, t3, t2
+; RV64I-NEXT: or t0, t3, t2
; RV64I-NEXT: slli t5, t5, 8
; RV64I-NEXT: slli t6, t6, 16
-; RV64I-NEXT: slli a1, a1, 24
+; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or t1, t5, t4
-; RV64I-NEXT: or a1, a1, t6
-; RV64I-NEXT: or a1, a1, t1
+; RV64I-NEXT: or a0, a0, t6
+; RV64I-NEXT: or a0, a0, t1
+; RV64I-NEXT: slli a7, a7, 32
+; RV64I-NEXT: or a6, t0, a6
; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: or a3, a7, a3
-; RV64I-NEXT: slli a1, a1, 32
-; RV64I-NEXT: or a0, a0, t0
-; RV64I-NEXT: or a3, a1, a3
-; RV64I-NEXT: srli a1, a3, 3
+; RV64I-NEXT: or a5, a7, a5
+; RV64I-NEXT: or a0, a0, a6
+; RV64I-NEXT: srli a6, a1, 3
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: sd zero, 8(sp)
; RV64I-NEXT: sd zero, 16(sp)
; RV64I-NEXT: sd zero, 24(sp)
-; RV64I-NEXT: andi a1, a1, 24
+; RV64I-NEXT: andi a6, a6, 24
; RV64I-NEXT: addi a7, sp, 32
-; RV64I-NEXT: sd a4, 32(sp)
-; RV64I-NEXT: sd a5, 40(sp)
-; RV64I-NEXT: sd a6, 48(sp)
+; RV64I-NEXT: sd a3, 32(sp)
+; RV64I-NEXT: sd a4, 40(sp)
+; RV64I-NEXT: sd a5, 48(sp)
; RV64I-NEXT: sd a0, 56(sp)
-; RV64I-NEXT: sub a0, a7, a1
+; RV64I-NEXT: sub a0, a7, a6
; RV64I-NEXT: ld a4, 0(a0)
; RV64I-NEXT: ld a5, 8(a0)
; RV64I-NEXT: ld a6, 16(a0)
-; RV64I-NEXT: andi a1, a3, 63
+; RV64I-NEXT: andi a3, a1, 63
; RV64I-NEXT: ld a7, 24(a0)
-; RV64I-NEXT: xori t0, a1, 63
; RV64I-NEXT: srli a0, a4, 1
-; RV64I-NEXT: sll a1, a5, a3
+; RV64I-NEXT: xori t0, a3, 63
+; RV64I-NEXT: sll a3, a5, a1
; RV64I-NEXT: srl a0, a0, t0
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: srli a1, a6, 1
-; RV64I-NEXT: sll a7, a7, a3
-; RV64I-NEXT: srl a1, a1, t0
-; RV64I-NEXT: or a1, a7, a1
+; RV64I-NEXT: or a0, a3, a0
+; RV64I-NEXT: srli a3, a6, 1
+; RV64I-NEXT: sll a7, a7, a1
+; RV64I-NEXT: srl a3, a3, t0
+; RV64I-NEXT: or a3, a7, a3
; RV64I-NEXT: srli a5, a5, 1
-; RV64I-NEXT: sll a6, a6, a3
+; RV64I-NEXT: sll a6, a6, a1
; RV64I-NEXT: srl a5, a5, t0
; RV64I-NEXT: or a5, a6, a5
-; RV64I-NEXT: sll a3, a4, a3
-; RV64I-NEXT: srli a4, a3, 56
-; RV64I-NEXT: srli a6, a3, 48
-; RV64I-NEXT: srli a7, a3, 40
-; RV64I-NEXT: srli t0, a3, 32
+; RV64I-NEXT: sll a1, a4, a1
+; RV64I-NEXT: srli a4, a1, 56
+; RV64I-NEXT: srli a6, a1, 48
+; RV64I-NEXT: srli a7, a1, 40
+; RV64I-NEXT: srli t0, a1, 32
; RV64I-NEXT: sb t0, 4(a2)
; RV64I-NEXT: sb a7, 5(a2)
; RV64I-NEXT: sb a6, 6(a2)
; RV64I-NEXT: sb a4, 7(a2)
-; RV64I-NEXT: srli a4, a3, 24
-; RV64I-NEXT: srli a6, a3, 16
-; RV64I-NEXT: srli a7, a3, 8
-; RV64I-NEXT: sb a3, 0(a2)
+; RV64I-NEXT: srli a4, a1, 24
+; RV64I-NEXT: srli a6, a1, 16
+; RV64I-NEXT: srli a7, a1, 8
+; RV64I-NEXT: sb a1, 0(a2)
; RV64I-NEXT: sb a7, 1(a2)
; RV64I-NEXT: sb a6, 2(a2)
; RV64I-NEXT: sb a4, 3(a2)
-; RV64I-NEXT: srli a3, a5, 56
+; RV64I-NEXT: srli a1, a5, 56
; RV64I-NEXT: srli a4, a5, 48
; RV64I-NEXT: srli a6, a5, 32
; RV64I-NEXT: srli a7, a5, 40
; RV64I-NEXT: sb a6, 20(a2)
; RV64I-NEXT: sb a7, 21(a2)
; RV64I-NEXT: sb a4, 22(a2)
-; RV64I-NEXT: sb a3, 23(a2)
-; RV64I-NEXT: srli a3, a5, 24
+; RV64I-NEXT: sb a1, 23(a2)
+; RV64I-NEXT: srli a1, a5, 24
; RV64I-NEXT: srli a4, a5, 16
; RV64I-NEXT: srli a6, a5, 8
; RV64I-NEXT: sb a5, 16(a2)
; RV64I-NEXT: sb a6, 17(a2)
; RV64I-NEXT: sb a4, 18(a2)
-; RV64I-NEXT: sb a3, 19(a2)
-; RV64I-NEXT: srli a3, a1, 56
-; RV64I-NEXT: srli a4, a1, 48
-; RV64I-NEXT: srli a5, a1, 40
-; RV64I-NEXT: srli a6, a1, 32
+; RV64I-NEXT: sb a1, 19(a2)
+; RV64I-NEXT: srli a1, a3, 56
+; RV64I-NEXT: srli a4, a3, 48
+; RV64I-NEXT: srli a5, a3, 40
+; RV64I-NEXT: srli a6, a3, 32
; RV64I-NEXT: sb a6, 28(a2)
; RV64I-NEXT: sb a5, 29(a2)
; RV64I-NEXT: sb a4, 30(a2)
-; RV64I-NEXT: sb a3, 31(a2)
-; RV64I-NEXT: srli a3, a1, 24
-; RV64I-NEXT: srli a4, a1, 16
-; RV64I-NEXT: srli a5, a1, 8
-; RV64I-NEXT: sb a1, 24(a2)
+; RV64I-NEXT: sb a1, 31(a2)
+; RV64I-NEXT: srli a1, a3, 24
+; RV64I-NEXT: srli a4, a3, 16
+; RV64I-NEXT: srli a5, a3, 8
+; RV64I-NEXT: sb a3, 24(a2)
; RV64I-NEXT: sb a5, 25(a2)
; RV64I-NEXT: sb a4, 26(a2)
-; RV64I-NEXT: sb a3, 27(a2)
+; RV64I-NEXT: sb a1, 27(a2)
; RV64I-NEXT: srli a1, a0, 56
; RV64I-NEXT: srli a3, a0, 48
; RV64I-NEXT: srli a4, a0, 32
@@ -1937,96 +1859,87 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw s0, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 72(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lbu a4, 0(a1)
+; RV32I-NEXT: lbu a1, 0(a1)
; RV32I-NEXT: lbu a3, 1(a0)
+; RV32I-NEXT: lbu a4, 0(a0)
; RV32I-NEXT: lbu a5, 2(a0)
; RV32I-NEXT: lbu a6, 3(a0)
-; RV32I-NEXT: lbu a7, 0(a0)
-; RV32I-NEXT: lbu t0, 5(a0)
; RV32I-NEXT: slli a3, a3, 8
+; RV32I-NEXT: lbu a7, 5(a0)
+; RV32I-NEXT: lbu t0, 6(a0)
+; RV32I-NEXT: lbu t1, 7(a0)
+; RV32I-NEXT: lbu t2, 4(a0)
+; RV32I-NEXT: or a3, a3, a4
; RV32I-NEXT: slli a5, a5, 16
; RV32I-NEXT: slli a6, a6, 24
-; RV32I-NEXT: lbu t1, 6(a0)
-; RV32I-NEXT: lbu t2, 4(a0)
-; RV32I-NEXT: lbu t3, 7(a0)
-; RV32I-NEXT: or a3, a3, a7
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a3, a5, a3
-; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
+; RV32I-NEXT: or a4, a6, a5
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: slli t1, t1, 24
+; RV32I-NEXT: lbu a5, 8(a0)
; RV32I-NEXT: lbu a6, 9(a0)
-; RV32I-NEXT: slli t3, t3, 24
-; RV32I-NEXT: lbu a7, 10(a0)
-; RV32I-NEXT: lbu t4, 8(a0)
-; RV32I-NEXT: lbu t5, 11(a0)
-; RV32I-NEXT: or a5, t0, t2
-; RV32I-NEXT: or t0, t3, t1
-; RV32I-NEXT: or a5, t0, a5
+; RV32I-NEXT: lbu t3, 10(a0)
+; RV32I-NEXT: lbu t4, 11(a0)
+; RV32I-NEXT: or a7, a7, t2
+; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: or a4, t0, a7
; RV32I-NEXT: slli a6, a6, 8
-; RV32I-NEXT: slli a7, a7, 16
-; RV32I-NEXT: lbu t0, 13(a0)
-; RV32I-NEXT: slli t5, t5, 24
+; RV32I-NEXT: lbu a7, 13(a0)
+; RV32I-NEXT: slli t3, t3, 16
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a6, t4, t3
+; RV32I-NEXT: lbu t0, 12(a0)
; RV32I-NEXT: lbu t1, 14(a0)
-; RV32I-NEXT: lbu t2, 12(a0)
-; RV32I-NEXT: lbu t3, 15(a0)
-; RV32I-NEXT: or a6, a6, t4
-; RV32I-NEXT: or a7, t5, a7
-; RV32I-NEXT: or a6, a7, a6
-; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
+; RV32I-NEXT: lbu t2, 15(a0)
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: lbu t3, 16(a0)
; RV32I-NEXT: lbu t4, 17(a0)
-; RV32I-NEXT: slli t3, t3, 24
; RV32I-NEXT: lbu t5, 18(a0)
-; RV32I-NEXT: lbu t6, 16(a0)
-; RV32I-NEXT: lbu s0, 19(a0)
-; RV32I-NEXT: or a7, t0, t2
-; RV32I-NEXT: or t0, t3, t1
-; RV32I-NEXT: or a7, t0, a7
+; RV32I-NEXT: lbu t6, 19(a0)
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: or a6, a7, t0
+; RV32I-NEXT: slli t1, t1, 16
+; RV32I-NEXT: slli t2, t2, 24
+; RV32I-NEXT: or a7, t2, t1
; RV32I-NEXT: slli t4, t4, 8
; RV32I-NEXT: slli t5, t5, 16
+; RV32I-NEXT: slli t6, t6, 24
+; RV32I-NEXT: lbu t0, 20(a0)
; RV32I-NEXT: lbu t1, 21(a0)
-; RV32I-NEXT: slli s0, s0, 24
; RV32I-NEXT: lbu t2, 22(a0)
-; RV32I-NEXT: lbu t3, 20(a0)
-; RV32I-NEXT: lbu s1, 23(a0)
-; RV32I-NEXT: or t0, t4, t6
-; RV32I-NEXT: or t4, s0, t5
-; RV32I-NEXT: or t0, t4, t0
+; RV32I-NEXT: lbu s0, 23(a0)
+; RV32I-NEXT: or t3, t4, t3
+; RV32I-NEXT: or t4, t6, t5
+; RV32I-NEXT: or a6, a7, a6
+; RV32I-NEXT: or a7, t4, t3
; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: lbu t3, 25(a0)
; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: lbu t4, 25(a0)
-; RV32I-NEXT: slli s1, s1, 24
-; RV32I-NEXT: lbu t5, 24(a0)
-; RV32I-NEXT: lbu t6, 26(a0)
-; RV32I-NEXT: lbu s0, 27(a0)
-; RV32I-NEXT: or t1, t1, t3
-; RV32I-NEXT: or t2, s1, t2
-; RV32I-NEXT: or t1, t2, t1
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: or t2, t4, t5
-; RV32I-NEXT: lbu t3, 29(a0)
-; RV32I-NEXT: slli t6, t6, 16
; RV32I-NEXT: slli s0, s0, 24
-; RV32I-NEXT: or t4, s0, t6
-; RV32I-NEXT: lbu t5, 28(a0)
-; RV32I-NEXT: lbu t6, 30(a0)
-; RV32I-NEXT: lbu a0, 31(a0)
+; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: or t1, s0, t2
+; RV32I-NEXT: lbu t2, 24(a0)
+; RV32I-NEXT: lbu t4, 26(a0)
+; RV32I-NEXT: lbu t5, 27(a0)
; RV32I-NEXT: slli t3, t3, 8
-; RV32I-NEXT: lbu s0, 1(a1)
-; RV32I-NEXT: lbu s1, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
-; RV32I-NEXT: or t2, t4, t2
-; RV32I-NEXT: or t3, t3, t5
-; RV32I-NEXT: slli t6, t6, 16
-; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or a0, a0, t6
+; RV32I-NEXT: lbu t6, 28(a0)
+; RV32I-NEXT: lbu s0, 29(a0)
+; RV32I-NEXT: lbu s1, 30(a0)
+; RV32I-NEXT: lbu a0, 31(a0)
+; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: or t1, t3, t2
+; RV32I-NEXT: slli t4, t4, 16
+; RV32I-NEXT: slli t5, t5, 24
+; RV32I-NEXT: or t2, t5, t4
; RV32I-NEXT: slli s0, s0, 8
; RV32I-NEXT: slli s1, s1, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a4, s0, a4
-; RV32I-NEXT: or a1, a1, s1
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: or t3, s0, t6
+; RV32I-NEXT: or a0, a0, s1
+; RV32I-NEXT: or t1, t2, t1
; RV32I-NEXT: or a0, a0, t3
-; RV32I-NEXT: or a4, a1, a4
; RV32I-NEXT: sw zero, 24(sp)
; RV32I-NEXT: sw zero, 28(sp)
; RV32I-NEXT: sw zero, 32(sp)
@@ -2035,106 +1948,106 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: sw zero, 12(sp)
; RV32I-NEXT: sw zero, 16(sp)
; RV32I-NEXT: sw zero, 20(sp)
-; RV32I-NEXT: srli a1, a4, 3
-; RV32I-NEXT: sw t0, 56(sp)
-; RV32I-NEXT: sw t1, 60(sp)
-; RV32I-NEXT: sw t2, 64(sp)
+; RV32I-NEXT: srli t2, a1, 3
+; RV32I-NEXT: sw a7, 56(sp)
+; RV32I-NEXT: sw t0, 60(sp)
+; RV32I-NEXT: sw t1, 64(sp)
; RV32I-NEXT: sw a0, 68(sp)
-; RV32I-NEXT: andi a1, a1, 28
-; RV32I-NEXT: addi a0, sp, 40
+; RV32I-NEXT: andi a0, t2, 28
+; RV32I-NEXT: addi a7, sp, 40
; RV32I-NEXT: sw a3, 40(sp)
-; RV32I-NEXT: sw a5, 44(sp)
-; RV32I-NEXT: sw a6, 48(sp)
-; RV32I-NEXT: sw a7, 52(sp)
-; RV32I-NEXT: sub a5, a0, a1
+; RV32I-NEXT: sw a4, 44(sp)
+; RV32I-NEXT: sw a5, 48(sp)
+; RV32I-NEXT: sw a6, 52(sp)
+; RV32I-NEXT: sub a5, a7, a0
; RV32I-NEXT: lw a6, 0(a5)
-; RV32I-NEXT: lw a3, 4(a5)
+; RV32I-NEXT: lw a4, 4(a5)
; RV32I-NEXT: lw a7, 8(a5)
-; RV32I-NEXT: andi a0, a4, 31
+; RV32I-NEXT: andi a0, a1, 31
; RV32I-NEXT: lw t0, 12(a5)
+; RV32I-NEXT: srli a3, a6, 1
; RV32I-NEXT: xori t1, a0, 31
-; RV32I-NEXT: srli a0, a6, 1
-; RV32I-NEXT: sll a1, a3, a4
-; RV32I-NEXT: srl a0, a0, t1
-; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: srli a1, a7, 1
-; RV32I-NEXT: sll t2, t0, a4
-; RV32I-NEXT: srl a1, a1, t1
-; RV32I-NEXT: or a1, t2, a1
+; RV32I-NEXT: sll a0, a4, a1
+; RV32I-NEXT: srl a3, a3, t1
+; RV32I-NEXT: or a0, a0, a3
+; RV32I-NEXT: srli a3, a7, 1
+; RV32I-NEXT: sll t2, t0, a1
+; RV32I-NEXT: srl a3, a3, t1
+; RV32I-NEXT: or a3, t2, a3
; RV32I-NEXT: lw t2, 16(a5)
-; RV32I-NEXT: srli a3, a3, 1
+; RV32I-NEXT: srli a4, a4, 1
; RV32I-NEXT: lw t3, 20(a5)
-; RV32I-NEXT: sll a7, a7, a4
-; RV32I-NEXT: srl a3, a3, t1
-; RV32I-NEXT: or a3, a7, a3
+; RV32I-NEXT: sll a7, a7, a1
+; RV32I-NEXT: srl a4, a4, t1
+; RV32I-NEXT: or a4, a7, a4
; RV32I-NEXT: lw a7, 24(a5)
; RV32I-NEXT: lw t4, 28(a5)
; RV32I-NEXT: srli a5, t2, 1
-; RV32I-NEXT: sll t5, t3, a4
+; RV32I-NEXT: sll t5, t3, a1
; RV32I-NEXT: srl a5, a5, t1
; RV32I-NEXT: or a5, t5, a5
; RV32I-NEXT: srli t0, t0, 1
-; RV32I-NEXT: sll t2, t2, a4
+; RV32I-NEXT: sll t2, t2, a1
; RV32I-NEXT: srl t0, t0, t1
; RV32I-NEXT: or t0, t2, t0
; RV32I-NEXT: srli t2, a7, 1
-; RV32I-NEXT: sll t4, t4, a4
+; RV32I-NEXT: sll t4, t4, a1
; RV32I-NEXT: srl t2, t2, t1
; RV32I-NEXT: or t2, t4, t2
; RV32I-NEXT: srli t3, t3, 1
-; RV32I-NEXT: sll a7, a7, a4
+; RV32I-NEXT: sll a7, a7, a1
; RV32I-NEXT: srl t1, t3, t1
; RV32I-NEXT: or a7, a7, t1
-; RV32I-NEXT: sll a4, a6, a4
-; RV32I-NEXT: srli a6, a4, 24
-; RV32I-NEXT: srli t1, a4, 16
-; RV32I-NEXT: srli t3, a4, 8
-; RV32I-NEXT: sb a4, 0(a2)
+; RV32I-NEXT: sll a1, a6, a1
+; RV32I-NEXT: srli a6, a1, 24
+; RV32I-NEXT: srli t1, a1, 16
+; RV32I-NEXT: srli t3, a1, 8
+; RV32I-NEXT: sb a1, 0(a2)
; RV32I-NEXT: sb t3, 1(a2)
; RV32I-NEXT: sb t1, 2(a2)
; RV32I-NEXT: sb a6, 3(a2)
-; RV32I-NEXT: srli a4, a7, 24
+; RV32I-NEXT: srli a1, a7, 24
; RV32I-NEXT: srli a6, a7, 16
; RV32I-NEXT: srli t1, a7, 8
; RV32I-NEXT: sb a7, 24(a2)
; RV32I-NEXT: sb t1, 25(a2)
; RV32I-NEXT: sb a6, 26(a2)
-; RV32I-NEXT: sb a4, 27(a2)
-; RV32I-NEXT: srli a4, t2, 24
+; RV32I-NEXT: sb a1, 27(a2)
+; RV32I-NEXT: srli a1, t2, 24
; RV32I-NEXT: srli a6, t2, 16
; RV32I-NEXT: srli a7, t2, 8
; RV32I-NEXT: sb t2, 28(a2)
; RV32I-NEXT: sb a7, 29(a2)
; RV32I-NEXT: sb a6, 30(a2)
-; RV32I-NEXT: sb a4, 31(a2)
-; RV32I-NEXT: srli a4, t0, 24
+; RV32I-NEXT: sb a1, 31(a2)
+; RV32I-NEXT: srli a1, t0, 24
; RV32I-NEXT: srli a6, t0, 16
; RV32I-NEXT: srli a7, t0, 8
; RV32I-NEXT: sb t0, 16(a2)
; RV32I-NEXT: sb a7, 17(a2)
; RV32I-NEXT: sb a6, 18(a2)
-; RV32I-NEXT: sb a4, 19(a2)
-; RV32I-NEXT: srli a4, a5, 24
+; RV32I-NEXT: sb a1, 19(a2)
+; RV32I-NEXT: srli a1, a5, 24
; RV32I-NEXT: srli a6, a5, 16
; RV32I-NEXT: srli a7, a5, 8
; RV32I-NEXT: sb a5, 20(a2)
; RV32I-NEXT: sb a7, 21(a2)
; RV32I-NEXT: sb a6, 22(a2)
-; RV32I-NEXT: sb a4, 23(a2)
-; RV32I-NEXT: srli a4, a3, 24
-; RV32I-NEXT: srli a5, a3, 16
-; RV32I-NEXT: srli a6, a3, 8
-; RV32I-NEXT: sb a3, 8(a2)
+; RV32I-NEXT: sb a1, 23(a2)
+; RV32I-NEXT: srli a1, a4, 24
+; RV32I-NEXT: srli a5, a4, 16
+; RV32I-NEXT: srli a6, a4, 8
+; RV32I-NEXT: sb a4, 8(a2)
; RV32I-NEXT: sb a6, 9(a2)
; RV32I-NEXT: sb a5, 10(a2)
-; RV32I-NEXT: sb a4, 11(a2)
-; RV32I-NEXT: srli a3, a1, 24
-; RV32I-NEXT: srli a4, a1, 16
-; RV32I-NEXT: srli a5, a1, 8
-; RV32I-NEXT: sb a1, 12(a2)
+; RV32I-NEXT: sb a1, 11(a2)
+; RV32I-NEXT: srli a1, a3, 24
+; RV32I-NEXT: srli a4, a3, 16
+; RV32I-NEXT: srli a5, a3, 8
+; RV32I-NEXT: sb a3, 12(a2)
; RV32I-NEXT: sb a5, 13(a2)
; RV32I-NEXT: sb a4, 14(a2)
-; RV32I-NEXT: sb a3, 15(a2)
+; RV32I-NEXT: sb a1, 15(a2)
; RV32I-NEXT: srli a1, a0, 24
; RV32I-NEXT: srli a3, a0, 16
; RV32I-NEXT: srli a4, a0, 8
@@ -2155,195 +2068,173 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-LABEL: ashr_32bytes:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -80
-; RV64I-NEXT: sd s0, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lbu a3, 0(a1)
-; RV64I-NEXT: lbu a4, 1(a0)
-; RV64I-NEXT: lbu a5, 0(a0)
-; RV64I-NEXT: lbu a6, 2(a0)
-; RV64I-NEXT: lbu a7, 3(a0)
-; RV64I-NEXT: lbu t0, 5(a0)
-; RV64I-NEXT: slli a4, a4, 8
-; RV64I-NEXT: lbu t1, 4(a0)
-; RV64I-NEXT: lbu t2, 6(a0)
-; RV64I-NEXT: lbu t3, 7(a0)
-; RV64I-NEXT: or a4, a4, a5
-; RV64I-NEXT: slli a6, a6, 16
-; RV64I-NEXT: slli t0, t0, 8
-; RV64I-NEXT: slli a7, a7, 24
-; RV64I-NEXT: or a5, t0, t1
-; RV64I-NEXT: slli t2, t2, 16
-; RV64I-NEXT: slli t3, t3, 24
-; RV64I-NEXT: or t0, t3, t2
-; RV64I-NEXT: lbu t1, 9(a0)
-; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: or a5, t0, a5
-; RV64I-NEXT: or a4, a6, a4
-; RV64I-NEXT: slli a5, a5, 32
-; RV64I-NEXT: lbu a6, 8(a0)
+; RV64I-NEXT: addi sp, sp, -64
+; RV64I-NEXT: lbu a1, 0(a1)
+; RV64I-NEXT: lbu a3, 1(a0)
+; RV64I-NEXT: lbu a4, 0(a0)
+; RV64I-NEXT: lbu a5, 2(a0)
+; RV64I-NEXT: lbu a6, 3(a0)
+; RV64I-NEXT: lbu a7, 5(a0)
+; RV64I-NEXT: lbu t0, 6(a0)
+; RV64I-NEXT: lbu t1, 7(a0)
+; RV64I-NEXT: lbu t2, 4(a0)
+; RV64I-NEXT: slli a3, a3, 8
+; RV64I-NEXT: or a3, a3, a4
+; RV64I-NEXT: slli a5, a5, 16
+; RV64I-NEXT: slli a6, a6, 24
+; RV64I-NEXT: slli a7, a7, 8
+; RV64I-NEXT: slli t0, t0, 16
+; RV64I-NEXT: slli t1, t1, 24
+; RV64I-NEXT: or a4, a7, t2
+; RV64I-NEXT: or a7, t1, t0
+; RV64I-NEXT: or a5, a6, a5
+; RV64I-NEXT: or a4, a7, a4
+; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: slli a4, a4, 32
+; RV64I-NEXT: lbu a5, 8(a0)
+; RV64I-NEXT: lbu a6, 9(a0)
; RV64I-NEXT: lbu a7, 10(a0)
; RV64I-NEXT: lbu t0, 11(a0)
-; RV64I-NEXT: slli t1, t1, 8
-; RV64I-NEXT: lbu t2, 12(a0)
-; RV64I-NEXT: lbu t3, 13(a0)
-; RV64I-NEXT: lbu t4, 14(a0)
-; RV64I-NEXT: lbu t5, 15(a0)
-; RV64I-NEXT: or a4, a5, a4
-; RV64I-NEXT: or a5, t1, a6
+; RV64I-NEXT: lbu t1, 12(a0)
+; RV64I-NEXT: lbu t2, 13(a0)
+; RV64I-NEXT: lbu t3, 14(a0)
+; RV64I-NEXT: lbu t4, 15(a0)
+; RV64I-NEXT: or a3, a4, a3
+; RV64I-NEXT: slli a6, a6, 8
+; RV64I-NEXT: or a4, a6, a5
; RV64I-NEXT: slli a7, a7, 16
; RV64I-NEXT: slli t0, t0, 24
-; RV64I-NEXT: or a6, t0, a7
-; RV64I-NEXT: slli t3, t3, 8
-; RV64I-NEXT: slli t4, t4, 16
-; RV64I-NEXT: slli t5, t5, 24
-; RV64I-NEXT: or a7, t3, t2
-; RV64I-NEXT: or t0, t5, t4
+; RV64I-NEXT: slli t2, t2, 8
+; RV64I-NEXT: slli t3, t3, 16
+; RV64I-NEXT: slli t4, t4, 24
+; RV64I-NEXT: or a5, t2, t1
+; RV64I-NEXT: or a6, t4, t3
; RV64I-NEXT: or a7, t0, a7
-; RV64I-NEXT: lbu t0, 17(a0)
; RV64I-NEXT: or a5, a6, a5
-; RV64I-NEXT: slli a7, a7, 32
+; RV64I-NEXT: or a4, a7, a4
+; RV64I-NEXT: slli a5, a5, 32
; RV64I-NEXT: lbu a6, 16(a0)
-; RV64I-NEXT: lbu t1, 18(a0)
-; RV64I-NEXT: lbu t2, 19(a0)
+; RV64I-NEXT: lbu a7, 17(a0)
+; RV64I-NEXT: lbu t0, 18(a0)
+; RV64I-NEXT: lbu t1, 19(a0)
+; RV64I-NEXT: lbu t2, 20(a0)
; RV64I-NEXT: lbu t3, 21(a0)
-; RV64I-NEXT: slli t0, t0, 8
-; RV64I-NEXT: lbu t4, 20(a0)
-; RV64I-NEXT: lbu t5, 22(a0)
-; RV64I-NEXT: lbu t6, 23(a0)
-; RV64I-NEXT: or a5, a7, a5
-; RV64I-NEXT: or a6, t0, a6
-; RV64I-NEXT: slli t1, t1, 16
-; RV64I-NEXT: slli t3, t3, 8
-; RV64I-NEXT: slli t2, t2, 24
-; RV64I-NEXT: or a7, t3, t4
-; RV64I-NEXT: slli t5, t5, 16
-; RV64I-NEXT: slli t6, t6, 24
-; RV64I-NEXT: or t0, t6, t5
-; RV64I-NEXT: lbu t3, 25(a0)
-; RV64I-NEXT: or t1, t2, t1
-; RV64I-NEXT: or a7, t0, a7
-; RV64I-NEXT: or a6, t1, a6
-; RV64I-NEXT: slli a7, a7, 32
-; RV64I-NEXT: lbu t0, 24(a0)
-; RV64I-NEXT: lbu t1, 26(a0)
-; RV64I-NEXT: lbu t2, 27(a0)
-; RV64I-NEXT: slli t3, t3, 8
-; RV64I-NEXT: lbu t4, 28(a0)
-; RV64I-NEXT: lbu t5, 29(a0)
-; RV64I-NEXT: lbu t6, 30(a0)
-; RV64I-NEXT: lbu s0, 31(a0)
-; RV64I-NEXT: or a0, a7, a6
-; RV64I-NEXT: or a6, t3, t0
-; RV64I-NEXT: slli t1, t1, 16
-; RV64I-NEXT: slli t2, t2, 24
-; RV64I-NEXT: or a7, t2, t1
-; RV64I-NEXT: slli t5, t5, 8
-; RV64I-NEXT: slli t6, t6, 16
-; RV64I-NEXT: slli s0, s0, 24
-; RV64I-NEXT: or t0, t5, t4
-; RV64I-NEXT: or t1, s0, t6
-; RV64I-NEXT: or a6, a7, a6
-; RV64I-NEXT: or a7, t1, t0
-; RV64I-NEXT: slli t0, a7, 32
-; RV64I-NEXT: lbu t1, 1(a1)
-; RV64I-NEXT: lbu t2, 4(a1)
-; RV64I-NEXT: lbu t3, 5(a1)
-; RV64I-NEXT: lbu t4, 6(a1)
-; RV64I-NEXT: lbu t5, 7(a1)
-; RV64I-NEXT: or a6, t0, a6
-; RV64I-NEXT: lbu t0, 2(a1)
-; RV64I-NEXT: lbu a1, 3(a1)
-; RV64I-NEXT: slli t1, t1, 8
-; RV64I-NEXT: or a3, t1, a3
+; RV64I-NEXT: lbu t4, 22(a0)
+; RV64I-NEXT: lbu t5, 23(a0)
+; RV64I-NEXT: or a4, a5, a4
+; RV64I-NEXT: slli a7, a7, 8
+; RV64I-NEXT: or a5, a7, a6
+; RV64I-NEXT: slli t0, t0, 16
+; RV64I-NEXT: slli t1, t1, 24
; RV64I-NEXT: slli t3, t3, 8
; RV64I-NEXT: slli t4, t4, 16
; RV64I-NEXT: slli t5, t5, 24
-; RV64I-NEXT: or t1, t3, t2
-; RV64I-NEXT: or t2, t5, t4
-; RV64I-NEXT: slli t0, t0, 16
-; RV64I-NEXT: slli a1, a1, 24
-; RV64I-NEXT: or a1, a1, t0
+; RV64I-NEXT: or a6, t3, t2
+; RV64I-NEXT: or a7, t5, t4
+; RV64I-NEXT: or t0, t1, t0
+; RV64I-NEXT: or a6, a7, a6
+; RV64I-NEXT: or a5, t0, a5
+; RV64I-NEXT: slli a6, a6, 32
+; RV64I-NEXT: lbu a7, 24(a0)
+; RV64I-NEXT: lbu t0, 25(a0)
+; RV64I-NEXT: lbu t1, 28(a0)
+; RV64I-NEXT: lbu t2, 29(a0)
+; RV64I-NEXT: lbu t3, 30(a0)
+; RV64I-NEXT: lbu t4, 31(a0)
+; RV64I-NEXT: or a5, a6, a5
+; RV64I-NEXT: lbu a6, 26(a0)
+; RV64I-NEXT: lbu a0, 27(a0)
+; RV64I-NEXT: slli t0, t0, 8
+; RV64I-NEXT: or a7, t0, a7
+; RV64I-NEXT: slli t2, t2, 8
+; RV64I-NEXT: slli t3, t3, 16
+; RV64I-NEXT: slli t4, t4, 24
; RV64I-NEXT: or t0, t2, t1
-; RV64I-NEXT: or a1, a1, a3
-; RV64I-NEXT: slli t0, t0, 32
-; RV64I-NEXT: or a3, t0, a1
-; RV64I-NEXT: sraiw a1, a7, 31
-; RV64I-NEXT: srli a7, a3, 3
-; RV64I-NEXT: sd a1, 32(sp)
-; RV64I-NEXT: sd a1, 40(sp)
-; RV64I-NEXT: sd a1, 48(sp)
-; RV64I-NEXT: sd a1, 56(sp)
-; RV64I-NEXT: andi a1, a7, 24
+; RV64I-NEXT: or t1, t4, t3
+; RV64I-NEXT: slli a6, a6, 16
+; RV64I-NEXT: slli a0, a0, 24
+; RV64I-NEXT: or a0, a0, a6
+; RV64I-NEXT: or a6, t1, t0
+; RV64I-NEXT: or a0, a0, a7
+; RV64I-NEXT: slli a7, a6, 32
+; RV64I-NEXT: or a0, a7, a0
+; RV64I-NEXT: sraiw a6, a6, 31
+; RV64I-NEXT: srli a7, a1, 3
+; RV64I-NEXT: sd a6, 32(sp)
+; RV64I-NEXT: sd a6, 40(sp)
+; RV64I-NEXT: sd a6, 48(sp)
+; RV64I-NEXT: sd a6, 56(sp)
+; RV64I-NEXT: andi a6, a7, 24
; RV64I-NEXT: mv a7, sp
-; RV64I-NEXT: sd a4, 0(sp)
-; RV64I-NEXT: sd a5, 8(sp)
-; RV64I-NEXT: sd a0, 16(sp)
-; RV64I-NEXT: sd a6, 24(sp)
-; RV64I-NEXT: add a1, a7, a1
-; RV64I-NEXT: ld a4, 16(a1)
-; RV64I-NEXT: ld a5, 8(a1)
-; RV64I-NEXT: andi a0, a3, 63
-; RV64I-NEXT: xori a6, a0, 63
-; RV64I-NEXT: ld a7, 0(a1)
-; RV64I-NEXT: ld t0, 24(a1)
-; RV64I-NEXT: slli a0, a4, 1
-; RV64I-NEXT: srl a1, a5, a3
-; RV64I-NEXT: sll a0, a0, a6
-; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: slli a5, a5, 1
-; RV64I-NEXT: srl a1, a7, a3
-; RV64I-NEXT: sll a5, a5, a6
-; RV64I-NEXT: or a1, a1, a5
-; RV64I-NEXT: slli a5, t0, 1
-; RV64I-NEXT: srl a4, a4, a3
-; RV64I-NEXT: sll a5, a5, a6
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: sd a4, 8(sp)
+; RV64I-NEXT: sd a5, 16(sp)
+; RV64I-NEXT: sd a0, 24(sp)
+; RV64I-NEXT: add a6, a7, a6
+; RV64I-NEXT: ld a4, 16(a6)
+; RV64I-NEXT: ld a3, 8(a6)
+; RV64I-NEXT: andi a0, a1, 63
+; RV64I-NEXT: ld a5, 0(a6)
+; RV64I-NEXT: ld a6, 24(a6)
+; RV64I-NEXT: slli a7, a4, 1
+; RV64I-NEXT: xori t0, a0, 63
+; RV64I-NEXT: srl a0, a3, a1
+; RV64I-NEXT: sll a7, a7, t0
+; RV64I-NEXT: or a0, a0, a7
+; RV64I-NEXT: slli a3, a3, 1
+; RV64I-NEXT: srl a5, a5, a1
+; RV64I-NEXT: sll a3, a3, t0
+; RV64I-NEXT: or a3, a5, a3
+; RV64I-NEXT: slli a5, a6, 1
+; RV64I-NEXT: srl a4, a4, a1
+; RV64I-NEXT: sll a5, a5, t0
; RV64I-NEXT: or a4, a4, a5
-; RV64I-NEXT: sra a3, t0, a3
-; RV64I-NEXT: srli a5, a3, 56
-; RV64I-NEXT: srli a6, a3, 48
-; RV64I-NEXT: srli a7, a3, 40
-; RV64I-NEXT: srli t0, a3, 32
+; RV64I-NEXT: sra a1, a6, a1
+; RV64I-NEXT: srli a5, a1, 56
+; RV64I-NEXT: srli a6, a1, 48
+; RV64I-NEXT: srli a7, a1, 40
+; RV64I-NEXT: srli t0, a1, 32
; RV64I-NEXT: sb t0, 28(a2)
; RV64I-NEXT: sb a7, 29(a2)
; RV64I-NEXT: sb a6, 30(a2)
; RV64I-NEXT: sb a5, 31(a2)
-; RV64I-NEXT: srli a5, a3, 24
-; RV64I-NEXT: srli a6, a3, 16
-; RV64I-NEXT: srli a7, a3, 8
-; RV64I-NEXT: sb a3, 24(a2)
+; RV64I-NEXT: srli a5, a1, 24
+; RV64I-NEXT: srli a6, a1, 16
+; RV64I-NEXT: srli a7, a1, 8
+; RV64I-NEXT: sb a1, 24(a2)
; RV64I-NEXT: sb a7, 25(a2)
; RV64I-NEXT: sb a6, 26(a2)
; RV64I-NEXT: sb a5, 27(a2)
-; RV64I-NEXT: srli a3, a4, 56
+; RV64I-NEXT: srli a1, a4, 56
; RV64I-NEXT: srli a5, a4, 48
; RV64I-NEXT: srli a6, a4, 32
; RV64I-NEXT: srli a7, a4, 40
; RV64I-NEXT: sb a6, 20(a2)
; RV64I-NEXT: sb a7, 21(a2)
; RV64I-NEXT: sb a5, 22(a2)
-; RV64I-NEXT: sb a3, 23(a2)
-; RV64I-NEXT: srli a3, a4, 24
+; RV64I-NEXT: sb a1, 23(a2)
+; RV64I-NEXT: srli a1, a4, 24
; RV64I-NEXT: srli a5, a4, 16
; RV64I-NEXT: srli a6, a4, 8
; RV64I-NEXT: sb a4, 16(a2)
; RV64I-NEXT: sb a6, 17(a2)
; RV64I-NEXT: sb a5, 18(a2)
-; RV64I-NEXT: sb a3, 19(a2)
-; RV64I-NEXT: srli a3, a1, 56
-; RV64I-NEXT: srli a4, a1, 48
-; RV64I-NEXT: srli a5, a1, 40
-; RV64I-NEXT: srli a6, a1, 32
+; RV64I-NEXT: sb a1, 19(a2)
+; RV64I-NEXT: srli a1, a3, 56
+; RV64I-NEXT: srli a4, a3, 48
+; RV64I-NEXT: srli a5, a3, 40
+; RV64I-NEXT: srli a6, a3, 32
; RV64I-NEXT: sb a6, 4(a2)
; RV64I-NEXT: sb a5, 5(a2)
; RV64I-NEXT: sb a4, 6(a2)
-; RV64I-NEXT: sb a3, 7(a2)
-; RV64I-NEXT: srli a3, a1, 24
-; RV64I-NEXT: srli a4, a1, 16
-; RV64I-NEXT: srli a5, a1, 8
-; RV64I-NEXT: sb a1, 0(a2)
+; RV64I-NEXT: sb a1, 7(a2)
+; RV64I-NEXT: srli a1, a3, 24
+; RV64I-NEXT: srli a4, a3, 16
+; RV64I-NEXT: srli a5, a3, 8
+; RV64I-NEXT: sb a3, 0(a2)
; RV64I-NEXT: sb a5, 1(a2)
; RV64I-NEXT: sb a4, 2(a2)
-; RV64I-NEXT: sb a3, 3(a2)
+; RV64I-NEXT: sb a1, 3(a2)
; RV64I-NEXT: srli a1, a0, 56
; RV64I-NEXT: srli a3, a0, 48
; RV64I-NEXT: srli a4, a0, 32
@@ -2359,104 +2250,94 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: sb a4, 9(a2)
; RV64I-NEXT: sb a3, 10(a2)
; RV64I-NEXT: sb a1, 11(a2)
-; RV64I-NEXT: ld s0, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 80
+; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret
;
; RV32I-LABEL: ashr_32bytes:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw s0, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lbu a4, 0(a1)
+; RV32I-NEXT: lbu a1, 0(a1)
; RV32I-NEXT: lbu a3, 1(a0)
-; RV32I-NEXT: lbu a5, 2(a0)
-; RV32I-NEXT: lbu a6, 3(a0)
-; RV32I-NEXT: lbu a7, 0(a0)
+; RV32I-NEXT: lbu a4, 2(a0)
+; RV32I-NEXT: lbu a5, 3(a0)
+; RV32I-NEXT: lbu a6, 0(a0)
+; RV32I-NEXT: lbu a7, 5(a0)
; RV32I-NEXT: slli a3, a3, 8
-; RV32I-NEXT: slli a5, a5, 16
-; RV32I-NEXT: slli a6, a6, 24
-; RV32I-NEXT: lbu t0, 4(a0)
-; RV32I-NEXT: lbu t1, 5(a0)
-; RV32I-NEXT: lbu t2, 6(a0)
-; RV32I-NEXT: lbu t3, 7(a0)
-; RV32I-NEXT: or a3, a3, a7
-; RV32I-NEXT: or a5, a6, a5
-; RV32I-NEXT: or a3, a5, a3
-; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: slli a4, a4, 16
+; RV32I-NEXT: slli a5, a5, 24
+; RV32I-NEXT: lbu t0, 6(a0)
+; RV32I-NEXT: lbu t1, 4(a0)
+; RV32I-NEXT: lbu t2, 7(a0)
+; RV32I-NEXT: or a3, a3, a6
+; RV32I-NEXT: or a4, a5, a4
+; RV32I-NEXT: or a3, a4, a3
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t0, t0, 16
; RV32I-NEXT: lbu a5, 9(a0)
-; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: slli t3, t3, 24
-; RV32I-NEXT: or a6, t1, t0
-; RV32I-NEXT: or a7, t3, t2
-; RV32I-NEXT: lbu t0, 8(a0)
-; RV32I-NEXT: lbu t1, 10(a0)
-; RV32I-NEXT: lbu t2, 11(a0)
-; RV32I-NEXT: slli t3, a5, 8
-; RV32I-NEXT: lbu t4, 12(a0)
-; RV32I-NEXT: lbu t5, 13(a0)
-; RV32I-NEXT: lbu t6, 14(a0)
-; RV32I-NEXT: lbu s0, 15(a0)
-; RV32I-NEXT: or a5, a7, a6
-; RV32I-NEXT: or a6, t3, t0
-; RV32I-NEXT: slli t1, t1, 16
; RV32I-NEXT: slli t2, t2, 24
-; RV32I-NEXT: or a7, t2, t1
-; RV32I-NEXT: slli t5, t5, 8
-; RV32I-NEXT: slli t6, t6, 16
-; RV32I-NEXT: slli s0, s0, 24
-; RV32I-NEXT: lbu t0, 17(a0)
-; RV32I-NEXT: lbu t1, 18(a0)
-; RV32I-NEXT: lbu t2, 16(a0)
-; RV32I-NEXT: lbu t3, 19(a0)
-; RV32I-NEXT: or t4, t5, t4
-; RV32I-NEXT: or t5, s0, t6
+; RV32I-NEXT: lbu a6, 10(a0)
+; RV32I-NEXT: lbu t3, 8(a0)
+; RV32I-NEXT: lbu t4, 11(a0)
+; RV32I-NEXT: or a4, a7, t1
+; RV32I-NEXT: or a7, t2, t0
+; RV32I-NEXT: or a4, a7, a4
+; RV32I-NEXT: slli a5, a5, 8
+; RV32I-NEXT: slli a6, a6, 16
+; RV32I-NEXT: lbu a7, 13(a0)
+; RV32I-NEXT: slli t4, t4, 24
+; RV32I-NEXT: lbu t0, 14(a0)
+; RV32I-NEXT: lbu t1, 12(a0)
+; RV32I-NEXT: lbu t2, 15(a0)
+; RV32I-NEXT: or a5, a5, t3
+; RV32I-NEXT: or a6, t4, a6
+; RV32I-NEXT: or a5, a6, a5
+; RV32I-NEXT: slli a7, a7, 8
+; RV32I-NEXT: slli t0, t0, 16
+; RV32I-NEXT: lbu t3, 17(a0)
+; RV32I-NEXT: slli t2, t2, 24
+; RV32I-NEXT: lbu t4, 18(a0)
+; RV32I-NEXT: lbu t5, 16(a0)
+; RV32I-NEXT: lbu t6, 19(a0)
+; RV32I-NEXT: or a6, a7, t1
+; RV32I-NEXT: or a7, t2, t0
; RV32I-NEXT: or a6, a7, a6
-; RV32I-NEXT: or a7, t5, t4
-; RV32I-NEXT: slli t0, t0, 8
-; RV32I-NEXT: slli t1, t1, 16
-; RV32I-NEXT: slli t3, t3, 24
-; RV32I-NEXT: lbu t4, 21(a0)
-; RV32I-NEXT: or t0, t0, t2
-; RV32I-NEXT: or t1, t3, t1
-; RV32I-NEXT: or t0, t1, t0
+; RV32I-NEXT: slli t3, t3, 8
+; RV32I-NEXT: slli t4, t4, 16
+; RV32I-NEXT: lbu t0, 21(a0)
+; RV32I-NEXT: slli t6, t6, 24
; RV32I-NEXT: lbu t1, 20(a0)
; RV32I-NEXT: lbu t2, 22(a0)
-; RV32I-NEXT: lbu t3, 23(a0)
-; RV32I-NEXT: slli t4, t4, 8
-; RV32I-NEXT: lbu t5, 25(a0)
-; RV32I-NEXT: lbu t6, 24(a0)
-; RV32I-NEXT: lbu s0, 26(a0)
-; RV32I-NEXT: or t1, t4, t1
-; RV32I-NEXT: lbu t4, 27(a0)
+; RV32I-NEXT: lbu s0, 23(a0)
+; RV32I-NEXT: or a7, t3, t5
+; RV32I-NEXT: or t3, t6, t4
+; RV32I-NEXT: or a7, t3, a7
+; RV32I-NEXT: slli t0, t0, 8
+; RV32I-NEXT: or t0, t0, t1
+; RV32I-NEXT: lbu t1, 25(a0)
; RV32I-NEXT: slli t2, t2, 16
-; RV32I-NEXT: slli t3, t3, 24
-; RV32I-NEXT: or t2, t3, t2
-; RV32I-NEXT: slli t5, t5, 8
-; RV32I-NEXT: or t3, t5, t6
-; RV32I-NEXT: slli s0, s0, 16
-; RV32I-NEXT: slli t4, t4, 24
-; RV32I-NEXT: lbu t5, 29(a0)
-; RV32I-NEXT: or t4, t4, s0
-; RV32I-NEXT: lbu t6, 28(a0)
+; RV32I-NEXT: slli s0, s0, 24
+; RV32I-NEXT: or t2, s0, t2
+; RV32I-NEXT: lbu t3, 24(a0)
+; RV32I-NEXT: lbu t4, 26(a0)
+; RV32I-NEXT: lbu t5, 27(a0)
+; RV32I-NEXT: or t0, t2, t0
+; RV32I-NEXT: slli t1, t1, 8
+; RV32I-NEXT: lbu t2, 28(a0)
+; RV32I-NEXT: lbu t6, 29(a0)
; RV32I-NEXT: lbu s0, 30(a0)
; RV32I-NEXT: lbu a0, 31(a0)
-; RV32I-NEXT: or t1, t2, t1
-; RV32I-NEXT: or t2, t4, t3
-; RV32I-NEXT: slli t5, t5, 8
-; RV32I-NEXT: lbu t3, 1(a1)
-; RV32I-NEXT: lbu t4, 2(a1)
-; RV32I-NEXT: lbu a1, 3(a1)
+; RV32I-NEXT: slli t4, t4, 16
+; RV32I-NEXT: slli t5, t5, 24
+; RV32I-NEXT: or t1, t1, t3
+; RV32I-NEXT: or t3, t5, t4
+; RV32I-NEXT: or t1, t3, t1
+; RV32I-NEXT: slli t6, t6, 8
; RV32I-NEXT: slli s0, s0, 16
; RV32I-NEXT: slli a0, a0, 24
-; RV32I-NEXT: or t5, t5, t6
+; RV32I-NEXT: or t2, t6, t2
; RV32I-NEXT: or s0, a0, s0
-; RV32I-NEXT: or t5, s0, t5
-; RV32I-NEXT: slli t3, t3, 8
-; RV32I-NEXT: slli t4, t4, 16
-; RV32I-NEXT: slli a1, a1, 24
-; RV32I-NEXT: or a4, t3, a4
-; RV32I-NEXT: or a1, a1, t4
-; RV32I-NEXT: or a4, a1, a4
+; RV32I-NEXT: or t2, s0, t2
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: sw a0, 56(sp)
; RV32I-NEXT: sw a0, 60(sp)
@@ -2466,106 +2347,106 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV32I-NEXT: sw a0, 44(sp)
; RV32I-NEXT: sw a0, 48(sp)
; RV32I-NEXT: sw a0, 52(sp)
-; RV32I-NEXT: srli a0, a4, 3
-; RV32I-NEXT: sw t0, 24(sp)
-; RV32I-NEXT: sw t1, 28(sp)
-; RV32I-NEXT: sw t2, 32(sp)
-; RV32I-NEXT: sw t5, 36(sp)
+; RV32I-NEXT: srli a0, a1, 3
+; RV32I-NEXT: sw a7, 24(sp)
+; RV32I-NEXT: sw t0, 28(sp)
+; RV32I-NEXT: sw t1, 32(sp)
+; RV32I-NEXT: sw t2, 36(sp)
; RV32I-NEXT: andi a0, a0, 28
-; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: addi a7, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
-; RV32I-NEXT: sw a5, 12(sp)
-; RV32I-NEXT: sw a6, 16(sp)
-; RV32I-NEXT: sw a7, 20(sp)
-; RV32I-NEXT: add a3, a1, a0
-; RV32I-NEXT: lw a5, 8(a3)
-; RV32I-NEXT: lw a0, 4(a3)
-; RV32I-NEXT: andi a1, a4, 31
-; RV32I-NEXT: xori a6, a1, 31
-; RV32I-NEXT: lw a1, 0(a3)
-; RV32I-NEXT: lw a7, 12(a3)
+; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: sw a5, 16(sp)
+; RV32I-NEXT: sw a6, 20(sp)
+; RV32I-NEXT: add a7, a7, a0
+; RV32I-NEXT: lw a5, 8(a7)
+; RV32I-NEXT: lw a0, 4(a7)
+; RV32I-NEXT: andi a3, a1, 31
+; RV32I-NEXT: lw a4, 0(a7)
+; RV32I-NEXT: lw a6, 12(a7)
; RV32I-NEXT: slli t0, a5, 1
-; RV32I-NEXT: srl t1, a0, a4
-; RV32I-NEXT: sll t0, t0, a6
+; RV32I-NEXT: xori t1, a3, 31
+; RV32I-NEXT: srl a3, a0, a1
+; RV32I-NEXT: sll t0, t0, t1
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: lw t2, 16(a3)
-; RV32I-NEXT: srl a1, a1, a4
-; RV32I-NEXT: sll t3, a0, a6
-; RV32I-NEXT: or a0, t1, t0
-; RV32I-NEXT: or a1, a1, t3
-; RV32I-NEXT: lw t0, 20(a3)
-; RV32I-NEXT: lw t1, 24(a3)
-; RV32I-NEXT: lw t3, 28(a3)
-; RV32I-NEXT: slli a3, t2, 1
-; RV32I-NEXT: srl t4, a7, a4
-; RV32I-NEXT: sll a3, a3, a6
-; RV32I-NEXT: or a3, t4, a3
-; RV32I-NEXT: slli a7, a7, 1
-; RV32I-NEXT: srl a5, a5, a4
-; RV32I-NEXT: sll a7, a7, a6
-; RV32I-NEXT: or a5, a5, a7
-; RV32I-NEXT: slli a7, t1, 1
-; RV32I-NEXT: srl t4, t0, a4
-; RV32I-NEXT: sll a7, a7, a6
-; RV32I-NEXT: or a7, t4, a7
+; RV32I-NEXT: lw t2, 16(a7)
+; RV32I-NEXT: srl a4, a4, a1
+; RV32I-NEXT: sll t3, a0, t1
+; RV32I-NEXT: or a0, a3, t0
+; RV32I-NEXT: or a3, a4, t3
+; RV32I-NEXT: lw t0, 20(a7)
+; RV32I-NEXT: lw t3, 24(a7)
+; RV32I-NEXT: lw a7, 28(a7)
+; RV32I-NEXT: slli a4, t2, 1
+; RV32I-NEXT: srl t4, a6, a1
+; RV32I-NEXT: sll a4, a4, t1
+; RV32I-NEXT: or a4, t4, a4
+; RV32I-NEXT: slli a6, a6, 1
+; RV32I-NEXT: srl a5, a5, a1
+; RV32I-NEXT: sll a6, a6, t1
+; RV32I-NEXT: or a5, a5, a6
+; RV32I-NEXT: slli a6, t3, 1
+; RV32I-NEXT: srl t4, t0, a1
+; RV32I-NEXT: sll a6, a6, t1
+; RV32I-NEXT: or a6, t4, a6
; RV32I-NEXT: slli t0, t0, 1
-; RV32I-NEXT: srl t2, t2, a4
-; RV32I-NEXT: sll t0, t0, a6
+; RV32I-NEXT: srl t2, t2, a1
+; RV32I-NEXT: sll t0, t0, t1
; RV32I-NEXT: or t0, t2, t0
-; RV32I-NEXT: slli t2, t3, 1
-; RV32I-NEXT: srl t1, t1, a4
-; RV32I-NEXT: sll a6, t2, a6
-; RV32I-NEXT: or a6, t1, a6
-; RV32I-NEXT: sra a4, t3, a4
-; RV32I-NEXT: srli t1, a4, 24
-; RV32I-NEXT: srli t2, a4, 16
-; RV32I-NEXT: srli t3, a4, 8
-; RV32I-NEXT: sb a4, 28(a2)
+; RV32I-NEXT: slli t2, a7, 1
+; RV32I-NEXT: srl t3, t3, a1
+; RV32I-NEXT: sll t1, t2, t1
+; RV32I-NEXT: or t1, t3, t1
+; RV32I-NEXT: sra a1, a7, a1
+; RV32I-NEXT: srli a7, a1, 24
+; RV32I-NEXT: srli t2, a1, 16
+; RV32I-NEXT: srli t3, a1, 8
+; RV32I-NEXT: sb a1, 28(a2)
; RV32I-NEXT: sb t3, 29(a2)
; RV32I-NEXT: sb t2, 30(a2)
-; RV32I-NEXT: sb t1, 31(a2)
-; RV32I-NEXT: srli a4, a6, 24
-; RV32I-NEXT: srli t1, a6, 16
-; RV32I-NEXT: srli t2, a6, 8
-; RV32I-NEXT: sb a6, 24(a2)
+; RV32I-NEXT: sb a7, 31(a2)
+; RV32I-NEXT: srli a1, t1, 24
+; RV32I-NEXT: srli a7, t1, 16
+; RV32I-NEXT: srli t2, t1, 8
+; RV32I-NEXT: sb t1, 24(a2)
; RV32I-NEXT: sb t2, 25(a2)
-; RV32I-NEXT: sb t1, 26(a2)
-; RV32I-NEXT: sb a4, 27(a2)
-; RV32I-NEXT: srli a4, t0, 24
-; RV32I-NEXT: srli a6, t0, 16
+; RV32I-NEXT: sb a7, 26(a2)
+; RV32I-NEXT: sb a1, 27(a2)
+; RV32I-NEXT: srli a1, t0, 24
+; RV32I-NEXT: srli a7, t0, 16
; RV32I-NEXT: srli t1, t0, 8
; RV32I-NEXT: sb t0, 16(a2)
; RV32I-NEXT: sb t1, 17(a2)
-; RV32I-NEXT: sb a6, 18(a2)
-; RV32I-NEXT: sb a4, 19(a2)
-; RV32I-NEXT: srli a4, a7, 24
-; RV32I-NEXT: srli a6, a7, 16
-; RV32I-NEXT: srli t0, a7, 8
-; RV32I-NEXT: sb a7, 20(a2)
+; RV32I-NEXT: sb a7, 18(a2)
+; RV32I-NEXT: sb a1, 19(a2)
+; RV32I-NEXT: srli a1, a6, 24
+; RV32I-NEXT: srli a7, a6, 16
+; RV32I-NEXT: srli t0, a6, 8
+; RV32I-NEXT: sb a6, 20(a2)
; RV32I-NEXT: sb t0, 21(a2)
-; RV32I-NEXT: sb a6, 22(a2)
-; RV32I-NEXT: sb a4, 23(a2)
-; RV32I-NEXT: srli a4, a5, 24
+; RV32I-NEXT: sb a7, 22(a2)
+; RV32I-NEXT: sb a1, 23(a2)
+; RV32I-NEXT: srli a1, a5, 24
; RV32I-NEXT: srli a6, a5, 16
; RV32I-NEXT: srli a7, a5, 8
; RV32I-NEXT: sb a5, 8(a2)
; RV32I-NEXT: sb a7, 9(a2)
; RV32I-NEXT: sb a6, 10(a2)
-; RV32I-NEXT: sb a4, 11(a2)
-; RV32I-NEXT: srli a4, a3, 24
-; RV32I-NEXT: srli a5, a3, 16
-; RV32I-NEXT: srli a6, a3, 8
-; RV32I-NEXT: sb a3, 12(a2)
+; RV32I-NEXT: sb a1, 11(a2)
+; RV32I-NEXT: srli a1, a4, 24
+; RV32I-NEXT: srli a5, a4, 16
+; RV32I-NEXT: srli a6, a4, 8
+; RV32I-NEXT: sb a4, 12(a2)
; RV32I-NEXT: sb a6, 13(a2)
; RV32I-NEXT: sb a5, 14(a2)
-; RV32I-NEXT: sb a4, 15(a2)
-; RV32I-NEXT: srli a3, a1, 24
-; RV32I-NEXT: srli a4, a1, 16
-; RV32I-NEXT: srli a5, a1, 8
-; RV32I-NEXT: sb a1, 0(a2)
+; RV32I-NEXT: sb a1, 15(a2)
+; RV32I-NEXT: srli a1, a3, 24
+; RV32I-NEXT: srli a4, a3, 16
+; RV32I-NEXT: srli a5, a3, 8
+; RV32I-NEXT: sb a3, 0(a2)
; RV32I-NEXT: sb a5, 1(a2)
; RV32I-NEXT: sb a4, 2(a2)
-; RV32I-NEXT: sb a3, 3(a2)
+; RV32I-NEXT: sb a1, 3(a2)
; RV32I-NEXT: srli a1, a0, 24
; RV32I-NEXT: srli a3, a0, 16
; RV32I-NEXT: srli a4, a0, 8
diff --git a/llvm/test/CodeGen/SystemZ/pr60413.ll b/llvm/test/CodeGen/SystemZ/pr60413.ll
index 8a6a30318ae58..bbf4d50bd716d 100644
--- a/llvm/test/CodeGen/SystemZ/pr60413.ll
+++ b/llvm/test/CodeGen/SystemZ/pr60413.ll
@@ -16,31 +16,31 @@ define dso_local void @m() local_unnamed_addr #1 {
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: aghi %r15, -168
; CHECK-NEXT: lhrl %r1, f+4
-; CHECK-NEXT: sll %r1, 8
; CHECK-NEXT: larl %r2, f
-; CHECK-NEXT: ic %r1, 6(%r2)
-; CHECK-NEXT: larl %r2, e
-; CHECK-NEXT: lb %r0, 3(%r2)
-; CHECK-NEXT: vlvgp %v0, %r0, %r1
-; CHECK-NEXT: vlvgp %v1, %r1, %r0
-; CHECK-NEXT: vlvgf %v1, %r1, 0
-; CHECK-NEXT: vlvgf %v1, %r1, 2
-; CHECK-NEXT: vlvgp %v2, %r1, %r1
-; CHECK-NEXT: # kill: def $r1l killed $r1l killed $r1d
+; CHECK-NEXT: llc %r2, 6(%r2)
+; CHECK-NEXT: larl %r3, e
+; CHECK-NEXT: lb %r0, 3(%r3)
+; CHECK-NEXT: rosbg %r2, %r1, 32, 55, 8
+; CHECK-NEXT: vlvgp %v0, %r2, %r0
+; CHECK-NEXT: vlvgf %v0, %r2, 0
+; CHECK-NEXT: vlvgf %v0, %r2, 2
+; CHECK-NEXT: vlvgp %v1, %r0, %r2
+; CHECK-NEXT: vlvgp %v2, %r2, %r2
+; CHECK-NEXT: lr %r1, %r2
; CHECK-NEXT: nilh %r1, 255
; CHECK-NEXT: chi %r1, 128
; CHECK-NEXT: ipm %r1
; CHECK-NEXT: risbg %r1, %r1, 63, 191, 36
-; CHECK-NEXT: vlvgf %v0, %r0, 0
-; CHECK-NEXT: vlvgf %v0, %r0, 2
; CHECK-NEXT: vgbm %v3, 30583
; CHECK-NEXT: vn %v0, %v0, %v3
+; CHECK-NEXT: vlvgf %v1, %r0, 0
+; CHECK-NEXT: vlvgf %v1, %r0, 2
; CHECK-NEXT: vn %v1, %v1, %v3
; CHECK-NEXT: vrepf %v2, %v2, 1
; CHECK-NEXT: vn %v2, %v2, %v3
; CHECK-NEXT: vrepif %v3, 127
-; CHECK-NEXT: vchlf %v1, %v1, %v3
-; CHECK-NEXT: vlgvf %r13, %v1, 0
+; CHECK-NEXT: vchlf %v0, %v0, %v3
+; CHECK-NEXT: vlgvf %r13, %v0, 0
; CHECK-NEXT: vchlf %v2, %v2, %v3
; CHECK-NEXT: vlgvf %r3, %v2, 1
; CHECK-NEXT: nilf %r3, 1
@@ -54,13 +54,13 @@ define dso_local void @m() local_unnamed_addr #1 {
; CHECK-NEXT: nilf %r14, 1
; CHECK-NEXT: rosbg %r2, %r14, 32, 51, 12
; CHECK-NEXT: rosbg %r2, %r13, 52, 52, 11
-; CHECK-NEXT: vlgvf %r13, %v1, 1
+; CHECK-NEXT: vlgvf %r13, %v0, 1
; CHECK-NEXT: rosbg %r2, %r13, 53, 53, 10
-; CHECK-NEXT: vlgvf %r13, %v1, 2
+; CHECK-NEXT: vlgvf %r13, %v0, 2
; CHECK-NEXT: rosbg %r2, %r13, 54, 54, 9
-; CHECK-NEXT: vlgvf %r13, %v1, 3
+; CHECK-NEXT: vlgvf %r13, %v0, 3
; CHECK-NEXT: rosbg %r2, %r13, 55, 55, 8
-; CHECK-NEXT: vchlf %v0, %v0, %v3
+; CHECK-NEXT: vchlf %v0, %v1, %v3
; CHECK-NEXT: vlgvf %r13, %v0, 0
; CHECK-NEXT: rosbg %r2, %r13, 56, 56, 7
; CHECK-NEXT: vlgvf %r13, %v0, 1
diff --git a/llvm/test/CodeGen/Thumb2/mve-clmul.ll b/llvm/test/CodeGen/Thumb2/mve-clmul.ll
index aacba93e117ea..29d87fbc506f5 100644
--- a/llvm/test/CodeGen/Thumb2/mve-clmul.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-clmul.ll
@@ -5367,9 +5367,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q0, q2, q0
; CHECK-NEXT: lsll r4, r5, #2
@@ -5390,9 +5390,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #3
@@ -5413,9 +5413,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #4
@@ -5436,9 +5436,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #5
@@ -5459,9 +5459,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #6
@@ -5482,9 +5482,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #7
@@ -5505,9 +5505,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #8
@@ -5528,9 +5528,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #9
@@ -5551,9 +5551,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #10
@@ -5574,9 +5574,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #11
@@ -5597,9 +5597,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #12
@@ -5620,9 +5620,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #13
@@ -5643,9 +5643,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #14
@@ -5666,9 +5666,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #15
@@ -5689,9 +5689,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #16
@@ -5712,9 +5712,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #17
@@ -5735,9 +5735,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #18
@@ -5758,9 +5758,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #19
@@ -5781,9 +5781,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #20
@@ -5804,9 +5804,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #21
@@ -5827,9 +5827,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #22
@@ -5850,9 +5850,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #23
@@ -5873,9 +5873,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #24
@@ -5896,9 +5896,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #25
@@ -5919,9 +5919,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #26
@@ -5942,9 +5942,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #27
@@ -5965,9 +5965,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #28
@@ -5988,9 +5988,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #29
@@ -6011,9 +6011,9 @@ define <2 x i64> @clmul_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #30
@@ -9555,9 +9555,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q0, q2, q0
; CHECK-NEXT: lsll r4, r5, #2
@@ -9578,9 +9578,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #3
@@ -9601,9 +9601,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #4
@@ -9624,9 +9624,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #5
@@ -9647,9 +9647,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #6
@@ -9670,9 +9670,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #7
@@ -9693,9 +9693,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #8
@@ -9716,9 +9716,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #9
@@ -9739,9 +9739,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #10
@@ -9762,9 +9762,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #11
@@ -9785,9 +9785,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #12
@@ -9808,9 +9808,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #13
@@ -9831,9 +9831,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #14
@@ -9854,9 +9854,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #15
@@ -9877,9 +9877,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #16
@@ -9900,9 +9900,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #17
@@ -9923,9 +9923,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #18
@@ -9946,9 +9946,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #19
@@ -9969,9 +9969,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #20
@@ -9992,9 +9992,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #21
@@ -10015,9 +10015,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #22
@@ -10038,9 +10038,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #23
@@ -10061,9 +10061,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #24
@@ -10084,9 +10084,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #25
@@ -10107,9 +10107,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #26
@@ -10130,9 +10130,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #27
@@ -10153,9 +10153,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #28
@@ -10176,9 +10176,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #29
@@ -10199,9 +10199,9 @@ define <2 x i32> @clmulr_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #30
@@ -12754,9 +12754,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q0, q2, q0
; CHECK-NEXT: lsll r4, r5, #2
@@ -12777,9 +12777,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #3
@@ -12800,9 +12800,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #4
@@ -12823,9 +12823,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #5
@@ -12846,9 +12846,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #6
@@ -12869,9 +12869,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #7
@@ -12892,9 +12892,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #8
@@ -12915,9 +12915,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #9
@@ -12938,9 +12938,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #10
@@ -12961,9 +12961,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #11
@@ -12984,9 +12984,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #12
@@ -13007,9 +13007,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #13
@@ -13030,9 +13030,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #14
@@ -13053,9 +13053,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #15
@@ -13076,9 +13076,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #16
@@ -13099,9 +13099,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #17
@@ -13122,9 +13122,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #18
@@ -13145,9 +13145,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #19
@@ -13168,9 +13168,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #20
@@ -13191,9 +13191,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #21
@@ -13214,9 +13214,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #22
@@ -13237,9 +13237,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #23
@@ -13260,9 +13260,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #24
@@ -13283,9 +13283,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #25
@@ -13306,9 +13306,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #26
@@ -13329,9 +13329,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #27
@@ -13352,9 +13352,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #28
@@ -13375,9 +13375,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #29
@@ -13398,9 +13398,9 @@ define <2 x i32> @clmulh_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov q2[3], q2[1], r5, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vand q3, q1, q3
; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vand q3, q1, q3
+; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: veor q2, q0, q2
; CHECK-NEXT: lsll r4, r5, #30
diff --git a/llvm/test/CodeGen/X86/abds-neg.ll b/llvm/test/CodeGen/X86/abds-neg.ll
index d9064c684cb20..2911edfbfd409 100644
--- a/llvm/test/CodeGen/X86/abds-neg.ll
+++ b/llvm/test/CodeGen/X86/abds-neg.ll
@@ -1076,15 +1076,15 @@ define i64 @abd_subnsw_i64(i64 %a, i64 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: sbbl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: subl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx
-; X86-NEXT: xorl %edx, %esi
; X86-NEXT: xorl %edx, %ecx
+; X86-NEXT: xorl %edx, %esi
; X86-NEXT: movl %edx, %eax
-; X86-NEXT: subl %ecx, %eax
-; X86-NEXT: sbbl %esi, %edx
+; X86-NEXT: subl %esi, %eax
+; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -1107,15 +1107,15 @@ define i64 @abd_subnsw_i64_undef(i64 %a, i64 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: sbbl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: subl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx
-; X86-NEXT: xorl %edx, %esi
; X86-NEXT: xorl %edx, %ecx
+; X86-NEXT: xorl %edx, %esi
; X86-NEXT: movl %edx, %eax
-; X86-NEXT: subl %ecx, %eax
-; X86-NEXT: sbbl %esi, %edx
+; X86-NEXT: subl %esi, %eax
+; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: popl %esi
; X86-NEXT: retl
;
@@ -1142,32 +1142,32 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: subl 40(%ebp), %edi
+; X86-NEXT: movl 24(%ebp), %esi
+; X86-NEXT: subl 40(%ebp), %esi
; X86-NEXT: sbbl 44(%ebp), %edx
; X86-NEXT: sbbl 48(%ebp), %ecx
; X86-NEXT: sbbl 52(%ebp), %eax
-; X86-NEXT: movl %eax, %esi
-; X86-NEXT: sarl $31, %esi
-; X86-NEXT: xorl %esi, %eax
-; X86-NEXT: xorl %esi, %ecx
-; X86-NEXT: xorl %esi, %edx
-; X86-NEXT: xorl %esi, %edi
-; X86-NEXT: movl %esi, %ebx
-; X86-NEXT: subl %edi, %ebx
-; X86-NEXT: movl %esi, %edi
-; X86-NEXT: sbbl %edx, %edi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: sarl $31, %edi
+; X86-NEXT: xorl %edi, %eax
+; X86-NEXT: xorl %edi, %ecx
+; X86-NEXT: xorl %edi, %edx
+; X86-NEXT: xorl %edi, %esi
+; X86-NEXT: movl %edi, %ebx
+; X86-NEXT: subl %esi, %ebx
+; X86-NEXT: movl %edi, %esi
+; X86-NEXT: sbbl %edx, %esi
+; X86-NEXT: movl %edi, %edx
; X86-NEXT: sbbl %ecx, %edx
-; X86-NEXT: sbbl %eax, %esi
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl %ebx, (%eax)
-; X86-NEXT: movl %edi, 4(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
; X86-NEXT: movl %edx, 8(%eax)
-; X86-NEXT: movl %esi, 12(%eax)
+; X86-NEXT: movl %edi, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
@@ -1203,32 +1203,32 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl 24(%ebp), %edi
+; X86-NEXT: movl 32(%ebp), %ecx
; X86-NEXT: movl 28(%ebp), %edx
-; X86-NEXT: subl 40(%ebp), %edi
+; X86-NEXT: movl 24(%ebp), %esi
+; X86-NEXT: subl 40(%ebp), %esi
; X86-NEXT: sbbl 44(%ebp), %edx
; X86-NEXT: sbbl 48(%ebp), %ecx
; X86-NEXT: sbbl 52(%ebp), %eax
-; X86-NEXT: movl %eax, %esi
-; X86-NEXT: sarl $31, %esi
-; X86-NEXT: xorl %esi, %eax
-; X86-NEXT: xorl %esi, %ecx
-; X86-NEXT: xorl %esi, %edx
-; X86-NEXT: xorl %esi, %edi
-; X86-NEXT: movl %esi, %ebx
-; X86-NEXT: subl %edi, %ebx
-; X86-NEXT: movl %esi, %edi
-; X86-NEXT: sbbl %edx, %edi
-; X86-NEXT: movl %esi, %edx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: sarl $31, %edi
+; X86-NEXT: xorl %edi, %eax
+; X86-NEXT: xorl %edi, %ecx
+; X86-NEXT: xorl %edi, %edx
+; X86-NEXT: xorl %edi, %esi
+; X86-NEXT: movl %edi, %ebx
+; X86-NEXT: subl %esi, %ebx
+; X86-NEXT: movl %edi, %esi
+; X86-NEXT: sbbl %edx, %esi
+; X86-NEXT: movl %edi, %edx
; X86-NEXT: sbbl %ecx, %edx
-; X86-NEXT: sbbl %eax, %esi
+; X86-NEXT: sbbl %eax, %edi
; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl %ebx, (%eax)
-; X86-NEXT: movl %edi, 4(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
; X86-NEXT: movl %edx, 8(%eax)
-; X86-NEXT: movl %esi, 12(%eax)
+; X86-NEXT: movl %edi, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/avg-mask.ll b/llvm/test/CodeGen/X86/avg-mask.ll
index b049260f9daed..41e5cc17dda27 100644
--- a/llvm/test/CodeGen/X86/avg-mask.ll
+++ b/llvm/test/CodeGen/X86/avg-mask.ll
@@ -33,7 +33,14 @@ define <16 x i8> @avg_v16i8_mask(<16 x i8> %a, <16 x i8> %b, <16 x i8> %src, i16
define <16 x i8> @avg_v16i8_maskz(<16 x i8> %a, <16 x i8> %b, i16 %mask) nounwind {
; AVX512F-LABEL: avg_v16i8_maskz:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vpavgb %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512F-NEXT: vpaddw %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT: vpsubw %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
+; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 {%k1} {z} = -1
; AVX512F-NEXT: vpmovdb %zmm1, %xmm1
@@ -177,9 +184,9 @@ define <64 x i8> @avg_v64i8_maskz(<64 x i8> %a, <64 x i8> %b, i64 %mask) nounwin
; AVX512F-NEXT: shrq $32, %rdi
; AVX512F-NEXT: shrq $48, %rax
; AVX512F-NEXT: shrl $16, %ecx
-; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
-; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
-; AVX512F-NEXT: vpavgb %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; AVX512F-NEXT: vpavgb %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpavgb %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512F-NEXT: kmovw %ecx, %k2
@@ -246,7 +253,13 @@ define <8 x i16> @avg_v8i16_mask(<8 x i16> %a, <8 x i16> %b, <8 x i16> %src, i8
define <8 x i16> @avg_v8i16_maskz(<8 x i16> %a, <8 x i16> %b, i8 %mask) nounwind {
; AVX512F-LABEL: avg_v8i16_maskz:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vpavgw %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX512F-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT: vpsubd %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vpsrld $1, %ymm0, %ymm0
+; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 {%k1} {z} = -1
; AVX512F-NEXT: vpmovdw %zmm1, %ymm1
@@ -363,9 +376,9 @@ define <32 x i16> @avg_v32i16_maskz(<32 x i16> %a, <32 x i16> %b, i32 %mask) nou
; AVX512F: # %bb.0:
; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: shrl $16, %edi
-; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
-; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
-; AVX512F-NEXT: vpavgw %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; AVX512F-NEXT: vpavgw %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpavgw %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512F-NEXT: kmovw %edi, %k2
diff --git a/llvm/test/CodeGen/X86/avg.ll b/llvm/test/CodeGen/X86/avg.ll
index 5152c00521f81..5a016e14b204d 100644
--- a/llvm/test/CodeGen/X86/avg.ll
+++ b/llvm/test/CodeGen/X86/avg.ll
@@ -1758,20 +1758,20 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-LABEL: not_avg_v16i8_wide_constants:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps (%rdi), %xmm1
-; SSE2-NEXT: movdqa (%rsi), %xmm0
+; SSE2-NEXT: movdqa (%rsi), %xmm2
; SSE2-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm2
+; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm3
+; SSE2-NEXT: movd %eax, %xmm4
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm4
+; SSE2-NEXT: movd %eax, %xmm3
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm5
@@ -1786,9 +1786,6 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-NEXT: movd %eax, %xmm8
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: movd %eax, %xmm10
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm9
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
@@ -1798,6 +1795,9 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-NEXT: movd %eax, %xmm12
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
+; SSE2-NEXT: movd %eax, %xmm10
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
+; SSE2-NEXT: decl %eax
; SSE2-NEXT: movd %eax, %xmm13
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
@@ -1807,45 +1807,43 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; SSE2-NEXT: movd %eax, %xmm15
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: decl %eax
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
-; SSE2-NEXT: movd %eax, %xmm2
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,0,0,0]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-NEXT: movd %eax, %xmm0
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,0,0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm6[0,0,0,0]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3]
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm8[0,0,0,0]
-; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]
-; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm1[0],xmm4[1]
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
+; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1]
; SSE2-NEXT: pxor %xmm3, %xmm3
-; SSE2-NEXT: movdqa %xmm0, %xmm1
+; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
; SSE2-NEXT: movapd %xmm4, %xmm5
; SSE2-NEXT: andpd %xmm1, %xmm5
; SSE2-NEXT: xorpd %xmm4, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: paddw %xmm5, %xmm1
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm9 = xmm9[0],xmm10[0],xmm9[1],xmm10[1],xmm9[2],xmm10[2],xmm9[3],xmm10[3]
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm12 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm12[0,0,0,0]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm4[0],xmm9[1],xmm4[1]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm11 = xmm11[0],xmm9[0],xmm11[1],xmm9[1],xmm11[2],xmm9[2],xmm11[3],xmm9[3]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm10 = xmm10[0],xmm12[0],xmm10[1],xmm12[1],xmm10[2],xmm12[2],xmm10[3],xmm12[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm14 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3]
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm14[0,0,0,0]
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm15[0],xmm2[1],xmm15[1],xmm2[2],xmm15[2],xmm2[3],xmm15[3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
-; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm4[2],xmm2[3],xmm4[3]
-; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm9[0],xmm2[1]
-; SSE2-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm3[8],xmm0[9],xmm3[9],xmm0[10],xmm3[10],xmm0[11],xmm3[11],xmm0[12],xmm3[12],xmm0[13],xmm3[13],xmm0[14],xmm3[14],xmm0[15],xmm3[15]
-; SSE2-NEXT: movapd %xmm2, %xmm3
-; SSE2-NEXT: andpd %xmm0, %xmm3
-; SSE2-NEXT: xorpd %xmm2, %xmm0
-; SSE2-NEXT: psrlw $1, %xmm0
-; SSE2-NEXT: paddw %xmm3, %xmm0
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
-; SSE2-NEXT: pand %xmm2, %xmm0
-; SSE2-NEXT: pand %xmm2, %xmm1
-; SSE2-NEXT: packuswb %xmm0, %xmm1
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm15[0],xmm0[1],xmm15[1],xmm0[2],xmm15[2],xmm0[3],xmm15[3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm4[2],xmm0[3],xmm4[3]
+; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm10[0],xmm0[1]
+; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm3[8],xmm2[9],xmm3[9],xmm2[10],xmm3[10],xmm2[11],xmm3[11],xmm2[12],xmm3[12],xmm2[13],xmm3[13],xmm2[14],xmm3[14],xmm2[15],xmm3[15]
+; SSE2-NEXT: movapd %xmm0, %xmm3
+; SSE2-NEXT: andpd %xmm2, %xmm3
+; SSE2-NEXT: xorpd %xmm0, %xmm2
+; SSE2-NEXT: psrlw $1, %xmm2
+; SSE2-NEXT: paddw %xmm3, %xmm2
+; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; SSE2-NEXT: pand %xmm0, %xmm2
+; SSE2-NEXT: pand %xmm0, %xmm1
+; SSE2-NEXT: packuswb %xmm2, %xmm1
; SSE2-NEXT: movdqu %xmm1, (%rax)
; SSE2-NEXT: retq
;
@@ -1855,75 +1853,71 @@ define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX1-NEXT: vpextrw $7, %xmm3, %edx
-; AVX1-NEXT: vpextrw $6, %xmm3, %ecx
-; AVX1-NEXT: vpextrw $5, %xmm3, %eax
+; AVX1-NEXT: vpextrw $3, %xmm3, %edx
+; AVX1-NEXT: vpextrw $2, %xmm3, %ecx
+; AVX1-NEXT: vpextrw $1, %xmm3, %eax
; AVX1-NEXT: decl %edx
; AVX1-NEXT: vmovd %edx, %xmm4
-; AVX1-NEXT: vpextrw $4, %xmm3, %edx
+; AVX1-NEXT: vpextrw $0, %xmm3, %edx
; AVX1-NEXT: decl %ecx
; AVX1-NEXT: vmovd %ecx, %xmm5
-; AVX1-NEXT: vpextrw $1, %xmm3, %ecx
+; AVX1-NEXT: vpextrw $3, %xmm2, %ecx
; AVX1-NEXT: decl %eax
; AVX1-NEXT: vmovd %eax, %xmm6
-; AVX1-NEXT: vpextrw $0, %xmm3, %eax
+; AVX1-NEXT: vpextrw $2, %xmm2, %eax
; AVX1-NEXT: decl %edx
; AVX1-NEXT: vmovd %edx, %xmm7
-; AVX1-NEXT: vpextrw $3, %xmm3, %edx
-; AVX1-NEXT: decq %rcx
-; AVX1-NEXT: vmovq %rcx, %xmm8
-; AVX1-NEXT: vpextrw $2, %xmm3, %ecx
-; AVX1-NEXT: decq %rax
-; AVX1-NEXT: vmovq %rax, %xmm3
-; AVX1-NEXT: vpextrw $7, %xmm2, %eax
+; AVX1-NEXT: vpextrw $1, %xmm2, %edx
+; AVX1-NEXT: decl %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm8
+; AVX1-NEXT: vpextrw $0, %xmm2, %ecx
+; AVX1-NEXT: decl %eax
+; AVX1-NEXT: vmovd %eax, %xmm9
+; AVX1-NEXT: vpextrw $7, %xmm3, %eax
; AVX1-NEXT: decl %edx
-; AVX1-NEXT: vmovd %edx, %xmm9
-; AVX1-NEXT: vpextrw $6, %xmm2, %edx
+; AVX1-NEXT: vmovd %edx, %xmm10
+; AVX1-NEXT: vpextrw $6, %xmm3, %edx
; AVX1-NEXT: decl %ecx
-; AVX1-NEXT: vmovd %ecx, %xmm10
-; AVX1-NEXT: vpextrw $5, %xmm2, %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm11
+; AVX1-NEXT: vpextrw $7, %xmm2, %ecx
; AVX1-NEXT: decl %eax
-; AVX1-NEXT: vmovd %eax, %xmm11
-; AVX1-NEXT: vpextrw $4, %xmm2, %eax
+; AVX1-NEXT: vmovd %eax, %xmm12
+; AVX1-NEXT: vpextrw $6, %xmm2, %eax
; AVX1-NEXT: decl %edx
-; AVX1-NEXT: vmovd %edx, %xmm12
-; AVX1-NEXT: vpextrw $1, %xmm2, %edx
+; AVX1-NEXT: vmovd %edx, %xmm13
+; AVX1-NEXT: vpextrw $5, %xmm3, %edx
; AVX1-NEXT: decl %ecx
-; AVX1-NEXT: vmovd %ecx, %xmm13
-; AVX1-NEXT: vpextrw $0, %xmm2, %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm14
+; AVX1-NEXT: vpextrw $4, %xmm3, %ecx
; AVX1-NEXT: decl %eax
-; AVX1-NEXT: vmovd %eax, %xmm14
-; AVX1-NEXT: vpextrw $3, %xmm2, %eax
-; AVX1-NEXT: decq %rdx
-; AVX1-NEXT: vmovq %rdx, %xmm15
-; AVX1-NEXT: vpextrw $2, %xmm2, %edx
-; AVX1-NEXT: decq %rcx
-; AVX1-NEXT: vmovq %rcx, %xmm2
+; AVX1-NEXT: vmovd %eax, %xmm3
+; AVX1-NEXT: vpextrw $5, %xmm2, %eax
+; AVX1-NEXT: decl %edx
+; AVX1-NEXT: vmovd %edx, %xmm15
+; AVX1-NEXT: vpextrw $4, %xmm2, %edx
+; AVX1-NEXT: decl %ecx
+; AVX1-NEXT: vmovd %ecx, %xmm2
; AVX1-NEXT: decl %eax
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3]
; AVX1-NEXT: vmovd %eax, %xmm5
; AVX1-NEXT: decl %edx
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3]
; AVX1-NEXT: vmovd %edx, %xmm7
-; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[0,1,0,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm6[0,1,2,3,4,5],xmm4[6,7]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm8[0],xmm3[1],xmm8[1],xmm3[2],xmm8[2],xmm3[3],xmm8[3]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm10[0],xmm9[0],xmm10[1],xmm9[1],xmm10[2],xmm9[2],xmm10[3],xmm9[3]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[0,0,1,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm6[2,3],xmm3[4,5,6,7]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm4[4,5,6,7]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3]
-; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[0,1,0,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm6[0,1,2,3,4,5],xmm4[6,7]
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm6[0],xmm4[0],xmm6[1],xmm4[1]
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm9[0],xmm8[0],xmm9[1],xmm8[1],xmm9[2],xmm8[2],xmm9[3],xmm8[3]
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3]
+; AVX1-NEXT: vpunpckldq {{.*#+}} xmm6 = xmm8[0],xmm6[0],xmm8[1],xmm6[1]
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm6, %ymm4
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3]
+; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm14[0],xmm3[1],xmm14[1],xmm3[2],xmm14[2],xmm3[3],xmm14[3]
+; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm3, %ymm3
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm2[0],xmm15[0],xmm2[1],xmm15[1],xmm2[2],xmm15[2],xmm2[3],xmm15[3]
+; AVX1-NEXT: vshufps {{.*#+}} ymm3 = ymm3[0,0,0,0,4,4,4,4]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
-; AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[0,0,1,1]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5,6,7]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm4[4,5,6,7]
-; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm5, %ymm2
+; AVX1-NEXT: vmovddup {{.*#+}} ymm2 = ymm2[0,0,2,2]
+; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2],ymm3[3],ymm2[4,5,6],ymm3[7]
+; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3],ymm4[4,5],ymm2[6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm1
; AVX1-NEXT: vxorps %ymm0, %ymm2, %ymm0
diff --git a/llvm/test/CodeGen/X86/bit-manip-i256.ll b/llvm/test/CodeGen/X86/bit-manip-i256.ll
index 042b7d428ba5c..e3b1af285165e 100644
--- a/llvm/test/CodeGen/X86/bit-manip-i256.ll
+++ b/llvm/test/CodeGen/X86/bit-manip-i256.ll
@@ -2408,88 +2408,92 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; SSE-LABEL: isolate_msb_i256:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbx
-; SSE-NEXT: movq %rcx, %rax
-; SSE-NEXT: movq %rdx, %r9
-; SSE-NEXT: orq %r8, %r9
-; SSE-NEXT: bsrq %rsi, %rcx
-; SSE-NEXT: orq %rax, %rsi
-; SSE-NEXT: bsrq %r8, %r10
-; SSE-NEXT: xorq $63, %r10
-; SSE-NEXT: bsrq %rax, %r11
-; SSE-NEXT: xorq $63, %r11
-; SSE-NEXT: orq $64, %r11
+; SSE-NEXT: movq %rdx, %rax
+; SSE-NEXT: orq %r8, %rax
+; SSE-NEXT: movq %rsi, %r9
+; SSE-NEXT: orq %rcx, %r9
+; SSE-NEXT: bsrq %r8, %r11
+; SSE-NEXT: xorl $63, %r11d
+; SSE-NEXT: bsrq %rcx, %r10
+; SSE-NEXT: xorl $63, %r10d
+; SSE-NEXT: addb $64, %r10b
+; SSE-NEXT: movzbl %r10b, %r10d
; SSE-NEXT: testq %r8, %r8
-; SSE-NEXT: cmovneq %r10, %r11
-; SSE-NEXT: bsrq %rdx, %r10
-; SSE-NEXT: xorq $63, %r10
-; SSE-NEXT: xorq $63, %rcx
-; SSE-NEXT: orq $64, %rcx
+; SSE-NEXT: cmovnel %r11d, %r10d
+; SSE-NEXT: bsrq %rdx, %r11
+; SSE-NEXT: xorl $63, %r11d
+; SSE-NEXT: bsrq %rsi, %rsi
+; SSE-NEXT: xorl $63, %esi
+; SSE-NEXT: addb $64, %sil
+; SSE-NEXT: movzbl %sil, %esi
; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovneq %r10, %rcx
-; SSE-NEXT: orq $128, %rcx
-; SSE-NEXT: orq %r8, %rax
-; SSE-NEXT: cmovneq %r11, %rcx
+; SSE-NEXT: cmovnel %r11d, %esi
+; SSE-NEXT: addb $-128, %sil
+; SSE-NEXT: orq %r8, %rcx
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; SSE-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movl %ecx, %eax
-; SSE-NEXT: shrb $6, %al
-; SSE-NEXT: movzbl %al, %eax
+; SSE-NEXT: movzbl %sil, %ecx
+; SSE-NEXT: cmovnel %r10d, %ecx
+; SSE-NEXT: movl %ecx, %edx
+; SSE-NEXT: shrb $6, %dl
+; SSE-NEXT: movzbl %dl, %esi
; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE-NEXT: movq -40(%rsp,%rax,8), %rdx
-; SSE-NEXT: movq -48(%rsp,%rax,8), %r8
+; SSE-NEXT: movq -40(%rsp,%rsi,8), %rdx
+; SSE-NEXT: movq -48(%rsp,%rsi,8), %r8
; SSE-NEXT: movq %r8, %r10
; SSE-NEXT: shrdq %cl, %rdx, %r10
-; SSE-NEXT: movq -56(%rsp,%rax,8), %r11
+; SSE-NEXT: movq -56(%rsp,%rsi,8), %r11
; SSE-NEXT: movq %r11, %rbx
; SSE-NEXT: shrdq %cl, %r8, %rbx
-; SSE-NEXT: movq -64(%rsp,%rax,8), %r8
+; SSE-NEXT: movq -64(%rsp,%rsi,8), %rsi
; SSE-NEXT: shrq %cl, %rdx
-; SSE-NEXT: # kill: def $cl killed $cl killed $rcx
-; SSE-NEXT: shrdq %cl, %r11, %r8
+; SSE-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE-NEXT: shrdq %cl, %r11, %rsi
; SSE-NEXT: xorl %ecx, %ecx
-; SSE-NEXT: orq %r9, %rsi
+; SSE-NEXT: orq %rax, %r9
; SSE-NEXT: cmoveq %rcx, %rbx
; SSE-NEXT: cmoveq %rcx, %r10
-; SSE-NEXT: cmoveq %rcx, %r8
+; SSE-NEXT: cmoveq %rcx, %rsi
; SSE-NEXT: movq %rdi, %rax
; SSE-NEXT: cmoveq %rcx, %rdx
; SSE-NEXT: movq %rdx, 24(%rdi)
; SSE-NEXT: movq %r10, 16(%rdi)
; SSE-NEXT: movq %rbx, 8(%rdi)
-; SSE-NEXT: movq %r8, (%rdi)
+; SSE-NEXT: movq %rsi, (%rdi)
; SSE-NEXT: popq %rbx
; SSE-NEXT: retq
;
; AVX2-LABEL: isolate_msb_i256:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: movq %rdx, %r9
; AVX2-NEXT: orq %r8, %r9
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: lzcntq %rsi, %rcx
-; AVX2-NEXT: orq %rax, %rsi
+; AVX2-NEXT: lzcntq %rsi, %rax
+; AVX2-NEXT: orq %rcx, %rsi
; AVX2-NEXT: lzcntq %r8, %r10
-; AVX2-NEXT: lzcntq %rax, %r11
-; AVX2-NEXT: addq $64, %r11
+; AVX2-NEXT: lzcntq %rcx, %r11
+; AVX2-NEXT: addb $64, %r11b
+; AVX2-NEXT: movzbl %r11b, %r11d
; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %r10, %r11
+; AVX2-NEXT: cmovnel %r10d, %r11d
; AVX2-NEXT: xorl %r10d, %r10d
; AVX2-NEXT: lzcntq %rdx, %r10
-; AVX2-NEXT: addq $64, %rcx
+; AVX2-NEXT: addb $64, %al
+; AVX2-NEXT: movzbl %al, %eax
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
-; AVX2-NEXT: orq %r8, %rax
-; AVX2-NEXT: cmovneq %r11, %rcx
+; AVX2-NEXT: cmovnel %r10d, %eax
; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: addb $-128, %al
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: orq %r8, %rcx
+; AVX2-NEXT: movzbl %al, %ecx
+; AVX2-NEXT: cmovnel %r11d, %ecx
; AVX2-NEXT: movl %ecx, %eax
; AVX2-NEXT: shrb $6, %al
; AVX2-NEXT: movzbl %al, %eax
@@ -2521,25 +2525,27 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512F-LABEL: isolate_msb_i256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: pushq %rbx
-; AVX512F-NEXT: movq %rcx, %rax
; AVX512F-NEXT: movq %rdx, %r9
; AVX512F-NEXT: orq %r8, %r9
-; AVX512F-NEXT: lzcntq %rsi, %rcx
-; AVX512F-NEXT: orq %rax, %rsi
+; AVX512F-NEXT: lzcntq %rsi, %rax
+; AVX512F-NEXT: orq %rcx, %rsi
; AVX512F-NEXT: lzcntq %r8, %r10
-; AVX512F-NEXT: lzcntq %rax, %r11
-; AVX512F-NEXT: addq $64, %r11
+; AVX512F-NEXT: lzcntq %rcx, %r11
+; AVX512F-NEXT: addb $64, %r11b
+; AVX512F-NEXT: movzbl %r11b, %r11d
; AVX512F-NEXT: testq %r8, %r8
-; AVX512F-NEXT: cmovneq %r10, %r11
+; AVX512F-NEXT: cmovnel %r10d, %r11d
; AVX512F-NEXT: lzcntq %rdx, %r10
-; AVX512F-NEXT: addq $64, %rcx
+; AVX512F-NEXT: addb $64, %al
+; AVX512F-NEXT: movzbl %al, %eax
; AVX512F-NEXT: testq %rdx, %rdx
-; AVX512F-NEXT: cmovneq %r10, %rcx
-; AVX512F-NEXT: subq $-128, %rcx
-; AVX512F-NEXT: orq %r8, %rax
-; AVX512F-NEXT: cmovneq %r11, %rcx
+; AVX512F-NEXT: cmovnel %r10d, %eax
+; AVX512F-NEXT: addb $-128, %al
; AVX512F-NEXT: vmovaps {{.*#+}} zmm0 = [0,0,0,9223372036854775808,0,0,0,0]
; AVX512F-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp)
+; AVX512F-NEXT: orq %r8, %rcx
+; AVX512F-NEXT: movzbl %al, %ecx
+; AVX512F-NEXT: cmovnel %r11d, %ecx
; AVX512F-NEXT: movl %ecx, %eax
; AVX512F-NEXT: shrb $6, %al
; AVX512F-NEXT: movzbl %al, %eax
@@ -2570,27 +2576,29 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512VL-LABEL: isolate_msb_i256:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: pushq %rbx
-; AVX512VL-NEXT: movq %rcx, %rax
; AVX512VL-NEXT: movq %rdx, %r9
; AVX512VL-NEXT: orq %r8, %r9
-; AVX512VL-NEXT: lzcntq %rsi, %rcx
-; AVX512VL-NEXT: orq %rax, %rsi
+; AVX512VL-NEXT: lzcntq %rsi, %rax
+; AVX512VL-NEXT: orq %rcx, %rsi
; AVX512VL-NEXT: lzcntq %r8, %r10
-; AVX512VL-NEXT: lzcntq %rax, %r11
-; AVX512VL-NEXT: addq $64, %r11
+; AVX512VL-NEXT: lzcntq %rcx, %r11
+; AVX512VL-NEXT: addb $64, %r11b
+; AVX512VL-NEXT: movzbl %r11b, %r11d
; AVX512VL-NEXT: testq %r8, %r8
-; AVX512VL-NEXT: cmovneq %r10, %r11
+; AVX512VL-NEXT: cmovnel %r10d, %r11d
; AVX512VL-NEXT: lzcntq %rdx, %r10
-; AVX512VL-NEXT: addq $64, %rcx
+; AVX512VL-NEXT: addb $64, %al
+; AVX512VL-NEXT: movzbl %al, %eax
; AVX512VL-NEXT: testq %rdx, %rdx
-; AVX512VL-NEXT: cmovneq %r10, %rcx
-; AVX512VL-NEXT: subq $-128, %rcx
-; AVX512VL-NEXT: orq %r8, %rax
+; AVX512VL-NEXT: cmovnel %r10d, %eax
+; AVX512VL-NEXT: addb $-128, %al
+; AVX512VL-NEXT: orq %r8, %rcx
; AVX512VL-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,9223372036854775808]
; AVX512VL-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
-; AVX512VL-NEXT: cmovneq %r11, %rcx
; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX512VL-NEXT: movzbl %al, %ecx
+; AVX512VL-NEXT: cmovnel %r11d, %ecx
; AVX512VL-NEXT: movl %ecx, %eax
; AVX512VL-NEXT: shrb $6, %al
; AVX512VL-NEXT: movzbl %al, %eax
@@ -2622,27 +2630,29 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512VBMI-LABEL: isolate_msb_i256:
; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: pushq %rbx
-; AVX512VBMI-NEXT: movq %rcx, %rax
; AVX512VBMI-NEXT: movq %rdx, %r9
; AVX512VBMI-NEXT: orq %r8, %r9
-; AVX512VBMI-NEXT: lzcntq %rsi, %rcx
-; AVX512VBMI-NEXT: orq %rax, %rsi
+; AVX512VBMI-NEXT: lzcntq %rsi, %rax
+; AVX512VBMI-NEXT: orq %rcx, %rsi
; AVX512VBMI-NEXT: lzcntq %r8, %r10
-; AVX512VBMI-NEXT: lzcntq %rax, %r11
-; AVX512VBMI-NEXT: addq $64, %r11
+; AVX512VBMI-NEXT: lzcntq %rcx, %r11
+; AVX512VBMI-NEXT: addb $64, %r11b
+; AVX512VBMI-NEXT: movzbl %r11b, %r11d
; AVX512VBMI-NEXT: testq %r8, %r8
-; AVX512VBMI-NEXT: cmovneq %r10, %r11
+; AVX512VBMI-NEXT: cmovnel %r10d, %r11d
; AVX512VBMI-NEXT: lzcntq %rdx, %r10
-; AVX512VBMI-NEXT: addq $64, %rcx
+; AVX512VBMI-NEXT: addb $64, %al
+; AVX512VBMI-NEXT: movzbl %al, %eax
; AVX512VBMI-NEXT: testq %rdx, %rdx
-; AVX512VBMI-NEXT: cmovneq %r10, %rcx
-; AVX512VBMI-NEXT: subq $-128, %rcx
-; AVX512VBMI-NEXT: orq %r8, %rax
+; AVX512VBMI-NEXT: cmovnel %r10d, %eax
+; AVX512VBMI-NEXT: addb $-128, %al
+; AVX512VBMI-NEXT: orq %r8, %rcx
; AVX512VBMI-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,9223372036854775808]
; AVX512VBMI-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
-; AVX512VBMI-NEXT: cmovneq %r11, %rcx
; AVX512VBMI-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VBMI-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX512VBMI-NEXT: movzbl %al, %ecx
+; AVX512VBMI-NEXT: cmovnel %r11d, %ecx
; AVX512VBMI-NEXT: movl %ecx, %eax
; AVX512VBMI-NEXT: shrb $6, %al
; AVX512VBMI-NEXT: movzbl %al, %eax
@@ -2681,10 +2691,10 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE2-LABEL: isolate_msb_i256_vector:
; SSE2: # %bb.0:
-; SSE2-NEXT: movq %xmm0, %rcx
+; SSE2-NEXT: movq %xmm0, %rsi
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm2, %rdx
-; SSE2-NEXT: movq %xmm1, %rsi
+; SSE2-NEXT: movq %xmm2, %rcx
+; SSE2-NEXT: movq %xmm1, %rdx
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
; SSE2-NEXT: movq %xmm2, %r8
; SSE2-NEXT: por %xmm1, %xmm0
@@ -2693,29 +2703,32 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE2-NEXT: movmskps %xmm0, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: bsrq %r8, %r9
-; SSE2-NEXT: xorq $63, %r9
-; SSE2-NEXT: bsrq %rsi, %rsi
-; SSE2-NEXT: xorq $63, %rsi
-; SSE2-NEXT: orq $64, %rsi
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: bsrq %rdx, %rdx
+; SSE2-NEXT: xorl $63, %edx
+; SSE2-NEXT: addb $64, %dl
+; SSE2-NEXT: movzbl %dl, %edx
; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %r9, %rsi
-; SSE2-NEXT: bsrq %rdx, %r8
-; SSE2-NEXT: xorq $63, %r8
-; SSE2-NEXT: bsrq %rcx, %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: orq $64, %rcx
-; SSE2-NEXT: testq %rdx, %rdx
-; SSE2-NEXT: cmovneq %r8, %rcx
-; SSE2-NEXT: orq $128, %rcx
+; SSE2-NEXT: cmovnel %r9d, %edx
+; SSE2-NEXT: bsrq %rcx, %r8
+; SSE2-NEXT: xorl $63, %r8d
+; SSE2-NEXT: bsrq %rsi, %rsi
+; SSE2-NEXT: xorl $63, %esi
+; SSE2-NEXT: addb $64, %sil
+; SSE2-NEXT: movzbl %sil, %esi
+; SSE2-NEXT: testq %rcx, %rcx
+; SSE2-NEXT: cmovnel %r8d, %esi
+; SSE2-NEXT: addb $-128, %sil
; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
-; SSE2-NEXT: movmskps %xmm1, %edx
-; SSE2-NEXT: xorl $15, %edx
-; SSE2-NEXT: cmovneq %rsi, %rcx
+; SSE2-NEXT: movmskps %xmm1, %ecx
+; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
-; SSE2-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE2-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movzbl %sil, %ecx
+; SSE2-NEXT: cmovnel %edx, %ecx
; SSE2-NEXT: movl %ecx, %edx
; SSE2-NEXT: shrb $6, %dl
; SSE2-NEXT: movzbl %dl, %esi
@@ -2729,7 +2742,7 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE2-NEXT: shrdq %cl, %r8, %r11
; SSE2-NEXT: movq -72(%rsp,%rsi,8), %rsi
; SSE2-NEXT: shrq %cl, %rdx
-; SSE2-NEXT: # kill: def $cl killed $cl killed $rcx
+; SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; SSE2-NEXT: shrdq %cl, %r10, %rsi
; SSE2-NEXT: xorl %ecx, %ecx
; SSE2-NEXT: testl %eax, %eax
@@ -2746,33 +2759,36 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
;
; SSE42-LABEL: isolate_msb_i256_vector:
; SSE42: # %bb.0:
-; SSE42-NEXT: pextrq $1, %xmm0, %rdx
-; SSE42-NEXT: movq %xmm0, %rcx
-; SSE42-NEXT: movq %xmm1, %rax
-; SSE42-NEXT: pextrq $1, %xmm1, %rsi
-; SSE42-NEXT: bsrq %rsi, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: bsrq %rax, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
-; SSE42-NEXT: testq %rsi, %rsi
-; SSE42-NEXT: cmovneq %r8, %rax
-; SSE42-NEXT: bsrq %rdx, %rsi
-; SSE42-NEXT: xorq $63, %rsi
-; SSE42-NEXT: bsrq %rcx, %rcx
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: orq $64, %rcx
-; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rsi, %rcx
; SSE42-NEXT: xorps %xmm2, %xmm2
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: orq $128, %rcx
+; SSE42-NEXT: movq %xmm0, %rax
+; SSE42-NEXT: pextrq $1, %xmm0, %rcx
+; SSE42-NEXT: movq %xmm1, %rdx
+; SSE42-NEXT: pextrq $1, %xmm1, %rsi
+; SSE42-NEXT: bsrq %rsi, %r8
+; SSE42-NEXT: xorl $63, %r8d
+; SSE42-NEXT: bsrq %rdx, %rdx
+; SSE42-NEXT: xorl $63, %edx
+; SSE42-NEXT: addb $64, %dl
+; SSE42-NEXT: movzbl %dl, %edx
+; SSE42-NEXT: testq %rsi, %rsi
+; SSE42-NEXT: cmovnel %r8d, %edx
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %rax, %rax
+; SSE42-NEXT: xorl $63, %eax
+; SSE42-NEXT: addb $64, %al
+; SSE42-NEXT: movzbl %al, %eax
+; SSE42-NEXT: testq %rcx, %rcx
+; SSE42-NEXT: cmovnel %esi, %eax
+; SSE42-NEXT: addb $-128, %al
; SSE42-NEXT: ptest %xmm1, %xmm1
-; SSE42-NEXT: cmovneq %rax, %rcx
-; SSE42-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; SSE42-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE42-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movzbl %al, %ecx
+; SSE42-NEXT: cmovnel %edx, %ecx
; SSE42-NEXT: movl %ecx, %eax
; SSE42-NEXT: shrb $6, %al
; SSE42-NEXT: movzbl %al, %eax
@@ -2786,7 +2802,7 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE42-NEXT: shrdq %cl, %rsi, %r10
; SSE42-NEXT: movq -72(%rsp,%rax,8), %rsi
; SSE42-NEXT: shrq %cl, %rdx
-; SSE42-NEXT: # kill: def $cl killed $cl killed $rcx
+; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
; SSE42-NEXT: shrdq %cl, %r9, %rsi
; SSE42-NEXT: por %xmm1, %xmm0
; SSE42-NEXT: xorl %ecx, %ecx
@@ -2804,29 +2820,31 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
;
; AVX2-LABEL: isolate_msb_i256_vector:
; AVX2: # %bb.0:
-; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vpextrq $1, %xmm0, %rdx
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovq %xmm1, %rsi
-; AVX2-NEXT: vpextrq $1, %xmm1, %r8
-; AVX2-NEXT: lzcntq %r8, %rcx
-; AVX2-NEXT: lzcntq %rsi, %r9
-; AVX2-NEXT: addq $64, %r9
-; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %rcx, %r9
-; AVX2-NEXT: lzcntq %rdx, %r10
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: lzcntq %rax, %rcx
-; AVX2-NEXT: addq $64, %rcx
+; AVX2-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: lzcntq %rax, %rsi
+; AVX2-NEXT: lzcntq %rcx, %r8
+; AVX2-NEXT: addb $64, %r8b
+; AVX2-NEXT: movzbl %r8b, %r8d
+; AVX2-NEXT: testq %rax, %rax
+; AVX2-NEXT: cmovnel %esi, %r8d
+; AVX2-NEXT: vmovq %xmm0, %rsi
+; AVX2-NEXT: lzcntq %rdx, %r9
+; AVX2-NEXT: lzcntq %rsi, %rsi
+; AVX2-NEXT: addb $64, %sil
+; AVX2-NEXT: movzbl %sil, %esi
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
-; AVX2-NEXT: orq %r8, %rsi
-; AVX2-NEXT: cmovneq %r9, %rcx
+; AVX2-NEXT: cmovnel %r9d, %esi
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: addb $-128, %sil
; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: orq %rax, %rcx
+; AVX2-NEXT: movzbl %sil, %ecx
+; AVX2-NEXT: cmovnel %r8d, %ecx
; AVX2-NEXT: movl %ecx, %eax
; AVX2-NEXT: shrb $6, %al
; AVX2-NEXT: movzbl %al, %edx
@@ -2983,37 +3001,46 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; SSE2-LABEL: isolate_msb_i256_load:
; SSE2: # %bb.0:
-; SSE2-NEXT: movq 8(%rsi), %r9
+; SSE2-NEXT: movq 24(%rsi), %rcx
+; SSE2-NEXT: movq %rcx, %xmm0
; SSE2-NEXT: movq 16(%rsi), %rdx
-; SSE2-NEXT: movq 24(%rsi), %r8
-; SSE2-NEXT: movdqa (%rsi), %xmm1
-; SSE2-NEXT: por 16(%rsi), %xmm1
+; SSE2-NEXT: movq %rdx, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE2-NEXT: movq (%rsi), %r8
+; SSE2-NEXT: movq 8(%rsi), %rsi
+; SSE2-NEXT: movq %r8, %xmm2
+; SSE2-NEXT: movq %rsi, %xmm0
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
-; SSE2-NEXT: movmskps %xmm1, %eax
+; SSE2-NEXT: pcmpeqd %xmm0, %xmm2
+; SSE2-NEXT: movmskps %xmm2, %eax
; SSE2-NEXT: xorl $15, %eax
-; SSE2-NEXT: bsrq %r8, %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: bsrq %rdx, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
-; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %rcx, %r10
-; SSE2-NEXT: bsrq %r9, %r11
-; SSE2-NEXT: xorq $63, %r11
-; SSE2-NEXT: bsrq (%rsi), %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: orq $64, %rcx
-; SSE2-NEXT: testq %r9, %r9
-; SSE2-NEXT: cmovneq %r11, %rcx
-; SSE2-NEXT: orq $128, %rcx
-; SSE2-NEXT: orq %r8, %rdx
-; SSE2-NEXT: cmovneq %r10, %rcx
+; SSE2-NEXT: bsrq %rcx, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %rdx, %r9
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: addb $64, %r9b
+; SSE2-NEXT: movzbl %r9b, %r9d
+; SSE2-NEXT: testq %rcx, %rcx
+; SSE2-NEXT: cmovnel %r10d, %r9d
+; SSE2-NEXT: bsrq %rsi, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %r8, %r8
+; SSE2-NEXT: xorl $63, %r8d
+; SSE2-NEXT: addb $64, %r8b
+; SSE2-NEXT: movzbl %r8b, %r8d
+; SSE2-NEXT: testq %rsi, %rsi
+; SSE2-NEXT: cmovnel %r10d, %r8d
+; SSE2-NEXT: addb $-128, %r8b
+; SSE2-NEXT: orq %rcx, %rdx
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
-; SSE2-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE2-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movzbl %r8b, %ecx
+; SSE2-NEXT: cmovnel %r9d, %ecx
; SSE2-NEXT: movl %ecx, %edx
; SSE2-NEXT: shrb $6, %dl
; SSE2-NEXT: movzbl %dl, %esi
@@ -3027,7 +3054,7 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; SSE2-NEXT: shrdq %cl, %r8, %r11
; SSE2-NEXT: movq -72(%rsp,%rsi,8), %rsi
; SSE2-NEXT: shrq %cl, %rdx
-; SSE2-NEXT: # kill: def $cl killed $cl killed $rcx
+; SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; SSE2-NEXT: shrdq %cl, %r10, %rsi
; SSE2-NEXT: xorl %ecx, %ecx
; SSE2-NEXT: testl %eax, %eax
@@ -3044,125 +3071,153 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
;
; SSE42-LABEL: isolate_msb_i256_load:
; SSE42: # %bb.0:
-; SSE42-NEXT: movq 16(%rsi), %rax
-; SSE42-NEXT: movq 24(%rsi), %rdx
-; SSE42-NEXT: movdqa (%rsi), %xmm0
-; SSE42-NEXT: por 16(%rsi), %xmm0
-; SSE42-NEXT: bsrq %rdx, %rcx
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: bsrq %rax, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: orq $64, %r8
-; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rcx, %r8
-; SSE42-NEXT: movq 8(%rsi), %r9
-; SSE42-NEXT: bsrq %r9, %r10
-; SSE42-NEXT: bsrq (%rsi), %rcx
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: orq $64, %rcx
-; SSE42-NEXT: testq %r9, %r9
-; SSE42-NEXT: cmovneq %r10, %rcx
-; SSE42-NEXT: orq $128, %rcx
-; SSE42-NEXT: orq %rdx, %rax
-; SSE42-NEXT: cmovneq %r8, %rcx
+; SSE42-NEXT: pushq %rbx
+; SSE42-NEXT: movq 24(%rsi), %r8
+; SSE42-NEXT: movq 16(%rsi), %rcx
+; SSE42-NEXT: movq (%rsi), %rdx
+; SSE42-NEXT: movq 8(%rsi), %rax
+; SSE42-NEXT: bsrq %r8, %r9
+; SSE42-NEXT: xorl $63, %r9d
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: addb $64, %sil
+; SSE42-NEXT: movzbl %sil, %esi
+; SSE42-NEXT: testq %r8, %r8
+; SSE42-NEXT: cmovnel %r9d, %esi
+; SSE42-NEXT: bsrq %rax, %r9
+; SSE42-NEXT: xorl $63, %r9d
+; SSE42-NEXT: bsrq %rdx, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: addb $64, %r10b
+; SSE42-NEXT: movzbl %r10b, %r10d
+; SSE42-NEXT: testq %rax, %rax
+; SSE42-NEXT: cmovnel %r9d, %r10d
+; SSE42-NEXT: movq %rcx, %xmm0
+; SSE42-NEXT: addb $-128, %r10b
+; SSE42-NEXT: orq %r8, %rcx
; SSE42-NEXT: xorps %xmm1, %xmm1
; SSE42-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; SSE42-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE42-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movl %ecx, %eax
-; SSE42-NEXT: shrb $6, %al
-; SSE42-NEXT: movzbl %al, %eax
+; SSE42-NEXT: movzbl %r10b, %ecx
+; SSE42-NEXT: cmovnel %esi, %ecx
+; SSE42-NEXT: movl %ecx, %esi
+; SSE42-NEXT: shrb $6, %sil
+; SSE42-NEXT: movzbl %sil, %r10d
; SSE42-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movq -48(%rsp,%rax,8), %rdx
-; SSE42-NEXT: movq -56(%rsp,%rax,8), %rsi
-; SSE42-NEXT: movq %rsi, %r8
-; SSE42-NEXT: shrdq %cl, %rdx, %r8
-; SSE42-NEXT: movq -64(%rsp,%rax,8), %r9
-; SSE42-NEXT: movq %r9, %r10
-; SSE42-NEXT: shrdq %cl, %rsi, %r10
-; SSE42-NEXT: movq -72(%rsp,%rax,8), %rsi
-; SSE42-NEXT: shrq %cl, %rdx
-; SSE42-NEXT: # kill: def $cl killed $cl killed $rcx
-; SSE42-NEXT: shrdq %cl, %r9, %rsi
+; SSE42-NEXT: movq -40(%rsp,%r10,8), %rsi
+; SSE42-NEXT: movq -48(%rsp,%r10,8), %r11
+; SSE42-NEXT: movq %r11, %r9
+; SSE42-NEXT: shrdq %cl, %rsi, %r9
+; SSE42-NEXT: movq %r8, %xmm1
+; SSE42-NEXT: movq -56(%rsp,%r10,8), %r8
+; SSE42-NEXT: movq %r8, %rbx
+; SSE42-NEXT: shrdq %cl, %r11, %rbx
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE42-NEXT: movq %rdx, %xmm1
+; SSE42-NEXT: movq -64(%rsp,%r10,8), %rdx
+; SSE42-NEXT: shrq %cl, %rsi
+; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE42-NEXT: shrdq %cl, %r8, %rdx
+; SSE42-NEXT: movq %rax, %xmm2
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE42-NEXT: por %xmm0, %xmm1
; SSE42-NEXT: xorl %ecx, %ecx
-; SSE42-NEXT: ptest %xmm0, %xmm0
-; SSE42-NEXT: cmoveq %rcx, %r10
-; SSE42-NEXT: cmoveq %rcx, %r8
-; SSE42-NEXT: cmoveq %rcx, %rsi
-; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: ptest %xmm1, %xmm1
+; SSE42-NEXT: cmoveq %rcx, %rbx
+; SSE42-NEXT: cmoveq %rcx, %r9
; SSE42-NEXT: cmoveq %rcx, %rdx
-; SSE42-NEXT: movq %rdx, 24(%rdi)
-; SSE42-NEXT: movq %r8, 16(%rdi)
-; SSE42-NEXT: movq %r10, 8(%rdi)
-; SSE42-NEXT: movq %rsi, (%rdi)
+; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: cmoveq %rcx, %rsi
+; SSE42-NEXT: movq %rsi, 24(%rdi)
+; SSE42-NEXT: movq %r9, 16(%rdi)
+; SSE42-NEXT: movq %rbx, 8(%rdi)
+; SSE42-NEXT: movq %rdx, (%rdi)
+; SSE42-NEXT: popq %rbx
; SSE42-NEXT: retq
;
; AVX2-LABEL: isolate_msb_i256_load:
; AVX2: # %bb.0:
-; AVX2-NEXT: movq 16(%rsi), %rax
-; AVX2-NEXT: movq 24(%rsi), %rdx
-; AVX2-NEXT: lzcntq %rdx, %rcx
-; AVX2-NEXT: lzcntq %rax, %r8
-; AVX2-NEXT: addq $64, %r8
-; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %rcx, %r8
-; AVX2-NEXT: movq 8(%rsi), %r9
-; AVX2-NEXT: lzcntq %r9, %r10
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: lzcntq (%rsi), %rcx
-; AVX2-NEXT: addq $64, %rcx
-; AVX2-NEXT: testq %r9, %r9
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
-; AVX2-NEXT: orq %rdx, %rax
-; AVX2-NEXT: cmovneq %r8, %rcx
-; AVX2-NEXT: vmovdqu (%rsi), %ymm0
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: movq 24(%rsi), %rcx
+; AVX2-NEXT: vmovq %rcx, %xmm0
+; AVX2-NEXT: movq 16(%rsi), %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX2-NEXT: movq (%rsi), %rdi
+; AVX2-NEXT: movq 8(%rsi), %rsi
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %ecx, %eax
-; AVX2-NEXT: shrb $6, %al
-; AVX2-NEXT: movzbl %al, %edx
+; AVX2-NEXT: vmovq %rsi, %xmm1
+; AVX2-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovq %rdi, %xmm2
+; AVX2-NEXT: lzcntq %rcx, %r8
+; AVX2-NEXT: lzcntq %rdx, %r9
+; AVX2-NEXT: addb $64, %r9b
+; AVX2-NEXT: movzbl %r9b, %r9d
+; AVX2-NEXT: testq %rcx, %rcx
+; AVX2-NEXT: cmovnel %r8d, %r9d
+; AVX2-NEXT: xorl %r8d, %r8d
+; AVX2-NEXT: lzcntq %rsi, %r8
+; AVX2-NEXT: lzcntq %rdi, %rdi
+; AVX2-NEXT: addb $64, %dil
+; AVX2-NEXT: movzbl %dil, %edi
+; AVX2-NEXT: testq %rsi, %rsi
+; AVX2-NEXT: cmovnel %r8d, %edi
+; AVX2-NEXT: addb $-128, %dil
+; AVX2-NEXT: orq %rcx, %rdx
+; AVX2-NEXT: movzbl %dil, %ecx
+; AVX2-NEXT: cmovnel %r9d, %ecx
+; AVX2-NEXT: movl %ecx, %edx
+; AVX2-NEXT: shrb $6, %dl
+; AVX2-NEXT: movzbl %dl, %edx
; AVX2-NEXT: movq -48(%rsp,%rdx,8), %rsi
-; AVX2-NEXT: movq -56(%rsp,%rdx,8), %r8
-; AVX2-NEXT: movq %r8, %r9
-; AVX2-NEXT: shrdq %cl, %rsi, %r9
-; AVX2-NEXT: movq %rdi, %rax
-; AVX2-NEXT: movq -72(%rsp,%rdx,8), %rdi
+; AVX2-NEXT: movq -56(%rsp,%rdx,8), %rdi
+; AVX2-NEXT: movq %rdi, %r8
+; AVX2-NEXT: shrdq %cl, %rsi, %r8
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-NEXT: movq -72(%rsp,%rdx,8), %r9
; AVX2-NEXT: movq -64(%rsp,%rdx,8), %rdx
; AVX2-NEXT: movq %rdx, %r10
-; AVX2-NEXT: shrdq %cl, %r8, %r10
-; AVX2-NEXT: shrdq %cl, %rdx, %rdi
+; AVX2-NEXT: shrdq %cl, %rdi, %r10
+; AVX2-NEXT: shrdq %cl, %rdx, %r9
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: vptest %ymm0, %ymm0
; AVX2-NEXT: shrxq %rcx, %rsi, %rcx
; AVX2-NEXT: cmoveq %rdx, %r10
+; AVX2-NEXT: cmoveq %rdx, %r8
; AVX2-NEXT: cmoveq %rdx, %r9
-; AVX2-NEXT: cmoveq %rdx, %rdi
; AVX2-NEXT: cmoveq %rdx, %rcx
; AVX2-NEXT: movq %rcx, 24(%rax)
-; AVX2-NEXT: movq %r9, 16(%rax)
+; AVX2-NEXT: movq %r8, 16(%rax)
; AVX2-NEXT: movq %r10, 8(%rax)
-; AVX2-NEXT: movq %rdi, (%rax)
+; AVX2-NEXT: movq %r9, (%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512F-LABEL: isolate_msb_i256_load:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovdqu (%rsi), %ymm0
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,9223372036854775808,0,0,0,0]
-; AVX512F-NEXT: vmovups %zmm1, -{{[0-9]+}}(%rsp)
-; AVX512F-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
+; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; AVX512F-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; AVX512F-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; AVX512F-NEXT: vmovdqa (%rsi), %xmm0
+; AVX512F-NEXT: vinserti128 $1, 16(%rsi), %ymm0, %ymm0
+; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX512F-NEXT: vplzcntq %zmm1, %zmm2
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [0,64,128,192]
; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0
-; AVX512F-NEXT: vplzcntq %zmm1, %zmm1
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
-; AVX512F-NEXT: vpcompressq %zmm1, %zmm1 {%k1} {z}
+; AVX512F-NEXT: vpcompressq %zmm2, %zmm1 {%k1}
+; AVX512F-NEXT: vmovaps {{.*#+}} zmm2 = [0,0,0,9223372036854775808,0,0,0,0]
+; AVX512F-NEXT: vmovups %zmm2, -{{[0-9]+}}(%rsp)
; AVX512F-NEXT: vmovd %xmm1, %ecx
; AVX512F-NEXT: movl %ecx, %eax
; AVX512F-NEXT: shrb $6, %al
@@ -3198,7 +3253,7 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; AVX512VL-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VL-NEXT: vplzcntq %ymm1, %ymm1
; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
-; AVX512VL-NEXT: vpcompressq %ymm1, %ymm1 {%k1} {z}
+; AVX512VL-NEXT: vpcompressq %ymm1, %ymm1 {%k1}
; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,0,9223372036854775808]
; AVX512VL-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
; AVX512VL-NEXT: vxorps %xmm2, %xmm2, %xmm2
@@ -3238,7 +3293,7 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; AVX512VBMI-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VBMI-NEXT: vplzcntq %ymm1, %ymm1
; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
-; AVX512VBMI-NEXT: vpcompressq %ymm1, %ymm1 {%k1} {z}
+; AVX512VBMI-NEXT: vpcompressq %ymm1, %ymm1 {%k1}
; AVX512VBMI-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,0,9223372036854775808]
; AVX512VBMI-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
; AVX512VBMI-NEXT: vxorps %xmm2, %xmm2, %xmm2
diff --git a/llvm/test/CodeGen/X86/bit-manip-i512.ll b/llvm/test/CodeGen/X86/bit-manip-i512.ll
index 9e4d00650e613..064da412e9167 100644
--- a/llvm/test/CodeGen/X86/bit-manip-i512.ll
+++ b/llvm/test/CodeGen/X86/bit-manip-i512.ll
@@ -4105,58 +4105,57 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; SSE-NEXT: pushq %r12
; SSE-NEXT: pushq %rbx
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; SSE-NEXT: movq %r8, %r10
; SSE-NEXT: orq %r14, %r10
; SSE-NEXT: movq %rdx, %rax
-; SSE-NEXT: orq %r11, %rax
+; SSE-NEXT: orq %rbx, %rax
; SSE-NEXT: orq %r10, %rax
-; SSE-NEXT: movq %rcx, %r15
-; SSE-NEXT: orq %rbx, %r15
-; SSE-NEXT: movq %rsi, %r10
-; SSE-NEXT: orq %r9, %r10
+; SSE-NEXT: movq %rsi, %r15
+; SSE-NEXT: orq %r9, %r15
+; SSE-NEXT: movq %rcx, %r10
+; SSE-NEXT: orq %r11, %r10
; SSE-NEXT: orq %r15, %r10
; SSE-NEXT: bsrq %r14, %r15
-; SSE-NEXT: xorq $63, %r15
-; SSE-NEXT: bsrq %rbx, %r12
-; SSE-NEXT: xorq $63, %r12
-; SSE-NEXT: orq $64, %r12
+; SSE-NEXT: xorl $63, %r15d
+; SSE-NEXT: bsrq %r11, %r12
+; SSE-NEXT: xorl $63, %r12d
+; SSE-NEXT: addl $64, %r12d
; SSE-NEXT: testq %r14, %r14
-; SSE-NEXT: cmovneq %r15, %r12
-; SSE-NEXT: bsrq %r11, %r13
-; SSE-NEXT: xorq $63, %r13
+; SSE-NEXT: cmovnel %r15d, %r12d
+; SSE-NEXT: bsrq %rbx, %r13
+; SSE-NEXT: xorl $63, %r13d
; SSE-NEXT: bsrq %r9, %r15
-; SSE-NEXT: xorq $63, %r15
-; SSE-NEXT: orq $64, %r15
-; SSE-NEXT: testq %r11, %r11
-; SSE-NEXT: cmovneq %r13, %r15
-; SSE-NEXT: orq $128, %r15
-; SSE-NEXT: movq %rbx, %r13
+; SSE-NEXT: xorl $63, %r15d
+; SSE-NEXT: addl $64, %r15d
+; SSE-NEXT: testq %rbx, %rbx
+; SSE-NEXT: cmovnel %r13d, %r15d
+; SSE-NEXT: subl $-128, %r15d
+; SSE-NEXT: movq %r11, %r13
; SSE-NEXT: orq %r14, %r13
-; SSE-NEXT: cmovneq %r12, %r15
+; SSE-NEXT: cmovnel %r12d, %r15d
; SSE-NEXT: bsrq %r8, %r12
-; SSE-NEXT: xorq $63, %r12
+; SSE-NEXT: xorl $63, %r12d
; SSE-NEXT: bsrq %rcx, %r13
-; SSE-NEXT: xorq $63, %r13
-; SSE-NEXT: orq $64, %r13
+; SSE-NEXT: xorl $63, %r13d
+; SSE-NEXT: addl $64, %r13d
; SSE-NEXT: testq %r8, %r8
-; SSE-NEXT: cmovneq %r12, %r13
+; SSE-NEXT: cmovnel %r12d, %r13d
; SSE-NEXT: bsrq %rdx, %r12
-; SSE-NEXT: xorq $63, %r12
+; SSE-NEXT: xorl $63, %r12d
; SSE-NEXT: bsrq %rsi, %rsi
-; SSE-NEXT: xorq $63, %rsi
-; SSE-NEXT: orq $64, %rsi
+; SSE-NEXT: xorl $63, %esi
+; SSE-NEXT: addl $64, %esi
; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovneq %r12, %rsi
-; SSE-NEXT: orq $128, %rsi
+; SSE-NEXT: cmovnel %r12d, %esi
+; SSE-NEXT: subl $-128, %esi
; SSE-NEXT: orq %r8, %rcx
-; SSE-NEXT: cmovneq %r13, %rsi
-; SSE-NEXT: orq $256, %rsi # imm = 0x100
-; SSE-NEXT: orq %r14, %r11
-; SSE-NEXT: orq %rbx, %r9
+; SSE-NEXT: cmovnel %r13d, %esi
+; SSE-NEXT: addl $256, %esi # imm = 0x100
+; SSE-NEXT: orq %r14, %rbx
; SSE-NEXT: orq %r11, %r9
-; SSE-NEXT: cmovneq %r15, %rsi
+; SSE-NEXT: orq %rbx, %r9
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
@@ -4167,6 +4166,7 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE-NEXT: cmovnel %r15d, %esi
; SSE-NEXT: movl %esi, %ecx
; SSE-NEXT: andl $63, %ecx
; SSE-NEXT: shrl $3, %esi
@@ -4223,124 +4223,119 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
;
; AVX2-LABEL: isolate_msb_i512:
; AVX2: # %bb.0:
-; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: pushq %rax
; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r14
-; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; AVX2-NEXT: movq %r8, %rax
-; AVX2-NEXT: orq %r15, %rax
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; AVX2-NEXT: movq %r8, %r11
+; AVX2-NEXT: orq %r14, %r11
; AVX2-NEXT: movq %rdx, %r10
-; AVX2-NEXT: orq %rbx, %r10
; AVX2-NEXT: orq %rax, %r10
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: orq %r14, %rax
-; AVX2-NEXT: movq %rsi, %r11
-; AVX2-NEXT: orq %r9, %r11
-; AVX2-NEXT: orq %rax, %r11
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %r15, %rax
+; AVX2-NEXT: orq %r11, %r10
+; AVX2-NEXT: movq %rsi, %r15
+; AVX2-NEXT: orq %r9, %r15
+; AVX2-NEXT: movq %rcx, %r11
+; AVX2-NEXT: orq %rbx, %r11
+; AVX2-NEXT: orq %r15, %r11
+; AVX2-NEXT: xorl %r15d, %r15d
+; AVX2-NEXT: lzcntq %r14, %r15
+; AVX2-NEXT: xorl %r12d, %r12d
+; AVX2-NEXT: lzcntq %rbx, %r12
+; AVX2-NEXT: addl $64, %r12d
+; AVX2-NEXT: testq %r14, %r14
+; AVX2-NEXT: cmovnel %r15d, %r12d
; AVX2-NEXT: xorl %r13d, %r13d
-; AVX2-NEXT: lzcntq %r14, %r13
-; AVX2-NEXT: addq $64, %r13
-; AVX2-NEXT: testq %r15, %r15
-; AVX2-NEXT: cmovneq %rax, %r13
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %rbx, %rax
+; AVX2-NEXT: lzcntq %rax, %r13
+; AVX2-NEXT: xorl %r15d, %r15d
+; AVX2-NEXT: lzcntq %r9, %r15
+; AVX2-NEXT: addl $64, %r15d
+; AVX2-NEXT: testq %rax, %rax
+; AVX2-NEXT: cmovnel %r13d, %r15d
+; AVX2-NEXT: subl $-128, %r15d
+; AVX2-NEXT: movq %rbx, %r13
+; AVX2-NEXT: orq %r14, %r13
+; AVX2-NEXT: cmovnel %r12d, %r15d
; AVX2-NEXT: xorl %r12d, %r12d
-; AVX2-NEXT: lzcntq %r9, %r12
-; AVX2-NEXT: addq $64, %r12
-; AVX2-NEXT: testq %rbx, %rbx
-; AVX2-NEXT: cmovneq %rax, %r12
-; AVX2-NEXT: subq $-128, %r12
-; AVX2-NEXT: movq %r14, %rax
-; AVX2-NEXT: orq %r15, %rax
-; AVX2-NEXT: cmovneq %r13, %r12
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %r8, %rax
+; AVX2-NEXT: lzcntq %r8, %r12
; AVX2-NEXT: xorl %r13d, %r13d
; AVX2-NEXT: lzcntq %rcx, %r13
-; AVX2-NEXT: addq $64, %r13
+; AVX2-NEXT: addl $64, %r13d
; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %rax, %r13
-; AVX2-NEXT: xorl %ebp, %ebp
-; AVX2-NEXT: lzcntq %rdx, %rbp
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %rsi, %rax
-; AVX2-NEXT: addq $64, %rax
+; AVX2-NEXT: cmovnel %r12d, %r13d
+; AVX2-NEXT: xorl %r12d, %r12d
+; AVX2-NEXT: lzcntq %rdx, %r12
+; AVX2-NEXT: lzcntq %rsi, %rsi
+; AVX2-NEXT: addl $64, %esi
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %rbp, %rax
-; AVX2-NEXT: subq $-128, %rax
+; AVX2-NEXT: cmovnel %r12d, %esi
+; AVX2-NEXT: subl $-128, %esi
; AVX2-NEXT: orq %r8, %rcx
-; AVX2-NEXT: cmovneq %r13, %rax
-; AVX2-NEXT: addq $256, %rax # imm = 0x100
-; AVX2-NEXT: orq %r15, %rbx
-; AVX2-NEXT: orq %r14, %r9
-; AVX2-NEXT: orq %rbx, %r9
-; AVX2-NEXT: cmovneq %r12, %rax
+; AVX2-NEXT: cmovnel %r13d, %esi
+; AVX2-NEXT: addl $256, %esi # imm = 0x100
+; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: orq %rbx, %r9
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %eax, %ecx
+; AVX2-NEXT: orq %rax, %r9
+; AVX2-NEXT: cmovnel %r15d, %esi
+; AVX2-NEXT: movl %esi, %ecx
; AVX2-NEXT: andl $63, %ecx
-; AVX2-NEXT: shrl $3, %eax
-; AVX2-NEXT: andl $56, %eax
-; AVX2-NEXT: movq -72(%rsp,%rax), %rbx
-; AVX2-NEXT: movq -80(%rsp,%rax), %r8
-; AVX2-NEXT: movq %r8, %rdx
-; AVX2-NEXT: shrdq %cl, %rbx, %rdx
-; AVX2-NEXT: movq -88(%rsp,%rax), %r9
-; AVX2-NEXT: movq %r9, %rsi
-; AVX2-NEXT: shrdq %cl, %r8, %rsi
-; AVX2-NEXT: movq -96(%rsp,%rax), %r14
-; AVX2-NEXT: movq %r14, %r8
-; AVX2-NEXT: shrdq %cl, %r9, %r8
-; AVX2-NEXT: movq -104(%rsp,%rax), %r15
-; AVX2-NEXT: movq %r15, %r9
-; AVX2-NEXT: shrdq %cl, %r14, %r9
-; AVX2-NEXT: movq -112(%rsp,%rax), %r13
-; AVX2-NEXT: movq %r13, %r14
-; AVX2-NEXT: shrdq %cl, %r15, %r14
-; AVX2-NEXT: movq -128(%rsp,%rax), %r15
-; AVX2-NEXT: movq -120(%rsp,%rax), %rax
-; AVX2-NEXT: movq %rax, %r12
+; AVX2-NEXT: shrl $3, %esi
+; AVX2-NEXT: andl $56, %esi
+; AVX2-NEXT: movq -72(%rsp,%rsi), %r14
+; AVX2-NEXT: movq -80(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %rdx
+; AVX2-NEXT: shrdq %cl, %r14, %rdx
+; AVX2-NEXT: movq -88(%rsp,%rsi), %rbx
+; AVX2-NEXT: movq %rbx, %r8
+; AVX2-NEXT: shrdq %cl, %rax, %r8
+; AVX2-NEXT: movq -96(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %r9
+; AVX2-NEXT: shrdq %cl, %rbx, %r9
+; AVX2-NEXT: movq -104(%rsp,%rsi), %r12
+; AVX2-NEXT: movq %r12, %rbx
+; AVX2-NEXT: shrdq %cl, %rax, %rbx
+; AVX2-NEXT: movq -112(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %r15
+; AVX2-NEXT: shrdq %cl, %r12, %r15
+; AVX2-NEXT: movq -128(%rsp,%rsi), %r12
+; AVX2-NEXT: movq -120(%rsp,%rsi), %r13
+; AVX2-NEXT: movq %r13, %rsi
+; AVX2-NEXT: shrdq %cl, %rax, %rsi
; AVX2-NEXT: shrdq %cl, %r13, %r12
-; AVX2-NEXT: shrdq %cl, %rax, %r15
; AVX2-NEXT: movq %rdi, %rax
; AVX2-NEXT: xorl %edi, %edi
; AVX2-NEXT: orq %r10, %r11
-; AVX2-NEXT: shrxq %rcx, %rbx, %rcx
-; AVX2-NEXT: cmoveq %rdi, %r12
-; AVX2-NEXT: cmoveq %rdi, %r14
+; AVX2-NEXT: shrxq %rcx, %r14, %rcx
+; AVX2-NEXT: cmoveq %rdi, %rsi
+; AVX2-NEXT: cmoveq %rdi, %r15
+; AVX2-NEXT: cmoveq %rdi, %rbx
; AVX2-NEXT: cmoveq %rdi, %r9
; AVX2-NEXT: cmoveq %rdi, %r8
-; AVX2-NEXT: cmoveq %rdi, %rsi
; AVX2-NEXT: cmoveq %rdi, %rdx
-; AVX2-NEXT: cmoveq %rdi, %r15
+; AVX2-NEXT: cmoveq %rdi, %r12
; AVX2-NEXT: cmoveq %rdi, %rcx
; AVX2-NEXT: movq %rcx, 56(%rax)
; AVX2-NEXT: movq %rdx, 48(%rax)
-; AVX2-NEXT: movq %rsi, 40(%rax)
-; AVX2-NEXT: movq %r8, 32(%rax)
-; AVX2-NEXT: movq %r9, 24(%rax)
-; AVX2-NEXT: movq %r14, 16(%rax)
-; AVX2-NEXT: movq %r12, 8(%rax)
-; AVX2-NEXT: movq %r15, (%rax)
-; AVX2-NEXT: addq $8, %rsp
+; AVX2-NEXT: movq %r8, 40(%rax)
+; AVX2-NEXT: movq %r9, 32(%rax)
+; AVX2-NEXT: movq %rbx, 24(%rax)
+; AVX2-NEXT: movq %r15, 16(%rax)
+; AVX2-NEXT: movq %rsi, 8(%rax)
+; AVX2-NEXT: movq %r12, (%rax)
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13
; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15
-; AVX2-NEXT: popq %rbp
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -4517,49 +4512,48 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE2-NEXT: movmskps %xmm0, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: bsrq %rbx, %r14
-; SSE2-NEXT: xorq $63, %r14
+; SSE2-NEXT: xorl $63, %r14d
; SSE2-NEXT: bsrq %r10, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: addl $64, %r10d
; SSE2-NEXT: testq %rbx, %rbx
-; SSE2-NEXT: cmovneq %r14, %r10
+; SSE2-NEXT: cmovnel %r14d, %r10d
; SSE2-NEXT: bsrq %r11, %rbx
-; SSE2-NEXT: xorq $63, %rbx
+; SSE2-NEXT: xorl $63, %ebx
; SSE2-NEXT: bsrq %r9, %r9
-; SSE2-NEXT: xorq $63, %r9
-; SSE2-NEXT: orq $64, %r9
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: addl $64, %r9d
; SSE2-NEXT: testq %r11, %r11
-; SSE2-NEXT: cmovneq %rbx, %r9
-; SSE2-NEXT: orq $128, %r9
+; SSE2-NEXT: cmovnel %ebx, %r9d
+; SSE2-NEXT: subl $-128, %r9d
; SSE2-NEXT: por %xmm3, %xmm2
; SSE2-NEXT: pcmpeqd %xmm4, %xmm3
; SSE2-NEXT: movmskps %xmm3, %r11d
; SSE2-NEXT: xorl $15, %r11d
-; SSE2-NEXT: cmovneq %r10, %r9
+; SSE2-NEXT: cmovnel %r10d, %r9d
; SSE2-NEXT: bsrq %rsi, %r10
-; SSE2-NEXT: xorq $63, %r10
+; SSE2-NEXT: xorl $63, %r10d
; SSE2-NEXT: bsrq %r8, %r8
-; SSE2-NEXT: xorq $63, %r8
-; SSE2-NEXT: orq $64, %r8
+; SSE2-NEXT: xorl $63, %r8d
+; SSE2-NEXT: addl $64, %r8d
; SSE2-NEXT: testq %rsi, %rsi
-; SSE2-NEXT: cmovneq %r10, %r8
+; SSE2-NEXT: cmovnel %r10d, %r8d
; SSE2-NEXT: bsrq %rcx, %rsi
-; SSE2-NEXT: xorq $63, %rsi
+; SSE2-NEXT: xorl $63, %esi
; SSE2-NEXT: bsrq %rdx, %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: orq $64, %rdx
+; SSE2-NEXT: xorl $63, %edx
+; SSE2-NEXT: addl $64, %edx
; SSE2-NEXT: testq %rcx, %rcx
-; SSE2-NEXT: cmovneq %rsi, %rdx
-; SSE2-NEXT: orq $128, %rdx
+; SSE2-NEXT: cmovnel %esi, %edx
+; SSE2-NEXT: subl $-128, %edx
; SSE2-NEXT: pcmpeqd %xmm4, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r8, %rdx
-; SSE2-NEXT: orq $256, %rdx # imm = 0x100
+; SSE2-NEXT: cmovnel %r8d, %edx
+; SSE2-NEXT: addl $256, %edx # imm = 0x100
; SSE2-NEXT: pcmpeqd %xmm4, %xmm2
; SSE2-NEXT: movmskps %xmm2, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r9, %rdx
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
@@ -4569,6 +4563,7 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: cmovnel %r9d, %edx
; SSE2-NEXT: movl %edx, %ecx
; SSE2-NEXT: andl $63, %ecx
; SSE2-NEXT: shrl $3, %edx
@@ -4630,51 +4625,50 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE42-NEXT: pushq %rbx
; SSE42-NEXT: movq %xmm0, %rax
; SSE42-NEXT: pextrq $1, %xmm0, %rcx
-; SSE42-NEXT: pextrq $1, %xmm1, %rdx
+; SSE42-NEXT: pextrq $1, %xmm1, %rsi
; SSE42-NEXT: movq %xmm1, %r8
-; SSE42-NEXT: movq %xmm2, %rsi
+; SSE42-NEXT: movq %xmm2, %rdx
; SSE42-NEXT: pextrq $1, %xmm2, %r9
; SSE42-NEXT: movq %xmm3, %r10
; SSE42-NEXT: pextrq $1, %xmm3, %r11
; SSE42-NEXT: bsrq %r11, %rbx
-; SSE42-NEXT: xorq $63, %rbx
+; SSE42-NEXT: xorl $63, %ebx
; SSE42-NEXT: bsrq %r10, %r10
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: orq $64, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: addl $64, %r10d
; SSE42-NEXT: testq %r11, %r11
-; SSE42-NEXT: cmovneq %rbx, %r10
+; SSE42-NEXT: cmovnel %ebx, %r10d
; SSE42-NEXT: bsrq %r9, %r11
-; SSE42-NEXT: xorq $63, %r11
-; SSE42-NEXT: bsrq %rsi, %rsi
-; SSE42-NEXT: xorq $63, %rsi
-; SSE42-NEXT: orq $64, %rsi
+; SSE42-NEXT: xorl $63, %r11d
+; SSE42-NEXT: bsrq %rdx, %rdx
+; SSE42-NEXT: xorl $63, %edx
+; SSE42-NEXT: addl $64, %edx
; SSE42-NEXT: testq %r9, %r9
-; SSE42-NEXT: cmovneq %r11, %rsi
-; SSE42-NEXT: orq $128, %rsi
+; SSE42-NEXT: cmovnel %r11d, %edx
+; SSE42-NEXT: subl $-128, %edx
; SSE42-NEXT: ptest %xmm3, %xmm3
-; SSE42-NEXT: cmovneq %r10, %rsi
-; SSE42-NEXT: bsrq %rdx, %r9
-; SSE42-NEXT: xorq $63, %r9
+; SSE42-NEXT: cmovnel %r10d, %edx
+; SSE42-NEXT: bsrq %rsi, %r9
+; SSE42-NEXT: xorl $63, %r9d
; SSE42-NEXT: bsrq %r8, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: orq $64, %r8
-; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %r9, %r8
-; SSE42-NEXT: bsrq %rcx, %rdx
-; SSE42-NEXT: xorq $63, %rdx
+; SSE42-NEXT: xorl $63, %r8d
+; SSE42-NEXT: addl $64, %r8d
+; SSE42-NEXT: testq %rsi, %rsi
+; SSE42-NEXT: cmovnel %r9d, %r8d
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
; SSE42-NEXT: bsrq %rax, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
+; SSE42-NEXT: xorl $63, %eax
+; SSE42-NEXT: addl $64, %eax
; SSE42-NEXT: testq %rcx, %rcx
-; SSE42-NEXT: cmovneq %rdx, %rax
-; SSE42-NEXT: por %xmm2, %xmm0
-; SSE42-NEXT: orq $128, %rax
+; SSE42-NEXT: cmovnel %esi, %eax
+; SSE42-NEXT: subl $-128, %eax
; SSE42-NEXT: ptest %xmm1, %xmm1
-; SSE42-NEXT: cmovneq %r8, %rax
-; SSE42-NEXT: orq $256, %rax # imm = 0x100
+; SSE42-NEXT: por %xmm2, %xmm0
+; SSE42-NEXT: cmovnel %r8d, %eax
+; SSE42-NEXT: addl $256, %eax # imm = 0x100
; SSE42-NEXT: por %xmm3, %xmm2
; SSE42-NEXT: ptest %xmm2, %xmm2
-; SSE42-NEXT: cmovneq %rsi, %rax
; SSE42-NEXT: pxor %xmm2, %xmm2
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
@@ -4685,6 +4679,7 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: cmovnel %edx, %eax
; SSE42-NEXT: movl %eax, %ecx
; SSE42-NEXT: andl $63, %ecx
; SSE42-NEXT: shrl $3, %eax
@@ -4745,56 +4740,56 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: vpextrq $1, %xmm0, %rsi
+; AVX2-NEXT: vmovq %xmm0, %rdx
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX2-NEXT: vmovq %xmm2, %rax
-; AVX2-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX2-NEXT: vmovq %xmm1, %rdx
+; AVX2-NEXT: vpextrq $1, %xmm2, %rax
+; AVX2-NEXT: vmovq %xmm2, %rcx
+; AVX2-NEXT: vmovq %xmm1, %r8
; AVX2-NEXT: vpextrq $1, %xmm1, %r9
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vmovq %xmm2, %r10
; AVX2-NEXT: vpextrq $1, %xmm2, %r11
-; AVX2-NEXT: lzcntq %r11, %r8
; AVX2-NEXT: xorl %ebx, %ebx
-; AVX2-NEXT: lzcntq %r10, %rbx
-; AVX2-NEXT: addq $64, %rbx
-; AVX2-NEXT: testq %r11, %r11
-; AVX2-NEXT: cmovneq %r8, %rbx
+; AVX2-NEXT: lzcntq %r11, %rbx
; AVX2-NEXT: xorl %r14d, %r14d
-; AVX2-NEXT: lzcntq %r9, %r14
-; AVX2-NEXT: xorl %r8d, %r8d
-; AVX2-NEXT: lzcntq %rdx, %r8
-; AVX2-NEXT: addq $64, %r8
+; AVX2-NEXT: lzcntq %r10, %r14
+; AVX2-NEXT: addl $64, %r14d
+; AVX2-NEXT: testq %r11, %r11
+; AVX2-NEXT: cmovnel %ebx, %r14d
+; AVX2-NEXT: xorl %ebx, %ebx
+; AVX2-NEXT: lzcntq %r9, %rbx
+; AVX2-NEXT: lzcntq %r8, %r8
+; AVX2-NEXT: addl $64, %r8d
; AVX2-NEXT: testq %r9, %r9
-; AVX2-NEXT: cmovneq %r14, %r8
-; AVX2-NEXT: subq $-128, %r8
+; AVX2-NEXT: cmovnel %ebx, %r8d
+; AVX2-NEXT: subl $-128, %r8d
; AVX2-NEXT: orq %r11, %r10
-; AVX2-NEXT: cmovneq %rbx, %r8
-; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: lzcntq %rcx, %rdx
+; AVX2-NEXT: cmovnel %r14d, %r8d
; AVX2-NEXT: xorl %r9d, %r9d
; AVX2-NEXT: lzcntq %rax, %r9
-; AVX2-NEXT: addq $64, %r9
-; AVX2-NEXT: testq %rcx, %rcx
-; AVX2-NEXT: cmovneq %rdx, %r9
-; AVX2-NEXT: vmovq %xmm0, %rdx
; AVX2-NEXT: xorl %r10d, %r10d
-; AVX2-NEXT: lzcntq %rsi, %r10
+; AVX2-NEXT: lzcntq %rcx, %r10
+; AVX2-NEXT: addl $64, %r10d
+; AVX2-NEXT: testq %rax, %rax
+; AVX2-NEXT: cmovnel %r9d, %r10d
+; AVX2-NEXT: xorl %r9d, %r9d
+; AVX2-NEXT: lzcntq %rsi, %r9
; AVX2-NEXT: lzcntq %rdx, %rdx
-; AVX2-NEXT: addq $64, %rdx
+; AVX2-NEXT: addl $64, %edx
; AVX2-NEXT: testq %rsi, %rsi
-; AVX2-NEXT: cmovneq %r10, %rdx
-; AVX2-NEXT: subq $-128, %rdx
-; AVX2-NEXT: orq %rcx, %rax
-; AVX2-NEXT: cmovneq %r9, %rdx
-; AVX2-NEXT: addq $256, %rdx # imm = 0x100
+; AVX2-NEXT: cmovnel %r9d, %edx
+; AVX2-NEXT: subl $-128, %edx
+; AVX2-NEXT: orq %rax, %rcx
+; AVX2-NEXT: cmovnel %r10d, %edx
+; AVX2-NEXT: addl $256, %edx # imm = 0x100
; AVX2-NEXT: vptest %ymm1, %ymm1
-; AVX2-NEXT: cmovneq %r8, %rdx
; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: cmovnel %r8d, %edx
; AVX2-NEXT: movl %edx, %ecx
; AVX2-NEXT: andl $63, %ecx
; AVX2-NEXT: shrl $3, %edx
@@ -4949,72 +4944,82 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE2-NEXT: pushq %r12
; SSE2-NEXT: pushq %rbx
; SSE2-NEXT: pushq %rax
-; SSE2-NEXT: movq 8(%rsi), %r9
-; SSE2-NEXT: movq 16(%rsi), %rcx
-; SSE2-NEXT: movq 24(%rsi), %r8
-; SSE2-NEXT: movq 48(%rsi), %rdx
+; SSE2-NEXT: movq 40(%rsi), %r10
+; SSE2-NEXT: movq %r10, %xmm1
+; SSE2-NEXT: movq 32(%rsi), %r9
+; SSE2-NEXT: movq %r9, %xmm0
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-NEXT: movq (%rsi), %rdx
+; SSE2-NEXT: movq 8(%rsi), %rcx
+; SSE2-NEXT: movq %rdx, %xmm3
+; SSE2-NEXT: movq %rcx, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm1[0]
; SSE2-NEXT: movq 56(%rsi), %r11
-; SSE2-NEXT: movdqa 32(%rsi), %xmm1
-; SSE2-NEXT: movdqa 48(%rsi), %xmm2
-; SSE2-NEXT: movdqa 16(%rsi), %xmm0
-; SSE2-NEXT: por %xmm2, %xmm0
-; SSE2-NEXT: movdqa (%rsi), %xmm3
-; SSE2-NEXT: por %xmm1, %xmm3
+; SSE2-NEXT: movq %r11, %xmm2
+; SSE2-NEXT: movq 48(%rsi), %rbx
+; SSE2-NEXT: movq %rbx, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE2-NEXT: movq 24(%rsi), %r8
+; SSE2-NEXT: movq %r8, %xmm2
+; SSE2-NEXT: movq 16(%rsi), %rsi
+; SSE2-NEXT: movq %rsi, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0]
+; SSE2-NEXT: por %xmm1, %xmm4
; SSE2-NEXT: por %xmm0, %xmm3
-; SSE2-NEXT: pxor %xmm0, %xmm0
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm3
+; SSE2-NEXT: por %xmm4, %xmm3
+; SSE2-NEXT: pxor %xmm2, %xmm2
+; SSE2-NEXT: pcmpeqd %xmm2, %xmm3
; SSE2-NEXT: movmskps %xmm3, %eax
; SSE2-NEXT: xorl $15, %eax
-; SSE2-NEXT: bsrq %r11, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: bsrq %rdx, %rbx
-; SSE2-NEXT: xorq $63, %rbx
-; SSE2-NEXT: orq $64, %rbx
+; SSE2-NEXT: bsrq %r11, %r14
+; SSE2-NEXT: xorl $63, %r14d
+; SSE2-NEXT: bsrq %rbx, %r15
+; SSE2-NEXT: xorl $63, %r15d
+; SSE2-NEXT: addl $64, %r15d
; SSE2-NEXT: testq %r11, %r11
-; SSE2-NEXT: cmovneq %r10, %rbx
-; SSE2-NEXT: movq 40(%rsi), %r14
-; SSE2-NEXT: bsrq %r14, %r15
-; SSE2-NEXT: bsrq 32(%rsi), %r10
-; SSE2-NEXT: xorq $63, %r15
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
-; SSE2-NEXT: testq %r14, %r14
-; SSE2-NEXT: cmovneq %r15, %r10
-; SSE2-NEXT: orq $128, %r10
-; SSE2-NEXT: orq %r11, %rdx
-; SSE2-NEXT: cmovneq %rbx, %r10
-; SSE2-NEXT: bsrq %r8, %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: bsrq %rcx, %r11
-; SSE2-NEXT: xorq $63, %r11
-; SSE2-NEXT: orq $64, %r11
+; SSE2-NEXT: cmovnel %r14d, %r15d
+; SSE2-NEXT: bsrq %r10, %r14
+; SSE2-NEXT: xorl $63, %r14d
+; SSE2-NEXT: bsrq %r9, %r9
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: addl $64, %r9d
+; SSE2-NEXT: testq %r10, %r10
+; SSE2-NEXT: cmovnel %r14d, %r9d
+; SSE2-NEXT: subl $-128, %r9d
+; SSE2-NEXT: orq %r11, %rbx
+; SSE2-NEXT: cmovnel %r15d, %r9d
+; SSE2-NEXT: bsrq %r8, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %rsi, %r11
+; SSE2-NEXT: xorl $63, %r11d
+; SSE2-NEXT: addl $64, %r11d
; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %rdx, %r11
-; SSE2-NEXT: bsrq %r9, %rbx
-; SSE2-NEXT: xorq $63, %rbx
-; SSE2-NEXT: bsrq (%rsi), %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: orq $64, %rdx
-; SSE2-NEXT: testq %r9, %r9
-; SSE2-NEXT: cmovneq %rbx, %rdx
-; SSE2-NEXT: orq $128, %rdx
-; SSE2-NEXT: orq %r8, %rcx
-; SSE2-NEXT: cmovneq %r11, %rdx
-; SSE2-NEXT: orq $256, %rdx # imm = 0x100
-; SSE2-NEXT: por %xmm2, %xmm1
-; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
+; SSE2-NEXT: cmovnel %r10d, %r11d
+; SSE2-NEXT: bsrq %rcx, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq %rdx, %rdx
+; SSE2-NEXT: xorl $63, %edx
+; SSE2-NEXT: addl $64, %edx
+; SSE2-NEXT: testq %rcx, %rcx
+; SSE2-NEXT: cmovnel %r10d, %edx
+; SSE2-NEXT: subl $-128, %edx
+; SSE2-NEXT: orq %r8, %rsi
+; SSE2-NEXT: cmovnel %r11d, %edx
+; SSE2-NEXT: addl $256, %edx # imm = 0x100
+; SSE2-NEXT: por %xmm0, %xmm1
+; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r10, %rdx
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
; SSE2-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: cmovnel %r9d, %edx
; SSE2-NEXT: movl %edx, %ecx
; SSE2-NEXT: andl $63, %ecx
; SSE2-NEXT: shrl $3, %edx
@@ -5073,116 +5078,130 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE42: # %bb.0:
; SSE42-NEXT: pushq %r15
; SSE42-NEXT: pushq %r14
+; SSE42-NEXT: pushq %r13
+; SSE42-NEXT: pushq %r12
; SSE42-NEXT: pushq %rbx
-; SSE42-NEXT: movq 8(%rsi), %r8
-; SSE42-NEXT: movq 16(%rsi), %rcx
-; SSE42-NEXT: movq 24(%rsi), %rdx
-; SSE42-NEXT: movq 40(%rsi), %r11
-; SSE42-NEXT: movq 48(%rsi), %rax
-; SSE42-NEXT: movq 56(%rsi), %r10
-; SSE42-NEXT: movdqa 32(%rsi), %xmm2
-; SSE42-NEXT: movdqa 48(%rsi), %xmm0
-; SSE42-NEXT: movdqa (%rsi), %xmm1
-; SSE42-NEXT: bsrq %r10, %r9
-; SSE42-NEXT: xorq $63, %r9
-; SSE42-NEXT: bsrq %rax, %rbx
-; SSE42-NEXT: xorq $63, %rbx
-; SSE42-NEXT: orq $64, %rbx
-; SSE42-NEXT: testq %r10, %r10
-; SSE42-NEXT: cmovneq %r9, %rbx
-; SSE42-NEXT: bsrq %r11, %r14
-; SSE42-NEXT: xorq $63, %r14
-; SSE42-NEXT: bsrq 32(%rsi), %r9
-; SSE42-NEXT: xorq $63, %r9
-; SSE42-NEXT: orq $64, %r9
+; SSE42-NEXT: movq 40(%rsi), %r10
+; SSE42-NEXT: movq %r10, %xmm1
+; SSE42-NEXT: movq 32(%rsi), %r9
+; SSE42-NEXT: movq %r9, %xmm0
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE42-NEXT: movq (%rsi), %rax
+; SSE42-NEXT: movq 8(%rsi), %rdx
+; SSE42-NEXT: movq 56(%rsi), %r11
+; SSE42-NEXT: movq %r11, %xmm1
+; SSE42-NEXT: movq 48(%rsi), %rbx
+; SSE42-NEXT: movq %rbx, %xmm2
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE42-NEXT: movq 24(%rsi), %rcx
+; SSE42-NEXT: movq %rcx, %xmm3
+; SSE42-NEXT: movq 16(%rsi), %r8
+; SSE42-NEXT: movq %r8, %xmm1
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; SSE42-NEXT: por %xmm2, %xmm1
+; SSE42-NEXT: bsrq %r11, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %rbx, %r14
+; SSE42-NEXT: xorl $63, %r14d
+; SSE42-NEXT: addl $64, %r14d
; SSE42-NEXT: testq %r11, %r11
-; SSE42-NEXT: cmovneq %r14, %r9
-; SSE42-NEXT: orq $128, %r9
-; SSE42-NEXT: orq %r10, %rax
-; SSE42-NEXT: cmovneq %rbx, %r9
-; SSE42-NEXT: bsrq %rdx, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: bsrq %rcx, %r10
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: orq $64, %r10
+; SSE42-NEXT: cmovnel %esi, %r14d
+; SSE42-NEXT: bsrq %r10, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %r9, %r9
+; SSE42-NEXT: xorl $63, %r9d
+; SSE42-NEXT: addl $64, %r9d
+; SSE42-NEXT: testq %r10, %r10
+; SSE42-NEXT: cmovnel %esi, %r9d
+; SSE42-NEXT: subl $-128, %r9d
+; SSE42-NEXT: orq %r11, %rbx
+; SSE42-NEXT: cmovnel %r14d, %r9d
+; SSE42-NEXT: bsrq %rcx, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %r8, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: addl $64, %r10d
+; SSE42-NEXT: testq %rcx, %rcx
+; SSE42-NEXT: cmovnel %esi, %r10d
+; SSE42-NEXT: bsrq %rdx, %r11
+; SSE42-NEXT: xorl $63, %r11d
+; SSE42-NEXT: bsrq %rax, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: addl $64, %esi
; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rax, %r10
-; SSE42-NEXT: por %xmm2, %xmm1
-; SSE42-NEXT: bsrq %r8, %r11
-; SSE42-NEXT: bsrq (%rsi), %rax
-; SSE42-NEXT: xorq $63, %r11
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
-; SSE42-NEXT: testq %r8, %r8
-; SSE42-NEXT: cmovneq %r11, %rax
-; SSE42-NEXT: orq $128, %rax
-; SSE42-NEXT: orq %rdx, %rcx
-; SSE42-NEXT: cmovneq %r10, %rax
-; SSE42-NEXT: orq $256, %rax # imm = 0x100
+; SSE42-NEXT: cmovnel %r11d, %esi
+; SSE42-NEXT: subl $-128, %esi
+; SSE42-NEXT: orq %rcx, %r8
+; SSE42-NEXT: cmovnel %r10d, %esi
+; SSE42-NEXT: addl $256, %esi # imm = 0x100
; SSE42-NEXT: por %xmm0, %xmm2
; SSE42-NEXT: ptest %xmm2, %xmm2
-; SSE42-NEXT: cmovneq %r9, %rax
-; SSE42-NEXT: movdqa 16(%rsi), %xmm2
-; SSE42-NEXT: xorps %xmm3, %xmm3
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: pxor %xmm2, %xmm2
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
; SSE42-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movl %eax, %ecx
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: cmovnel %r9d, %esi
+; SSE42-NEXT: movl %esi, %ecx
; SSE42-NEXT: andl $63, %ecx
-; SSE42-NEXT: shrl $3, %eax
-; SSE42-NEXT: andl $56, %eax
+; SSE42-NEXT: shrl $3, %esi
+; SSE42-NEXT: andl $56, %esi
; SSE42-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movq -72(%rsp,%rax), %rdx
-; SSE42-NEXT: movq -80(%rsp,%rax), %r9
-; SSE42-NEXT: movq %r9, %rsi
-; SSE42-NEXT: shrdq %cl, %rdx, %rsi
-; SSE42-NEXT: movq -88(%rsp,%rax), %r10
-; SSE42-NEXT: movq %r10, %r8
-; SSE42-NEXT: shrdq %cl, %r9, %r8
-; SSE42-NEXT: movq -96(%rsp,%rax), %r11
+; SSE42-NEXT: movq -72(%rsp,%rsi), %r8
+; SSE42-NEXT: movq -80(%rsp,%rsi), %r11
; SSE42-NEXT: movq %r11, %r9
-; SSE42-NEXT: shrdq %cl, %r10, %r9
-; SSE42-NEXT: movq -104(%rsp,%rax), %rbx
+; SSE42-NEXT: shrdq %cl, %r8, %r9
+; SSE42-NEXT: movq -88(%rsp,%rsi), %rbx
; SSE42-NEXT: movq %rbx, %r10
; SSE42-NEXT: shrdq %cl, %r11, %r10
-; SSE42-NEXT: movq -112(%rsp,%rax), %r14
+; SSE42-NEXT: movq -96(%rsp,%rsi), %r14
; SSE42-NEXT: movq %r14, %r11
; SSE42-NEXT: shrdq %cl, %rbx, %r11
-; SSE42-NEXT: movq -120(%rsp,%rax), %r15
+; SSE42-NEXT: movq -104(%rsp,%rsi), %r15
; SSE42-NEXT: movq %r15, %rbx
; SSE42-NEXT: shrdq %cl, %r14, %rbx
-; SSE42-NEXT: movq -128(%rsp,%rax), %r14
-; SSE42-NEXT: shrq %cl, %rdx
-; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE42-NEXT: movq -112(%rsp,%rsi), %r12
+; SSE42-NEXT: movq %r12, %r14
; SSE42-NEXT: shrdq %cl, %r15, %r14
+; SSE42-NEXT: movq -120(%rsp,%rsi), %r13
+; SSE42-NEXT: movq %r13, %r15
+; SSE42-NEXT: shrdq %cl, %r12, %r15
+; SSE42-NEXT: movq %rax, %xmm2
+; SSE42-NEXT: movq %rdx, %xmm3
+; SSE42-NEXT: movq -128(%rsp,%rsi), %rdx
+; SSE42-NEXT: shrq %cl, %r8
+; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
+; SSE42-NEXT: shrdq %cl, %r13, %rdx
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE42-NEXT: por %xmm0, %xmm2
-; SSE42-NEXT: por %xmm2, %xmm1
+; SSE42-NEXT: por %xmm1, %xmm2
; SSE42-NEXT: xorl %ecx, %ecx
-; SSE42-NEXT: ptest %xmm1, %xmm1
+; SSE42-NEXT: ptest %xmm2, %xmm2
+; SSE42-NEXT: cmoveq %rcx, %r15
+; SSE42-NEXT: cmoveq %rcx, %r14
; SSE42-NEXT: cmoveq %rcx, %rbx
; SSE42-NEXT: cmoveq %rcx, %r11
; SSE42-NEXT: cmoveq %rcx, %r10
; SSE42-NEXT: cmoveq %rcx, %r9
-; SSE42-NEXT: cmoveq %rcx, %r8
-; SSE42-NEXT: cmoveq %rcx, %rsi
-; SSE42-NEXT: cmoveq %rcx, %r14
-; SSE42-NEXT: movq %rdi, %rax
; SSE42-NEXT: cmoveq %rcx, %rdx
-; SSE42-NEXT: movq %rdx, 56(%rdi)
-; SSE42-NEXT: movq %rsi, 48(%rdi)
-; SSE42-NEXT: movq %r8, 40(%rdi)
-; SSE42-NEXT: movq %r9, 32(%rdi)
-; SSE42-NEXT: movq %r10, 24(%rdi)
-; SSE42-NEXT: movq %r11, 16(%rdi)
-; SSE42-NEXT: movq %rbx, 8(%rdi)
-; SSE42-NEXT: movq %r14, (%rdi)
+; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: cmoveq %rcx, %r8
+; SSE42-NEXT: movq %r8, 56(%rdi)
+; SSE42-NEXT: movq %r9, 48(%rdi)
+; SSE42-NEXT: movq %r10, 40(%rdi)
+; SSE42-NEXT: movq %r11, 32(%rdi)
+; SSE42-NEXT: movq %rbx, 24(%rdi)
+; SSE42-NEXT: movq %r14, 16(%rdi)
+; SSE42-NEXT: movq %r15, 8(%rdi)
+; SSE42-NEXT: movq %rdx, (%rdi)
; SSE42-NEXT: popq %rbx
+; SSE42-NEXT: popq %r12
+; SSE42-NEXT: popq %r13
; SSE42-NEXT: popq %r14
; SSE42-NEXT: popq %r15
; SSE42-NEXT: retq
@@ -5192,101 +5211,117 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: vmovdqu 32(%rsi), %ymm1
+; AVX2-NEXT: movq 56(%rsi), %r9
+; AVX2-NEXT: vmovq %r9, %xmm0
+; AVX2-NEXT: movq 48(%rsi), %r10
+; AVX2-NEXT: vmovq %r10, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX2-NEXT: movq 40(%rsi), %r11
+; AVX2-NEXT: vmovq %r11, %xmm1
+; AVX2-NEXT: movq 32(%rsi), %rcx
+; AVX2-NEXT: vmovq %rcx, %xmm2
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX2-NEXT: movq 24(%rsi), %r8
; AVX2-NEXT: movq 16(%rsi), %rax
-; AVX2-NEXT: movq 24(%rsi), %rcx
-; AVX2-NEXT: movq 40(%rsi), %rdx
-; AVX2-NEXT: movq 48(%rsi), %r9
-; AVX2-NEXT: vpor (%rsi), %ymm1, %ymm0
-; AVX2-NEXT: movq 56(%rsi), %r10
-; AVX2-NEXT: lzcntq %r10, %r8
-; AVX2-NEXT: lzcntq %r9, %r11
-; AVX2-NEXT: addq $64, %r11
-; AVX2-NEXT: testq %r10, %r10
-; AVX2-NEXT: cmovneq %r8, %r11
+; AVX2-NEXT: vmovq %rax, %xmm2
+; AVX2-NEXT: movq (%rsi), %rdx
+; AVX2-NEXT: movq 8(%rsi), %rsi
; AVX2-NEXT: xorl %ebx, %ebx
-; AVX2-NEXT: lzcntq %rdx, %rbx
-; AVX2-NEXT: xorl %r8d, %r8d
-; AVX2-NEXT: lzcntq 32(%rsi), %r8
-; AVX2-NEXT: addq $64, %r8
-; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %rbx, %r8
-; AVX2-NEXT: subq $-128, %r8
-; AVX2-NEXT: orq %r10, %r9
-; AVX2-NEXT: cmovneq %r11, %r8
-; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: lzcntq %rcx, %rdx
+; AVX2-NEXT: lzcntq %r9, %rbx
+; AVX2-NEXT: xorl %r14d, %r14d
+; AVX2-NEXT: lzcntq %r10, %r14
+; AVX2-NEXT: addl $64, %r14d
+; AVX2-NEXT: testq %r9, %r9
+; AVX2-NEXT: cmovnel %ebx, %r14d
+; AVX2-NEXT: xorl %ebx, %ebx
+; AVX2-NEXT: lzcntq %r11, %rbx
+; AVX2-NEXT: lzcntq %rcx, %rcx
+; AVX2-NEXT: addl $64, %ecx
+; AVX2-NEXT: testq %r11, %r11
+; AVX2-NEXT: cmovnel %ebx, %ecx
+; AVX2-NEXT: subl $-128, %ecx
+; AVX2-NEXT: orq %r9, %r10
+; AVX2-NEXT: cmovnel %r14d, %ecx
; AVX2-NEXT: xorl %r9d, %r9d
-; AVX2-NEXT: lzcntq %rax, %r9
-; AVX2-NEXT: addq $64, %r9
-; AVX2-NEXT: testq %rcx, %rcx
-; AVX2-NEXT: cmovneq %rdx, %r9
-; AVX2-NEXT: movq 8(%rsi), %r10
+; AVX2-NEXT: lzcntq %r8, %r9
+; AVX2-NEXT: xorl %r10d, %r10d
+; AVX2-NEXT: lzcntq %rax, %r10
+; AVX2-NEXT: addl $64, %r10d
+; AVX2-NEXT: testq %r8, %r8
+; AVX2-NEXT: cmovnel %r9d, %r10d
; AVX2-NEXT: xorl %r11d, %r11d
-; AVX2-NEXT: lzcntq %r10, %r11
-; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: lzcntq (%rsi), %rdx
-; AVX2-NEXT: addq $64, %rdx
-; AVX2-NEXT: testq %r10, %r10
-; AVX2-NEXT: cmovneq %r11, %rdx
-; AVX2-NEXT: subq $-128, %rdx
-; AVX2-NEXT: orq %rcx, %rax
-; AVX2-NEXT: cmovneq %r9, %rdx
-; AVX2-NEXT: addq $256, %rdx # imm = 0x100
-; AVX2-NEXT: vpor 48(%rsi), %xmm1, %xmm1
-; AVX2-NEXT: vptest %xmm1, %xmm1
-; AVX2-NEXT: cmovneq %r8, %rdx
-; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,9223372036854775808]
-; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %edx, %ecx
+; AVX2-NEXT: lzcntq %rsi, %r11
+; AVX2-NEXT: xorl %r9d, %r9d
+; AVX2-NEXT: lzcntq %rdx, %r9
+; AVX2-NEXT: addl $64, %r9d
+; AVX2-NEXT: testq %rsi, %rsi
+; AVX2-NEXT: cmovnel %r11d, %r9d
+; AVX2-NEXT: subl $-128, %r9d
+; AVX2-NEXT: orq %r8, %rax
+; AVX2-NEXT: cmovnel %r10d, %r9d
+; AVX2-NEXT: addl $256, %r9d # imm = 0x100
+; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm3
+; AVX2-NEXT: vptest %xmm3, %xmm3
+; AVX2-NEXT: vmovaps {{.*#+}} ymm3 = [0,0,0,9223372036854775808]
+; AVX2-NEXT: vmovups %ymm3, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vxorps %xmm3, %xmm3, %xmm3
+; AVX2-NEXT: vmovups %ymm3, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovups %ymm3, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: vmovups %ymm3, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT: cmovnel %ecx, %r9d
+; AVX2-NEXT: movl %r9d, %ecx
; AVX2-NEXT: andl $63, %ecx
-; AVX2-NEXT: shrl $3, %edx
-; AVX2-NEXT: andl $56, %edx
-; AVX2-NEXT: movq -72(%rsp,%rdx), %r11
-; AVX2-NEXT: movq -80(%rsp,%rdx), %rax
-; AVX2-NEXT: movq %rax, %rsi
-; AVX2-NEXT: shrdq %cl, %r11, %rsi
-; AVX2-NEXT: movq -88(%rsp,%rdx), %r10
-; AVX2-NEXT: movq %r10, %r8
-; AVX2-NEXT: shrdq %cl, %rax, %r8
-; AVX2-NEXT: movq -96(%rsp,%rdx), %rax
-; AVX2-NEXT: movq %rax, %r9
-; AVX2-NEXT: shrdq %cl, %r10, %r9
-; AVX2-NEXT: movq -104(%rsp,%rdx), %r14
-; AVX2-NEXT: movq %r14, %r10
-; AVX2-NEXT: shrdq %cl, %rax, %r10
-; AVX2-NEXT: movq -112(%rsp,%rdx), %r15
-; AVX2-NEXT: movq %r15, %rbx
-; AVX2-NEXT: shrdq %cl, %r14, %rbx
+; AVX2-NEXT: shrl $3, %r9d
+; AVX2-NEXT: andl $56, %r9d
+; AVX2-NEXT: movq -72(%rsp,%r9), %rbx
+; AVX2-NEXT: movq -80(%rsp,%r9), %rax
+; AVX2-NEXT: movq %rax, %r10
+; AVX2-NEXT: shrdq %cl, %rbx, %r10
+; AVX2-NEXT: movq -88(%rsp,%r9), %r14
+; AVX2-NEXT: movq %r14, %r11
+; AVX2-NEXT: shrdq %cl, %rax, %r11
; AVX2-NEXT: movq %rdi, %rax
-; AVX2-NEXT: movq -128(%rsp,%rdx), %rdi
-; AVX2-NEXT: movq -120(%rsp,%rdx), %r14
-; AVX2-NEXT: movq %r14, %rdx
-; AVX2-NEXT: shrdq %cl, %r15, %rdx
+; AVX2-NEXT: movq -96(%rsp,%r9), %r15
+; AVX2-NEXT: movq %r15, %rdi
; AVX2-NEXT: shrdq %cl, %r14, %rdi
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-NEXT: vmovq %r8, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX2-NEXT: movq -104(%rsp,%r9), %r14
+; AVX2-NEXT: movq %r14, %r8
+; AVX2-NEXT: shrdq %cl, %r15, %r8
+; AVX2-NEXT: vmovq %rsi, %xmm2
+; AVX2-NEXT: vmovq %rdx, %xmm3
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX2-NEXT: movq -112(%rsp,%r9), %r15
+; AVX2-NEXT: movq %r15, %rdx
+; AVX2-NEXT: shrdq %cl, %r14, %rdx
+; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX2-NEXT: vpor %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: movq -128(%rsp,%r9), %rsi
+; AVX2-NEXT: movq -120(%rsp,%r9), %r14
+; AVX2-NEXT: movq %r14, %r9
+; AVX2-NEXT: shrdq %cl, %r15, %r9
+; AVX2-NEXT: shrdq %cl, %r14, %rsi
; AVX2-NEXT: xorl %r14d, %r14d
; AVX2-NEXT: vptest %ymm0, %ymm0
-; AVX2-NEXT: shrxq %rcx, %r11, %rcx
-; AVX2-NEXT: cmoveq %r14, %rdx
-; AVX2-NEXT: cmoveq %r14, %rbx
-; AVX2-NEXT: cmoveq %r14, %r10
+; AVX2-NEXT: shrxq %rcx, %rbx, %rcx
; AVX2-NEXT: cmoveq %r14, %r9
+; AVX2-NEXT: cmoveq %r14, %rdx
; AVX2-NEXT: cmoveq %r14, %r8
-; AVX2-NEXT: cmoveq %r14, %rsi
; AVX2-NEXT: cmoveq %r14, %rdi
+; AVX2-NEXT: cmoveq %r14, %r11
+; AVX2-NEXT: cmoveq %r14, %r10
+; AVX2-NEXT: cmoveq %r14, %rsi
; AVX2-NEXT: cmoveq %r14, %rcx
; AVX2-NEXT: movq %rcx, 56(%rax)
-; AVX2-NEXT: movq %rsi, 48(%rax)
-; AVX2-NEXT: movq %r8, 40(%rax)
-; AVX2-NEXT: movq %r9, 32(%rax)
-; AVX2-NEXT: movq %r10, 24(%rax)
-; AVX2-NEXT: movq %rbx, 16(%rax)
-; AVX2-NEXT: movq %rdx, 8(%rax)
-; AVX2-NEXT: movq %rdi, (%rax)
+; AVX2-NEXT: movq %r10, 48(%rax)
+; AVX2-NEXT: movq %r11, 40(%rax)
+; AVX2-NEXT: movq %rdi, 32(%rax)
+; AVX2-NEXT: movq %r8, 24(%rax)
+; AVX2-NEXT: movq %rdx, 16(%rax)
+; AVX2-NEXT: movq %r9, 8(%rax)
+; AVX2-NEXT: movq %rsi, (%rax)
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15
diff --git a/llvm/test/CodeGen/X86/bmi.ll b/llvm/test/CodeGen/X86/bmi.ll
index b0a56bd9b5fbd..3bd681d4498cd 100644
--- a/llvm/test/CodeGen/X86/bmi.ll
+++ b/llvm/test/CodeGen/X86/bmi.ll
@@ -836,11 +836,11 @@ define i64 @blsi64_z2(i64 %a, i64 %b, i64 %c) nounwind {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: movl %eax, %esi
+; X86-NEXT: movl %ecx, %esi
; X86-NEXT: negl %esi
-; X86-NEXT: sbbl %ecx, %edx
-; X86-NEXT: andl %ecx, %edx
-; X86-NEXT: andl %eax, %esi
+; X86-NEXT: sbbl %eax, %edx
+; X86-NEXT: andl %eax, %edx
+; X86-NEXT: andl %ecx, %esi
; X86-NEXT: orl %edx, %esi
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
@@ -877,11 +877,11 @@ define i64 @blsi64_sle(i64 %a, i64 %b, i64 %c) nounwind {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: movl %eax, %esi
+; X86-NEXT: movl %ecx, %esi
; X86-NEXT: negl %esi
-; X86-NEXT: sbbl %ecx, %edx
-; X86-NEXT: andl %ecx, %edx
-; X86-NEXT: andl %eax, %esi
+; X86-NEXT: sbbl %eax, %edx
+; X86-NEXT: andl %eax, %edx
+; X86-NEXT: andl %ecx, %esi
; X86-NEXT: cmpl $1, %esi
; X86-NEXT: sbbl $0, %edx
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
@@ -1120,12 +1120,12 @@ define i64 @blsmsk64_z2(i64 %a, i64 %b, i64 %c) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, %edx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: addl $-1, %edx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %eax, %esi
; X86-NEXT: adcl $-1, %esi
-; X86-NEXT: xorl %eax, %edx
-; X86-NEXT: xorl %ecx, %esi
+; X86-NEXT: xorl %ecx, %edx
+; X86-NEXT: xorl %eax, %esi
; X86-NEXT: orl %edx, %esi
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
@@ -1161,12 +1161,12 @@ define i64 @blsmsk64_sle(i64 %a, i64 %b, i64 %c) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, %edx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: addl $-1, %edx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %eax, %esi
; X86-NEXT: adcl $-1, %esi
-; X86-NEXT: xorl %ecx, %esi
-; X86-NEXT: xorl %eax, %edx
+; X86-NEXT: xorl %eax, %esi
+; X86-NEXT: xorl %ecx, %edx
; X86-NEXT: cmpl $1, %edx
; X86-NEXT: sbbl $0, %esi
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
@@ -1405,12 +1405,12 @@ define i64 @blsr64_z2(i64 %a, i64 %b, i64 %c) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, %edx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: addl $-1, %edx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %eax, %esi
; X86-NEXT: adcl $-1, %esi
-; X86-NEXT: andl %eax, %edx
-; X86-NEXT: andl %ecx, %esi
+; X86-NEXT: andl %ecx, %edx
+; X86-NEXT: andl %eax, %esi
; X86-NEXT: orl %edx, %esi
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
@@ -1446,12 +1446,12 @@ define i64 @blsr64_sle(i64 %a, i64 %b, i64 %c) nounwind {
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, %edx
+; X86-NEXT: movl %ecx, %edx
; X86-NEXT: addl $-1, %edx
-; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl %eax, %esi
; X86-NEXT: adcl $-1, %esi
-; X86-NEXT: andl %ecx, %esi
-; X86-NEXT: andl %eax, %edx
+; X86-NEXT: andl %eax, %esi
+; X86-NEXT: andl %ecx, %edx
; X86-NEXT: cmpl $1, %edx
; X86-NEXT: sbbl $0, %esi
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
diff --git a/llvm/test/CodeGen/X86/clmul-vector.ll b/llvm/test/CodeGen/X86/clmul-vector.ll
index 098a0d1cb12d7..4b63b67930fee 100644
--- a/llvm/test/CodeGen/X86/clmul-vector.ll
+++ b/llvm/test/CodeGen/X86/clmul-vector.ll
@@ -1041,9 +1041,9 @@ define <2 x i64> @clmul_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
define <16 x i8> @clmulr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; SSE2-LABEL: clmulr_v16i8:
; SSE2: # %bb.0:
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrlw $4, %xmm3
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: psllw $4, %xmm0
@@ -1427,64 +1427,64 @@ define <8 x i16> @clmulr_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: por %xmm1, %xmm5
-; SSE2-NEXT: movdqa %xmm5, %xmm6
-; SSE2-NEXT: psrlw $1, %xmm6
-; SSE2-NEXT: movdqa %xmm6, %xmm1
+; SSE2-NEXT: movdqa %xmm5, %xmm1
+; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm5
; SSE2-NEXT: paddb %xmm5, %xmm5
; SSE2-NEXT: por %xmm5, %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [4,4,4,4,4,4,4,4]
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [4,4,4,4,4,4,4,4]
+; SSE2-NEXT: pand %xmm1, %xmm6
+; SSE2-NEXT: pmullw %xmm0, %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [1,1,1,1,1,1,1,1]
; SSE2-NEXT: pand %xmm1, %xmm7
; SSE2-NEXT: pmullw %xmm0, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2,2,2,2,2,2,2,2]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [1,1,1,1,1,1,1,1]
-; SSE2-NEXT: pand %xmm6, %xmm9
-; SSE2-NEXT: pmullw %xmm0, %xmm9
-; SSE2-NEXT: pxor %xmm8, %xmm9
-; SSE2-NEXT: pxor %xmm7, %xmm9
+; SSE2-NEXT: pxor %xmm7, %xmm8
; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [8,8,8,8,8,8,8,8]
; SSE2-NEXT: pand %xmm5, %xmm7
; SSE2-NEXT: pmullw %xmm0, %xmm7
-; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [16,16,16,16,16,16,16,16]
-; SSE2-NEXT: pand %xmm1, %xmm8
+; SSE2-NEXT: pxor %xmm6, %xmm7
+; SSE2-NEXT: pxor %xmm8, %xmm7
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [16,16,16,16,16,16,16,16]
+; SSE2-NEXT: pand %xmm1, %xmm6
+; SSE2-NEXT: pmullw %xmm0, %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [32,32,32,32,32,32,32,32]
+; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: pxor %xmm7, %xmm8
-; SSE2-NEXT: pxor %xmm9, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [32,32,32,32,32,32,32,32]
-; SSE2-NEXT: pand %xmm5, %xmm7
-; SSE2-NEXT: pmullw %xmm0, %xmm7
+; SSE2-NEXT: pxor %xmm6, %xmm8
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [64,64,64,64,64,64,64,64]
; SSE2-NEXT: pand %xmm1, %xmm9
; SSE2-NEXT: pmullw %xmm0, %xmm9
+; SSE2-NEXT: pxor %xmm8, %xmm9
; SSE2-NEXT: pxor %xmm7, %xmm9
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [128,128,128,128,128,128,128,128]
-; SSE2-NEXT: pand %xmm5, %xmm7
-; SSE2-NEXT: pmullw %xmm0, %xmm7
-; SSE2-NEXT: pxor %xmm9, %xmm7
-; SSE2-NEXT: pxor %xmm8, %xmm7
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [128,128,128,128,128,128,128,128]
+; SSE2-NEXT: pand %xmm5, %xmm6
; SSE2-NEXT: pmullw %xmm0, %xmm6
+; SSE2-NEXT: pxor %xmm9, %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [256,256,256,256,256,256,256,256]
+; SSE2-NEXT: pand %xmm1, %xmm7
+; SSE2-NEXT: pmullw %xmm0, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [512,512,512,512,512,512,512,512]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: pxor %xmm6, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [1024,1024,1024,1024,1024,1024,1024,1024]
-; SSE2-NEXT: pand %xmm1, %xmm6
-; SSE2-NEXT: pmullw %xmm0, %xmm6
-; SSE2-NEXT: pxor %xmm8, %xmm6
+; SSE2-NEXT: pxor %xmm7, %xmm8
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [1024,1024,1024,1024,1024,1024,1024,1024]
+; SSE2-NEXT: pand %xmm1, %xmm7
+; SSE2-NEXT: pmullw %xmm0, %xmm7
+; SSE2-NEXT: pxor %xmm8, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2048,2048,2048,2048,2048,2048,2048,2048]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: pxor %xmm6, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [4096,4096,4096,4096,4096,4096,4096,4096]
-; SSE2-NEXT: pand %xmm1, %xmm6
-; SSE2-NEXT: pmullw %xmm0, %xmm6
-; SSE2-NEXT: pxor %xmm8, %xmm6
-; SSE2-NEXT: pxor %xmm7, %xmm6
-; SSE2-NEXT: psllw $8, %xmm7
+; SSE2-NEXT: pxor %xmm7, %xmm8
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [4096,4096,4096,4096,4096,4096,4096,4096]
+; SSE2-NEXT: pand %xmm1, %xmm7
+; SSE2-NEXT: pmullw %xmm0, %xmm7
+; SSE2-NEXT: pxor %xmm8, %xmm7
+; SSE2-NEXT: pxor %xmm6, %xmm7
+; SSE2-NEXT: psllw $8, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [8192,8192,8192,8192,8192,8192,8192,8192]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
@@ -1494,9 +1494,9 @@ define <8 x i16> @clmulr_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE2-NEXT: pmullw %xmm5, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm0
-; SSE2-NEXT: pxor %xmm6, %xmm0
+; SSE2-NEXT: pxor %xmm7, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: por %xmm7, %xmm0
+; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm2, %xmm1
@@ -2774,9 +2774,9 @@ define <2 x i64> @clmulr_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
define <16 x i8> @clmulh_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; SSE2-LABEL: clmulh_v16i8:
; SSE2: # %bb.0:
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrlw $4, %xmm3
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: psllw $4, %xmm0
@@ -3163,64 +3163,64 @@ define <8 x i16> @clmulh_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: por %xmm1, %xmm5
-; SSE2-NEXT: movdqa %xmm5, %xmm6
-; SSE2-NEXT: psrlw $1, %xmm6
-; SSE2-NEXT: movdqa %xmm6, %xmm1
+; SSE2-NEXT: movdqa %xmm5, %xmm1
+; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm5
; SSE2-NEXT: paddb %xmm5, %xmm5
; SSE2-NEXT: por %xmm5, %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [4,4,4,4,4,4,4,4]
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [4,4,4,4,4,4,4,4]
+; SSE2-NEXT: pand %xmm1, %xmm6
+; SSE2-NEXT: pmullw %xmm0, %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [1,1,1,1,1,1,1,1]
; SSE2-NEXT: pand %xmm1, %xmm7
; SSE2-NEXT: pmullw %xmm0, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2,2,2,2,2,2,2,2]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [1,1,1,1,1,1,1,1]
-; SSE2-NEXT: pand %xmm6, %xmm9
-; SSE2-NEXT: pmullw %xmm0, %xmm9
-; SSE2-NEXT: pxor %xmm8, %xmm9
-; SSE2-NEXT: pxor %xmm7, %xmm9
+; SSE2-NEXT: pxor %xmm7, %xmm8
; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [8,8,8,8,8,8,8,8]
; SSE2-NEXT: pand %xmm5, %xmm7
; SSE2-NEXT: pmullw %xmm0, %xmm7
-; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [16,16,16,16,16,16,16,16]
-; SSE2-NEXT: pand %xmm1, %xmm8
+; SSE2-NEXT: pxor %xmm6, %xmm7
+; SSE2-NEXT: pxor %xmm8, %xmm7
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [16,16,16,16,16,16,16,16]
+; SSE2-NEXT: pand %xmm1, %xmm6
+; SSE2-NEXT: pmullw %xmm0, %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [32,32,32,32,32,32,32,32]
+; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: pxor %xmm7, %xmm8
-; SSE2-NEXT: pxor %xmm9, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [32,32,32,32,32,32,32,32]
-; SSE2-NEXT: pand %xmm5, %xmm7
-; SSE2-NEXT: pmullw %xmm0, %xmm7
+; SSE2-NEXT: pxor %xmm6, %xmm8
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [64,64,64,64,64,64,64,64]
; SSE2-NEXT: pand %xmm1, %xmm9
; SSE2-NEXT: pmullw %xmm0, %xmm9
+; SSE2-NEXT: pxor %xmm8, %xmm9
; SSE2-NEXT: pxor %xmm7, %xmm9
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [128,128,128,128,128,128,128,128]
-; SSE2-NEXT: pand %xmm5, %xmm7
-; SSE2-NEXT: pmullw %xmm0, %xmm7
-; SSE2-NEXT: pxor %xmm9, %xmm7
-; SSE2-NEXT: pxor %xmm8, %xmm7
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [128,128,128,128,128,128,128,128]
+; SSE2-NEXT: pand %xmm5, %xmm6
; SSE2-NEXT: pmullw %xmm0, %xmm6
+; SSE2-NEXT: pxor %xmm9, %xmm6
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [256,256,256,256,256,256,256,256]
+; SSE2-NEXT: pand %xmm1, %xmm7
+; SSE2-NEXT: pmullw %xmm0, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [512,512,512,512,512,512,512,512]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: pxor %xmm6, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [1024,1024,1024,1024,1024,1024,1024,1024]
-; SSE2-NEXT: pand %xmm1, %xmm6
-; SSE2-NEXT: pmullw %xmm0, %xmm6
-; SSE2-NEXT: pxor %xmm8, %xmm6
+; SSE2-NEXT: pxor %xmm7, %xmm8
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [1024,1024,1024,1024,1024,1024,1024,1024]
+; SSE2-NEXT: pand %xmm1, %xmm7
+; SSE2-NEXT: pmullw %xmm0, %xmm7
+; SSE2-NEXT: pxor %xmm8, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2048,2048,2048,2048,2048,2048,2048,2048]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
-; SSE2-NEXT: pxor %xmm6, %xmm8
-; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [4096,4096,4096,4096,4096,4096,4096,4096]
-; SSE2-NEXT: pand %xmm1, %xmm6
-; SSE2-NEXT: pmullw %xmm0, %xmm6
-; SSE2-NEXT: pxor %xmm8, %xmm6
-; SSE2-NEXT: pxor %xmm7, %xmm6
-; SSE2-NEXT: psllw $8, %xmm7
+; SSE2-NEXT: pxor %xmm7, %xmm8
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [4096,4096,4096,4096,4096,4096,4096,4096]
+; SSE2-NEXT: pand %xmm1, %xmm7
+; SSE2-NEXT: pmullw %xmm0, %xmm7
+; SSE2-NEXT: pxor %xmm8, %xmm7
+; SSE2-NEXT: pxor %xmm6, %xmm7
+; SSE2-NEXT: psllw $8, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [8192,8192,8192,8192,8192,8192,8192,8192]
; SSE2-NEXT: pand %xmm5, %xmm8
; SSE2-NEXT: pmullw %xmm0, %xmm8
@@ -3230,9 +3230,9 @@ define <8 x i16> @clmulh_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE2-NEXT: pmullw %xmm5, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm0
-; SSE2-NEXT: pxor %xmm6, %xmm0
+; SSE2-NEXT: pxor %xmm7, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: por %xmm7, %xmm0
+; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm2, %xmm1
diff --git a/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll b/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
index 0924ea85a0126..e27f2d7fa02e0 100644
--- a/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
+++ b/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
@@ -53,10 +53,10 @@ define i129 @v_sdiv_i129_v_pow2k(i129 %lhs) nounwind {
; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: movl %edx, %ebx
; X86-NEXT: andl $1, %ebx
; X86-NEXT: negl %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -65,18 +65,18 @@ define i129 @v_sdiv_i129_v_pow2k(i129 %lhs) nounwind {
; X86-NEXT: addl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi
; X86-NEXT: adcl $0, %esi
-; X86-NEXT: adcl $0, %edx
; X86-NEXT: adcl $0, %ecx
-; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: adcl $0, %edx
+; X86-NEXT: movl %edx, %ebx
; X86-NEXT: andl $1, %ebx
; X86-NEXT: movl %ebx, %ebp
; X86-NEXT: negl %ebp
-; X86-NEXT: shldl $31, %edx, %ecx
-; X86-NEXT: shldl $31, %esi, %edx
+; X86-NEXT: shldl $31, %ecx, %edx
+; X86-NEXT: shldl $31, %esi, %ecx
; X86-NEXT: shldl $31, %edi, %esi
; X86-NEXT: movl %esi, (%eax)
-; X86-NEXT: movl %edx, 4(%eax)
-; X86-NEXT: movl %ecx, 8(%eax)
+; X86-NEXT: movl %ecx, 4(%eax)
+; X86-NEXT: movl %edx, 8(%eax)
; X86-NEXT: movl %ebp, 12(%eax)
; X86-NEXT: movb %bl, 16(%eax)
; X86-NEXT: popl %esi
diff --git a/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll b/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
index b3f9e68fc3368..43649a4e8f9f7 100644
--- a/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
+++ b/llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
@@ -234,39 +234,42 @@ define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [23,23,23,23]
; CHECK-NEXT: psubd %xmm1, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
-; CHECK-NEXT: movdqa %xmm2, %xmm3
-; CHECK-NEXT: pxor %xmm4, %xmm3
-; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; CHECK-NEXT: movdqa %xmm3, %xmm5
-; CHECK-NEXT: pandn %xmm2, %xmm5
+; CHECK-NEXT: movdqa %xmm2, %xmm5
+; CHECK-NEXT: pxor %xmm4, %xmm5
+; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [2147483679,2147483679,2147483679,2147483679]
+; CHECK-NEXT: pcmpgtd %xmm5, %xmm3
+; CHECK-NEXT: movdqa %xmm5, %xmm6
+; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; CHECK-NEXT: pandn %xmm2, %xmm6
+; CHECK-NEXT: pcmpeqd %xmm5, %xmm5
+; CHECK-NEXT: pxor %xmm5, %xmm3
; CHECK-NEXT: psrld $27, %xmm3
-; CHECK-NEXT: por %xmm5, %xmm3
+; CHECK-NEXT: por %xmm6, %xmm3
; CHECK-NEXT: pxor %xmm2, %xmm2
; CHECK-NEXT: movdqa %xmm3, %xmm7
; CHECK-NEXT: pcmpeqd %xmm2, %xmm7
-; CHECK-NEXT: pcmpeqd %xmm6, %xmm6
-; CHECK-NEXT: pxor %xmm6, %xmm7
+; CHECK-NEXT: pxor %xmm5, %xmm7
; CHECK-NEXT: paddd %xmm3, %xmm7
; CHECK-NEXT: pshuflw {{.*#+}} xmm9 = xmm7[2,3,3,3,4,5,6,7]
-; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload
-; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1]
+; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm6 # 16-byte Reload
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm0[0],xmm6[1],xmm0[1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm14 # 16-byte Reload
; CHECK-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm14 # 16-byte Folded Reload
; CHECK-NEXT: # xmm14 = xmm14[0],mem[0],xmm14[1],mem[1]
-; CHECK-NEXT: movlhps {{.*#+}} xmm14 = xmm14[0],xmm5[0]
+; CHECK-NEXT: movlhps {{.*#+}} xmm14 = xmm14[0],xmm6[0]
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [8388607,8388607,8388607,8388607]
; CHECK-NEXT: andps %xmm14, %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm8 = [8388608,8388608,8388608,8388608]
; CHECK-NEXT: orps %xmm0, %xmm8
-; CHECK-NEXT: movaps %xmm8, %xmm5
+; CHECK-NEXT: movaps %xmm8, %xmm6
; CHECK-NEXT: movaps %xmm8, %xmm10
; CHECK-NEXT: movaps %xmm8, %xmm11
; CHECK-NEXT: movaps %xmm8, %xmm12
; CHECK-NEXT: movaps %xmm8, %xmm13
; CHECK-NEXT: psrld %xmm9, %xmm13
; CHECK-NEXT: pshuflw {{.*#+}} xmm9 = xmm7[0,1,1,1,4,5,6,7]
-; CHECK-NEXT: psrld %xmm9, %xmm5
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm13[0]
+; CHECK-NEXT: psrld %xmm9, %xmm6
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm13[0]
; CHECK-NEXT: pshufd {{.*#+}} xmm13 = xmm7[2,3,2,3]
; CHECK-NEXT: pshuflw {{.*#+}} xmm9 = xmm13[2,3,3,3,4,5,6,7]
; CHECK-NEXT: psrld %xmm9, %xmm10
@@ -274,13 +277,13 @@ define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: pslld $23, %xmm7
; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm7 # [1065353216,1065353216,1065353216,1065353216]
; CHECK-NEXT: cvttps2dq %xmm7, %xmm7
-; CHECK-NEXT: paddd %xmm6, %xmm7
-; CHECK-NEXT: movaps %xmm8, %xmm6
+; CHECK-NEXT: paddd %xmm5, %xmm7
+; CHECK-NEXT: movaps %xmm8, %xmm5
; CHECK-NEXT: pand %xmm8, %xmm7
; CHECK-NEXT: pshuflw {{.*#+}} xmm13 = xmm13[0,1,1,1,4,5,6,7]
; CHECK-NEXT: psrld %xmm13, %xmm11
; CHECK-NEXT: punpckhqdq {{.*#+}} xmm11 = xmm11[1],xmm10[1]
-; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm11[0,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,3],xmm11[0,3]
; CHECK-NEXT: pshuflw {{.*#+}} xmm10 = xmm3[2,3,3,3,4,5,6,7]
; CHECK-NEXT: psrld %xmm10, %xmm12
; CHECK-NEXT: pshuflw {{.*#+}} xmm10 = xmm3[0,1,1,1,4,5,6,7]
@@ -288,16 +291,16 @@ define <4 x i4> @to_f4e2m1fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm12[0]
; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm3[2,3,2,3]
; CHECK-NEXT: pshuflw {{.*#+}} xmm11 = xmm10[2,3,3,3,4,5,6,7]
-; CHECK-NEXT: psrld %xmm11, %xmm6
+; CHECK-NEXT: psrld %xmm11, %xmm5
; CHECK-NEXT: pshuflw {{.*#+}} xmm10 = xmm10[0,1,1,1,4,5,6,7]
; CHECK-NEXT: psrld %xmm10, %xmm8
-; CHECK-NEXT: punpckhqdq {{.*#+}} xmm8 = xmm8[1],xmm6[1]
+; CHECK-NEXT: punpckhqdq {{.*#+}} xmm8 = xmm8[1],xmm5[1]
; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,3],xmm8[0,3]
; CHECK-NEXT: pcmpgtd %xmm2, %xmm7
; CHECK-NEXT: por %xmm9, %xmm7
; CHECK-NEXT: pxor %xmm4, %xmm3
; CHECK-NEXT: pcmpgtd %xmm4, %xmm3
-; CHECK-NEXT: pand %xmm5, %xmm3
+; CHECK-NEXT: pand %xmm6, %xmm3
; CHECK-NEXT: movdqa {{.*#+}} xmm4 = [1,1,1,1]
; CHECK-NEXT: pand %xmm4, %xmm3
; CHECK-NEXT: pand %xmm7, %xmm3
diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll
index e4b2dcf0a62dd..722c31452ec9f 100644
--- a/llvm/test/CodeGen/X86/freeze-binary.ll
+++ b/llvm/test/CodeGen/X86/freeze-binary.ll
@@ -564,8 +564,7 @@ define i32 @freeze_lshr(i32 %a0) nounwind {
; X86-LABEL: freeze_lshr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: shrl $2, %eax
-; X86-NEXT: shrl %eax
+; X86-NEXT: shrl $3, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_lshr:
@@ -583,15 +582,13 @@ define i32 @freeze_lshr_exact(i32 %a0) nounwind {
; X86-LABEL: freeze_lshr_exact:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: shrl $3, %eax
-; X86-NEXT: shrl $5, %eax
+; X86-NEXT: shrl $8, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_lshr_exact:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: shrl $3, %eax
-; X64-NEXT: shrl $5, %eax
+; X64-NEXT: shrl $8, %eax
; X64-NEXT: retq
%x = lshr exact i32 %a0, 3
%y = freeze i32 %x
@@ -602,20 +599,20 @@ define i32 @freeze_lshr_exact(i32 %a0) nounwind {
define i32 @freeze_lshr_exact_extra_use(i32 %a0, ptr %escape) nounwind {
; X86-LABEL: freeze_lshr_exact_extra_use:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: shrl $3, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %eax, %edx
-; X86-NEXT: shrl $5, %eax
+; X86-NEXT: shrl $3, %edx
+; X86-NEXT: shrl $8, %eax
; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: freeze_lshr_exact_extra_use:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: shrl $3, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: shrl $5, %eax
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: shrl $3, %ecx
+; X64-NEXT: shrl $8, %eax
; X64-NEXT: movl %ecx, (%rsi)
; X64-NEXT: retq
%x = lshr exact i32 %a0, 3
diff --git a/llvm/test/CodeGen/X86/freeze-vector.ll b/llvm/test/CodeGen/X86/freeze-vector.ll
index 7062ace700512..c6c294168bb86 100644
--- a/llvm/test/CodeGen/X86/freeze-vector.ll
+++ b/llvm/test/CodeGen/X86/freeze-vector.ll
@@ -213,15 +213,15 @@ define void @freeze_extractelement(ptr %origin0, ptr %origin1, ptr %dst) nounwin
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: vmovdqa (%edx), %xmm0
-; X86-NEXT: vpand (%ecx), %xmm0, %xmm0
+; X86-NEXT: vmovdqa (%ecx), %xmm0
+; X86-NEXT: vpand (%edx), %xmm0, %xmm0
; X86-NEXT: vpextrb $6, %xmm0, (%eax)
; X86-NEXT: retl
;
; X64-LABEL: freeze_extractelement:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa (%rdi), %xmm0
-; X64-NEXT: vpand (%rsi), %xmm0, %xmm0
+; X64-NEXT: vmovdqa (%rsi), %xmm0
+; X64-NEXT: vpand (%rdi), %xmm0, %xmm0
; X64-NEXT: vpextrb $6, %xmm0, (%rdx)
; X64-NEXT: retq
%i0 = load <16 x i8>, ptr %origin0
@@ -240,8 +240,8 @@ define void @freeze_extractelement_escape(ptr %origin0, ptr %origin1, ptr %dst,
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: vmovdqa (%esi), %xmm0
-; X86-NEXT: vpand (%edx), %xmm0, %xmm0
+; X86-NEXT: vmovdqa (%edx), %xmm0
+; X86-NEXT: vpand (%esi), %xmm0, %xmm0
; X86-NEXT: vmovdqa %xmm0, (%ecx)
; X86-NEXT: vpextrb $6, %xmm0, (%eax)
; X86-NEXT: popl %esi
@@ -249,8 +249,8 @@ define void @freeze_extractelement_escape(ptr %origin0, ptr %origin1, ptr %dst,
;
; X64-LABEL: freeze_extractelement_escape:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa (%rdi), %xmm0
-; X64-NEXT: vpand (%rsi), %xmm0, %xmm0
+; X64-NEXT: vmovdqa (%rsi), %xmm0
+; X64-NEXT: vpand (%rdi), %xmm0, %xmm0
; X64-NEXT: vmovdqa %xmm0, (%rcx)
; X64-NEXT: vpextrb $6, %xmm0, (%rdx)
; X64-NEXT: retq
@@ -281,8 +281,8 @@ define void @freeze_extractelement_extra_use(ptr %origin0, ptr %origin1, i64 %id
; X86-NEXT: movl 32(%ebp), %edx
; X86-NEXT: movl 12(%ebp), %esi
; X86-NEXT: movl 8(%ebp), %edi
-; X86-NEXT: vmovaps (%edi), %xmm0
-; X86-NEXT: vandps (%esi), %xmm0, %xmm0
+; X86-NEXT: vmovaps (%esi), %xmm0
+; X86-NEXT: vandps (%edi), %xmm0, %xmm0
; X86-NEXT: vmovaps %xmm0, (%esp)
; X86-NEXT: movzbl (%esp,%ecx), %ecx
; X86-NEXT: cmpb (%esp,%eax), %cl
@@ -297,8 +297,8 @@ define void @freeze_extractelement_extra_use(ptr %origin0, ptr %origin1, i64 %id
; X64: # %bb.0:
; X64-NEXT: andl $15, %ecx
; X64-NEXT: andl $15, %edx
-; X64-NEXT: vmovaps (%rdi), %xmm0
-; X64-NEXT: vandps (%rsi), %xmm0, %xmm0
+; X64-NEXT: vmovaps (%rsi), %xmm0
+; X64-NEXT: vandps (%rdi), %xmm0, %xmm0
; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; X64-NEXT: movzbl -24(%rsp,%rdx), %eax
; X64-NEXT: cmpb -24(%rsp,%rcx), %al
@@ -756,24 +756,10 @@ define <4 x i32> @freeze_lshr_extract_concat_high_demanded(<4 x i32> %a, <4 x i3
}
define i32 @freeze_select_scalar_demanded(i1 %c, <2 x i32> %a, <2 x i32> %b, <2 x i32> %d) {
-; X86-LABEL: freeze_select_scalar_demanded:
-; X86: # %bb.0:
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: jne .LBB27_1
-; X86-NEXT: # %bb.2:
-; X86-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm1
-; X86-NEXT: jmp .LBB27_3
-; X86-NEXT: .LBB27_1:
-; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # [2147483647,2147483647,u,u]
-; X86-NEXT: .LBB27_3:
-; X86-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X86-NEXT: vmovd %xmm0, %eax
-; X86-NEXT: retl
-;
-; X64-LABEL: freeze_select_scalar_demanded:
-; X64: # %bb.0:
-; X64-NEXT: vmovd %xmm0, %eax
-; X64-NEXT: retq
+; CHECK-LABEL: freeze_select_scalar_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: ret{{[l|q]}}
%poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
%poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
%lhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -794,15 +780,10 @@ define <2 x i32> @freeze_vselect_high_demanded(<4 x i32> %csrc, <2 x i32> %a, <2
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: vmovdqa 24(%ebp), %xmm3
-; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm4 # [2147483647,2147483647,2147483647,2147483647]
-; X86-NEXT: vpxor %xmm5, %xmm5, %xmm5
-; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm4[0,1,2,3],xmm0[4,5,6,7]
-; X86-NEXT: vpcmpgtd %xmm5, %xmm0, %xmm0
-; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2 # [2147483647,2147483647,u,u]
-; X86-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
-; X86-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; X86-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],mem[0]
+; X86-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0
+; X86-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,1,0,1]
+; X86-NEXT: vpermilps {{.*#+}} xmm2 = mem[0,1,0,1]
; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X86-NEXT: movl %ebp, %esp
@@ -812,16 +793,10 @@ define <2 x i32> @freeze_vselect_high_demanded(<4 x i32> %csrc, <2 x i32> %a, <2
;
; X64-LABEL: freeze_vselect_high_demanded:
; X64: # %bb.0:
-; X64-NEXT: vpbroadcastd {{.*#+}} xmm5 = [2147483647,2147483647,2147483647,2147483647]
-; X64-NEXT: vpaddd %xmm5, %xmm0, %xmm6
-; X64-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; X64-NEXT: vpblendd {{.*#+}} xmm0 = xmm6[0,1],xmm0[2,3]
-; X64-NEXT: vpcmpgtd %xmm7, %xmm0, %xmm0
-; X64-NEXT: vpaddd %xmm5, %xmm2, %xmm2
-; X64-NEXT: vpbroadcastd {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
-; X64-NEXT: vpsubd %xmm5, %xmm4, %xmm4
-; X64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; X64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm4[0],xmm3[0]
+; X64-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; X64-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0
+; X64-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
+; X64-NEXT: vmovddup {{.*#+}} xmm2 = xmm3[0,0]
; X64-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X64-NEXT: retq
@@ -849,17 +824,10 @@ define i32 @freeze_vselect_demanded(<4 x i32> %csrc, <2 x i32> %a, <2 x i32> %b,
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-16, %esp
; X86-NEXT: subl $16, %esp
-; X86-NEXT: vmovdqa 8(%ebp), %xmm3
-; X86-NEXT: vmovdqa 24(%ebp), %xmm4
-; X86-NEXT: vpxor %xmm5, %xmm5, %xmm5
-; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm6 # [2147483647,2147483647,2147483647,2147483647]
-; X86-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
-; X86-NEXT: vpcmpgtd %xmm5, %xmm0, %xmm0
-; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2 # [2147483647,2147483647,u,u]
-; X86-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4, %xmm4
-; X86-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
-; X86-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm3, %xmm0
+; X86-NEXT: vmovaps 8(%ebp), %xmm2
+; X86-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; X86-NEXT: vpcmpgtd %xmm3, %xmm0, %xmm0
+; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
@@ -908,8 +876,7 @@ define <2 x i64> @freeze_vselect_knownbits(<8 x i32> %csrc, <4 x i32> %a, <4 x i
; X86-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; X86-NEXT: vblendvps %ymm0, {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X86-NEXT: vmovaps %ymm0, (%eax)
-; X86-NEXT: vextractf128 $1, %ymm0, %xmm0
-; X86-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm0
; X86-NEXT: vzeroupper
; X86-NEXT: retl
;
diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
index 64ff0014d6cb7..b238a1932e2e1 100644
--- a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
+++ b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
@@ -855,22 +855,21 @@ define <64 x i8> @vec512_i8_signed_mem_reg(ptr %a1_addr, <64 x i8> %a2) nounwind
; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm5
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm0, %ymm1, %ymm5
; AVX512F-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512F-NEXT: vpsubb %ymm5, %ymm0, %ymm0
-; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512F-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm5
-; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512F-NEXT: vpand %ymm6, %ymm0, %ymm0
-; AVX512F-NEXT: vpsubb %ymm0, %ymm7, %ymm0
+; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512F-NEXT: vpsubb %ymm0, %ymm6, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm2
@@ -887,22 +886,21 @@ define <64 x i8> @vec512_i8_signed_mem_reg(ptr %a1_addr, <64 x i8> %a2) nounwind
; AVX512VL-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512VL-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm5
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpminsb %ymm0, %ymm1, %ymm5
; AVX512VL-NEXT: vpmaxsb %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: vpsubb %ymm5, %ymm0, %ymm0
-; AVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm0
+; AVX512VL-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm5
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512VL-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512VL-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512VL-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512VL-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512VL-NEXT: vpand %ymm6, %ymm0, %ymm0
-; AVX512VL-NEXT: vpsubb %ymm0, %ymm7, %ymm0
+; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512VL-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm0, %ymm6, %ymm0
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))
; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
@@ -945,22 +943,21 @@ define <64 x i8> @vec512_i8_signed_reg_mem(<64 x i8> %a1, ptr %a2_addr) nounwind
; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm2, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512F-NEXT: vpminsb %ymm3, %ymm2, %ymm5
-; AVX512F-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
-; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpminsb %ymm3, %ymm2, %ymm5
+; AVX512F-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
+; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $1, %ymm3, %ymm3
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512F-NEXT: vpand %ymm5, %ymm3, %ymm3
+; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm5
-; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512F-NEXT: vpsubb %ymm3, %ymm7, %ymm3
-; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512F-NEXT: vpsubb %ymm3, %ymm6, %ymm3
+; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm3
@@ -977,22 +974,21 @@ define <64 x i8> @vec512_i8_signed_reg_mem(<64 x i8> %a1, ptr %a2_addr) nounwind
; AVX512VL-NEXT: vpcmpgtb %ymm3, %ymm2, %ymm4
; AVX512VL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512VL-NEXT: vpminsb %ymm3, %ymm2, %ymm5
-; AVX512VL-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
-; AVX512VL-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VL-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpminsb %ymm3, %ymm2, %ymm5
+; AVX512VL-NEXT: vpmaxsb %ymm3, %ymm2, %ymm3
+; AVX512VL-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512VL-NEXT: vpsrlw $1, %ymm3, %ymm3
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512VL-NEXT: vpand %ymm5, %ymm3, %ymm3
+; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm5
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512VL-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3
-; AVX512VL-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512VL-NEXT: vpsubb %ymm3, %ymm7, %ymm3
-; AVX512VL-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512VL-NEXT: vpsubb %ymm3, %ymm6, %ymm3
+; AVX512VL-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm3
@@ -1036,22 +1032,21 @@ define <64 x i8> @vec512_i8_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind
; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5
-; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
@@ -1069,22 +1064,21 @@ define <64 x i8> @vec512_i8_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind
; AVX512VL-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4
; AVX512VL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
-; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
-; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
-; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm5
; AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1
; AVX512VL-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpminsb %ymm2, %ymm3, %ymm5
+; AVX512VL-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm5, %ymm2, %ymm2
; AVX512VL-NEXT: vpsrlw $1, %ymm2, %ymm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
+; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2
+; AVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
+; AVX512VL-NEXT: vpand %ymm5, %ymm1, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; AVX512VL-NEXT: vpandq %zmm6, %zmm5, %zmm5
-; AVX512VL-NEXT: vpand %ymm6, %ymm2, %ymm2
-; AVX512VL-NEXT: vpxor %xmm7, %xmm7, %xmm7
-; AVX512VL-NEXT: vpsubb %ymm2, %ymm7, %ymm2
-; AVX512VL-NEXT: vpand %ymm6, %ymm1, %ymm1
-; AVX512VL-NEXT: vpsubb %ymm1, %ymm7, %ymm1
+; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX512VL-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; AVX512VL-NEXT: vpsubb %ymm1, %ymm6, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))
; AVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm2
diff --git a/llvm/test/CodeGen/X86/pdep-vector-128.ll b/llvm/test/CodeGen/X86/pdep-vector-128.ll
index e9e1afc636599..778ed6b0fc376 100644
--- a/llvm/test/CodeGen/X86/pdep-vector-128.ll
+++ b/llvm/test/CodeGen/X86/pdep-vector-128.ll
@@ -9,11 +9,11 @@
define <16 x i8> @pdep_v16i8(<16 x i8> %val, <16 x i8> %mask) nounwind {
; SSE-LABEL: pdep_v16i8:
; SSE: # %bb.0:
-; SSE-NEXT: pcmpeqd %xmm5, %xmm5
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm3
-; SSE-NEXT: pxor %xmm5, %xmm3
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: psubb %xmm3, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm3
+; SSE-NEXT: movdqa %xmm1, %xmm5
+; SSE-NEXT: psubb %xmm3, %xmm5
; SSE-NEXT: paddb %xmm3, %xmm3
; SSE-NEXT: movdqa %xmm3, %xmm4
; SSE-NEXT: paddb %xmm3, %xmm4
@@ -27,11 +27,24 @@ define <16 x i8> @pdep_v16i8(<16 x i8> %val, <16 x i8> %mask) nounwind {
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: pxor %xmm6, %xmm3
-; SSE-NEXT: por %xmm3, %xmm2
-; SSE-NEXT: pxor %xmm5, %xmm2
-; SSE-NEXT: movdqa %xmm2, %xmm5
-; SSE-NEXT: paddb %xmm2, %xmm5
+; SSE-NEXT: por %xmm3, %xmm5
; SSE-NEXT: pxor %xmm2, %xmm5
+; SSE-NEXT: movdqa %xmm5, %xmm2
+; SSE-NEXT: paddb %xmm5, %xmm2
+; SSE-NEXT: pxor %xmm5, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm6
+; SSE-NEXT: paddb %xmm2, %xmm6
+; SSE-NEXT: paddb %xmm6, %xmm6
+; SSE-NEXT: pxor %xmm2, %xmm6
+; SSE-NEXT: movdqa %xmm6, %xmm2
+; SSE-NEXT: psllw $4, %xmm2
+; SSE-NEXT: pand %xmm4, %xmm2
+; SSE-NEXT: pxor %xmm6, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm6
+; SSE-NEXT: pandn %xmm5, %xmm6
+; SSE-NEXT: movdqa %xmm6, %xmm5
+; SSE-NEXT: paddb %xmm6, %xmm5
+; SSE-NEXT: pxor %xmm6, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm6
; SSE-NEXT: paddb %xmm5, %xmm6
; SSE-NEXT: paddb %xmm6, %xmm6
@@ -40,44 +53,31 @@ define <16 x i8> @pdep_v16i8(<16 x i8> %val, <16 x i8> %mask) nounwind {
; SSE-NEXT: psllw $4, %xmm5
; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: pxor %xmm6, %xmm5
-; SSE-NEXT: movdqa %xmm5, %xmm6
-; SSE-NEXT: pandn %xmm2, %xmm6
-; SSE-NEXT: movdqa %xmm6, %xmm2
-; SSE-NEXT: paddb %xmm6, %xmm2
-; SSE-NEXT: pxor %xmm6, %xmm2
-; SSE-NEXT: movdqa %xmm2, %xmm6
-; SSE-NEXT: paddb %xmm2, %xmm6
-; SSE-NEXT: paddb %xmm6, %xmm6
-; SSE-NEXT: pxor %xmm2, %xmm6
-; SSE-NEXT: movdqa %xmm6, %xmm7
-; SSE-NEXT: psllw $4, %xmm7
-; SSE-NEXT: pand %xmm4, %xmm7
-; SSE-NEXT: pxor %xmm6, %xmm7
; SSE-NEXT: pand %xmm1, %xmm3
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pxor %xmm3, %xmm2
-; SSE-NEXT: movdqa %xmm3, %xmm6
-; SSE-NEXT: psrlw $1, %xmm6
+; SSE-NEXT: movdqa %xmm1, %xmm6
+; SSE-NEXT: pxor %xmm3, %xmm6
+; SSE-NEXT: movdqa %xmm3, %xmm7
+; SSE-NEXT: psrlw $1, %xmm7
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm7
+; SSE-NEXT: por %xmm6, %xmm7
+; SSE-NEXT: pand %xmm7, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm7
+; SSE-NEXT: movdqa %xmm2, %xmm6
+; SSE-NEXT: psrlw $2, %xmm6
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
-; SSE-NEXT: por %xmm2, %xmm6
+; SSE-NEXT: por %xmm7, %xmm6
+; SSE-NEXT: pand %xmm5, %xmm6
+; SSE-NEXT: movdqa %xmm0, %xmm5
+; SSE-NEXT: psllw $4, %xmm5
+; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: pand %xmm6, %xmm5
-; SSE-NEXT: pxor %xmm5, %xmm6
-; SSE-NEXT: movdqa %xmm5, %xmm2
-; SSE-NEXT: psrlw $2, %xmm2
-; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT: por %xmm6, %xmm2
-; SSE-NEXT: pand %xmm7, %xmm2
-; SSE-NEXT: movdqa %xmm0, %xmm6
-; SSE-NEXT: psllw $4, %xmm6
-; SSE-NEXT: pand %xmm4, %xmm6
-; SSE-NEXT: pand %xmm2, %xmm6
-; SSE-NEXT: pandn %xmm0, %xmm2
-; SSE-NEXT: por %xmm6, %xmm2
-; SSE-NEXT: movdqa %xmm5, %xmm0
-; SSE-NEXT: pandn %xmm2, %xmm0
-; SSE-NEXT: psllw $2, %xmm2
+; SSE-NEXT: pandn %xmm0, %xmm6
+; SSE-NEXT: por %xmm5, %xmm6
+; SSE-NEXT: movdqa %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm6, %xmm0
+; SSE-NEXT: psllw $2, %xmm6
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT: pand %xmm5, %xmm2
+; SSE-NEXT: pand %xmm6, %xmm2
; SSE-NEXT: por %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm0
; SSE-NEXT: pandn %xmm2, %xmm0
@@ -138,11 +138,11 @@ define <16 x i8> @pdep_v16i8(<16 x i8> %val, <16 x i8> %mask) nounwind {
; AVX2-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpandn %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpsllw $2, %xmm0, %xmm2
-; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX2-NEXT: vpandn %xmm0, %xmm4, %xmm0
-; AVX2-NEXT: vpand %xmm4, %xmm2, %xmm2
-; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpandn %xmm0, %xmm4, %xmm2
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm3
+; AVX2-NEXT: vpsllw $2, %xmm0, %xmm0
+; AVX2-NEXT: vpand %xmm3, %xmm0, %xmm0
+; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vpandn %xmm0, %xmm5, %xmm2
; AVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm5, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/pdep-vector-256.ll b/llvm/test/CodeGen/X86/pdep-vector-256.ll
index 958f60af49ca4..f61319275c8f3 100644
--- a/llvm/test/CodeGen/X86/pdep-vector-256.ll
+++ b/llvm/test/CodeGen/X86/pdep-vector-256.ll
@@ -54,11 +54,11 @@ define <32 x i8> @pdep_v32i8(<32 x i8> %val, <32 x i8> %mask) nounwind {
; AVX2-NEXT: vpand %ymm3, %ymm2, %ymm2
; AVX2-NEXT: vpandn %ymm0, %ymm3, %ymm0
; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpsllw $2, %ymm0, %ymm2
-; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
-; AVX2-NEXT: vpandn %ymm0, %ymm4, %ymm0
-; AVX2-NEXT: vpand %ymm4, %ymm2, %ymm2
-; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpandn %ymm0, %ymm4, %ymm2
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm3
+; AVX2-NEXT: vpsllw $2, %ymm0, %ymm0
+; AVX2-NEXT: vpand %ymm3, %ymm0, %ymm0
+; AVX2-NEXT: vpor %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpandn %ymm0, %ymm5, %ymm2
; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm5, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll
index 2ac2be5545dfd..d2b292f1a7996 100644
--- a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll
+++ b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll
@@ -119,8 +119,8 @@ define void @failing(ptr %0, ptr %1) nounwind {
; CHECK-AVX2-NEXT: .LBB0_2: # %vector.body
; CHECK-AVX2-NEXT: # Parent Loop BB0_1 Depth=1
; CHECK-AVX2-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-AVX2-NEXT: vmovdqu 1024(%rdx,%rsi), %xmm5
-; CHECK-AVX2-NEXT: vmovdqu 1040(%rdx,%rsi), %xmm6
+; CHECK-AVX2-NEXT: vmovdqu 1024(%rdx,%rsi), %ymm5
+; CHECK-AVX2-NEXT: vextracti128 $1, %ymm5, %xmm6
; CHECK-AVX2-NEXT: vpextrq $1, %xmm5, %rdi
; CHECK-AVX2-NEXT: vpextrq $1, %xmm6, %r8
; CHECK-AVX2-NEXT: vmovq %xmm5, %r9
diff --git a/llvm/test/CodeGen/X86/shift-i128.ll b/llvm/test/CodeGen/X86/shift-i128.ll
index 6c9cdb1b62ca4..06a343abba779 100644
--- a/llvm/test/CodeGen/X86/shift-i128.ll
+++ b/llvm/test/CodeGen/X86/shift-i128.ll
@@ -1077,25 +1077,25 @@ define i128 @shift_i128_limited_shamt_unknown_lhs(i128 noundef %a, i32 noundef %
; i686-NEXT: pushl %esi
; i686-NEXT: andl $-16, %esp
; i686-NEXT: subl $48, %esp
+; i686-NEXT: movl 44(%ebp), %ecx
; i686-NEXT: movl 24(%ebp), %eax
; i686-NEXT: movl 28(%ebp), %edx
; i686-NEXT: movl 32(%ebp), %esi
; i686-NEXT: movl 36(%ebp), %edi
-; i686-NEXT: movl 44(%ebp), %ecx
; i686-NEXT: subl 40(%ebp), %ecx
; i686-NEXT: movl %edi, {{[0-9]+}}(%esp)
; i686-NEXT: movl %esi, {{[0-9]+}}(%esp)
; i686-NEXT: movl %edx, {{[0-9]+}}(%esp)
; i686-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
-; i686-NEXT: movl $0, (%esp)
; i686-NEXT: movl %ecx, %eax
; i686-NEXT: shrb $3, %al
; i686-NEXT: andb $12, %al
; i686-NEXT: negb %al
; i686-NEXT: movsbl %al, %eax
+; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
+; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
+; i686-NEXT: movl $0, {{[0-9]+}}(%esp)
+; i686-NEXT: movl $0, (%esp)
; i686-NEXT: movl 20(%esp,%eax), %edx
; i686-NEXT: movl 24(%esp,%eax), %ebx
; i686-NEXT: movl %ebx, %edi
diff --git a/llvm/test/CodeGen/X86/vector-fshr-128.ll b/llvm/test/CodeGen/X86/vector-fshr-128.ll
index f29afd9f3af0e..5f0d670db69bb 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-128.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-128.ll
@@ -733,65 +733,65 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt)
define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) nounwind {
; SSE2-LABEL: var_funnnel_v16i8:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; SSE2-NEXT: movdqa %xmm2, %xmm6
-; SSE2-NEXT: pand %xmm5, %xmm6
-; SSE2-NEXT: psllw $5, %xmm6
-; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; SSE2-NEXT: movdqa %xmm2, %xmm5
+; SSE2-NEXT: pandn %xmm4, %xmm5
+; SSE2-NEXT: psllw $5, %xmm5
; SSE2-NEXT: pxor %xmm3, %xmm3
-; SSE2-NEXT: pcmpgtb %xmm6, %xmm3
-; SSE2-NEXT: movdqa %xmm3, %xmm7
-; SSE2-NEXT: pandn %xmm1, %xmm7
-; SSE2-NEXT: psrlw $4, %xmm1
-; SSE2-NEXT: pand %xmm1, %xmm3
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE2-NEXT: por %xmm7, %xmm3
-; SSE2-NEXT: paddb %xmm6, %xmm6
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm7
-; SSE2-NEXT: pandn %xmm3, %xmm7
-; SSE2-NEXT: psrlw $2, %xmm3
-; SSE2-NEXT: pand %xmm1, %xmm3
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE2-NEXT: por %xmm7, %xmm3
-; SSE2-NEXT: paddb %xmm6, %xmm6
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm6
-; SSE2-NEXT: pandn %xmm3, %xmm6
-; SSE2-NEXT: psrlw $1, %xmm3
-; SSE2-NEXT: pand %xmm1, %xmm3
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE2-NEXT: por %xmm6, %xmm3
-; SSE2-NEXT: pandn %xmm5, %xmm2
-; SSE2-NEXT: psllw $5, %xmm2
-; SSE2-NEXT: pxor %xmm1, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm2, %xmm1
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm5, %xmm6
; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: movdqa %xmm1, %xmm5
-; SSE2-NEXT: pandn %xmm0, %xmm5
+; SSE2-NEXT: movdqa %xmm6, %xmm7
+; SSE2-NEXT: pandn %xmm0, %xmm7
; SSE2-NEXT: psllw $4, %xmm0
-; SSE2-NEXT: pand %xmm1, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: por %xmm7, %xmm0
+; SSE2-NEXT: paddb %xmm5, %xmm5
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm7
+; SSE2-NEXT: pandn %xmm0, %xmm7
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
+; SSE2-NEXT: por %xmm7, %xmm0
+; SSE2-NEXT: paddb %xmm5, %xmm5
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm5
+; SSE2-NEXT: pandn %xmm0, %xmm5
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0
+; SSE2-NEXT: pand %xmm4, %xmm2
+; SSE2-NEXT: psllw $5, %xmm2
+; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
+; SSE2-NEXT: movdqa %xmm4, %xmm5
+; SSE2-NEXT: pandn %xmm1, %xmm5
+; SSE2-NEXT: psrlw $4, %xmm1
+; SSE2-NEXT: pand %xmm1, %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: por %xmm5, %xmm4
; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm5
-; SSE2-NEXT: pandn %xmm0, %xmm5
-; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: pand %xmm1, %xmm0
-; SSE2-NEXT: por %xmm5, %xmm0
+; SSE2-NEXT: pandn %xmm4, %xmm5
+; SSE2-NEXT: psrlw $2, %xmm4
+; SSE2-NEXT: pand %xmm1, %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: por %xmm5, %xmm4
; SSE2-NEXT: paddb %xmm2, %xmm2
-; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
-; SSE2-NEXT: movdqa %xmm4, %xmm1
-; SSE2-NEXT: pandn %xmm0, %xmm1
-; SSE2-NEXT: paddb %xmm0, %xmm0
-; SSE2-NEXT: pand %xmm4, %xmm0
-; SSE2-NEXT: por %xmm1, %xmm0
-; SSE2-NEXT: por %xmm3, %xmm0
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm3
+; SSE2-NEXT: movdqa %xmm3, %xmm1
+; SSE2-NEXT: pandn %xmm4, %xmm1
+; SSE2-NEXT: psrlw $1, %xmm4
+; SSE2-NEXT: pand %xmm3, %xmm4
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; SSE2-NEXT: por %xmm1, %xmm4
+; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: var_funnnel_v16i8:
@@ -1023,65 +1023,65 @@ define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt)
;
; X86-SSE2-LABEL: var_funnnel_v16i8:
; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; X86-SSE2-NEXT: movdqa %xmm2, %xmm6
-; X86-SSE2-NEXT: pand %xmm5, %xmm6
-; X86-SSE2-NEXT: psllw $5, %xmm6
-; X86-SSE2-NEXT: pxor %xmm4, %xmm4
+; X86-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; X86-SSE2-NEXT: movdqa %xmm2, %xmm5
+; X86-SSE2-NEXT: pandn %xmm4, %xmm5
+; X86-SSE2-NEXT: psllw $5, %xmm5
; X86-SSE2-NEXT: pxor %xmm3, %xmm3
-; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3
-; X86-SSE2-NEXT: movdqa %xmm3, %xmm7
-; X86-SSE2-NEXT: pandn %xmm1, %xmm7
-; X86-SSE2-NEXT: psrlw $4, %xmm1
-; X86-SSE2-NEXT: pand %xmm1, %xmm3
-; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: por %xmm7, %xmm3
-; X86-SSE2-NEXT: paddb %xmm6, %xmm6
-; X86-SSE2-NEXT: pxor %xmm1, %xmm1
-; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; X86-SSE2-NEXT: movdqa %xmm1, %xmm7
-; X86-SSE2-NEXT: pandn %xmm3, %xmm7
-; X86-SSE2-NEXT: psrlw $2, %xmm3
-; X86-SSE2-NEXT: pand %xmm1, %xmm3
-; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: por %xmm7, %xmm3
-; X86-SSE2-NEXT: paddb %xmm6, %xmm6
-; X86-SSE2-NEXT: pxor %xmm1, %xmm1
-; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
-; X86-SSE2-NEXT: movdqa %xmm1, %xmm6
-; X86-SSE2-NEXT: pandn %xmm3, %xmm6
-; X86-SSE2-NEXT: psrlw $1, %xmm3
-; X86-SSE2-NEXT: pand %xmm1, %xmm3
-; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3
-; X86-SSE2-NEXT: por %xmm6, %xmm3
-; X86-SSE2-NEXT: pandn %xmm5, %xmm2
-; X86-SSE2-NEXT: psllw $5, %xmm2
-; X86-SSE2-NEXT: pxor %xmm1, %xmm1
-; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
+; X86-SSE2-NEXT: pxor %xmm6, %xmm6
+; X86-SSE2-NEXT: pcmpgtb %xmm5, %xmm6
; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: movdqa %xmm1, %xmm5
-; X86-SSE2-NEXT: pandn %xmm0, %xmm5
+; X86-SSE2-NEXT: movdqa %xmm6, %xmm7
+; X86-SSE2-NEXT: pandn %xmm0, %xmm7
; X86-SSE2-NEXT: psllw $4, %xmm0
-; X86-SSE2-NEXT: pand %xmm1, %xmm0
+; X86-SSE2-NEXT: pand %xmm6, %xmm0
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: por %xmm7, %xmm0
+; X86-SSE2-NEXT: paddb %xmm5, %xmm5
+; X86-SSE2-NEXT: pxor %xmm6, %xmm6
+; X86-SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; X86-SSE2-NEXT: movdqa %xmm6, %xmm7
+; X86-SSE2-NEXT: pandn %xmm0, %xmm7
+; X86-SSE2-NEXT: paddb %xmm0, %xmm0
+; X86-SSE2-NEXT: paddb %xmm0, %xmm0
+; X86-SSE2-NEXT: pand %xmm6, %xmm0
+; X86-SSE2-NEXT: por %xmm7, %xmm0
+; X86-SSE2-NEXT: paddb %xmm5, %xmm5
+; X86-SSE2-NEXT: pxor %xmm6, %xmm6
+; X86-SSE2-NEXT: pcmpgtb %xmm5, %xmm6
+; X86-SSE2-NEXT: movdqa %xmm6, %xmm5
+; X86-SSE2-NEXT: pandn %xmm0, %xmm5
+; X86-SSE2-NEXT: paddb %xmm0, %xmm0
+; X86-SSE2-NEXT: pand %xmm6, %xmm0
; X86-SSE2-NEXT: por %xmm5, %xmm0
+; X86-SSE2-NEXT: pand %xmm4, %xmm2
+; X86-SSE2-NEXT: psllw $5, %xmm2
+; X86-SSE2-NEXT: pxor %xmm4, %xmm4
+; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm4
+; X86-SSE2-NEXT: movdqa %xmm4, %xmm5
+; X86-SSE2-NEXT: pandn %xmm1, %xmm5
+; X86-SSE2-NEXT: psrlw $4, %xmm1
+; X86-SSE2-NEXT: pand %xmm1, %xmm4
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
+; X86-SSE2-NEXT: por %xmm5, %xmm4
; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm5
-; X86-SSE2-NEXT: pandn %xmm0, %xmm5
-; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: pand %xmm1, %xmm0
-; X86-SSE2-NEXT: por %xmm5, %xmm0
+; X86-SSE2-NEXT: pandn %xmm4, %xmm5
+; X86-SSE2-NEXT: psrlw $2, %xmm4
+; X86-SSE2-NEXT: pand %xmm1, %xmm4
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
+; X86-SSE2-NEXT: por %xmm5, %xmm4
; X86-SSE2-NEXT: paddb %xmm2, %xmm2
-; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm4
-; X86-SSE2-NEXT: movdqa %xmm4, %xmm1
-; X86-SSE2-NEXT: pandn %xmm0, %xmm1
-; X86-SSE2-NEXT: paddb %xmm0, %xmm0
-; X86-SSE2-NEXT: pand %xmm4, %xmm0
-; X86-SSE2-NEXT: por %xmm1, %xmm0
-; X86-SSE2-NEXT: por %xmm3, %xmm0
+; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm3
+; X86-SSE2-NEXT: movdqa %xmm3, %xmm1
+; X86-SSE2-NEXT: pandn %xmm4, %xmm1
+; X86-SSE2-NEXT: psrlw $1, %xmm4
+; X86-SSE2-NEXT: pand %xmm3, %xmm4
+; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
+; X86-SSE2-NEXT: por %xmm1, %xmm4
+; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt)
ret <16 x i8> %res
diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll
index 0b8647ba10575..ae473a07b044e 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll
@@ -519,48 +519,48 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; AVX1-NEXT: vandps %ymm3, %ymm2, %ymm2
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
; AVX1-NEXT: vpsllw $5, %xmm7, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm6, %xmm5, %xmm5
-; AVX1-NEXT: vpsrlw $2, %xmm5, %xmm9
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX1-NEXT: vpand %xmm6, %xmm9, %xmm9
+; AVX1-NEXT: vpblendvb %xmm8, %xmm6, %xmm5, %xmm6
+; AVX1-NEXT: vpsrlw $2, %xmm6, %xmm9
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX1-NEXT: vpand %xmm5, %xmm9, %xmm9
; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm5, %xmm5
-; AVX1-NEXT: vpsrlw $1, %xmm5, %xmm9
+; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm6, %xmm6
+; AVX1-NEXT: vpsrlw $1, %xmm6, %xmm9
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm10 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; AVX1-NEXT: vpand %xmm10, %xmm9, %xmm9
; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm5, %xmm8
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm9
-; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm9
-; AVX1-NEXT: vpsllw $4, %xmm9, %xmm11
-; AVX1-NEXT: vpand %xmm5, %xmm11, %xmm11
+; AVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm6, %xmm6
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm8
+; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
+; AVX1-NEXT: vpsllw $4, %xmm8, %xmm9
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm11 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX1-NEXT: vpand %xmm11, %xmm9, %xmm9
; AVX1-NEXT: vpxor %xmm3, %xmm7, %xmm7
; AVX1-NEXT: vpsllw $5, %xmm7, %xmm7
-; AVX1-NEXT: vpblendvb %xmm7, %xmm11, %xmm9, %xmm9
-; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm11
-; AVX1-NEXT: vpaddb %xmm11, %xmm11, %xmm11
+; AVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm8
+; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm9
+; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm9
; AVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; AVX1-NEXT: vpblendvb %xmm7, %xmm11, %xmm9, %xmm9
-; AVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm11
+; AVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm8
+; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm9
; AVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; AVX1-NEXT: vpblendvb %xmm7, %xmm11, %xmm9, %xmm7
-; AVX1-NEXT: vpor %xmm7, %xmm8, %xmm7
-; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm8
-; AVX1-NEXT: vpand %xmm4, %xmm8, %xmm4
-; AVX1-NEXT: vpsllw $5, %xmm2, %xmm8
-; AVX1-NEXT: vpblendvb %xmm8, %xmm4, %xmm1, %xmm1
+; AVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm7
+; AVX1-NEXT: vpor %xmm6, %xmm7, %xmm6
+; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm7
+; AVX1-NEXT: vpand %xmm4, %xmm7, %xmm4
+; AVX1-NEXT: vpsllw $5, %xmm2, %xmm7
+; AVX1-NEXT: vpblendvb %xmm7, %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm4
-; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
-; AVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm6
-; AVX1-NEXT: vpblendvb %xmm6, %xmm4, %xmm1, %xmm1
+; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
+; AVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm5
+; AVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm4
; AVX1-NEXT: vpand %xmm4, %xmm10, %xmm4
-; AVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm6
-; AVX1-NEXT: vpblendvb %xmm6, %xmm4, %xmm1, %xmm1
+; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
+; AVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm4
-; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
+; AVX1-NEXT: vpand %xmm4, %xmm11, %xmm4
; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsllw $5, %xmm2, %xmm2
; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm0, %xmm0
@@ -572,7 +572,7 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm7, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: var_funnnel_v32i8:
diff --git a/llvm/test/CodeGen/X86/vector-fshr-512.ll b/llvm/test/CodeGen/X86/vector-fshr-512.ll
index 9362fcadd43d6..c8e89b6fc729c 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-512.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-512.ll
@@ -254,24 +254,24 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %amt)
; AVX512F-NEXT: vpaddb %ymm7, %ymm7, %ymm7
; AVX512F-NEXT: vpblendvb %ymm7, %ymm6, %ymm1, %ymm1
; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm1
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm6
-; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm6
-; AVX512F-NEXT: vpsllw $4, %ymm6, %ymm7
-; AVX512F-NEXT: vpand %ymm5, %ymm7, %ymm7
+; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm5
+; AVX512F-NEXT: vpaddb %ymm5, %ymm5, %ymm5
+; AVX512F-NEXT: vpsllw $4, %ymm5, %ymm6
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX512F-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512F-NEXT: vpxor %ymm3, %ymm4, %ymm4
; AVX512F-NEXT: vpsllw $5, %ymm4, %ymm4
-; AVX512F-NEXT: vpblendvb %ymm4, %ymm7, %ymm6, %ymm6
-; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm7
-; AVX512F-NEXT: vpaddb %ymm7, %ymm7, %ymm7
+; AVX512F-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm5
+; AVX512F-NEXT: vpaddb %ymm5, %ymm5, %ymm6
+; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm6
; AVX512F-NEXT: vpaddb %ymm4, %ymm4, %ymm4
-; AVX512F-NEXT: vpblendvb %ymm4, %ymm7, %ymm6, %ymm6
-; AVX512F-NEXT: vpaddb %ymm6, %ymm6, %ymm7
+; AVX512F-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm5
+; AVX512F-NEXT: vpaddb %ymm5, %ymm5, %ymm6
; AVX512F-NEXT: vpaddb %ymm4, %ymm4, %ymm4
-; AVX512F-NEXT: vpblendvb %ymm4, %ymm7, %ymm6, %ymm4
+; AVX512F-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm4
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6
-; AVX512F-NEXT: vpand %ymm5, %ymm6, %ymm5
+; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm5
+; AVX512F-NEXT: vpand %ymm7, %ymm5, %ymm5
; AVX512F-NEXT: vpxor %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
@@ -320,24 +320,24 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y, <64 x i8> %amt)
; AVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
; AVX512VL-NEXT: vpblendvb %ymm6, %ymm5, %ymm1, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm5
-; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
-; AVX512VL-NEXT: vpsllw $4, %ymm5, %ymm6
-; AVX512VL-NEXT: vpand %ymm4, %ymm6, %ymm6
+; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm4
+; AVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm4
+; AVX512VL-NEXT: vpsllw $4, %ymm4, %ymm5
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX512VL-NEXT: vpand %ymm6, %ymm5, %ymm5
; AVX512VL-NEXT: vpxor %ymm7, %ymm3, %ymm3
; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
-; AVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm5
-; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm6
-; AVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; AVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
+; AVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm5
+; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; AVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm5
-; AVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm6
+; AVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
+; AVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm5
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; AVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm3
+; AVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm3
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm5
-; AVX512VL-NEXT: vpand %ymm4, %ymm5, %ymm4
+; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
+; AVX512VL-NEXT: vpand %ymm6, %ymm4, %ymm4
; AVX512VL-NEXT: vpxor %ymm7, %ymm2, %ymm2
; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
index 4435515ae42ef..9119e7b148f4f 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
@@ -3686,8 +3686,8 @@ define void @SpinningCube() {
; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: movss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,1]
-; SSE2-NEXT: movd {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
-; SSE2-NEXT: movq {{.*#+}} xmm2 = xmm2[0],zero
+; SSE2-NEXT: movss {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
+; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
; SSE2-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
@@ -3705,8 +3705,8 @@ define void @SpinningCube() {
; SSSE3-NEXT: xorps %xmm0, %xmm0
; SSSE3-NEXT: movss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,1]
-; SSSE3-NEXT: movd {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
-; SSSE3-NEXT: movq {{.*#+}} xmm2 = xmm2[0],zero
+; SSSE3-NEXT: movss {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
+; SSSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
; SSSE3-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
@@ -3720,11 +3720,12 @@ define void @SpinningCube() {
;
; SSE41-LABEL: SpinningCube:
; SSE41: # %bb.0: # %entry
-; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,zero,mem[0]
-; SSE41-NEXT: movaps %xmm0, %xmm1
+; SSE41-NEXT: movl $1065353216, (%rax) # imm = 0x3F800000
+; SSE41-NEXT: movss {{.*#+}} xmm0 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,zero,xmm0[0]
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
; SSE41-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE41-NEXT: movl $1065353216, (%rax) # imm = 0x3F800000
+; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[0]
; SSE41-NEXT: movaps %xmm1, (%rax)
; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,2]
@@ -3737,7 +3738,8 @@ define void @SpinningCube() {
; AVX: # %bb.0: # %entry
; AVX-NEXT: movl $1065353216, (%rax) # imm = 0x3F800000
; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [0.0E+0,0.0E+0,0.0E+0,1.0E+0]
-; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],mem[0],xmm0[2,3]
+; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],zero,zero,xmm0[3]
+; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
; AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vmovaps %xmm1, (%rax)
; AVX-NEXT: vbroadcastss (%rax), %xmm1
diff --git a/llvm/test/CodeGen/X86/vector-trunc-packus.ll b/llvm/test/CodeGen/X86/vector-trunc-packus.ll
index 9481d9ae70471..394b36a423034 100644
--- a/llvm/test/CodeGen/X86/vector-trunc-packus.ll
+++ b/llvm/test/CodeGen/X86/vector-trunc-packus.ll
@@ -698,29 +698,29 @@ define <8 x i32> @trunc_packus_v8i64_v8i32(ptr %p0) "min-legal-vector-width"="25
;
; AVX1-LABEL: trunc_packus_v8i64_v8i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovsxbd {{.*#+}} xmm4 = [4294967295,0,4294967295,0]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4294967295,0,4294967295,0]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm4[0,2],xmm0[0,2]
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm2[0,2],xmm1[0,2]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
@@ -1688,31 +1688,32 @@ define <8 x i16> @trunc_packus_v8i64_v8i16(ptr %p0) "min-legal-vector-width"="25
;
; AVX1-LABEL: trunc_packus_v8i64_v8i16:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm4 = [65535,65535]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm2 = [65535,65535]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpackusdw %xmm0, %xmm4, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v8i64_v8i16:
@@ -3123,32 +3124,33 @@ define <8 x i8> @trunc_packus_v8i64_v8i8(ptr %p0) "min-legal-vector-width"="256"
;
; AVX1-LABEL: trunc_packus_v8i64_v8i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm4 = [255,255]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm2 = [255,255]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpackusdw %xmm0, %xmm4, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v8i64_v8i8:
@@ -3425,33 +3427,34 @@ define void @trunc_packus_v8i64_v8i8_store(ptr %p0, ptr%p1) "min-legal-vector-wi
;
; AVX1-LABEL: trunc_packus_v8i64_v8i8_store:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm2
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm3
-; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm4 = [255,255]
-; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm4, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm1, %xmm5
-; AVX1-NEXT: vpand %xmm1, %xmm5, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm0, %xmm5
+; AVX1-NEXT: vmovdqa (%rdi), %ymm0
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm2 = [255,255]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm3
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm0, %xmm5, %xmm0
-; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm3
-; AVX1-NEXT: vpand %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm5
+; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpackusdw %xmm0, %xmm4, %xmm0
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm4
+; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, (%rsi)
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v8i64_v8i8_store:
@@ -3936,55 +3939,56 @@ define <16 x i8> @trunc_packus_v16i64_v16i8(ptr %p0) "min-legal-vector-width"="2
;
; AVX1-LABEL: trunc_packus_v16i64_v16i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa 96(%rdi), %xmm0
-; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm2 = [255,255]
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm1
-; AVX1-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0
-; AVX1-NEXT: vmovdqa 112(%rdi), %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
-; AVX1-NEXT: vblendvpd %xmm3, %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vmovdqa 64(%rdi), %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm4
-; AVX1-NEXT: vblendvpd %xmm4, %xmm3, %xmm2, %xmm3
-; AVX1-NEXT: vmovdqa 80(%rdi), %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm4, %xmm2, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm4, %xmm2, %xmm4
-; AVX1-NEXT: vmovdqa (%rdi), %xmm5
-; AVX1-NEXT: vmovdqa 16(%rdi), %xmm6
-; AVX1-NEXT: vmovdqa 32(%rdi), %xmm7
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm8
-; AVX1-NEXT: vpcmpgtq %xmm7, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm7, %xmm2, %xmm7
-; AVX1-NEXT: vpcmpgtq %xmm8, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm8, %xmm2, %xmm8
+; AVX1-NEXT: vmovdqa (%rdi), %ymm2
+; AVX1-NEXT: vmovdqa 32(%rdi), %ymm3
+; AVX1-NEXT: vmovdqa 64(%rdi), %ymm4
+; AVX1-NEXT: vmovdqa 96(%rdi), %ymm1
+; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm5 = [255,255]
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm5, %xmm0
+; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm5, %xmm0
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm5, %xmm6
+; AVX1-NEXT: vblendvpd %xmm6, %xmm1, %xmm5, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm6
+; AVX1-NEXT: vblendvpd %xmm6, %xmm4, %xmm5, %xmm6
+; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm7
+; AVX1-NEXT: vblendvpd %xmm7, %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm3, %xmm5, %xmm7
+; AVX1-NEXT: vblendvpd %xmm7, %xmm3, %xmm5, %xmm7
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm3, %xmm5, %xmm8
+; AVX1-NEXT: vblendvpd %xmm8, %xmm3, %xmm5, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm5, %xmm8
+; AVX1-NEXT: vblendvpd %xmm8, %xmm2, %xmm5, %xmm8
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm5, %xmm9
+; AVX1-NEXT: vblendvpd %xmm9, %xmm2, %xmm5, %xmm2
+; AVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpcmpgtq %xmm5, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm5, %xmm2, %xmm5
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm2, %xmm9
-; AVX1-NEXT: vblendvpd %xmm9, %xmm6, %xmm2, %xmm2
-; AVX1-NEXT: vpxor %xmm6, %xmm6, %xmm6
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm2, %xmm9
; AVX1-NEXT: vpand %xmm2, %xmm9, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm5, %xmm9
-; AVX1-NEXT: vpand %xmm5, %xmm9, %xmm5
-; AVX1-NEXT: vpackusdw %xmm2, %xmm5, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm8, %xmm5
-; AVX1-NEXT: vpand %xmm5, %xmm8, %xmm5
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm8
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm8, %xmm9
+; AVX1-NEXT: vpand %xmm8, %xmm9, %xmm8
+; AVX1-NEXT: vpackusdw %xmm2, %xmm8, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm3, %xmm8
+; AVX1-NEXT: vpand %xmm3, %xmm8, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm7, %xmm8
; AVX1-NEXT: vpand %xmm7, %xmm8, %xmm7
-; AVX1-NEXT: vpackusdw %xmm5, %xmm7, %xmm5
-; AVX1-NEXT: vpackusdw %xmm5, %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm4, %xmm5
-; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm3, %xmm5
-; AVX1-NEXT: vpand %xmm3, %xmm5, %xmm3
-; AVX1-NEXT: vpackusdw %xmm4, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm1, %xmm4
+; AVX1-NEXT: vpackusdw %xmm3, %xmm7, %xmm3
+; AVX1-NEXT: vpackusdw %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm3
+; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm6, %xmm4
+; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
+; AVX1-NEXT: vpackusdw %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm1, %xmm4
; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm6, %xmm0, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm0, %xmm4
; AVX1-NEXT: vpand %xmm0, %xmm4, %xmm0
; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackusdw %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_packus_v16i64_v16i8:
diff --git a/llvm/test/CodeGen/X86/vshift-6.ll b/llvm/test/CodeGen/X86/vshift-6.ll
index 671de15488168..c3e49b87873ba 100644
--- a/llvm/test/CodeGen/X86/vshift-6.ll
+++ b/llvm/test/CodeGen/X86/vshift-6.ll
@@ -27,9 +27,10 @@
define <16 x i8> @do_not_crash(ptr, ptr, ptr, i32, i64, i8) {
; X86-LABEL: do_not_crash:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movb %al, (%ecx)
+; X86-NEXT: movzbl %al, %eax
; X86-NEXT: movd %eax, %xmm1
; X86-NEXT: psllq $56, %xmm1
; X86-NEXT: pcmpeqd %xmm3, %xmm3
diff --git a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
index 6489f950482b6..1e181dc932eac 100644
--- a/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
+++ b/llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
@@ -3273,19 +3273,19 @@ define void @vec384_i8_widen_to_i128_factor16_broadcast_to_v3i128_factor3(ptr %i
;
; AVX1-LABEL: vec384_i8_widen_to_i128_factor16_broadcast_to_v3i128_factor3:
; AVX1: # %bb.0:
-; AVX1-NEXT: vmovdqa (%rdi), %xmm0
-; AVX1-NEXT: vmovdqa 48(%rdi), %xmm1
-; AVX1-NEXT: vpaddb 48(%rsi), %xmm1, %xmm1
-; AVX1-NEXT: vpaddb (%rsi), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa (%rsi), %xmm0
+; AVX1-NEXT: vmovdqa 48(%rsi), %xmm1
+; AVX1-NEXT: vpaddb 48(%rdi), %xmm1, %xmm1
+; AVX1-NEXT: vpaddb (%rdi), %xmm0, %xmm0
; AVX1-NEXT: vpmovsxwq {{.*#+}} xmm2 = [18446744073709551360,18446744073709551615]
; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb (%rdx), %xmm1, %xmm1
; AVX1-NEXT: vpaddb 32(%rdx), %xmm0, %xmm2
; AVX1-NEXT: vpaddb 16(%rdx), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqa %xmm1, (%rcx)
; AVX1-NEXT: vmovdqa %xmm0, 16(%rcx)
; AVX1-NEXT: vmovdqa %xmm2, 32(%rcx)
-; AVX1-NEXT: vmovdqa %xmm1, (%rcx)
; AVX1-NEXT: retq
;
; AVX2-LABEL: vec384_i8_widen_to_i128_factor16_broadcast_to_v3i128_factor3:
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