[llvm] [GlobalISel] [AArch64] Skip redundant shift amount masking during isel (PR #223136)

[Craig Topper via llvm-commits]

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@@ -2964,6 +2964,17 @@ def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
 def : ShiftAlias<"rorv", RORVWr, GPR32>;
 def : ShiftAlias<"rorv", RORVXr, GPR64>;
 
+// ComplexPattern to match shift amounts with redundant AND masks.
+// AArch64 shift instructions only use the low 5 bits (i32) or 6 bits (i64),
+// so AND masks that cover those bits are redundant.
+def shiftMask32 : ComplexPattern<i32, 1, "SelectShiftMask<32>", [], [], 0>;
+def gi_shift_mask32 : GIComplexOperandMatcher<s32, "selectShiftMask32">,
+                      GIComplexPatternEquiv<shiftMask32>;
+
+def : Pat<(i32 (shl GPR32:$Rn, shiftMask32:$Rm)), (LSLVWr GPR32:$Rn, shiftMask32:$Rm)>;
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topperc wrote:

Why no i64 patterns?

https://github.com/llvm/llvm-project/pull/223136