[llvm] [AMDGPU] Use S_CMP to lower a copy of a lane mask to SCC (PR #221445)

Jay Foad via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 14 08:01:01 PDT 2026


================
@@ -5037,6 +5037,106 @@ bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
   return pseudoToMCOpcode(Op32) != -1;
 }
 
+/// Return true if \p MI is a VALU comparison, i.e. an instruction that writes
+/// a lane mask with one bit per lane, and zeroes the bits of lanes that were
+/// inactive when it executed. The VOP3 (_e64) encodings are not themselves
+/// marked as VOPC, so also check the VOPC (_e32) equivalent.
+///
+/// TODO: Also handle the sdst result of V_ADD_CO_U32 and V_SUB_CO_U32 amd
+/// V_DIV_SCALE_F32.
+static bool isVCmp(const SIInstrInfo &TII, const MachineInstr &MI) {
+  if (TII.isVOPC(MI))
+    return true;
+  int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
+  return Op32 != -1 && TII.isVOPC(Op32);
+}
+
+/// Worker for SIInstrInfo::isMaskedByExec. Every definition the result depends
+/// on must be in \p MBB, and is added to \p Defs so that the caller can check
+/// that EXEC is not modified between it and the use. Definitions are removed
+/// again when a branch of the search fails, so that on success \p Defs only
+/// holds definitions the result really depends on.
+static bool isMaskedByExecImpl(const SIInstrInfo &TII,
+                               const AMDGPU::LaneMaskConstants &LMC,
+                               Register Reg, const MachineBasicBlock *MBB,
+                               SmallSetVector<const MachineInstr *, 8> &Defs,
+                               const MachineRegisterInfo &MRI, unsigned Depth) {
+  // EXEC itself is trivially masked by EXEC.
+  if (Reg == LMC.ExecReg)
+    return true;
+
+  if (Depth == 0 || !Reg.isVirtual())
+    return false;
+
+  // Only look at definitions that can execute under the same EXEC mask as the
+  // use. Note that this also rules out instructions that write EXEC
+  // themselves, such as V_CMPX, since those would be found by the caller's
+  // scan for writes to EXEC.
+  const MachineInstr *Def = MRI.getVRegDef(Reg);
+  if (Def->getParent() != MBB)
----------------
jayfoad wrote:

Done.

https://github.com/llvm/llvm-project/pull/221445


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