[llvm] [SystemZ] Expand and automate .insn directive coverage (PR #222031)
Dominik Steenken via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 06:57:15 PDT 2026
https://github.com/dominik-steenken updated https://github.com/llvm/llvm-project/pull/222031
>From 3ed8eff7ce0b33816124d551fafd1a5eeead9c49 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Thu, 26 Jun 2025 14:44:30 +0200
Subject: [PATCH 01/11] [SystemZ] Support all formats with .insn directive
This commit expands the set of supported instruction formats for the .insn
directive to all published instruction formats. This includes all of the
subformats (e.g., RI-a, RI-b, etc.). Subformats are indicated by an
underscore `_`, followed by the subscript letter of the subformat in the
assembly (e.g. "ri_a" for RI-a). Newly supported formats are:
- I
- IE
- MII
- RI-[abc]
- RIE-[abcdefg]
- RIL[abc]
- RRD
- RRF-[abcde]
- RS-[ab]
- RSL-[ab]
- RSY-[ab]
- RX-[ab]
- RXY-[abc]
- SMI
- SS-[abcdef]
- VRI-[abcdefghijkl]
- VRR-[abcdefghijk]
- VRS-[abcd]
Note that some of these formats have immediate operands which are interpreted
inconsistently by the instructions using the format, i.e. some instructions
use them as signed immediates, while some use them as unsigned immediates.
This commit adds assembler operand types to support a range check on these
immediates that uses the union of the signed and unsigned ranges. So, an
8-bit immediate in a format that is used in both signed and unsigned forms
will accept the range [-128..255].
This commit also reorganizes the tests for the .insn directives to group
them by machine, to mirror the regular assembly tests.
---
.../SystemZ/AsmParser/SystemZAsmParser.cpp | 404 ++++++++++++---
.../MCTargetDesc/SystemZInstPrinterCommon.cpp | 27 +
.../MCTargetDesc/SystemZInstPrinterCommon.h | 3 +
.../MCTargetDesc/SystemZMCAsmBackend.cpp | 12 +
.../SystemZ/MCTargetDesc/SystemZMCFixups.h | 7 +
.../lib/Target/SystemZ/SystemZInstrFormats.td | 471 +++++++++++++++++-
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 413 ++++++++++++---
llvm/lib/Target/SystemZ/SystemZOperands.td | 18 +
llvm/test/MC/SystemZ/directive-insn-z13.s | 59 +++
llvm/test/MC/SystemZ/directive-insn-z14.s | 33 ++
llvm/test/MC/SystemZ/directive-insn-z16.s | 14 +
llvm/test/MC/SystemZ/directive-insn-z17.s | 23 +
llvm/test/MC/SystemZ/directive-insn.s | 136 ++++-
13 files changed, 1470 insertions(+), 150 deletions(-)
create mode 100644 llvm/test/MC/SystemZ/directive-insn-z13.s
create mode 100644 llvm/test/MC/SystemZ/directive-insn-z14.s
create mode 100644 llvm/test/MC/SystemZ/directive-insn-z16.s
create mode 100644 llvm/test/MC/SystemZ/directive-insn-z17.s
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 761cbaaedd22d..9484030c87aa1 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -397,11 +397,14 @@ class SystemZOperand : public MCParsedAsmOperand {
bool isU4Imm() const { return isImm(0, 15); }
bool isU8Imm() const { return isImm(0, 255); }
bool isS8Imm() const { return isImm(-128, 127); }
+ bool isX8Imm() const { return isS8Imm() || isU8Imm(); }
bool isU12Imm() const { return isImm(0, 4095); }
bool isU16Imm() const { return isImm(0, 65535); }
bool isS16Imm() const { return isImm(-32768, 32767); }
+ bool isX16Imm() const { return isS16Imm() || isU16Imm(); }
bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
+ bool isX32Imm() const { return isS32Imm() || isU32Imm(); }
bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
};
@@ -663,71 +666,333 @@ struct CompareInsn {
// Table initializing information for parsing the .insn directive.
static struct InsnMatchEntry InsnMatchTable[] = {
- /* Format, Opcode, NumOperands, OperandKinds */
- { "e", SystemZ::InsnE, 1,
- { MCK_U16Imm } },
- { "ri", SystemZ::InsnRI, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
- { "rie", SystemZ::InsnRIE, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
- { "ril", SystemZ::InsnRIL, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
- { "rilu", SystemZ::InsnRILU, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
- { "ris", SystemZ::InsnRIS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
- { "rr", SystemZ::InsnRR, 3,
- { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
- { "rre", SystemZ::InsnRRE, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
- { "rrf", SystemZ::InsnRRF, 5,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
- { "rrs", SystemZ::InsnRRS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
- { "rs", SystemZ::InsnRS, 4,
- { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
- { "rse", SystemZ::InsnRSE, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
- { "rsi", SystemZ::InsnRSI, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
- { "rsy", SystemZ::InsnRSY, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
- { "rx", SystemZ::InsnRX, 3,
- { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxe", SystemZ::InsnRXE, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxf", SystemZ::InsnRXF, 4,
- { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
- { "rxy", SystemZ::InsnRXY, 3,
- { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
- { "s", SystemZ::InsnS, 2,
- { MCK_U32Imm, MCK_BDAddr64Disp12 } },
- { "si", SystemZ::InsnSI, 3,
- { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
- { "sil", SystemZ::InsnSIL, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
- { "siy", SystemZ::InsnSIY, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
- { "ss", SystemZ::InsnSS, 4,
- { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
- { "sse", SystemZ::InsnSSE, 3,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
- { "ssf", SystemZ::InsnSSF, 4,
- { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
- { "vri", SystemZ::InsnVRI, 6,
- { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
- { "vrr", SystemZ::InsnVRR, 7,
- { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
- MCK_U4Imm } },
- { "vrs", SystemZ::InsnVRS, 5,
- { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
- { "vrv", SystemZ::InsnVRV, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
- { "vrx", SystemZ::InsnVRX, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
- { "vsi", SystemZ::InsnVSI, 4,
- { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
-};
+ /* Format, Opcode, NumOperands, OperandKinds */
+ {"e", SystemZ::InsnE, 1, {MCK_U16Imm}},
+ {"i", SystemZ::InsnI, 2, {MCK_U16Imm, MCK_U8Imm}},
+ {"ie", SystemZ::InsnIE, 3, {MCK_U32Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"mii",
+ SystemZ::InsnMII,
+ 4,
+ {MCK_U48Imm, MCK_U4Imm, MCK_PCRel12, MCK_PCRel24}},
+ {"ri", SystemZ::InsnRIa, 3, {MCK_U32Imm, MCK_AnyReg, MCK_S16Imm}},
+ {"ri_a", SystemZ::InsnRIa, 3, {MCK_U32Imm, MCK_AnyReg, MCK_X16Imm}},
+ {"ri_b", SystemZ::InsnRIb, 3, {MCK_U32Imm, MCK_AnyReg, MCK_PCRel16}},
+ {"ri_c", SystemZ::InsnRIc, 3, {MCK_U32Imm, MCK_U4Imm, MCK_PCRel16}},
+ {"rie",
+ SystemZ::InsnRIE,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16}},
+ {"rie_a",
+ SystemZ::InsnRIEa,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_X16Imm, MCK_U4Imm}},
+ {"rie_b",
+ SystemZ::InsnRIEb,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_PCRel16}},
+ {"rie_c",
+ SystemZ::InsnRIEc,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_X8Imm, MCK_U4Imm, MCK_PCRel16}},
+ {"rie_d",
+ SystemZ::InsnRIEd,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_S16Imm, MCK_AnyReg}},
+ {"rie_e",
+ SystemZ::InsnRIEe,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_PCRel16, MCK_AnyReg}},
+ {"rie_f",
+ SystemZ::InsnRIEf,
+ 6,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U8Imm, MCK_U8Imm, MCK_U8Imm}},
+ {"rie_g",
+ SystemZ::InsnRIEg,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_S16Imm, MCK_U4Imm}},
+ {"ril", SystemZ::InsnRIL, 3, {MCK_U48Imm, MCK_AnyReg, MCK_PCRel32}},
+ {"ril_a", SystemZ::InsnRILa, 3, {MCK_U48Imm, MCK_AnyReg, MCK_X32Imm}},
+ {"ril_b", SystemZ::InsnRILb, 3, {MCK_U48Imm, MCK_AnyReg, MCK_PCRel32}},
+ {"ril_c", SystemZ::InsnRILc, 3, {MCK_U48Imm, MCK_U4Imm, MCK_PCRel32}},
+ {"rilu", SystemZ::InsnRILU, 3, {MCK_U48Imm, MCK_AnyReg, MCK_U32Imm}},
+ {"ris",
+ SystemZ::InsnRIS,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_X8Imm, MCK_U4Imm, MCK_BDAddr64Disp12}},
+ {"rr", SystemZ::InsnRR, 3, {MCK_U16Imm, MCK_AnyReg, MCK_AnyReg}},
+ {"rrd",
+ SystemZ::InsnRRD,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg}},
+ {"rre", SystemZ::InsnRRE, 3, {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg}},
+
+ {"rrf",
+ SystemZ::InsnRRF,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_a",
+ SystemZ::InsnRRFa,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_b",
+ SystemZ::InsnRRFb,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_c",
+ SystemZ::InsnRRFc,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_d",
+ SystemZ::InsnRRFd,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
+ {"rrf_e",
+ SystemZ::InsnRRFe,
+ 5,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_U4Imm}},
+ {"rrs",
+ SystemZ::InsnRRS,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12}},
+ {"rs",
+ SystemZ::InsnRS,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12}},
+ {"rs_a",
+ SystemZ::InsnRSa,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"rs_b",
+ SystemZ::InsnRSb,
+ 4,
+ {MCK_U32Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U4Imm}},
+ {"rse",
+ SystemZ::InsnRSE,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12}},
+ {"rsi",
+ SystemZ::InsnRSI,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16}},
+ {"rsl_a", SystemZ::InsnRSLa, 2, {MCK_U48Imm, MCK_BDLAddr64Disp12Len4}},
+ {"rsl_b",
+ SystemZ::InsnRSLb,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDLAddr64Disp12Len8, MCK_U4Imm}},
+ {"rsy",
+ SystemZ::InsnRSY,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20}},
+ {"rsy_a",
+ SystemZ::InsnRSYa,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp20, MCK_AnyReg}},
+ {"rsy_b",
+ SystemZ::InsnRSYb,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp20, MCK_U4Imm}},
+ {"rx", SystemZ::InsnRX, 3, {MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rx_a",
+ SystemZ::InsnRXa,
+ 3,
+ {MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rx_b", SystemZ::InsnRXb, 3, {MCK_U32Imm, MCK_U4Imm, MCK_BDXAddr64Disp12}},
+ {"rxe", SystemZ::InsnRXE, 3, {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rxf",
+ SystemZ::InsnRXF,
+ 4,
+ {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12}},
+ {"rxy", SystemZ::InsnRXY, 3, {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
+ {"rxy_a",
+ SystemZ::InsnRXYa,
+ 3,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
+ {"rxy_b",
+ SystemZ::InsnRXYb,
+ 3,
+ {MCK_U48Imm, MCK_U4Imm, MCK_BDXAddr64Disp20}},
+ {"rxy_c",
+ SystemZ::InsnRXYc,
+ 3,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
+ {"s", SystemZ::InsnS, 2, {MCK_U32Imm, MCK_BDAddr64Disp12}},
+ {"si", SystemZ::InsnSI, 3, {MCK_U32Imm, MCK_BDAddr64Disp12, MCK_X8Imm}},
+ {"sil", SystemZ::InsnSIL, 3, {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_X16Imm}},
+ {"siy", SystemZ::InsnSIY, 3, {MCK_U48Imm, MCK_BDAddr64Disp20, MCK_X8Imm}},
+ {"smi",
+ SystemZ::InsnSMI,
+ 4,
+ {MCK_U48Imm, MCK_U4Imm, MCK_PCRel16, MCK_BDAddr64Disp12}},
+ {"ss",
+ SystemZ::InsnSS,
+ 4,
+ {MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"ss_a",
+ SystemZ::InsnSSa,
+ 3,
+ {MCK_U48Imm, MCK_BDLAddr64Disp12Len8, MCK_BDAddr64Disp12}},
+ {"ss_b",
+ SystemZ::InsnSSb,
+ 3,
+ {MCK_U48Imm, MCK_BDLAddr64Disp12Len4, MCK_BDLAddr64Disp12Len4}},
+ {"ss_c",
+ SystemZ::InsnSSc,
+ 4,
+ {MCK_U48Imm, MCK_BDLAddr64Disp12Len4, MCK_BDAddr64Disp12, MCK_U4Imm}},
+ {"ss_d",
+ SystemZ::InsnSSd,
+ 4,
+ {MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"ss_e",
+ SystemZ::InsnSSe,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_AnyReg,
+ MCK_BDAddr64Disp12}},
+ {"ss_f",
+ SystemZ::InsnSSf,
+ 3,
+ {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDLAddr64Disp12Len8}},
+ {"sse",
+ SystemZ::InsnSSE,
+ 3,
+ {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12}},
+ {"ssf",
+ SystemZ::InsnSSF,
+ 4,
+ {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"vri",
+ SystemZ::InsnVRIe,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vri_a",
+ SystemZ::InsnVRIa,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_X16Imm, MCK_U4Imm}},
+ {"vri_b",
+ SystemZ::InsnVRIb,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_U8Imm, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_c",
+ SystemZ::InsnVRIc,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_U16Imm, MCK_VR128, MCK_U4Imm}},
+ {"vri_d",
+ SystemZ::InsnVRId,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_e",
+ SystemZ::InsnVRIe,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U16Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vri_f",
+ SystemZ::InsnVRIf,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_g",
+ SystemZ::InsnVRIg,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_h",
+ SystemZ::InsnVRIh,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_U16Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vri_i",
+ SystemZ::InsnVRIi,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_AnyReg, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_j",
+ SystemZ::InsnVRIj,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
+ {"vri_k",
+ SystemZ::InsnVRIk,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm}},
+ {"vri_l",
+ SystemZ::InsnVRIl,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U16Imm}},
+ {"vrr",
+ SystemZ::InsnVRR,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_a",
+ SystemZ::InsnVRRa,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm, MCK_U4Imm}},
+ {"vrr_b",
+ SystemZ::InsnVRRb,
+ 6,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm}},
+ {"vrr_c",
+ SystemZ::InsnVRRc,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_d",
+ SystemZ::InsnVRRd,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_e",
+ SystemZ::InsnVRRe,
+ 7,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm,
+ MCK_U4Imm}},
+ {"vrr_f",
+ SystemZ::InsnVRRf,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_AnyReg, MCK_AnyReg}},
+ {"vrr_g", SystemZ::InsnVRRg, 3, {MCK_U48Imm, MCK_VR128, MCK_U16Imm}},
+ {"vrr_h",
+ SystemZ::InsnVRRh,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm}},
+ {"vrr_i",
+ SystemZ::InsnVRRi,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_U4Imm, MCK_U4Imm}},
+ {"vrr_j",
+ SystemZ::InsnVRRj,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm}},
+ {"vrr_k",
+ SystemZ::InsnVRRk,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm}},
+ {"vrs",
+ SystemZ::InsnVRS,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm}},
+ {"vrs_a",
+ SystemZ::InsnVRSa,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_VR128, MCK_U4Imm}},
+ {"vrs_b",
+ SystemZ::InsnVRSb,
+ 5,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_AnyReg, MCK_U4Imm}},
+ {"vrs_c",
+ SystemZ::InsnVRSc,
+ 5,
+ {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_VR128, MCK_U4Imm}},
+ {"vrs_d",
+ SystemZ::InsnVRSd,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_AnyReg}},
+ {"vrv",
+ SystemZ::InsnVRV,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm}},
+ {"vrx",
+ SystemZ::InsnVRX,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm}},
+ {"vsi",
+ SystemZ::InsnVSI,
+ 4,
+ {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm}}};
void SystemZOperand::print(raw_ostream &OS, const MCAsmInfo &MAI) const {
switch (Kind) {
@@ -1311,6 +1576,12 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ResTy = parsePCRel32(Operands);
else if (Kind == MCK_PCRel16)
ResTy = parsePCRel16(Operands);
+ else if (Kind == MCK_PCRel12)
+ ResTy = parsePCRel12(Operands);
+ else if (Kind == MCK_PCRel24)
+ ResTy = parsePCRel24(Operands);
+ else if (Kind == MCK_BDLAddr64Disp12Len4 || Kind == MCK_BDLAddr64Disp12Len8)
+ ResTy = parseBDLAddr64(Operands);
else {
// Only remaining operand kind is an immediate.
const MCExpr *Expr;
@@ -1319,7 +1590,6 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
// Expect immediate expression.
if (Parser.parseExpression(Expr))
return Error(StartLoc, "unexpected token in directive");
-
SMLoc EndLoc =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
@@ -1353,6 +1623,8 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ZOperand.addBDXAddrOperands(Inst, 3);
else if (ZOperand.isMem(BDVMem))
ZOperand.addBDVAddrOperands(Inst, 3);
+ else if (ZOperand.isMem(BDLMem))
+ ZOperand.addBDLAddrOperands(Inst, 3);
else if (ZOperand.isMem(LXAMem))
ZOperand.addLXAAddrOperands(Inst, 3);
else if (ZOperand.isImm())
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
index a24543b699ab4..1e9936194c94a 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
@@ -118,6 +118,15 @@ void SystemZInstPrinterCommon::printU8ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<8>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX8ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<8>(MI, OpNum, O);
+ else
+ printSImmOperand<8>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printU12ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printUImmOperand<12>(MI, OpNum, O);
@@ -133,6 +142,15 @@ void SystemZInstPrinterCommon::printU16ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<16>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX16ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<16>(MI, OpNum, O);
+ else
+ printSImmOperand<16>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printS32ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printSImmOperand<32>(MI, OpNum, O);
@@ -143,6 +161,15 @@ void SystemZInstPrinterCommon::printU32ImmOperand(const MCInst *MI, int OpNum,
printUImmOperand<32>(MI, OpNum, O);
}
+void SystemZInstPrinterCommon::printX32ImmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ if (Value >= 0)
+ printUImmOperand<32>(MI, OpNum, O);
+ else
+ printSImmOperand<32>(MI, OpNum, O);
+}
+
void SystemZInstPrinterCommon::printU48ImmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
printUImmOperand<48>(MI, OpNum, O);
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
index 427dbba6ad1b4..3d6aa3c12eb52 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
@@ -65,11 +65,14 @@ class SystemZInstPrinterCommon : public MCInstPrinter {
void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printX32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printU48ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printPCRelOperand(const MCInst *MI, uint64_t Address, int OpNum,
raw_ostream &O);
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
index d692cbed129ca..0cfe4db5cae65 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
@@ -54,6 +54,12 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
return Value;
};
+ auto handleXImmValue = [&](unsigned W) -> uint64_t {
+ if (!checkFixupInRange(minIntN(W), maxUIntN(W)))
+ return 0;
+ return Value;
+ };
+
switch (unsigned(Kind)) {
case SystemZ::FK_390_PC12DBL:
return handlePCRelFixupValue(12);
@@ -91,12 +97,18 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
return handleImmValue(false, 4);
case SystemZ::FK_390_U8Imm:
return handleImmValue(false, 8);
+ case SystemZ::FK_390_X8Imm:
+ return handleXImmValue(8);
case SystemZ::FK_390_U12Imm:
return handleImmValue(false, 12);
case SystemZ::FK_390_U16Imm:
return handleImmValue(false, 16);
+ case SystemZ::FK_390_X16Imm:
+ return handleXImmValue(16);
case SystemZ::FK_390_U32Imm:
return handleImmValue(false, 32);
+ case SystemZ::FK_390_X32Imm:
+ return handleXImmValue(32);
case SystemZ::FK_390_U48Imm:
return handleImmValue(false, 48);
}
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
index 1ff4217018f1f..aa8ca7e2312d0 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
@@ -36,6 +36,10 @@ enum FixupKind {
FK_390_U32Imm,
FK_390_U48Imm,
+ FK_390_X8Imm,
+ FK_390_X16Imm,
+ FK_390_X32Imm,
+
// Marker
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
@@ -61,6 +65,9 @@ const static MCFixupKindInfo MCFixupKindInfos[SystemZ::NumTargetFixupKinds] = {
{"FK_390_U16Imm", 0, 16, 0},
{"FK_390_U32Imm", 0, 32, 0},
{"FK_390_U48Imm", 0, 48, 0},
+ {"FK_390_X8Imm", 0, 8, 0},
+ {"FK_390_X16Imm", 0, 16, 0},
+ {"FK_390_X32Imm", 0, 32, 0},
};
// clang-format on
} // end namespace SystemZ
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 82415f412509f..00452377bbf5f 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -1768,26 +1768,129 @@ class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst = enc;
}
-class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIa<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnI<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstI<0, outs, ins, asmstr, pattern> {
+ bits<16> enc;
+
+ let Inst{15 -8} = enc{15 -8};
+}
+
+class DirectiveInsnIE<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstIE<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -16} = enc{31 -16};
+}
+
+class DirectiveInsnMII<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstMII<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+}
+
+class DirectiveInsnRIa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
let Inst{19-16} = enc{19-16};
}
-class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEd<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnRIb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIb<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -24} = enc{31 -24};
+ let Inst{19 -16} = enc{19 -16};
+}
+
+class DirectiveInsnRIc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIc<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -24} = enc{31 -24};
+ let Inst{19 -16} = enc{19 -16};
+}
+
+class DirectiveInsnRIEa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIEa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRIEb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIEb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRIEc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIEc<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRIEd<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIEd<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
-class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRILa<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnRIEe<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIEe<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRIEf<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIEf<0, outs, ins, asmstr, pattern> {
bits<48> enc;
- string type;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRIEg<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRIEg<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRILa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRILa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+ // string type;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{35 -32} = enc{35 -32};
+}
+
+class DirectiveInsnRILb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRILb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+ // string type;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{35 -32} = enc{35 -32};
+}
+
+class DirectiveInsnRILc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRILc<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+ // string type;
let Inst{47-40} = enc{47-40};
let Inst{35-32} = enc{35-32};
@@ -1808,6 +1911,13 @@ class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{15-8} = enc{15-8};
}
+class DirectiveInsnRRD<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRRD<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -16} = enc{31 -16};
+}
+
class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRRE<0, outs, ins, asmstr, pattern> {
bits<32> enc;
@@ -1815,13 +1925,36 @@ class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{31-16} = enc{31-16};
}
-class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRFa<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnRRFa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRRFa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-16} = enc{31-16};
}
+// RRF-b is identical to RRF-a, and is thus omitted
+
+class DirectiveInsnRRFc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRRFc<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -16} = enc{31 -16};
+}
+
+class DirectiveInsnRRFd<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRRFd<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -16} = enc{31 -16};
+}
+
+class DirectiveInsnRRFe<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRRFe<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -16} = enc{31 -16};
+}
+
class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRRS<0, outs, ins, asmstr, pattern> {
bits<48> enc;
@@ -1830,13 +1963,20 @@ class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{7-0} = enc{7-0};
}
-class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSa<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnRSa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRSa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
}
+class DirectiveInsnRSb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRSb<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -24} = enc{31 -24};
+}
+
class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRSEa<6, outs, ins, asmstr, pattern> {
bits <48> enc;
@@ -1852,21 +1992,52 @@ class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{31-24} = enc{31-24};
}
-class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSYa<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnRSLa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRSLa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRSLb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRSLb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRSYa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRSYa<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
-class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXa<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnRSYb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRSYb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRXa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRXa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
}
+class DirectiveInsnRXb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRXb<0, outs, ins, asmstr, pattern> {
+ bits<32> enc;
+
+ let Inst{31 -24} = enc{31 -24};
+}
+
class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRXE<0, outs, ins, asmstr, pattern> {
bits<48> enc;
@@ -1885,8 +2056,24 @@ class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{7-0} = enc{7-0};
}
-class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXYa<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnRXYa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRXYa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRXYb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRXYb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnRXYc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstRXYa<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
@@ -1922,13 +2109,55 @@ class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{47-32} = enc{47-32};
}
-class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSd<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnSMI<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSMI<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+}
+
+class DirectiveInsnSSa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSSa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+}
+
+class DirectiveInsnSSb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSSb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+}
+
+class DirectiveInsnSSc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSSc<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+}
+
+class DirectiveInsnSSd<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSSd<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
}
+class DirectiveInsnSSe<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSSe<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+}
+
+class DirectiveInsnSSf<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSSf<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+}
+
class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSSE<0, outs, ins, asmstr, pattern> {
bits<48> enc;
@@ -1944,30 +2173,222 @@ class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{35-32} = enc{35-32};
}
-class DirectiveInsnVRI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIe<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnVRIa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIc<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRId<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRId<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIe<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIe<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
-class DirectiveInsnVRR<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRc<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnVRIf<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIf<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIg<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIg<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIh<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIh<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIi<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIi<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIj<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIj<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIk<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIk<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRIl<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRIl<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRc<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
-class DirectiveInsnVRS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRSc<0, outs, ins, asmstr, pattern> {
+class DirectiveInsnVRRd<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRd<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRe<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRe<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRf<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRf<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRg<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRg<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRh<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRh<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRi<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRi<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRj<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRj<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRRk<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRRk<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRSa<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRSa<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRSb<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRSb<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
+class DirectiveInsnVRSc<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRSc<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
+class DirectiveInsnVRSd<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstVRSd<0, outs, ins, asmstr, pattern> {
+ bits<48> enc;
+
+ let Inst{47 -40} = enc{47 -40};
+ let Inst{7 -0} = enc{7 -0};
+}
+
class DirectiveInsnVRV<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstVRV<0, outs, ins, asmstr, pattern> {
bits<48> enc;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index f53716a663ed8..73708d3a4e0b3 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2277,42 +2277,140 @@ let hasSideEffects = 1 in {
let isCodeGenOnly = 1, hasSideEffects = 1 in {
def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
- def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
- imm32sx16:$I2),
+ def InsnI : DirectiveInsnI<(outs), (ins imm64zx16:$enc, imm32zx8:$I1),
+ ".insn i,$enc,$I1", []>;
+ def InsnIE : DirectiveInsnIE<(outs),
+ (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
+ ".insn ie,$enc,$I1,$I2", []>;
+ def InsnMII : DirectiveInsnMII<(outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1,
+ brtarget12bpp:$RI2, brtarget24bpp:$RI3),
+ ".insn mii,$enc,$M1,$RI2,$RI3", []>;
+ def InsnRI : DirectiveInsnRIa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
".insn ri,$enc,$R1,$I2", []>;
- def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, brtarget16:$I2),
- ".insn rie,$enc,$R1,$R3,$I2", []>;
- def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- brtarget32:$I2),
- ".insn ril,$enc,$R1,$I2", []>;
- def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- uimm32:$I2),
- ".insn rilu,$enc,$R1,$I2", []>;
- def InsnRIS : DirectiveInsnRIS<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- imm32sx8:$I2, imm32zx4:$M3,
- (bdaddr12only $B4, $D4):$BD4),
- ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
+ def InsnRIa
+ : DirectiveInsnRIa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
+ ".insn ri_a,$enc,$R1,$I2", []>;
+ def InsnRIb
+ : DirectiveInsnRIb<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
+ ".insn ri_b,$enc,$R1,$RI2", []>;
+ def InsnRIc
+ : DirectiveInsnRIc<(outs),
+ (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
+ ".insn ri_c,$enc,$M1,$RI2", []>;
+ def InsnRIE : DirectiveInsnRIEd<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ brtarget16:$I2),
+ ".insn rie,$enc,$R1,$R3,$I2", []>;
+ def InsnRIEa : DirectiveInsnRIEa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ imm32xx16:$I2, imm32zx4:$M3),
+ ".insn rie_a,$enc,$R1,$I2,$M3", []>;
+ def InsnRIEb : DirectiveInsnRIEb<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx4:$M3, brtarget16:$RI4),
+ ".insn rie_b,$enc,$R1,$R2,$M3,$RI4", []>;
+ def InsnRIEc
+ : DirectiveInsnRIEc<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
+ imm32zx4:$M3, brtarget16:$RI4),
+ ".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>;
+ def InsnRIEd
+ : DirectiveInsnRIEd<
+ (outs), (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
+ ".insn rie_d,$enc,$R1,$I2,$R3", []>;
+ def InsnRIEe : DirectiveInsnRIEe<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ brtarget16:$RI2, AnyReg:$R3),
+ ".insn rie_e,$enc,$R1,$RI2,$R3", []>;
+ def InsnRIEf
+ : DirectiveInsnRIEf<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
+ ".insn rie_f,$enc,$R1,$R2,$I3,$I4,$I5", []>;
+ def InsnRIEg : DirectiveInsnRIEg<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ imm32sx16:$I2, imm32zx4:$M3),
+ ".insn rie_g,$enc,$R1,$I2,$M3", []>;
+ def InsnRIL
+ : DirectiveInsnRILa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
+ ".insn ril,$enc,$R1,$I2", []>;
+ def InsnRILa
+ : DirectiveInsnRILa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
+ ".insn ril_a,$enc,$R1,$I2", []>;
+ def InsnRILb
+ : DirectiveInsnRILb<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
+ ".insn ril_b,$enc,$R1,$RI2", []>;
+ def InsnRILc
+ : DirectiveInsnRILc<(outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
+ ".insn ril_c,$enc,$M1,$RI2", []>;
+ def InsnRILU
+ : DirectiveInsnRILa<(outs), (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
+ ".insn rilu,$enc,$R1,$I2", []>;
+ def InsnRIS
+ : DirectiveInsnRIS<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
+ imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
+ ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
def InsnRR : DirectiveInsnRR<(outs),
(ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
".insn rr,$enc,$R1,$R2", []>;
+ def InsnRRD
+ : DirectiveInsnRRD<
+ (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3),
+ ".insn rrd,$enc,$R1,$R2,%R3", []>;
def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc,
AnyReg:$R1, AnyReg:$R2),
".insn rre,$enc,$R1,$R2", []>;
- def InsnRRF : DirectiveInsnRRF<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
+ def InsnRRF : DirectiveInsnRRFa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
AnyReg:$R3, imm32zx4:$M4),
- ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
+ ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
+ def InsnRRFa : DirectiveInsnRRFa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
+ AnyReg:$R3, imm32zx4:$M4),
+ ".insn rrf_a,$enc,$R1,$R2,$R3,$M4", []>;
+ def InsnRRFb : DirectiveInsnRRFa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
+ AnyReg:$R3, imm32zx4:$M4),
+ ".insn rrf_b,$enc,$R1,$R2,$R3,$M4", []>;
+ def InsnRRFc
+ : DirectiveInsnRRFc<
+ (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
+ ".insn rrf_c,$enc,$R1,$R2,$M3", []>;
+ def InsnRRFd
+ : DirectiveInsnRRFd<
+ (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
+ ".insn rrf_d,$enc,$R1,$R2,$M4", []>;
+ def InsnRRFe : DirectiveInsnRRFe<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx4:$M3, imm32zx4:$M4),
+ ".insn rrf_e,$enc,$R1,$R2,$M3,$M4", []>;
def InsnRRS : DirectiveInsnRRS<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
AnyReg:$R2, imm32zx4:$M3,
(bdaddr12only $B4, $D4):$BD4),
".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
- def InsnRS : DirectiveInsnRS<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
+ def InsnRS : DirectiveInsnRSa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr12only $B2, $D2):$BD2),
".insn rs,$enc,$R1,$R3,$BD2", []>;
+ def InsnRSa : DirectiveInsnRSa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn rs_a,$enc,$R1,$BD2,$R3", []>;
+ def InsnRSb
+ : DirectiveInsnRSb<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
+ ".insn rs_b,$enc,$R1,$BD2,$M3", []>;
def InsnRSE : DirectiveInsnRSE<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
@@ -2321,13 +2419,41 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
(ins imm64zx48:$enc, AnyReg:$R1,
AnyReg:$R3, brtarget16:$RI2),
".insn rsi,$enc,$R1,$R3,$RI2", []>;
- def InsnRSY : DirectiveInsnRSY<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2),
- ".insn rsy,$enc,$R1,$R3,$BD2", []>;
- def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ def InsnRSLa : DirectiveInsnRSLa<(outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1,
+ $D1, $L1):$BDL1),
+ ".insn rsl_a,$enc,$BDL1", []>;
+ def InsnRSLb : DirectiveInsnRSLb<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2,
+ imm32zx4:$M3),
+ ".insn rsl_b,$enc,$R1,$BDL2,$M3", []>;
+ def InsnRSY : DirectiveInsnRSYa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr20only $B2, $D2):$BD2),
+ ".insn rsy,$enc,$R1,$R3,$BD2", []>;
+ def InsnRSYa
+ : DirectiveInsnRSYa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn rsy_a,$enc,$R1,$BD2,$R3", []>;
+ def InsnRSYb
+ : DirectiveInsnRSYb<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
+ ".insn rsy_b,$enc,$R1,$BD2,$M3", []>;
+ def InsnRX : DirectiveInsnRXa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rx,$enc,$R1,$XBD2", []>;
+ def InsnRXa : DirectiveInsnRXa<(outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx_a,$enc,$R1,$XBD2", []>;
+ def InsnRXb : DirectiveInsnRXb<(outs),
+ (ins imm64zx32:$enc, imm32zx4:$M1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx_b,$enc,$M1,$XBD2", []>;
def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rxe,$enc,$R1,$XBD2", []>;
@@ -2335,28 +2461,80 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
(ins imm64zx48:$enc, AnyReg:$R1,
AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rxf,$enc,$R1,$R3,$XBD2", []>;
- def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy,$enc,$R1,$XBD2", []>;
+ def InsnRXY : DirectiveInsnRXYa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy,$enc,$R1,$XBD2", []>;
+ def InsnRXYa : DirectiveInsnRXYa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_a,$enc,$R1,$XBD2", []>;
+ def InsnRXYb : DirectiveInsnRXYb<(outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_b,$enc,$M1,$XBD2", []>;
+ def InsnRXYc : DirectiveInsnRXYa<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_c,$enc,$R1,$XBD2", []>;
def InsnS : DirectiveInsnS<(outs),
(ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
".insn s,$enc,$BD2", []>;
def InsnSI : DirectiveInsnSI<(outs),
- (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1,
- imm32sx8:$I2),
+ (ins imm64zx32:$enc,
+ (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
".insn si,$enc,$BD1,$I2", []>;
- def InsnSIY : DirectiveInsnSIY<(outs),
- (ins imm64zx48:$enc,
- (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2),
- ".insn siy,$enc,$BD1,$I2", []>;
- def InsnSIL : DirectiveInsnSIL<(outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- imm32zx16:$I2),
- ".insn sil,$enc,$BD1,$I2", []>;
- def InsnSS : DirectiveInsnSS<(outs),
- (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
+ def InsnSIY
+ : DirectiveInsnSIY<(outs),
+ (ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1,
+ imm32xx8:$I2),
+ ".insn siy,$enc,$BD1,$I2", []>;
+ def InsnSIL
+ : DirectiveInsnSIL<(outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ imm32xx16:$I2),
+ ".insn sil,$enc,$BD1,$I2", []>;
+ def InsnSMI
+ : DirectiveInsnSMI<(outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1, brtarget16bpp:$RI2,
+ (bdaddr12only $B3, $D3):$BD3),
+ ".insn smi,$enc,$M1,$RI2,$BD3", []>;
+ def InsnSS : DirectiveInsnSSd<(outs),
+ (ins imm64zx48:$enc,
+ (bdraddr12only $B1, $D1, $R1):$RBD1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
+ ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
+ def InsnSSa : DirectiveInsnSSa<(outs),
+ (ins imm64zx48:$enc,
+ (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn ss_a,$enc,$BDL1,$BD2", []>;
+ def InsnSSb : DirectiveInsnSSb<(outs),
+ (ins imm64zx48:$enc,
+ (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
+ ".insn ss_b,$enc,$BDL1,$BDL2", []>;
+ def InsnSSc
+ : DirectiveInsnSSc<(outs),
+ (ins imm64zx48:$enc,
+ (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
+ ".insn ss_c,$enc,$BDL1,$BD2,$I3", []>;
+ def InsnSSd : DirectiveInsnSSd<(outs),
+ (ins imm64zx48:$enc,
+ (bdraddr12only $B1, $D1, $R1):$RBD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn ss_d,$enc,$RBD1,$BD2,$R3", []>;
+ def InsnSSe : DirectiveInsnSSe<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3,
+ (bdaddr12only $B4, $D4):$BD4),
+ ".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>;
+ def InsnSSf
+ : DirectiveInsnSSf<(outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
+ ".insn ss_f,$enc,$BD1,$BDL2", []>;
def InsnSSE : DirectiveInsnSSE<(outs),
(ins imm64zx48:$enc,
(bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2),
@@ -2365,19 +2543,140 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ssf,$enc,$BD1,$BD2,$R3", []>;
- def InsnVRI : DirectiveInsnVRI<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
- ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
- def InsnVRR : DirectiveInsnVRR<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
- imm32zx4:$M6),
- ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
- def InsnVRS : DirectiveInsnVRS<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
- ".insn vrs,$enc,$BD2,$M4", []>;
+ def InsnVRI
+ : DirectiveInsnVRIe<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
+ def InsnVRIa : DirectiveInsnVRIa<(outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ imm32xx16:$I2, imm32zx4:$M3),
+ ".insn vri_a,$enc,$V1,$I2,$M3", []>;
+ def InsnVRIb : DirectiveInsnVRIb<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx8:$I2,
+ imm32zx8:$I3, imm32zx4:$M4),
+ ".insn vri_b,$enc,$V1,$I2,$I3,$M4", []>;
+ def InsnVRIc : DirectiveInsnVRIc<(outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ imm32zx16:$I2, VR128:$V3, imm32zx4:$M4),
+ ".insn vri_c,$enc,$V1,$I2,$V3,$M4", []>;
+ def InsnVRId : DirectiveInsnVRId<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ VR128:$V3, imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_d,$enc,$V1,$V2,$V3,$I4,$M5", []>;
+ def InsnVRIe
+ : DirectiveInsnVRIe<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vri_e,$enc,$V1,$V2,$I3,$M4,$M5", []>;
+ def InsnVRIf : DirectiveInsnVRIf<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ VR128:$V3, imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_f,$enc,$V1,$V2,$V3,$I4,$M5", []>;
+ def InsnVRIg
+ : DirectiveInsnVRIg<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ imm32zx8:$I3, imm32zx16:$I4, imm32zx4:$M5),
+ ".insn vri_g,$enc,$V1,$V2,$I3,$I4,$M5", []>;
+ def InsnVRIh
+ : DirectiveInsnVRIh<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
+ imm32zx4:$I3, imm32zx4:$M4),
+ ".insn vri_h,$enc,$V1,$I2,$I3,$M4", []>;
+ def InsnVRIi : DirectiveInsnVRIi<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2,
+ imm32zx8:$I3, imm32zx4:$M4),
+ ".insn vri_i,$enc,$V1,$R2,$I3,$M4", []>;
+ def InsnVRIj : DirectiveInsnVRIj<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ imm32zx8:$I3, imm32zx4:$M4),
+ ".insn vri_j,$enc,$V1,$V2,$I3,$M4", []>;
+ def InsnVRIk : DirectiveInsnVRIk<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ VR128:$V3, VR128:$V4, imm32zx8:$I5),
+ ".insn vri_k,$enc,$V1,$V2,$V3,$V4,$I5", []>;
+ def InsnVRIl
+ : DirectiveInsnVRIl<
+ (outs), (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
+ ".insn vri_l,$enc,$V1,$V2,$I3", []>;
+ def InsnVRR
+ : DirectiveInsnVRRc<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
+ def InsnVRRa
+ : DirectiveInsnVRRa<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vrr_a,$enc,$V1,$V2,$M3,$M4,$M5", []>;
+ def InsnVRRb : DirectiveInsnVRRb<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vrr_b,$enc,$V1,$V2,$V3,$M4,$M5", []>;
+ def InsnVRRc
+ : DirectiveInsnVRRc<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_c,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
+ def InsnVRRd
+ : DirectiveInsnVRRd<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_d,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
+ def InsnVRRe
+ : DirectiveInsnVRRe<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_e,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
+ def InsnVRRf
+ : DirectiveInsnVRRf<
+ (outs), (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2, AnyReg:$R3),
+ ".insn vrr_f,$enc,$V1,$R2,$R3", []>;
+ def InsnVRRg
+ : DirectiveInsnVRRg<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
+ ".insn vrr_g,$enc,$V1,$I2", []>;
+ def InsnVRRh
+ : DirectiveInsnVRRh<
+ (outs), (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_h,$enc,$V1,$V2,$M3", []>;
+ def InsnVRRi : DirectiveInsnVRRi<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V2,
+ imm32zx4:$M3, imm32zx4:$M4),
+ ".insn vrr_i,$enc,$R1,$V2,$M3", []>;
+ def InsnVRRj : DirectiveInsnVRRj<(outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vrr_j,$enc,$V1,$V2,$V3,$M4", []>;
+ def InsnVRRk
+ : DirectiveInsnVRRk<
+ (outs), (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_k,$enc,$V1,$V2,$M3", []>;
+ def InsnVRS
+ : DirectiveInsnVRSc<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
+ ".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>;
+ def InsnVRSa : DirectiveInsnVRSa<(outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdaddr12only $B2, $D2):$BD2, VR128:$V3,
+ imm32zx4:$M4),
+ ".insn_a vrs_a,$enc,$V1,$BD2,$V3,$M4", []>;
+ def InsnVRSb : DirectiveInsnVRSb<(outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3,
+ imm32zx4:$M4),
+ ".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>;
+ def InsnVRSc : DirectiveInsnVRSc<(outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, VR128:$V3,
+ imm32zx4:$M4),
+ ".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>;
+ def InsnVRSd
+ : DirectiveInsnVRSd<(outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn vrs_d,$enc,$V1,$BD2,$R3", []>;
def InsnVRV : DirectiveInsnVRV<(outs),
(ins imm64zx48:$enc, VR128:$V1,
(bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td
index 8a2049c518473..f0ab67e421149 100644
--- a/llvm/lib/Target/SystemZ/SystemZOperands.td
+++ b/llvm/lib/Target/SystemZ/SystemZOperands.td
@@ -302,11 +302,14 @@ def U3Imm : ImmediateAsmOperand<"U3Imm">;
def U4Imm : ImmediateAsmOperand<"U4Imm">;
def S8Imm : ImmediateAsmOperand<"S8Imm">;
def U8Imm : ImmediateAsmOperand<"U8Imm">;
+def X8Imm : ImmediateAsmOperand<"X8Imm">;
def U12Imm : ImmediateAsmOperand<"U12Imm">;
def S16Imm : ImmediateAsmOperand<"S16Imm">;
def U16Imm : ImmediateAsmOperand<"U16Imm">;
+def X16Imm : ImmediateAsmOperand<"X16Imm">;
def S32Imm : ImmediateAsmOperand<"S32Imm">;
def U32Imm : ImmediateAsmOperand<"U32Imm">;
+def X32Imm : ImmediateAsmOperand<"X32Imm">;
def U48Imm : ImmediateAsmOperand<"U48Imm">;
//===----------------------------------------------------------------------===//
@@ -366,6 +369,11 @@ defm imm32zx8 : Immediate<i32, [{
return Imm.isIntN(8);
}], UIMM8, "U8Imm">;
+// Disable for codegen - only relevant for .insn directives.
+defm imm32xx8 : Immediate<i32, [{
+ return false;
+}], UIMM8, "X8Imm">;
+
defm imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
// Immediates for the 8-bit LSB chunk of an i32, with the other bits being one.
@@ -397,6 +405,11 @@ defm imm32zx16 : Immediate<i32, [{
return Imm.isIntN(16);
}], UIMM16, "U16Imm">;
+// Disable for codegen - only relevant for .insn directives.
+defm imm32xx16 : Immediate<i32, [{
+ return false;
+}], UIMM16, "X16Imm">;
+
defm imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
defm imm32zx16trunc : Immediate<i32, [{}], UIMM16, "U16Imm">;
@@ -543,6 +556,11 @@ defm imm64zx32 : Immediate<i64, [{
return Imm.isIntN(32);
}], UIMM32, "U32Imm">;
+// Disable for codegen - only relevant for .insn directives.
+defm imm64xx32 : Immediate<i64, [{
+ return false;
+}], UIMM32, "X32Imm">;
+
defm imm64zx32n : Immediate<i64, [{
return (-Imm).isIntN(32);
}], NEGUIMM32, "U32Imm">;
diff --git a/llvm/test/MC/SystemZ/directive-insn-z13.s b/llvm/test/MC/SystemZ/directive-insn-z13.s
new file mode 100644
index 0000000000000..19d5e6dd76e1f
--- /dev/null
+++ b/llvm/test/MC/SystemZ/directive-insn-z13.s
@@ -0,0 +1,59 @@
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z13 -filetype=obj %s | \
+# RUN: llvm-objdump --mcpu=z13 -d - | FileCheck %s
+
+# Test the .insn directive which provides a way of encoding an instruction
+# directly. It takes a format, encoding, and operands based on the format.
+# This file covers instruction formats newly supported.
+
+label.START:
+#CHECK: ec 12 af fe 00 42 lochih %r1, -20482
+ .insn rie_g,0xec0000000042,%r1,-20482,2
+
+#CHECK: ed 12 34 56 78 ae cdpt %f7, 1110(19,%r3), 8
+ .insn rsl_b,0xed00000000ae,%r7,1110(19,%r3),8
+
+#CHECK: eb 12 34 56 78 23 clth %r1, 492630(%r3)
+ .insn rsy_b,0xeb0000000023,%r1,492630(%r3),2
+
+#CHECK: c7 00 12 34 56 78 bpp 0, 0xad02, 564(%r1)
+ .insn smi,0xc70000000000,0,44272,564(%r1)
+
+#CHECK: e7 10 23 45 00 44 vgbm %v1, 9029
+ .insn vri_a,0xe70000000044,%v1,9029,0
+
+#CHECK: e7 10 ff fc 00 44 vgbm %v1, 65532
+ .insn vri_a,0xe70000000044,%v1,-4,0
+
+#CHECK: e7 10 23 45 60 46 vgm %v1, 35, 69, 6
+ .insn vri_b,0xe70000000046,%v1,35,69,6
+
+#CHECK: e7 12 34 56 70 4d vrep %v1, %v2, 13398, 7
+ .insn vri_c,0xe7000000004d,%v1,13398,%v2,7
+
+#CHECK: e7 12 30 45 60 72 verim %v1, %v2, %v3, 69, 6
+ .insn vri_d,0xe70000000072,%v1,%v2,%v3,69,6
+
+#CHECK: e7 12 34 56 70 4a vftci %v1, %v2, 837, 7, 6
+ .insn vri_e,0xe7000000004a,%v1,%v2,837,7,6
+
+#CHECK: e7 12 30 40 50 97 vpks %v1, %v2, %v3, 5, 4
+ .insn vrr_b,0xe70000000097,%v1,%v2,%v3,5,4
+
+#CHECK: e7 12 30 00 40 94 vpk %v1, %v2, %v3, 4
+ .insn vrr_c,0xe70000000094,%v1,%v2,%v3,4,0,0
+
+#CHECK: e7 12 34 00 50 bb vacq %v1, %v2, %v3, %v5
+ .insn vrr_d,0xe700000000bb,%v1,%v2,%v3,%v5,4,0
+
+#CHECK: e7 12 34 05 60 8f vfma %v1, %v2, %v3, %v6, 5, 4
+ .insn vrr_e,0xe7000000008f,%v1,%v2,%v3,%v6,5,4
+
+#CHECK: e7 12 34 56 78 36 vlm %v17, %v2, 1110(%r3), 7
+ .insn vrs_a,0xe70000000036,%v17,1110(%r3),%v2,7
+
+#CHECK: e7 12 34 56 78 22 vlvg %v17, %r2, 1110(%r3), 7
+ .insn vrs_b,0xe70000000022,%v17,1110(%r3),%r2,7
+
+#CHECK: e7 12 34 56 70 21 vlgv %r1, %v2, 1110(%r3), 7
+ .insn vrs_c,0xe70000000021,%r1,1110(%r3),%v2,7
+
diff --git a/llvm/test/MC/SystemZ/directive-insn-z14.s b/llvm/test/MC/SystemZ/directive-insn-z14.s
new file mode 100644
index 0000000000000..af0a549d78ecf
--- /dev/null
+++ b/llvm/test/MC/SystemZ/directive-insn-z14.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z14 -filetype=obj %s | \
+# RUN: llvm-objdump --mcpu=z14 -d - | FileCheck %s
+
+# Test the .insn directive which provides a way of encoding an instruction
+# directly. It takes a format, encoding, and operands based on the format.
+# This file covers instruction formats newly supported.
+
+label.START:
+#CHECK: e6 12 30 45 60 71 vap %v1, %v2, %v3, 86, 4
+ .insn vri_f,0xe60000000071,%v1,%v2,%v3,86,4
+
+
+#CHECK: e6 12 34 56 70 5b vpsop %v1, %v2, 103, 52, 5
+ .insn vri_g,0xe6000000005b,%v1,%v2,103,52,5
+
+#CHECK: e6 10 34 56 70 49 vlip %v1, 13398, 7
+ .insn vri_h,0xe60000000049,%v1,13398,7,0
+
+#CHECK: e6 12 00 34 50 58 vcvd %v1, %r2, 69, 3
+ .insn vri_i,0xe60000000058,%v1,%r2,69,3
+
+#CHECK: e6 12 00 30 00 50 vcvb %r1, %v2, 3
+ .insn vrr_i,0xe60000000050,%r1,%v2,3,0
+
+#CHECK: e6 01 23 45 60 37 vlrlr %v6, %r1, 837(%r2)
+ .insn vrs_d,0xe60000000037,%v6,837(%r2),%r1
+
+#CHECK: e6 0f 00 00 00 5f vtp %v15
+ .insn vrr_g,0xe6000000005f,%v15,0
+
+#CHECK: e6 01 20 30 00 77 vcp %v1, %v2, 3
+ .insn vrr_h,0xe60000000077,%v1,%v2,3
+
diff --git a/llvm/test/MC/SystemZ/directive-insn-z16.s b/llvm/test/MC/SystemZ/directive-insn-z16.s
new file mode 100644
index 0000000000000..4bf5be7e6ebe6
--- /dev/null
+++ b/llvm/test/MC/SystemZ/directive-insn-z16.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z16 -filetype=obj %s | \
+# RUN: llvm-objdump --mcpu=z16 -d - | FileCheck %s
+
+# Test the .insn directive which provides a way of encoding an instruction
+# directly. It takes a format, encoding, and operands based on the format.
+# This file covers instruction formats newly supported.
+
+label.START:
+#CHECK: e6 12 30 40 00 7d vcsph %v1, %v2, %v3, 4
+ .insn vrr_j,0xe6000000007d,%v1,%v2,%v3,4
+
+#CHECK: e6 12 00 30 00 51 vclzdp %v1, %v2, 3
+ .insn vrr_k,0xe60000000051,%v1,%v2,3
+
diff --git a/llvm/test/MC/SystemZ/directive-insn-z17.s b/llvm/test/MC/SystemZ/directive-insn-z17.s
new file mode 100644
index 0000000000000..fcee4161e1055
--- /dev/null
+++ b/llvm/test/MC/SystemZ/directive-insn-z17.s
@@ -0,0 +1,23 @@
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z17 -filetype=obj %s | \
+# RUN: llvm-objdump --mcpu=z17 -d - | FileCheck %s
+
+# Test the .insn directive which provides a way of encoding an instruction
+# directly. It takes a format, encoding, and operands based on the format.
+# This file covers instruction formats newly supported.
+
+label.START:
+#CHECK: e3 12 34 56 78 60 lxab %r1, 492630(%r2,%r3)
+ .insn rxy_c,0xe30000000060,%r1,492630(%r2,%r3)
+
+#CHECK: e6 12 00 34 50 4a vcvdq %v1, %v2, 69, 3
+ .insn vri_j,0xe6000000004a,%v1,%v2,69,3
+
+#CHECK: e7 12 30 45 60 88 veval %v1, %v2, %v3, %v6, 69
+ .insn vri_k,0xe70000000088,%v1,%v2,%v3,%v6,69
+
+#CHECK: e6 01 23 45 60 7f vtz %v1, %v2, 13398
+ .insn vri_l,0xe6000000007f,%v1,%v2,13398
+
+#CHECK: e7 12 00 00 30 54 vgemg %v1, %v2
+ .insn vrr_a,0xe70000000054,%v1,%v2,3,0,0
+
diff --git a/llvm/test/MC/SystemZ/directive-insn.s b/llvm/test/MC/SystemZ/directive-insn.s
index f25082705c52e..5827e13497f61 100644
--- a/llvm/test/MC/SystemZ/directive-insn.s
+++ b/llvm/test/MC/SystemZ/directive-insn.s
@@ -32,6 +32,9 @@ label.ril:
#CHECK: ec 1c f0 a0 34 fc cgible %r1, 52, 160(%r15)
.insn ris,0xec00000000fc,%r1,0x34,0xc,160(%r15)
+#CHECK: ec 1c f0 a0 ff fc cgible %r1, -1, 160(%r15)
+ .insn ris,0xec00000000fc,%r1,255,0xc,160(%r15)
+
# Test using an integer in place of a register.
#CHECK: 18 23 lr %r2, %r3
.insn rr,0x1800,2,3
@@ -54,9 +57,9 @@ label.ril:
.insn rs,0xba000000,%r0,%r1,160(%r15)
# GAS considers this instruction's immediate operand to be PC relative.
-#CHECK: 84 13 00 04 brxh %r1, %r3, 0x4a
+#CHECK: 84 13 00 04 brxh %r1, %r3, 0x50
.insn rsi,0x84000000,%r1,%r3,8
-#CHECK: 84 13 00 02 brxh %r1, %r3, 0x4a
+#CHECK: 84 13 00 02 brxh %r1, %r3, 0x50
.insn rsi,0x84000000,%r1,%r3,label.rsi
#CHECK: <label.rsi>:
label.rsi:
@@ -86,12 +89,21 @@ label.rsi:
#CHECK: 91 34 f0 a0 tm 160(%r15), 52
.insn si,0x91000000,160(%r15),52
+#CHECK: 91 ff f0 a0 tm 160(%r15), 255
+ .insn si,0x91000000,160(%r15),-1
+
#CHECK: eb f0 fc de ab 51 tmy -344866(%r15), 240
.insn siy,0xeb0000000051,-344866(%r15),240
+#CHECK: eb ff fc de ab 51 tmy -344866(%r15), 255
+ .insn siy,0xeb0000000051,-344866(%r15),-1
+
#CHECK: e5 60 f0 a0 12 34 tbegin 160(%r15), 4660
.insn sil,0xe56000000000,160(%r15),0x1234
+#CHECK: e5 60 f0 a0 ff ff tbegin 160(%r15), 65535
+ .insn sil,0xe56000000000,160(%r15),-1
+
#CHECK: d9 13 f1 23 e4 56 mvck 291(%r1,%r15), 1110(%r14), %r3
.insn ss,0xd90000000000,291(%r1,%r15),1110(%r14),%r3
@@ -100,3 +112,123 @@ label.rsi:
#CHECK: c8 31 f0 a0 e2 34 ectg 160(%r15), 564(%r14), %r3
.insn ssf,0xc80100000000,160(%r15),564(%r14),%r3
+
+#CHECK: 0a bc svc 188
+ .insn i,0x0a00,0xbc
+
+#CHECK: b2 fa 00 12 niai 1, 2
+ .insn ie,0xb2fa0000,0x1,0x2
+
+#CHECK: c5 f1 00 00 10 00 bprp 15, 0x2ae, 0x20ae
+ .insn mii,0xc50000000000,15,512,8192
+
+#CHECK: a7 1a af fe ahi %r1, -20482
+ .insn ri,0xa70a0000,%r1,-20482
+
+#CHECK: a7 12 ff ff tmhh %r1, 65535
+ .insn ri_a,0xa7020000,%r1,65535
+
+#CHECK: a7 15 ff fc bras %r1, 0xb4
+ .insn ri_b,0xa7050000,%r1,-8
+
+#CHECK: a7 34 ff fc jnle 0xb8
+ .insn ri_c,0xa7040000,3,-8
+
+#CHECK: ec 10 ff ff 70 72 cit %r1, -1, 7
+ .insn rie_a,0xec0000000072,%r1,65535,7
+
+#CHECK: ec 10 23 45 70 72 cit %r1, 9029, 7
+ .insn rie_a,0xec0000000072,%r1,0x2345,7
+
+#CHECK: ec 12 00 00 70 77 clrj %r1, %r2, 7, 0xd0
+ .insn rie_b,0xec0000000077,%r1,%r2,7,0
+
+#CHECK: ec 12 ff fc 34 7e cijh %r1, 52, 0xce
+ .insn rie_c,0xec000000007e,%r1,52,2,-8
+
+#CHECK: ec 12 ff fc ff 7e cijh %r1, -1, 0xd4
+ .insn rie_c,0xec000000007e,%r1,255,2,-8
+
+#CHECK: ec 12 af fe 00 d8 ahik %r1, %r2, -20482
+ .insn rie_d,0xec00000000d8,%r1,-20482,%r2
+
+#CHECK: ec 12 ff fc 00 44 brxhg %r1, %r2, 0xe0
+ .insn rie_e,0xec0000000044,%r1,-8,%r2
+
+#CHECK: ec 12 fa ca de 5d risbhg %r1, %r2, 250, 202, 222
+ .insn rie_f,0xec000000005d,%r1,%r2,250,202,222
+
+#CHECK: c2 15 00 fa ca de slfi %r1, 16435934
+ .insn ril_a,0xc20500000000,%r1,16435934
+
+#CHECK: c2 15 ff ff ff ff slfi %r1, 4294967295
+ .insn ril_a,0xc20500000000,%r1,4294967295
+
+#CHECK: c0 15 ff ff ff fc brasl %r1, 0xf8
+ .insn ril_b,0xc00500000000,%r1,-8
+
+#CHECK: c0 04 ff ff ff fc jgnop 0xfe
+ .insn ril_c,0xc00400000000,0,-8
+
+#CHECK: b3 3e 10 23 madr %f1, %f2, %f3
+ .insn rrd,0xb33e0000,%f1,%f3,%f2
+
+#CHECK: b3 d2 30 12 adtr %f1, %f2, %f3
+ .insn rrf,0xb3d20000,%f1,%f2,%f3,0
+
+#CHECK: b3 d2 31 12 adtra %f1, %f2, %f3, 1
+ .insn rrf_a,0xb3d20000,%f1,%f2,%f3,1
+
+#CHECK: b3 f6 20 13 iedtr %f1, %f2, %r3
+ .insn rrf_b,0xb3f60000,%f1,%r3,%f2,0
+
+#CHECK: b9 72 10 23 crt %r2, %r3, 1
+ .insn rrf_c,0xb9720000,%r2,%r3,1
+
+#CHECK: b3 e3 01 23 csdtr %r2, %f3, 1
+ .insn rrf_d,0xb3e30000,%r2,%f3,1
+
+#CHECK: b3 d7 12 34 fidtr %f3, 1, %f4, 2
+ .insn rrf_e,0xb3d70000,%r3,%f4,1,2
+
+#CHECK: 86 12 34 56 bxh %r1, %r2, 1110(%r3)
+ .insn rs_a,0x86000000,%r1,1110(%r3),%r2
+
+#CHECK: bd 12 34 56 clm %r1, 2, 1110(%r3)
+ .insn rs_b,0xbd000000,%r1,1110(%r3),2
+
+#CHECK: eb 10 23 45 00 c0 tp 837(2,%r2)
+ .insn rsl_a,0xeb00000000c0,837(2,%r2)
+
+#CHECK: eb 12 34 56 78 44 bxhg %r1, %r2, 492630(%r3)
+ .insn rsy_a,0xeb0000000044,%r1,492630(%r3),%r2
+
+#CHECK: 5a 12 34 56 a %r1, 1110(%r2,%r3)
+ .insn rx_a,0x5a000000,%r1,1110(%r2,%r3)
+
+#CHECK: 47 12 34 56 bo 1110(%r2,%r3)
+ .insn rx_b,0x47000000,1,1110(%r2,%r3)
+
+#CHECK: e3 12 34 56 78 16 llgf %r1, 492630(%r2,%r3)
+ .insn rxy_a,0xe30000000016,%r1,492630(%r2,%r3)
+
+#CHECK: e3 12 34 56 78 36 pfd 1, 492630(%r2,%r3)
+ .insn rxy_b,0xe30000000036,1,492630(%r2,%r3)
+
+#CHECK: d5 12 34 56 78 90 clc 1110(19,%r3), 2192(%r7)
+ .insn ss_a,0xd50000000000,1110(19,%r3),2192(%r7)
+
+#CHECK: f1 12 34 56 78 90 mvo 1110(2,%r3), 2192(3,%r7)
+ .insn ss_b,0xf10000000000,1110(2,%r3),2192(3,%r7)
+
+#CHECK: f0 12 34 56 78 90 srp 1110(2,%r3), 2192(%r7), 2
+ .insn ss_c,0xf00000000000,1110(2,%r3),2192(%r7),2
+
+#CHECK: da 12 34 56 78 90 mvcp 1110(%r1,%r3), 2192(%r7), %r2
+ .insn ss_d,0xda0000000000,1110(%r1,%r3),2192(%r7),%r2
+
+#CHECK: ef 12 34 56 78 90 lmd %r1, %r2, 1110(%r3), 2192(%r7)
+ .insn ss_e,0xef0000000000,%r1,1110(%r3),%r2,2192(%r7)
+
+#CHECK: e9 12 34 56 78 90 pka 1110(%r3), 2192(19,%r7)
+ .insn ss_f,0xe90000000000,1110(%r3),2192(19,%r7)
>From 269d3936971d5dd659eea3bc807ce795cb8ce658 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Mon, 19 Jan 2026 10:05:11 +0100
Subject: [PATCH 02/11] [SystemZ] Simplify insn directive maintenance
This commit changes how the .insn directives for SystemZ are implemented
in significant ways:
- Implement a marker class InsnDirectiveBase which sets the necessary bits
and can be used to easily identify Insn* defs in a TableGen backend.
- Autogenerate the match table in SystemZAsmParser.cpp via a new TableGen
backend from the Insn* defs in SystemZInstrInfo.td.
- Remove the class layer between the Inst* format classes and the Insn* defs
by moving the content of those classes into the Insn* def.
- Add tests covering all of the newly supported instruction formats for
.insn directives.
After this commit, the process for supporting a new instruction format
changes from:
1. Add format class
2. Add DirectiveInsn class
3. Add Insn def
4. Update sorted match table
to:
1. Add format class
2. Add Insn def
---
.../SystemZ/AsmParser/SystemZAsmParser.cpp | 337 +----
llvm/lib/Target/SystemZ/CMakeLists.txt | 1 +
.../lib/Target/SystemZ/SystemZInstrFormats.td | 661 +--------
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 1281 +++++++++++------
llvm/test/MC/SystemZ/directive-insn-bad.s | 97 ++
llvm/test/MC/SystemZ/directive-insn-z13.s | 5 +
llvm/test/MC/SystemZ/directive-insn.s | 7 +
llvm/utils/TableGen/CMakeLists.txt | 1 +
.../TableGen/SystemZInsnDirectiveEmitter.cpp | 135 ++
9 files changed, 1130 insertions(+), 1395 deletions(-)
create mode 100644 llvm/test/MC/SystemZ/directive-insn-bad.s
create mode 100644 llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 9484030c87aa1..f0d842ac93dc8 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -660,339 +660,16 @@ struct CompareInsn {
return LHS < RHS.Format;
}
bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
- return LHS.Format < RHS.Format;
+ if (LHS.Format != RHS.Format)
+ return LHS.Format < RHS.Format;
+ return LHS.Opcode < RHS.Opcode;
}
};
// Table initializing information for parsing the .insn directive.
static struct InsnMatchEntry InsnMatchTable[] = {
- /* Format, Opcode, NumOperands, OperandKinds */
- {"e", SystemZ::InsnE, 1, {MCK_U16Imm}},
- {"i", SystemZ::InsnI, 2, {MCK_U16Imm, MCK_U8Imm}},
- {"ie", SystemZ::InsnIE, 3, {MCK_U32Imm, MCK_U4Imm, MCK_U4Imm}},
- {"mii",
- SystemZ::InsnMII,
- 4,
- {MCK_U48Imm, MCK_U4Imm, MCK_PCRel12, MCK_PCRel24}},
- {"ri", SystemZ::InsnRIa, 3, {MCK_U32Imm, MCK_AnyReg, MCK_S16Imm}},
- {"ri_a", SystemZ::InsnRIa, 3, {MCK_U32Imm, MCK_AnyReg, MCK_X16Imm}},
- {"ri_b", SystemZ::InsnRIb, 3, {MCK_U32Imm, MCK_AnyReg, MCK_PCRel16}},
- {"ri_c", SystemZ::InsnRIc, 3, {MCK_U32Imm, MCK_U4Imm, MCK_PCRel16}},
- {"rie",
- SystemZ::InsnRIE,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16}},
- {"rie_a",
- SystemZ::InsnRIEa,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_X16Imm, MCK_U4Imm}},
- {"rie_b",
- SystemZ::InsnRIEb,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_PCRel16}},
- {"rie_c",
- SystemZ::InsnRIEc,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_X8Imm, MCK_U4Imm, MCK_PCRel16}},
- {"rie_d",
- SystemZ::InsnRIEd,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_S16Imm, MCK_AnyReg}},
- {"rie_e",
- SystemZ::InsnRIEe,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_PCRel16, MCK_AnyReg}},
- {"rie_f",
- SystemZ::InsnRIEf,
- 6,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U8Imm, MCK_U8Imm, MCK_U8Imm}},
- {"rie_g",
- SystemZ::InsnRIEg,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_S16Imm, MCK_U4Imm}},
- {"ril", SystemZ::InsnRIL, 3, {MCK_U48Imm, MCK_AnyReg, MCK_PCRel32}},
- {"ril_a", SystemZ::InsnRILa, 3, {MCK_U48Imm, MCK_AnyReg, MCK_X32Imm}},
- {"ril_b", SystemZ::InsnRILb, 3, {MCK_U48Imm, MCK_AnyReg, MCK_PCRel32}},
- {"ril_c", SystemZ::InsnRILc, 3, {MCK_U48Imm, MCK_U4Imm, MCK_PCRel32}},
- {"rilu", SystemZ::InsnRILU, 3, {MCK_U48Imm, MCK_AnyReg, MCK_U32Imm}},
- {"ris",
- SystemZ::InsnRIS,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_X8Imm, MCK_U4Imm, MCK_BDAddr64Disp12}},
- {"rr", SystemZ::InsnRR, 3, {MCK_U16Imm, MCK_AnyReg, MCK_AnyReg}},
- {"rrd",
- SystemZ::InsnRRD,
- 4,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg}},
- {"rre", SystemZ::InsnRRE, 3, {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg}},
-
- {"rrf",
- SystemZ::InsnRRF,
- 5,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
- {"rrf_a",
- SystemZ::InsnRRFa,
- 5,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
- {"rrf_b",
- SystemZ::InsnRRFb,
- 5,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
- {"rrf_c",
- SystemZ::InsnRRFc,
- 4,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
- {"rrf_d",
- SystemZ::InsnRRFd,
- 4,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm}},
- {"rrf_e",
- SystemZ::InsnRRFe,
- 5,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_U4Imm}},
- {"rrs",
- SystemZ::InsnRRS,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12}},
- {"rs",
- SystemZ::InsnRS,
- 4,
- {MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12}},
- {"rs_a",
- SystemZ::InsnRSa,
- 4,
- {MCK_U32Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_AnyReg}},
- {"rs_b",
- SystemZ::InsnRSb,
- 4,
- {MCK_U32Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U4Imm}},
- {"rse",
- SystemZ::InsnRSE,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12}},
- {"rsi",
- SystemZ::InsnRSI,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16}},
- {"rsl_a", SystemZ::InsnRSLa, 2, {MCK_U48Imm, MCK_BDLAddr64Disp12Len4}},
- {"rsl_b",
- SystemZ::InsnRSLb,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_BDLAddr64Disp12Len8, MCK_U4Imm}},
- {"rsy",
- SystemZ::InsnRSY,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20}},
- {"rsy_a",
- SystemZ::InsnRSYa,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp20, MCK_AnyReg}},
- {"rsy_b",
- SystemZ::InsnRSYb,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp20, MCK_U4Imm}},
- {"rx", SystemZ::InsnRX, 3, {MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
- {"rx_a",
- SystemZ::InsnRXa,
- 3,
- {MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
- {"rx_b", SystemZ::InsnRXb, 3, {MCK_U32Imm, MCK_U4Imm, MCK_BDXAddr64Disp12}},
- {"rxe", SystemZ::InsnRXE, 3, {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12}},
- {"rxf",
- SystemZ::InsnRXF,
- 4,
- {MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12}},
- {"rxy", SystemZ::InsnRXY, 3, {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
- {"rxy_a",
- SystemZ::InsnRXYa,
- 3,
- {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
- {"rxy_b",
- SystemZ::InsnRXYb,
- 3,
- {MCK_U48Imm, MCK_U4Imm, MCK_BDXAddr64Disp20}},
- {"rxy_c",
- SystemZ::InsnRXYc,
- 3,
- {MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20}},
- {"s", SystemZ::InsnS, 2, {MCK_U32Imm, MCK_BDAddr64Disp12}},
- {"si", SystemZ::InsnSI, 3, {MCK_U32Imm, MCK_BDAddr64Disp12, MCK_X8Imm}},
- {"sil", SystemZ::InsnSIL, 3, {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_X16Imm}},
- {"siy", SystemZ::InsnSIY, 3, {MCK_U48Imm, MCK_BDAddr64Disp20, MCK_X8Imm}},
- {"smi",
- SystemZ::InsnSMI,
- 4,
- {MCK_U48Imm, MCK_U4Imm, MCK_PCRel16, MCK_BDAddr64Disp12}},
- {"ss",
- SystemZ::InsnSS,
- 4,
- {MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
- {"ss_a",
- SystemZ::InsnSSa,
- 3,
- {MCK_U48Imm, MCK_BDLAddr64Disp12Len8, MCK_BDAddr64Disp12}},
- {"ss_b",
- SystemZ::InsnSSb,
- 3,
- {MCK_U48Imm, MCK_BDLAddr64Disp12Len4, MCK_BDLAddr64Disp12Len4}},
- {"ss_c",
- SystemZ::InsnSSc,
- 4,
- {MCK_U48Imm, MCK_BDLAddr64Disp12Len4, MCK_BDAddr64Disp12, MCK_U4Imm}},
- {"ss_d",
- SystemZ::InsnSSd,
- 4,
- {MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
- {"ss_e",
- SystemZ::InsnSSe,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_AnyReg,
- MCK_BDAddr64Disp12}},
- {"ss_f",
- SystemZ::InsnSSf,
- 3,
- {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDLAddr64Disp12Len8}},
- {"sse",
- SystemZ::InsnSSE,
- 3,
- {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12}},
- {"ssf",
- SystemZ::InsnSSF,
- 4,
- {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg}},
- {"vri",
- SystemZ::InsnVRIe,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm}},
- {"vri_a",
- SystemZ::InsnVRIa,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_X16Imm, MCK_U4Imm}},
- {"vri_b",
- SystemZ::InsnVRIb,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_U8Imm, MCK_U8Imm, MCK_U4Imm}},
- {"vri_c",
- SystemZ::InsnVRIc,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_U16Imm, MCK_VR128, MCK_U4Imm}},
- {"vri_d",
- SystemZ::InsnVRId,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
- {"vri_e",
- SystemZ::InsnVRIe,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U16Imm, MCK_U4Imm, MCK_U4Imm}},
- {"vri_f",
- SystemZ::InsnVRIf,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
- {"vri_g",
- SystemZ::InsnVRIg,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U8Imm, MCK_U4Imm}},
- {"vri_h",
- SystemZ::InsnVRIh,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_U16Imm, MCK_U4Imm, MCK_U4Imm}},
- {"vri_i",
- SystemZ::InsnVRIi,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_AnyReg, MCK_U8Imm, MCK_U4Imm}},
- {"vri_j",
- SystemZ::InsnVRIj,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U8Imm, MCK_U4Imm}},
- {"vri_k",
- SystemZ::InsnVRIk,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U8Imm}},
- {"vri_l",
- SystemZ::InsnVRIl,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U16Imm}},
- {"vrr",
- SystemZ::InsnVRR,
- 7,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
- MCK_U4Imm}},
- {"vrr_a",
- SystemZ::InsnVRRa,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm, MCK_U4Imm}},
- {"vrr_b",
- SystemZ::InsnVRRb,
- 6,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm}},
- {"vrr_c",
- SystemZ::InsnVRRc,
- 7,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
- MCK_U4Imm}},
- {"vrr_d",
- SystemZ::InsnVRRd,
- 7,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm,
- MCK_U4Imm}},
- {"vrr_e",
- SystemZ::InsnVRRe,
- 7,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm,
- MCK_U4Imm}},
- {"vrr_f",
- SystemZ::InsnVRRf,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_AnyReg, MCK_AnyReg}},
- {"vrr_g", SystemZ::InsnVRRg, 3, {MCK_U48Imm, MCK_VR128, MCK_U16Imm}},
- {"vrr_h",
- SystemZ::InsnVRRh,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm}},
- {"vrr_i",
- SystemZ::InsnVRRi,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_U4Imm, MCK_U4Imm}},
- {"vrr_j",
- SystemZ::InsnVRRj,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm}},
- {"vrr_k",
- SystemZ::InsnVRRk,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U4Imm}},
- {"vrs",
- SystemZ::InsnVRS,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm}},
- {"vrs_a",
- SystemZ::InsnVRSa,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_VR128, MCK_U4Imm}},
- {"vrs_b",
- SystemZ::InsnVRSb,
- 5,
- {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_AnyReg, MCK_U4Imm}},
- {"vrs_c",
- SystemZ::InsnVRSc,
- 5,
- {MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_VR128, MCK_U4Imm}},
- {"vrs_d",
- SystemZ::InsnVRSd,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_AnyReg}},
- {"vrv",
- SystemZ::InsnVRV,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm}},
- {"vrx",
- SystemZ::InsnVRX,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm}},
- {"vsi",
- SystemZ::InsnVSI,
- 4,
- {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm}}};
+#include "SystemZGenInsnMatchTable.inc"
+};
void SystemZOperand::print(raw_ostream &OS, const MCAsmInfo &MAI) const {
switch (Kind) {
@@ -1566,6 +1243,8 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ResTy = parseVR128(Operands);
else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
ResTy = parseBDXAddr64(Operands);
+ else if (Kind == MCK_BDRAddr64Disp12)
+ ResTy = parseBDRAddr64(Operands);
else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
ResTy = parseBDAddr64(Operands);
else if (Kind == MCK_BDVAddr64Disp12)
@@ -1621,6 +1300,8 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
ZOperand.addBDAddrOperands(Inst, 2);
else if (ZOperand.isMem(BDXMem))
ZOperand.addBDXAddrOperands(Inst, 3);
+ else if (ZOperand.isMem(BDRMem))
+ ZOperand.addBDRAddrOperands(Inst, 3);
else if (ZOperand.isMem(BDVMem))
ZOperand.addBDVAddrOperands(Inst, 3);
else if (ZOperand.isMem(BDLMem))
diff --git a/llvm/lib/Target/SystemZ/CMakeLists.txt b/llvm/lib/Target/SystemZ/CMakeLists.txt
index 51021b30fd073..c990acff16d58 100644
--- a/llvm/lib/Target/SystemZ/CMakeLists.txt
+++ b/llvm/lib/Target/SystemZ/CMakeLists.txt
@@ -8,6 +8,7 @@ tablegen(LLVM SystemZGenHLASMAsmWriter.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv)
tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler)
+tablegen(LLVM SystemZGenInsnMatchTable.inc -gen-insn-directive-match-table)
tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 00452377bbf5f..10d09ecd637f8 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -1758,662 +1758,17 @@ class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
}
//===----------------------------------------------------------------------===//
-// Instruction classes for .insn directives
+// Base class for all .insn directive instructions
//===----------------------------------------------------------------------===//
-
-class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstE<0, outs, ins, asmstr, pattern> {
- bits<16> enc;
-
- let Inst = enc;
-}
-
-class DirectiveInsnI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstI<0, outs, ins, asmstr, pattern> {
- bits<16> enc;
-
- let Inst{15 -8} = enc{15 -8};
-}
-
-class DirectiveInsnIE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstIE<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -16} = enc{31 -16};
-}
-
-class DirectiveInsnMII<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstMII<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
-}
-
-class DirectiveInsnRIa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
- let Inst{19-16} = enc{19-16};
-}
-
-class DirectiveInsnRIb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIb<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -24} = enc{31 -24};
- let Inst{19 -16} = enc{19 -16};
-}
-
-class DirectiveInsnRIc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIc<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -24} = enc{31 -24};
- let Inst{19 -16} = enc{19 -16};
-}
-
-class DirectiveInsnRIEa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRIEb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRIEc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRIEd<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEd<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRIEe<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEe<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRIEf<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEf<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRIEg<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIEg<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRILa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRILa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
- // string type;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{35 -32} = enc{35 -32};
-}
-
-class DirectiveInsnRILb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRILb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
- // string type;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{35 -32} = enc{35 -32};
-}
-
-class DirectiveInsnRILc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRILc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
- // string type;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
-
-class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRIS<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRR<0, outs, ins, asmstr, pattern> {
- bits<16> enc;
-
- let Inst{15-8} = enc{15-8};
-}
-
-class DirectiveInsnRRD<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRD<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -16} = enc{31 -16};
-}
-
-class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRE<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
-
-class DirectiveInsnRRFa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRFa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
-
-// RRF-b is identical to RRF-a, and is thus omitted
-
-class DirectiveInsnRRFc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRFc<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -16} = enc{31 -16};
-}
-
-class DirectiveInsnRRFd<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRFd<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -16} = enc{31 -16};
-}
-
-class DirectiveInsnRRFe<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRFe<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -16} = enc{31 -16};
-}
-
-class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRS<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRSa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRSb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSb<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -24} = enc{31 -24};
-}
-
-class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSEa<6, outs, ins, asmstr, pattern> {
- bits <48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSI<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRSLa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSLa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRSLb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSLb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRSYa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSYa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRSYb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRSYb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRXa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXa<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRXb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXb<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31 -24} = enc{31 -24};
-}
-
-class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXE<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let M3 = 0;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXF<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnRXYa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXYa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRXYb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXYb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnRXYc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRXYa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstS<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
+// This marker class is used to identify .insn directive instructions
+// for the SystemZInsnDirectiveEmitter. It must be the rightmost parent
+// in the inheritance list to ensure these properties take precedence over
+// the ones set by the InstFoo base classes.
+class InsnDirectiveBase {
+ bit isCodeGenOnly = 1;
+ bit hasSideEffects = 1;
}
-class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSI<0, outs, ins, asmstr, pattern> {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSIY<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSIL<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-32} = enc{47-32};
-}
-
-class DirectiveInsnSMI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSMI<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
-}
-
-class DirectiveInsnSSa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
-}
-
-class DirectiveInsnSSb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
-}
-
-class DirectiveInsnSSc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
-}
-
-class DirectiveInsnSSd<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSd<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
-}
-
-class DirectiveInsnSSe<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSe<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
-}
-
-class DirectiveInsnSSf<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSf<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
-}
-
-class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSE<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-32} = enc{47-32};
-}
-
-class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstSSF<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
-
-class DirectiveInsnVRIa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRId<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRId<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIe<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIe<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRIf<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIf<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIg<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIg<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIh<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIh<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIi<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIi<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIj<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIj<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIk<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIk<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRIl<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRIl<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRRd<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRd<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRe<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRe<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRf<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRf<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRg<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRg<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRh<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRh<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRi<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRi<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRj<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRj<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRRk<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRRk<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRSa<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRSa<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRSb<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRSb<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRSc<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRSc<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRSd<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRSd<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47 -40} = enc{47 -40};
- let Inst{7 -0} = enc{7 -0};
-}
-
-class DirectiveInsnVRV<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRV<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVRX<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVRX<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-class DirectiveInsnVSI<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstVSI<0, outs, ins, asmstr, pattern> {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
-
-
//===----------------------------------------------------------------------===//
// Variants of instructions with condition mask
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 73708d3a4e0b3..459d574b6cfdd 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2275,420 +2275,873 @@ let hasSideEffects = 1 in {
// .insn directive instructions
//===----------------------------------------------------------------------===//
-let isCodeGenOnly = 1, hasSideEffects = 1 in {
- def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
- def InsnI : DirectiveInsnI<(outs), (ins imm64zx16:$enc, imm32zx8:$I1),
- ".insn i,$enc,$I1", []>;
- def InsnIE : DirectiveInsnIE<(outs),
- (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
- ".insn ie,$enc,$I1,$I2", []>;
- def InsnMII : DirectiveInsnMII<(outs),
- (ins imm64zx48:$enc, imm32zx4:$M1,
- brtarget12bpp:$RI2, brtarget24bpp:$RI3),
- ".insn mii,$enc,$M1,$RI2,$RI3", []>;
- def InsnRI : DirectiveInsnRIa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
- ".insn ri,$enc,$R1,$I2", []>;
- def InsnRIa
- : DirectiveInsnRIa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
- ".insn ri_a,$enc,$R1,$I2", []>;
- def InsnRIb
- : DirectiveInsnRIb<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
- ".insn ri_b,$enc,$R1,$RI2", []>;
- def InsnRIc
- : DirectiveInsnRIc<(outs),
- (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
- ".insn ri_c,$enc,$M1,$RI2", []>;
- def InsnRIE : DirectiveInsnRIEd<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- brtarget16:$I2),
- ".insn rie,$enc,$R1,$R3,$I2", []>;
- def InsnRIEa : DirectiveInsnRIEa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- imm32xx16:$I2, imm32zx4:$M3),
- ".insn rie_a,$enc,$R1,$I2,$M3", []>;
- def InsnRIEb : DirectiveInsnRIEb<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx4:$M3, brtarget16:$RI4),
- ".insn rie_b,$enc,$R1,$R2,$M3,$RI4", []>;
- def InsnRIEc
- : DirectiveInsnRIEc<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
- imm32zx4:$M3, brtarget16:$RI4),
- ".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>;
- def InsnRIEd
- : DirectiveInsnRIEd<
- (outs), (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
- ".insn rie_d,$enc,$R1,$I2,$R3", []>;
- def InsnRIEe : DirectiveInsnRIEe<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- brtarget16:$RI2, AnyReg:$R3),
- ".insn rie_e,$enc,$R1,$RI2,$R3", []>;
- def InsnRIEf
- : DirectiveInsnRIEf<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
- ".insn rie_f,$enc,$R1,$R2,$I3,$I4,$I5", []>;
- def InsnRIEg : DirectiveInsnRIEg<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- imm32sx16:$I2, imm32zx4:$M3),
- ".insn rie_g,$enc,$R1,$I2,$M3", []>;
- def InsnRIL
- : DirectiveInsnRILa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
- ".insn ril,$enc,$R1,$I2", []>;
- def InsnRILa
- : DirectiveInsnRILa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
- ".insn ril_a,$enc,$R1,$I2", []>;
- def InsnRILb
- : DirectiveInsnRILb<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
- ".insn ril_b,$enc,$R1,$RI2", []>;
- def InsnRILc
- : DirectiveInsnRILc<(outs),
- (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
- ".insn ril_c,$enc,$M1,$RI2", []>;
- def InsnRILU
- : DirectiveInsnRILa<(outs), (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
- ".insn rilu,$enc,$R1,$I2", []>;
- def InsnRIS
- : DirectiveInsnRIS<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
- imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
- ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
- def InsnRR : DirectiveInsnRR<(outs),
- (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
- ".insn rr,$enc,$R1,$R2", []>;
- def InsnRRD
- : DirectiveInsnRRD<
- (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3),
- ".insn rrd,$enc,$R1,$R2,%R3", []>;
- def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc,
- AnyReg:$R1, AnyReg:$R2),
- ".insn rre,$enc,$R1,$R2", []>;
- def InsnRRF : DirectiveInsnRRFa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- AnyReg:$R3, imm32zx4:$M4),
- ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
- def InsnRRFa : DirectiveInsnRRFa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- AnyReg:$R3, imm32zx4:$M4),
- ".insn rrf_a,$enc,$R1,$R2,$R3,$M4", []>;
- def InsnRRFb : DirectiveInsnRRFa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- AnyReg:$R3, imm32zx4:$M4),
- ".insn rrf_b,$enc,$R1,$R2,$R3,$M4", []>;
- def InsnRRFc
- : DirectiveInsnRRFc<
- (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
- ".insn rrf_c,$enc,$R1,$R2,$M3", []>;
- def InsnRRFd
- : DirectiveInsnRRFd<
- (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
- ".insn rrf_d,$enc,$R1,$R2,$M4", []>;
- def InsnRRFe : DirectiveInsnRRFe<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx4:$M3, imm32zx4:$M4),
- ".insn rrf_e,$enc,$R1,$R2,$M3,$M4", []>;
- def InsnRRS : DirectiveInsnRRS<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R2, imm32zx4:$M3,
- (bdaddr12only $B4, $D4):$BD4),
- ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
- def InsnRS : DirectiveInsnRSa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn rs,$enc,$R1,$R3,$BD2", []>;
- def InsnRSa : DirectiveInsnRSa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn rs_a,$enc,$R1,$BD2,$R3", []>;
- def InsnRSb
- : DirectiveInsnRSb<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
- ".insn rs_b,$enc,$R1,$BD2,$M3", []>;
- def InsnRSE : DirectiveInsnRSE<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
- ".insn rse,$enc,$R1,$R3,$BD2", []>;
- def InsnRSI : DirectiveInsnRSI<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, brtarget16:$RI2),
- ".insn rsi,$enc,$R1,$R3,$RI2", []>;
- def InsnRSLa : DirectiveInsnRSLa<(outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1,
- $D1, $L1):$BDL1),
- ".insn rsl_a,$enc,$BDL1", []>;
- def InsnRSLb : DirectiveInsnRSLb<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2,
- imm32zx4:$M3),
- ".insn rsl_b,$enc,$R1,$BDL2,$M3", []>;
- def InsnRSY : DirectiveInsnRSYa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr20only $B2, $D2):$BD2),
- ".insn rsy,$enc,$R1,$R3,$BD2", []>;
- def InsnRSYa
- : DirectiveInsnRSYa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn rsy_a,$enc,$R1,$BD2,$R3", []>;
- def InsnRSYb
- : DirectiveInsnRSYb<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
- ".insn rsy_b,$enc,$R1,$BD2,$M3", []>;
- def InsnRX : DirectiveInsnRXa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx,$enc,$R1,$XBD2", []>;
- def InsnRXa : DirectiveInsnRXa<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx_a,$enc,$R1,$XBD2", []>;
- def InsnRXb : DirectiveInsnRXb<(outs),
- (ins imm64zx32:$enc, imm32zx4:$M1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx_b,$enc,$M1,$XBD2", []>;
- def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxe,$enc,$R1,$XBD2", []>;
- def InsnRXF : DirectiveInsnRXF<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
- def InsnRXY : DirectiveInsnRXYa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy,$enc,$R1,$XBD2", []>;
- def InsnRXYa : DirectiveInsnRXYa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy_a,$enc,$R1,$XBD2", []>;
- def InsnRXYb : DirectiveInsnRXYb<(outs),
- (ins imm64zx48:$enc, imm32zx4:$M1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy_b,$enc,$M1,$XBD2", []>;
- def InsnRXYc : DirectiveInsnRXYa<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy_c,$enc,$R1,$XBD2", []>;
- def InsnS : DirectiveInsnS<(outs),
- (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
- ".insn s,$enc,$BD2", []>;
- def InsnSI : DirectiveInsnSI<(outs),
- (ins imm64zx32:$enc,
- (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
- ".insn si,$enc,$BD1,$I2", []>;
- def InsnSIY
- : DirectiveInsnSIY<(outs),
- (ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1,
- imm32xx8:$I2),
- ".insn siy,$enc,$BD1,$I2", []>;
- def InsnSIL
- : DirectiveInsnSIL<(outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- imm32xx16:$I2),
- ".insn sil,$enc,$BD1,$I2", []>;
- def InsnSMI
- : DirectiveInsnSMI<(outs),
- (ins imm64zx48:$enc, imm32zx4:$M1, brtarget16bpp:$RI2,
- (bdaddr12only $B3, $D3):$BD3),
- ".insn smi,$enc,$M1,$RI2,$BD3", []>;
- def InsnSS : DirectiveInsnSSd<(outs),
- (ins imm64zx48:$enc,
- (bdraddr12only $B1, $D1, $R1):$RBD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
- def InsnSSa : DirectiveInsnSSa<(outs),
- (ins imm64zx48:$enc,
- (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn ss_a,$enc,$BDL1,$BD2", []>;
- def InsnSSb : DirectiveInsnSSb<(outs),
- (ins imm64zx48:$enc,
- (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
- (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
- ".insn ss_b,$enc,$BDL1,$BDL2", []>;
- def InsnSSc
- : DirectiveInsnSSc<(outs),
- (ins imm64zx48:$enc,
- (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
- ".insn ss_c,$enc,$BDL1,$BD2,$I3", []>;
- def InsnSSd : DirectiveInsnSSd<(outs),
- (ins imm64zx48:$enc,
- (bdraddr12only $B1, $D1, $R1):$RBD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ss_d,$enc,$RBD1,$BD2,$R3", []>;
- def InsnSSe : DirectiveInsnSSe<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3,
- (bdaddr12only $B4, $D4):$BD4),
- ".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>;
- def InsnSSf
- : DirectiveInsnSSf<(outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
- ".insn ss_f,$enc,$BD1,$BDL2", []>;
- def InsnSSE : DirectiveInsnSSE<(outs),
- (ins imm64zx48:$enc,
- (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2),
- ".insn sse,$enc,$BD1,$BD2", []>;
- def InsnSSF : DirectiveInsnSSF<(outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ssf,$enc,$BD1,$BD2,$R3", []>;
- def InsnVRI
- : DirectiveInsnVRIe<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
- ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
- def InsnVRIa : DirectiveInsnVRIa<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- imm32xx16:$I2, imm32zx4:$M3),
- ".insn vri_a,$enc,$V1,$I2,$M3", []>;
- def InsnVRIb : DirectiveInsnVRIb<(outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32zx8:$I2,
- imm32zx8:$I3, imm32zx4:$M4),
- ".insn vri_b,$enc,$V1,$I2,$I3,$M4", []>;
- def InsnVRIc : DirectiveInsnVRIc<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- imm32zx16:$I2, VR128:$V3, imm32zx4:$M4),
- ".insn vri_c,$enc,$V1,$I2,$V3,$M4", []>;
- def InsnVRId : DirectiveInsnVRId<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- VR128:$V3, imm32zx8:$I4, imm32zx4:$M5),
- ".insn vri_d,$enc,$V1,$V2,$V3,$I4,$M5", []>;
- def InsnVRIe
- : DirectiveInsnVRIe<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
- ".insn vri_e,$enc,$V1,$V2,$I3,$M4,$M5", []>;
- def InsnVRIf : DirectiveInsnVRIf<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- VR128:$V3, imm32zx8:$I4, imm32zx4:$M5),
- ".insn vri_f,$enc,$V1,$V2,$V3,$I4,$M5", []>;
- def InsnVRIg
- : DirectiveInsnVRIg<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx8:$I3, imm32zx16:$I4, imm32zx4:$M5),
- ".insn vri_g,$enc,$V1,$V2,$I3,$I4,$M5", []>;
- def InsnVRIh
- : DirectiveInsnVRIh<(outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
- imm32zx4:$I3, imm32zx4:$M4),
- ".insn vri_h,$enc,$V1,$I2,$I3,$M4", []>;
- def InsnVRIi : DirectiveInsnVRIi<(outs),
- (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2,
- imm32zx8:$I3, imm32zx4:$M4),
- ".insn vri_i,$enc,$V1,$R2,$I3,$M4", []>;
- def InsnVRIj : DirectiveInsnVRIj<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx8:$I3, imm32zx4:$M4),
- ".insn vri_j,$enc,$V1,$V2,$I3,$M4", []>;
- def InsnVRIk : DirectiveInsnVRIk<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- VR128:$V3, VR128:$V4, imm32zx8:$I5),
- ".insn vri_k,$enc,$V1,$V2,$V3,$V4,$I5", []>;
- def InsnVRIl
- : DirectiveInsnVRIl<
- (outs), (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
- ".insn vri_l,$enc,$V1,$V2,$I3", []>;
- def InsnVRR
- : DirectiveInsnVRRc<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
- def InsnVRRa
- : DirectiveInsnVRRa<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
- ".insn vrr_a,$enc,$V1,$V2,$M3,$M4,$M5", []>;
- def InsnVRRb : DirectiveInsnVRRb<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
- ".insn vrr_b,$enc,$V1,$V2,$V3,$M4,$M5", []>;
- def InsnVRRc
- : DirectiveInsnVRRc<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr_c,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
- def InsnVRRd
- : DirectiveInsnVRRd<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr_d,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
- def InsnVRRe
- : DirectiveInsnVRRe<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr_e,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
- def InsnVRRf
- : DirectiveInsnVRRf<
- (outs), (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2, AnyReg:$R3),
- ".insn vrr_f,$enc,$V1,$R2,$R3", []>;
- def InsnVRRg
- : DirectiveInsnVRRg<(outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
- ".insn vrr_g,$enc,$V1,$I2", []>;
- def InsnVRRh
- : DirectiveInsnVRRh<
- (outs), (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
- ".insn vrr_h,$enc,$V1,$V2,$M3", []>;
- def InsnVRRi : DirectiveInsnVRRi<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V2,
- imm32zx4:$M3, imm32zx4:$M4),
- ".insn vrr_i,$enc,$R1,$V2,$M3", []>;
- def InsnVRRj : DirectiveInsnVRRj<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- VR128:$V3, imm32zx4:$M4),
- ".insn vrr_j,$enc,$V1,$V2,$V3,$M4", []>;
- def InsnVRRk
- : DirectiveInsnVRRk<
- (outs), (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
- ".insn vrr_k,$enc,$V1,$V2,$M3", []>;
- def InsnVRS
- : DirectiveInsnVRSc<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
- ".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>;
- def InsnVRSa : DirectiveInsnVRSa<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, VR128:$V3,
- imm32zx4:$M4),
- ".insn_a vrs_a,$enc,$V1,$BD2,$V3,$M4", []>;
- def InsnVRSb : DirectiveInsnVRSb<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3,
- imm32zx4:$M4),
- ".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>;
- def InsnVRSc : DirectiveInsnVRSc<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, VR128:$V3,
- imm32zx4:$M4),
- ".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>;
- def InsnVRSd
- : DirectiveInsnVRSd<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn vrs_d,$enc,$V1,$BD2,$R3", []>;
- def InsnVRV : DirectiveInsnVRV<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
- ".insn vrv,$enc,$V1,$VBD2,$M3", []>;
- def InsnVRX : DirectiveInsnVRX<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
- ".insn vrx,$enc,$V1,$XBD2,$M3", []>;
- def InsnVSI : DirectiveInsnVSI<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
- ".insn vsi,$enc,$V1,$BD2,$I3", []>;
+def InsnE : InstE<0, (outs), (ins imm64zx16:$enc), ".insn e,$enc", []>,
+ InsnDirectiveBase {
+ bits<16> enc;
+ let Inst = enc;
+}
+def InsnI : InstI<0, (outs), (ins imm64zx16:$enc, imm32zx8:$I1),
+ ".insn i,$enc,$I1", []>,
+ InsnDirectiveBase {
+ bits<16> enc;
+ let Inst{15-8} = enc{15-8};
+}
+def InsnIE : InstIE<0, (outs), (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
+ ".insn ie,$enc,$I1,$I2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-16} = enc{31-16};
+}
+def InsnMII : InstMII<0, (outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1, brtarget12bpp:$RI2,
+ brtarget24bpp:$RI3),
+ ".insn mii,$enc,$M1,$RI2,$RI3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnRI : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
+ ".insn ri,$enc,$R1,$I2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+ let Inst{19-16} = enc{19-16};
+}
+def InsnRIa
+ : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
+ ".insn ri_a,$enc,$R1,$I2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+ let Inst{19-16} = enc{19-16};
+}
+def InsnRIb
+ : InstRIb<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
+ ".insn ri_b,$enc,$R1,$RI2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+ let Inst{19-16} = enc{19-16};
+}
+def InsnRIc
+ : InstRIc<0, (outs), (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
+ ".insn ri_c,$enc,$M1,$RI2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+ let Inst{19-16} = enc{19-16};
+}
+// RIE base format - legacy operand order preserved
+def InsnRIE
+ : InstRIEd<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$I2),
+ ".insn rie,$enc,$R1,$R3,$I2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIEa
+ : InstRIEa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx16:$I2, imm32zx4:$M3),
+ ".insn rie_a,$enc,$R1,$I2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIEb : InstRIEb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx4:$M3, brtarget16:$RI4),
+ ".insn rie_b,$enc,$R1,$R2,$M3,$RI4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIEc : InstRIEc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
+ imm32zx4:$M3, brtarget16:$RI4),
+ ".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIEd
+ : InstRIEd<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
+ ".insn rie_d,$enc,$R1,$I2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIEe
+ : InstRIEe<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, brtarget16:$RI2, AnyReg:$R3),
+ ".insn rie_e,$enc,$R1,$RI2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIEf : InstRIEf<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
+ ".insn rie_f,$enc,$R1,$R2,$I3,$I4,$I5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIEg
+ : InstRIEg<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, imm32zx4:$M3),
+ ".insn rie_g,$enc,$R1,$I2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRIL
+ : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
+ ".insn ril,$enc,$R1,$I2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{35-32} = enc{35-32};
+}
+def InsnRILa
+ : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
+ ".insn ril_a,$enc,$R1,$I2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{35-32} = enc{35-32};
+}
+def InsnRILb
+ : InstRILb<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
+ ".insn ril_b,$enc,$R1,$RI2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{35-32} = enc{35-32};
+}
+def InsnRILc
+ : InstRILc<0, (outs), (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
+ ".insn ril_c,$enc,$M1,$RI2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{35-32} = enc{35-32};
+}
+def InsnRILU : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
+ ".insn rilu,$enc,$R1,$I2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{35-32} = enc{35-32};
+}
+def InsnRIS : InstRIS<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
+ imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
+ ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRR : InstRR<0, (outs), (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
+ ".insn rr,$enc,$R1,$R2", []>,
+ InsnDirectiveBase {
+ bits<16> enc;
+
+ let Inst{15-8} = enc{15-8};
+}
+def InsnRRD : InstRRD<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3),
+ ".insn rrd,$enc,$R1,$R2,$R3", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRE : InstRRE<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2),
+ ".insn rre,$enc,$R1,$R2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRF : InstRRFa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
+ imm32zx4:$M4),
+ ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRFa : InstRRFa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
+ imm32zx4:$M4),
+ ".insn rrf_a,$enc,$R1,$R2,$R3,$M4", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRFb : InstRRFb<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
+ imm32zx4:$M4),
+ ".insn rrf_b,$enc,$R1,$R2,$R3,$M4", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRFc
+ : InstRRFc<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
+ ".insn rrf_c,$enc,$R1,$R2,$M3", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRFd
+ : InstRRFd<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
+ ".insn rrf_d,$enc,$R1,$R2,$M4", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRFe : InstRRFe<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx4:$M3, imm32zx4:$M4),
+ ".insn rrf_e,$enc,$R1,$R2,$M3,$M4", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-16} = enc{31-16};
+}
+def InsnRRS : InstRRS<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3,
+ (bdaddr12only $B4, $D4):$BD4),
+ ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+// RS - legacy operand order preserved
+def InsnRS : InstRSa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn rs,$enc,$R1,$R3,$BD2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-24} = enc{31-24};
+}
+def InsnRSa : InstRSa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn rs_a,$enc,$R1,$BD2,$R3", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-24} = enc{31-24};
+}
+def InsnRSb : InstRSb<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
+ ".insn rs_b,$enc,$R1,$BD2,$M3", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-24} = enc{31-24};
+}
+// RRSE - legacy operand order preserved
+def InsnRSE : InstRSEa<6, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn rse,$enc,$R1,$R3,$BD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+// RSI - legacy operand order preserved
+def InsnRSI
+ : InstRSI<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
+ ".insn rsi,$enc,$R1,$R3,$RI2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+
+ let Inst{31-24} = enc{31-24};
+}
+def InsnRSLa
+ : InstRSLa<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
+ ".insn rsl_a,$enc,$BDL1", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRSLb
+ : InstRSLb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
+ ".insn rsl_b,$enc,$R1,$BDL2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+// RSY - legacy operand order preserved
+def InsnRSY : InstRSYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr20only $B2, $D2):$BD2),
+ ".insn rsy,$enc,$R1,$R3,$BD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRSYa : InstRSYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn rsy_a,$enc,$R1,$BD2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRSYb : InstRSYb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
+ ".insn rsy_b,$enc,$R1,$BD2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRX : InstRXa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx,$enc,$R1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+}
+def InsnRXa : InstRXa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx_a,$enc,$R1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+}
+def InsnRXb : InstRXb<0, (outs),
+ (ins imm64zx32:$enc, imm32zx4:$M1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx_b,$enc,$M1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+}
+def InsnRXE : InstRXE<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rxe,$enc,$R1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let M3 = 0;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+// RXF - legacy operand order preserved
+def InsnRXF : InstRXF<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rxf,$enc,$R1,$R3,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+// RXY - legacy operand order preserved
+def InsnRXY : InstRXYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy,$enc,$R1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRXYa : InstRXYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_a,$enc,$R1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRXYb : InstRXYb<0, (outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_b,$enc,$M1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnRXYc : InstRXYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_c,$enc,$R1,$XBD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnS : InstS<0, (outs), (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
+ ".insn s,$enc,$BD2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-16} = enc{31-16};
+}
+def InsnSI
+ : InstSI<0, (outs),
+ (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
+ ".insn si,$enc,$BD1,$I2", []>,
+ InsnDirectiveBase {
+ bits<32> enc;
+ let Inst{31-24} = enc{31-24};
+}
+def InsnSIY
+ : InstSIY<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1, imm32xx8:$I2),
+ ".insn siy,$enc,$BD1,$I2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnSIL
+ : InstSIL<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx16:$I2),
+ ".insn sil,$enc,$BD1,$I2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-32} = enc{47-32};
+}
+def InsnSMI : InstSMI<0, (outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1, brtarget16bpp:$RI2,
+ (bdaddr12only $B3, $D3):$BD3),
+ ".insn smi,$enc,$M1,$RI2,$BD3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSS : InstSSd<0, (outs),
+ (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn ss,$enc,$RBD1,$BD2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSSa
+ : InstSSa<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn ss_a,$enc,$BDL1,$BD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSSb
+ : InstSSb<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
+ ".insn ss_b,$enc,$BDL1,$BDL2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSSc
+ : InstSSc<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
+ ".insn ss_c,$enc,$BDL1,$BD2,$I3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSSd : InstSSd<0, (outs),
+ (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn ss_d,$enc,$RBD1,$BD2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSSe
+ : InstSSe<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
+ AnyReg:$R3, (bdaddr12only $B4, $D4):$BD4),
+ ".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSSf : InstSSf<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
+ ".insn ss_f,$enc,$BD1,$BDL2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+}
+def InsnSSE : InstSSE<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn sse,$enc,$BD1,$BD2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-32} = enc{47-32};
+}
+def InsnSSF : InstSSF<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn ssf,$enc,$BD1,$BD2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{35-32} = enc{35-32};
+}
+def InsnVRI : InstVRIe<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx12:$I3,
+ imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIa
+ : InstVRIa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32xx16:$I2, imm32zx4:$M3),
+ ".insn vri_a,$enc,$V1,$I2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIb : InstVRIb<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx8:$I2,
+ imm32zx8:$I3, imm32zx4:$M4),
+ ".insn vri_b,$enc,$V1,$I2,$I3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIc : InstVRIc<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vri_c,$enc,$V1,$I2,$V3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRId : InstVRId<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_d,$enc,$V1,$V2,$V3,$I4,$M5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIe : InstVRIe<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vri_e,$enc,$V1,$V2,$I3,$M4,$M5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIf : InstVRIf<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_f,$enc,$V1,$V2,$V3,$I4,$M5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIg : InstVRIg<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
+ imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_g,$enc,$V1,$V2,$I3,$I4,$M5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIh : InstVRIh<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
+ imm32zx4:$I3, imm32zx4:$M4),
+ ".insn vri_h,$enc,$V1,$I2,$I3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIi : InstVRIi<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2,
+ imm32zx8:$I3, imm32zx4:$M4),
+ ".insn vri_i,$enc,$V1,$R2,$I3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIj : InstVRIj<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
+ imm32zx4:$M4),
+ ".insn vri_j,$enc,$V1,$V2,$I3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIk : InstVRIk<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx8:$I5),
+ ".insn vri_k,$enc,$V1,$V2,$V3,$V4,$I5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRIl
+ : InstVRIl<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
+ ".insn vri_l,$enc,$V1,$V2,$I3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRR : InstVRRc<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRa : InstVRRa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3,
+ imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vrr_a,$enc,$V1,$V2,$M3,$M4,$M5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRb : InstVRRb<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vrr_b,$enc,$V1,$V2,$V3,$M4,$M5", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRc : InstVRRc<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_c,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRd : InstVRRd<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_d,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRe : InstVRRe<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_e,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRf : InstVRRf<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2, AnyReg:$R3),
+ ".insn vrr_f,$enc,$V1,$R2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRg
+ : InstVRRg<0, (outs), (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
+ ".insn vrr_g,$enc,$V1,$I2", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRh
+ : InstVRRh<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_h,$enc,$V1,$V2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRi : InstVRRi<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V2,
+ imm32zx4:$M3, imm32zx4:$M4),
+ ".insn vrr_i,$enc,$R1,$V2,$M3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRj : InstVRRj<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4),
+ ".insn vrr_j,$enc,$V1,$V2,$V3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRRk
+ : InstVRRk<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_k,$enc,$V1,$V2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+// VRS - legacy operand order preserved
+def InsnVRS : InstVRSc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
+ ".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRSa
+ : InstVRSa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vrs_a,$enc,$V1,$BD2,$V3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRSb
+ : InstVRSb<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
+ AnyReg:$R3, imm32zx4:$M4),
+ ".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRSc
+ : InstVRSc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRSd : InstVRSd<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn vrs_d,$enc,$V1,$BD2,$R3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRV : InstVRV<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
+ ".insn vrv,$enc,$V1,$VBD2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVRX : InstVRX<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
+ ".insn vrx,$enc,$V1,$XBD2,$M3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
+}
+def InsnVSI : InstVSI<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
+ ".insn vsi,$enc,$V1,$BD2,$I3", []>,
+ InsnDirectiveBase {
+ bits<48> enc;
+ let Inst{47-40} = enc{47-40};
+ let Inst{7-0} = enc{7-0};
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/SystemZ/directive-insn-bad.s b/llvm/test/MC/SystemZ/directive-insn-bad.s
new file mode 100644
index 0000000000000..63a4212501378
--- /dev/null
+++ b/llvm/test/MC/SystemZ/directive-insn-bad.s
@@ -0,0 +1,97 @@
+# RUN: not llvm-mc -triple s390x-linux-gnu %s 2>&1 | FileCheck %s
+
+# CHECK: error: unrecognized format
+# CHECK: .insn not_a_format,0x0
+ .insn not_a_format,0x0
+
+# CHECK: error: unexpected token in directive
+# CHECK: .insn rr,0x0101
+ .insn rr,0x0101
+
+# CHECK: error: unexpected token at start of statement
+# CHECK: .insn e,0x0101,0
+ .insn e,0x0101,0
+
+# CHECK: error: unexpected token in directive
+# CHECK: .insn rr,0x1800,0
+ .insn rr,0x1800,0
+
+# CHECK: error: unexpected token at start of statement
+# CHECK: .insn rr,0x1800,%r1,0(%r2)
+ .insn rr,0x1800,%r1,0(%r2)
+
+# CHECK: error: unknown token in expression
+# CHECK: .insn rxy_a,0xe30000000016,%r1,%r2,0
+ .insn rxy_a,0xe30000000016,%r1,%r2,0
+
+# CHECK: error: unknown token in expression
+# CHECK: .insn ril_c,0xc00400000000,%r1,0
+ .insn ril_c,0xc00400000000,%r1,0
+
+# CHECK: error: invalid operand for instruction
+# CHECK: .insn vri_e,0xe7000000004a,%r1,%v2,837,7,6
+ .insn vri_e,0xe7000000004a,%r1,%v2,837,7,6
+
+# Test immediate value range validation
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn ri,0xa7080000,%r1,0x10000
+ .insn ri,0xa7080000,%r1,0x10000 # 16-bit immediate, value too large (max 0xFFFF)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn ri,0xa7090000,%r1,0x8000
+ .insn ri,0xa7090000,%r1,0x8000 # 16-bit signed immediate, value too large (max 0x7FFF)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn ri,0xa7090000,%r1,-0x8001
+ .insn ri,0xa7090000,%r1,-0x8001 # 16-bit signed immediate, value too small (min -0x8000)
+
+# CHECK: error: offset out of range
+# CHECK: .insn ril,0xc20b00000000,%r2,0x100000000
+ .insn ril,0xc20b00000000,%r2,0x100000000 # 32-bit immediate, value too large
+
+# Test displacement range validation
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rx,0x5a000000,%r1,4096(%r2)
+ .insn rx,0x5a000000,%r1,4096(%r2) # 12-bit displacement, value too large (max 4095)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rx,0x5a000000,%r1,-1(%r2)
+ .insn rx,0x5a000000,%r1,-1(%r2) # 12-bit unsigned displacement, negative value
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rxy,0xe30000000004,%r1,524288(%r2)
+ .insn rxy,0xe30000000004,%r1,524288(%r2) # 20-bit displacement, value too large (max 524287)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rxy,0xe30000000004,%r1,-524289(%r2)
+ .insn rxy,0xe30000000004,%r1,-524289(%r2) # 20-bit signed displacement, value too small (min -524288)
+
+# Test mask/field range validation
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rie_c,0xec000000007e,%r1,256,2,0
+ .insn rie_c,0xec000000007e,%r1,256,2,0 # 8-bit immediate field, value too large (max 255)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rie_f,0xec000000005d,%r1,%r2,256,202,222
+ .insn rie_f,0xec000000005d,%r1,%r2,256,202,222 # 8-bit field, value too large
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rie_f,0xec000000005d,%r1,%r2,250,256,222
+ .insn rie_f,0xec000000005d,%r1,%r2,250,256,222 # 8-bit field, value too large
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rie_f,0xec000000005d,%r1,%r2,250,202,256
+ .insn rie_f,0xec000000005d,%r1,%r2,250,202,256 # 8-bit field, value too large
+
+# Test signed vs unsigned immediate validation
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rilu,0xc20b00000000,%r2,-1
+ .insn rilu,0xc20b00000000,%r2,-1 # rilu expects unsigned 32-bit, negative value rejected
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn sil,0xe56000000000,160(%r15),-32769
+ .insn sil,0xe56000000000,160(%r15),-32769 # sil expects unsigned 16-bit, value too negative
diff --git a/llvm/test/MC/SystemZ/directive-insn-z13.s b/llvm/test/MC/SystemZ/directive-insn-z13.s
index 19d5e6dd76e1f..29b7659d7a02f 100644
--- a/llvm/test/MC/SystemZ/directive-insn-z13.s
+++ b/llvm/test/MC/SystemZ/directive-insn-z13.s
@@ -56,4 +56,9 @@ label.START:
#CHECK: e7 12 34 56 70 21 vlgv %r1, %v2, 1110(%r3), 7
.insn vrs_c,0xe70000000021,%r1,1110(%r3),%v2,7
+#CHECK: e7 16 00 00 30 21 vlgvg %r1, %v6, 0
+ .insn vrs,0xe70000000021,%r1,%v6,0(%r0),3
+#CHECK: e7 12 30 00 00 62 vlvgp %v1, %r2, %r3
+ .insn vrr_f,0xe70000000062,%v1,%r2,%r3
+
diff --git a/llvm/test/MC/SystemZ/directive-insn.s b/llvm/test/MC/SystemZ/directive-insn.s
index 5827e13497f61..980578e561e78 100644
--- a/llvm/test/MC/SystemZ/directive-insn.s
+++ b/llvm/test/MC/SystemZ/directive-insn.s
@@ -232,3 +232,10 @@ label.rsi:
#CHECK: e9 12 34 56 78 90 pka 1110(%r3), 2192(19,%r7)
.insn ss_f,0xe90000000000,1110(%r3),2192(19,%r7)
+
+#CHECK: c0 04 00 00 00 03 jgnop 0x17a
+ .insn ril_c,0xc00400000000,0,label.autogen_ril_c
+label.autogen_ril_c:
+
+#CHECK: e3 12 34 56 78 16 llgf %r1, 492630(%r2,%r3)
+ .insn rxy_a,0xe30000000016,%r1,492630(%r2,%r3)
diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt
index e18279cffa74c..4f6957b93275b 100644
--- a/llvm/utils/TableGen/CMakeLists.txt
+++ b/llvm/utils/TableGen/CMakeLists.txt
@@ -73,6 +73,7 @@ add_tablegen(llvm-tblgen LLVM
X86MnemonicTables.cpp
X86ModRMFilters.cpp
X86RecognizableInstr.cpp
+ SystemZInsnDirectiveEmitter.cpp
$<TARGET_OBJECTS:obj.LLVMTableGenBasic>
$<TARGET_OBJECTS:obj.LLVMTableGenCommon>
diff --git a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
new file mode 100644
index 0000000000000..25eda39b3d44e
--- /dev/null
+++ b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
@@ -0,0 +1,135 @@
+//===- SystemZInsnDirectiveEmitter.cpp - Generate .insn match table -------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend emits a match table for SystemZ .insn directives.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+#include <string>
+
+using namespace llvm;
+
+namespace {
+
+struct InsnMatchEntry {
+ std::string Format;
+ std::string Opcode;
+ SmallVector<std::string, 8> OperandKinds;
+};
+
+static StringRef getFormatName(const Record &Def) {
+ StringRef AsmString = Def.getValueAsString("AsmString");
+ if (!AsmString.consume_front(".insn "))
+ PrintFatalError(&Def, "expected .insn asm string");
+ return AsmString.take_until([](char C) { return C == ','; });
+}
+
+static StringRef getMatchClassKind(const Record &Def, const Init *Arg,
+ unsigned OperandIndex) {
+ static const StringMap<StringRef> KindMap = {
+ {"AnyReg", "MCK_AnyReg"},
+ {"VR128", "MCK_VR128"},
+ {"brtarget12", "MCK_PCRel12"},
+ {"brtarget12bpp", "MCK_PCRel12"},
+ {"brtarget16", "MCK_PCRel16"},
+ {"brtarget16bpp", "MCK_PCRel16"},
+ {"brtarget24bpp", "MCK_PCRel24"},
+ {"brtarget32", "MCK_PCRel32"},
+ {"uimm32", "MCK_U32Imm"},
+ {"imm32zx4", "MCK_U4Imm"},
+ {"imm32zx8", "MCK_U8Imm"},
+ {"imm32sx8", "MCK_S8Imm"},
+ {"imm32xx8", "MCK_X8Imm"},
+ {"imm32zx12", "MCK_U12Imm"},
+ {"imm32zx16", "MCK_U16Imm"},
+ {"imm32sx16", "MCK_S16Imm"},
+ {"imm32xx16", "MCK_X16Imm"},
+ {"imm64zx16", "MCK_U16Imm"},
+ {"imm64zx32", "MCK_U32Imm"},
+ {"imm64xx32", "MCK_X32Imm"},
+ {"imm64zx48", "MCK_U48Imm"},
+ {"bdxaddr12only", "MCK_BDXAddr64Disp12"},
+ {"bdxaddr20only", "MCK_BDXAddr64Disp20"},
+ {"bdaddr12only", "MCK_BDAddr64Disp12"},
+ {"bdaddr20only", "MCK_BDAddr64Disp20"},
+ {"bdvaddr12only", "MCK_BDVAddr64Disp12"},
+ {"bdladdr12onlylen4", "MCK_BDLAddr64Disp12Len4"},
+ {"bdladdr12onlylen8", "MCK_BDLAddr64Disp12Len8"},
+ {"bdraddr12only", "MCK_BDRAddr64Disp12"}};
+
+ std::string ArgTextStorage = Arg->getAsString();
+ StringRef ArgText(ArgTextStorage);
+ if (!ArgText.empty() && ArgText.front() == '(') {
+ ArgText = ArgText.drop_front();
+ ArgText = ArgText.take_while([](char C) { return C != ' '; });
+ }
+
+ // Check registered mappings
+ auto It = KindMap.find(ArgText);
+ if (It != KindMap.end())
+ return It->second;
+
+ PrintFatalError(&Def, "unsupported operand kind in .insn directive operand " +
+ Twine(OperandIndex) + ": " + ArgText);
+}
+
+static InsnMatchEntry buildInsnMatchEntry(const Record &Def) {
+ const DagInit *OutOperands = Def.getValueAsDag("OutOperandList");
+ const DagInit *InOperands = Def.getValueAsDag("InOperandList");
+ if (OutOperands->getNumArgs() > 0)
+ PrintFatalError(&Def, ".insn directive may not have output operands");
+ if (InOperands->getNumArgs() == 0)
+ PrintFatalError(&Def, ".insn directive missing encoding operand");
+
+ InsnMatchEntry Entry;
+ Entry.Format = getFormatName(Def).str();
+ Entry.Opcode = ("SystemZ::" + Def.getName()).str();
+
+ for (unsigned I = 0; I < InOperands->getNumArgs(); ++I)
+ Entry.OperandKinds.push_back(
+ getMatchClassKind(Def, InOperands->getArg(I), I).str());
+
+ return Entry;
+}
+
+static void emitInsnDirectiveMatchTable(const RecordKeeper &RK,
+ raw_ostream &OS) {
+ // This will hold all .insn directive definitions (~100 plus margin).
+ SmallVector<InsnMatchEntry, 128> Entries;
+ // All .insn directive instructions inherit from InsnDirectiveBase.
+ for (const Record *Def : RK.getAllDerivedDefinitions("InsnDirectiveBase")) {
+ Entries.push_back(buildInsnMatchEntry(*Def));
+ }
+
+ llvm::sort(Entries, [](const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
+ return std::tie(LHS.Format, LHS.Opcode) < std::tie(RHS.Format, RHS.Opcode);
+ });
+
+ OS << "/* Format, Opcode, NumOperands, OperandKinds */\n";
+ for (const InsnMatchEntry &Entry : Entries) {
+ OS << " {\"" << Entry.Format << "\", " << Entry.Opcode << ", "
+ << Entry.OperandKinds.size() << ", {";
+ for (unsigned I = 0; I < Entry.OperandKinds.size(); ++I) {
+ if (I != 0)
+ OS << ", ";
+ OS << Entry.OperandKinds[I];
+ }
+ OS << "}},\n";
+ }
+}
+} // namespace
+
+static TableGen::Emitter::Opt X("gen-insn-directive-match-table",
+ emitInsnDirectiveMatchTable,
+ "Generate SystemZ .insn match table.");
>From 4bad524696b56ddcd71098228d94cbfb1976431b Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Tue, 8 Sep 2026 09:46:15 +0200
Subject: [PATCH 03/11] [SystemZ] Improve .insn directive test coverage
This commit adds tests for four targets previously uncovered:
1. X8Imm lower bound: add a negative test for .insn si with -129, which
is below the X8Imm union range [-128..255]. The existing test only
covered the upper bound (256) and the sign extension case (-1).
2. X32Imm lower bound: add a negative test for .insn ril_a with
-2147483649, which is below the X32Imm union range
[-2147483648..4294967295]. The existing test only covered the upper
bound (4294967295).
3. BDL address displacement: add a negative test for .insn rsl_a with
a 12-bit displacement value out of range (4096). The rsl_a format
uses parseBDLAddr64, a code path added in the .insn expansion but
previously untested for error handling.
4. TableGen backend: add a lit test for the new
SystemZInsnDirectiveEmitter (-gen-insn-directive-match-table).
Checks cover representative entries across format families,
X-imm MCK assignments (X8Imm, X16Imm, X32Imm), BDL address
operands, PC-relative immediates, and the (format, opcode) sort
order guarantee.
assisted-by: IBM Bob
---
llvm/test/MC/SystemZ/directive-insn-bad.s | 16 ++++++
.../TableGen/SystemZInsnDirectiveEmitter.td | 56 +++++++++++++++++++
2 files changed, 72 insertions(+)
create mode 100644 llvm/test/TableGen/SystemZInsnDirectiveEmitter.td
diff --git a/llvm/test/MC/SystemZ/directive-insn-bad.s b/llvm/test/MC/SystemZ/directive-insn-bad.s
index 63a4212501378..b839d577b1236 100644
--- a/llvm/test/MC/SystemZ/directive-insn-bad.s
+++ b/llvm/test/MC/SystemZ/directive-insn-bad.s
@@ -95,3 +95,19 @@
# CHECK: error: unexpected operand type
# CHECK: .insn sil,0xe56000000000,160(%r15),-32769
.insn sil,0xe56000000000,160(%r15),-32769 # sil expects unsigned 16-bit, value too negative
+
+# Test X-imm (union signed/unsigned) lower bound validation
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn si,0x91000000,160(%r15),-129
+ .insn si,0x91000000,160(%r15),-129 # X8Imm lower bound (min -128)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn ril_a,0xc20500000000,%r1,-2147483649
+ .insn ril_a,0xc20500000000,%r1,-2147483649 # X32Imm lower bound (min -2147483648)
+
+# Test BD-length address range validation
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn rsl_a,0xeb00000000c0,4096(2,%r2)
+ .insn rsl_a,0xeb00000000c0,4096(2,%r2) # 12-bit displacement in BDL address, value too large (max 4095)
diff --git a/llvm/test/TableGen/SystemZInsnDirectiveEmitter.td b/llvm/test/TableGen/SystemZInsnDirectiveEmitter.td
new file mode 100644
index 0000000000000..90f8f49900a1b
--- /dev/null
+++ b/llvm/test/TableGen/SystemZInsnDirectiveEmitter.td
@@ -0,0 +1,56 @@
+// RUN: llvm-tblgen -gen-insn-directive-match-table %p/../../lib/Target/SystemZ/SystemZ.td \
+// RUN: -I %p/../../lib/Target/SystemZ -I %p/../../include | FileCheck %s
+
+// Verify that the SystemZ .insn directive match table is generated correctly.
+// Checks cover:
+// - Representative entries from several format families to confirm format
+// name, opcode symbol, operand count, and MCK kinds.
+// - X-imm (union signed/unsigned) operands are mapped to the right MCK.
+// - Entries are sorted by (format, opcode): verified with adjacent pairs.
+// Checks must appear in output order (FileCheck is sequential).
+
+// Single-operand format.
+// CHECK: {"e", SystemZ::InsnE, 1, {MCK_U16Imm}},
+
+// I format: opcode + 1 immediate.
+// CHECK: {"i", SystemZ::InsnI, 2, {MCK_U16Imm, MCK_U8Imm}},
+
+// MII: opcode + mask + two PC-relative immediates of different widths.
+// CHECK: {"mii", SystemZ::InsnMII, 4, {MCK_U48Imm, MCK_U4Imm, MCK_PCRel12, MCK_PCRel24}},
+
+// RI alias uses signed 16-bit immediate; RI-a subformat uses the union X16Imm.
+// CHECK: {"ri", SystemZ::InsnRI, 3, {MCK_U32Imm, MCK_AnyReg, MCK_S16Imm}},
+// CHECK: {"ri_a", SystemZ::InsnRIa, 3, {MCK_U32Imm, MCK_AnyReg, MCK_X16Imm}},
+
+// RIE-c uses X8Imm (union of signed/unsigned 8-bit) for its immediate field.
+// CHECK: {"rie_c", SystemZ::InsnRIEc, 5, {MCK_U48Imm, MCK_AnyReg, MCK_X8Imm, MCK_U4Imm, MCK_PCRel16}},
+
+// RIL-a uses X32Imm (union of signed/unsigned 32-bit).
+// CHECK: {"ril_a", SystemZ::InsnRILa, 3, {MCK_U48Imm, MCK_AnyReg, MCK_X32Imm}},
+
+// RSL-a uses a BDL address with 4-bit length.
+// CHECK: {"rsl_a", SystemZ::InsnRSLa, 2, {MCK_U48Imm, MCK_BDLAddr64Disp12Len4}},
+
+// RSL-b uses a BDL address with 8-bit length.
+// CHECK: {"rsl_b", SystemZ::InsnRSLb, 4, {MCK_U48Imm, MCK_AnyReg, MCK_BDLAddr64Disp12Len8, MCK_U4Imm}},
+
+// SI, SIL and SIY use X-imm for the immediate field.
+// CHECK: {"si", SystemZ::InsnSI, 3, {MCK_U32Imm, MCK_BDAddr64Disp12, MCK_X8Imm}},
+// CHECK: {"sil", SystemZ::InsnSIL, 3, {MCK_U48Imm, MCK_BDAddr64Disp12, MCK_X16Imm}},
+// CHECK: {"siy", SystemZ::InsnSIY, 3, {MCK_U48Imm, MCK_BDAddr64Disp20, MCK_X8Imm}},
+
+// SMI (branch-prediction): opcode + mask + PC-relative 16 + BD address.
+// CHECK: {"smi", SystemZ::InsnSMI, 4, {MCK_U48Imm, MCK_U4Imm, MCK_PCRel16, MCK_BDAddr64Disp12}},
+
+// SS-a uses an 8-bit-length BDL for the first operand.
+// CHECK: {"ss_a", SystemZ::InsnSSa, 3, {MCK_U48Imm, MCK_BDLAddr64Disp12Len8, MCK_BDAddr64Disp12}},
+
+// VRI-a uses X16Imm.
+// CHECK: {"vri_a", SystemZ::InsnVRIa, 4, {MCK_U48Imm, MCK_VR128, MCK_X16Imm, MCK_U4Imm}},
+
+// Verify format-then-opcode sort order: vrr_j comes before vrr_k.
+// CHECK: {"vrr_j",
+// CHECK: {"vrr_k",
+
+// VRS-d (z14): opcode + vector + BD address + GP register.
+// CHECK: {"vrs_d", SystemZ::InsnVRSd, 4, {MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_AnyReg}},
>From 7522bdf968b711c9314e710baabe83c0ca52fe96 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Wed, 9 Sep 2026 11:15:34 +0200
Subject: [PATCH 04/11] Various smaller improvements
- Remove match table ordering tiebreak
The tiebreak covered cases that weren't going to occur (equally-named
formats) and only worked by coincidence anyway since the ordering is by
string on the emitter side and by an enum on the parser side.
- Various test improvements
- Various Comment improvements
- Make operand parsing slightly less brittle
- cmake targets in alphabetical order
- minor fixes, typos, etc.
---
.../SystemZ/AsmParser/SystemZAsmParser.cpp | 4 +---
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 12 +++++++---
llvm/test/MC/SystemZ/directive-insn-bad.s | 22 +++++++++++++++----
llvm/test/MC/SystemZ/directive-insn.s | 17 +++++++-------
.../TableGen/SystemZInsnDirectiveEmitter.td | 2 +-
llvm/utils/TableGen/CMakeLists.txt | 2 +-
.../TableGen/SystemZInsnDirectiveEmitter.cpp | 18 +++++++--------
7 files changed, 48 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index f0d842ac93dc8..bb0a409f2e71e 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -660,9 +660,7 @@ struct CompareInsn {
return LHS < RHS.Format;
}
bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
- if (LHS.Format != RHS.Format)
- return LHS.Format < RHS.Format;
- return LHS.Opcode < RHS.Opcode;
+ return LHS.Format < RHS.Format;
}
};
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 459d574b6cfdd..a2886e90ebc8e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2487,6 +2487,7 @@ def InsnRRE : InstRRE<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2),
let Inst{31-16} = enc{31-16};
}
+// Alias for rrf-a. Kept for backwards compatibility.
def InsnRRF : InstRRFa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
imm32zx4:$M4),
@@ -2579,7 +2580,7 @@ def InsnRSb : InstRSb<0, (outs),
let Inst{31-24} = enc{31-24};
}
-// RRSE - legacy operand order preserved
+// RSE - legacy operand order preserved
def InsnRSE : InstRSEa<6, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
(bdaddr12only $B2, $D2):$BD2),
@@ -2593,7 +2594,7 @@ def InsnRSE : InstRSEa<6, (outs),
// RSI - legacy operand order preserved
def InsnRSI
: InstRSI<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
".insn rsi,$enc,$R1,$R3,$RI2", []>,
InsnDirectiveBase {
bits<32> enc;
@@ -2647,6 +2648,7 @@ def InsnRSYb : InstRSYb<0, (outs),
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
+// Alias for rx-a. Kept for backwards compatibility.
def InsnRX : InstRXa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
@@ -2691,7 +2693,7 @@ def InsnRXF : InstRXF<0, (outs),
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
-// RXY - legacy operand order preserved
+
def InsnRXY : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
@@ -2719,6 +2721,7 @@ def InsnRXYb : InstRXYb<0, (outs),
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
+// There is no InstRXYc - it is identical to InstRXYa.
def InsnRXYc : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
@@ -2767,6 +2770,7 @@ def InsnSMI : InstSMI<0, (outs),
bits<48> enc;
let Inst{47-40} = enc{47-40};
}
+// Alias for ss-. Kept for backwards compatibility.
def InsnSS : InstSSd<0, (outs),
(ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
@@ -2844,6 +2848,7 @@ def InsnSSF : InstSSF<0, (outs),
let Inst{47-40} = enc{47-40};
let Inst{35-32} = enc{35-32};
}
+// Alias for vri-e. Kept for backwards compatibility.
def InsnVRI : InstVRIe<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx12:$I3,
imm32zx4:$M4, imm32zx4:$M5),
@@ -2961,6 +2966,7 @@ def InsnVRIl
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
+// Alias for vrr-c. Kept for backwards compatibility.
def InsnVRR : InstVRRc<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
diff --git a/llvm/test/MC/SystemZ/directive-insn-bad.s b/llvm/test/MC/SystemZ/directive-insn-bad.s
index b839d577b1236..f7a169495c821 100644
--- a/llvm/test/MC/SystemZ/directive-insn-bad.s
+++ b/llvm/test/MC/SystemZ/directive-insn-bad.s
@@ -92,20 +92,34 @@
# CHECK: .insn rilu,0xc20b00000000,%r2,-1
.insn rilu,0xc20b00000000,%r2,-1 # rilu expects unsigned 32-bit, negative value rejected
-# CHECK: error: unexpected operand type
-# CHECK: .insn sil,0xe56000000000,160(%r15),-32769
- .insn sil,0xe56000000000,160(%r15),-32769 # sil expects unsigned 16-bit, value too negative
-
# Test X-imm (union signed/unsigned) lower bound validation
# CHECK: error: unexpected operand type
# CHECK: .insn si,0x91000000,160(%r15),-129
.insn si,0x91000000,160(%r15),-129 # X8Imm lower bound (min -128)
+# CHECK: error: unexpected operand type
+# CHECK: .insn sil,0xe56000000000,160(%r15),-32769
+ .insn sil,0xe56000000000,160(%r15),-32769 # X16Imm lower bound
+
# CHECK: error: unexpected operand type
# CHECK: .insn ril_a,0xc20500000000,%r1,-2147483649
.insn ril_a,0xc20500000000,%r1,-2147483649 # X32Imm lower bound (min -2147483648)
+# Test X-imm (union signed/unsigned) upper bound validation
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn si,0x91000000,160(%r15),256
+ .insn si,0x91000000,160(%r15),256 # X8Imm upper bound (max 255)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn sil,0xe56000000000,160(%r15),65536
+ .insn sil,0xe56000000000,160(%r15),65536 # X16Imm upper bound (max 65535)
+
+# CHECK: error: unexpected operand type
+# CHECK: .insn ril_a,0xc20500000000,%r1,4294967296
+ .insn ril_a,0xc20500000000,%r1,4294967296 # X32Imm upper bound (max 4294967295)
+
# Test BD-length address range validation
# CHECK: error: unexpected operand type
diff --git a/llvm/test/MC/SystemZ/directive-insn.s b/llvm/test/MC/SystemZ/directive-insn.s
index 980578e561e78..caa8899b3e7ab 100644
--- a/llvm/test/MC/SystemZ/directive-insn.s
+++ b/llvm/test/MC/SystemZ/directive-insn.s
@@ -164,10 +164,13 @@ label.rsi:
#CHECK: c2 15 ff ff ff ff slfi %r1, 4294967295
.insn ril_a,0xc20500000000,%r1,4294967295
-#CHECK: c0 15 ff ff ff fc brasl %r1, 0xf8
+#CHECK: c2 15 00 fa ca de slfi %r1, 16435934
+ .insn ril_a,0xc20500000000,%r1,(0x00fa0000 | 0xcade)
+
+#CHECK: c0 15 ff ff ff fc brasl %r1, 0xfe
.insn ril_b,0xc00500000000,%r1,-8
-#CHECK: c0 04 ff ff ff fc jgnop 0xfe
+#CHECK: c0 04 ff ff ff fc jgnop 0x104
.insn ril_c,0xc00400000000,0,-8
#CHECK: b3 3e 10 23 madr %f1, %f2, %f3
@@ -189,7 +192,7 @@ label.rsi:
.insn rrf_d,0xb3e30000,%r2,%f3,1
#CHECK: b3 d7 12 34 fidtr %f3, 1, %f4, 2
- .insn rrf_e,0xb3d70000,%r3,%f4,1,2
+ .insn rrf_e,0xb3d70000,%f3,%f4,1,2
#CHECK: 86 12 34 56 bxh %r1, %r2, 1110(%r3)
.insn rs_a,0x86000000,%r1,1110(%r3),%r2
@@ -233,9 +236,7 @@ label.rsi:
#CHECK: e9 12 34 56 78 90 pka 1110(%r3), 2192(19,%r7)
.insn ss_f,0xe90000000000,1110(%r3),2192(19,%r7)
-#CHECK: c0 04 00 00 00 03 jgnop 0x17a
- .insn ril_c,0xc00400000000,0,label.autogen_ril_c
-label.autogen_ril_c:
+#CHECK: c0 04 00 00 00 03 jgnop 0x180
+ .insn ril_c,0xc00400000000,0,label.ril_c
+label.ril_c:
-#CHECK: e3 12 34 56 78 16 llgf %r1, 492630(%r2,%r3)
- .insn rxy_a,0xe30000000016,%r1,492630(%r2,%r3)
diff --git a/llvm/test/TableGen/SystemZInsnDirectiveEmitter.td b/llvm/test/TableGen/SystemZInsnDirectiveEmitter.td
index 90f8f49900a1b..42cb56fa5f2aa 100644
--- a/llvm/test/TableGen/SystemZInsnDirectiveEmitter.td
+++ b/llvm/test/TableGen/SystemZInsnDirectiveEmitter.td
@@ -6,7 +6,7 @@
// - Representative entries from several format families to confirm format
// name, opcode symbol, operand count, and MCK kinds.
// - X-imm (union signed/unsigned) operands are mapped to the right MCK.
-// - Entries are sorted by (format, opcode): verified with adjacent pairs.
+// - Entries are sorted by format.
// Checks must appear in output order (FileCheck is sequential).
// Single-operand format.
diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt
index 4f6957b93275b..23dcd6fcafad6 100644
--- a/llvm/utils/TableGen/CMakeLists.txt
+++ b/llvm/utils/TableGen/CMakeLists.txt
@@ -66,6 +66,7 @@ add_tablegen(llvm-tblgen LLVM
SDNodeInfoEmitter.cpp
SearchableTableEmitter.cpp
SubtargetEmitter.cpp
+ SystemZInsnDirectiveEmitter.cpp
WebAssemblyDisassemblerEmitter.cpp
X86InstrMappingEmitter.cpp
X86DisassemblerTables.cpp
@@ -73,7 +74,6 @@ add_tablegen(llvm-tblgen LLVM
X86MnemonicTables.cpp
X86ModRMFilters.cpp
X86RecognizableInstr.cpp
- SystemZInsnDirectiveEmitter.cpp
$<TARGET_OBJECTS:obj.LLVMTableGenBasic>
$<TARGET_OBJECTS:obj.LLVMTableGenCommon>
diff --git a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
index 25eda39b3d44e..417710f783779 100644
--- a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
@@ -68,12 +68,11 @@ static StringRef getMatchClassKind(const Record &Def, const Init *Arg,
{"bdladdr12onlylen8", "MCK_BDLAddr64Disp12Len8"},
{"bdraddr12only", "MCK_BDRAddr64Disp12"}};
- std::string ArgTextStorage = Arg->getAsString();
- StringRef ArgText(ArgTextStorage);
- if (!ArgText.empty() && ArgText.front() == '(') {
- ArgText = ArgText.drop_front();
- ArgText = ArgText.take_while([](char C) { return C != ' '; });
- }
+ StringRef ArgText;
+ if (const DefInit *DefOp = dyn_cast<DefInit>(Arg))
+ ArgText = DefOp->getDef()->getName();
+ if (const DagInit *DagOp = dyn_cast<DagInit>(Arg))
+ ArgText = DagOp->getOperatorAsDef(Def.getLoc())->getName();
// Check registered mappings
auto It = KindMap.find(ArgText);
@@ -105,15 +104,16 @@ static InsnMatchEntry buildInsnMatchEntry(const Record &Def) {
static void emitInsnDirectiveMatchTable(const RecordKeeper &RK,
raw_ostream &OS) {
+ emitSourceFileHeader("Match Table for SystemZ .insn directive operand types",
+ OS);
// This will hold all .insn directive definitions (~100 plus margin).
SmallVector<InsnMatchEntry, 128> Entries;
// All .insn directive instructions inherit from InsnDirectiveBase.
- for (const Record *Def : RK.getAllDerivedDefinitions("InsnDirectiveBase")) {
+ for (const Record *Def : RK.getAllDerivedDefinitions("InsnDirectiveBase"))
Entries.push_back(buildInsnMatchEntry(*Def));
- }
llvm::sort(Entries, [](const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
- return std::tie(LHS.Format, LHS.Opcode) < std::tie(RHS.Format, RHS.Opcode);
+ return LHS.Format < RHS.Format;
});
OS << "/* Format, Opcode, NumOperands, OperandKinds */\n";
>From 73767d8991a75a90d3c3be201afafb10e7321677 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Thu, 10 Sep 2026 11:26:16 +0200
Subject: [PATCH 05/11] Derive match class from ParserMatchClass record
---
.../TableGen/SystemZInsnDirectiveEmitter.cpp | 68 ++++++-------------
1 file changed, 22 insertions(+), 46 deletions(-)
diff --git a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
index 417710f783779..22aef8325e2bb 100644
--- a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
@@ -35,52 +35,28 @@ static StringRef getFormatName(const Record &Def) {
return AsmString.take_until([](char C) { return C == ','; });
}
-static StringRef getMatchClassKind(const Record &Def, const Init *Arg,
- unsigned OperandIndex) {
- static const StringMap<StringRef> KindMap = {
- {"AnyReg", "MCK_AnyReg"},
- {"VR128", "MCK_VR128"},
- {"brtarget12", "MCK_PCRel12"},
- {"brtarget12bpp", "MCK_PCRel12"},
- {"brtarget16", "MCK_PCRel16"},
- {"brtarget16bpp", "MCK_PCRel16"},
- {"brtarget24bpp", "MCK_PCRel24"},
- {"brtarget32", "MCK_PCRel32"},
- {"uimm32", "MCK_U32Imm"},
- {"imm32zx4", "MCK_U4Imm"},
- {"imm32zx8", "MCK_U8Imm"},
- {"imm32sx8", "MCK_S8Imm"},
- {"imm32xx8", "MCK_X8Imm"},
- {"imm32zx12", "MCK_U12Imm"},
- {"imm32zx16", "MCK_U16Imm"},
- {"imm32sx16", "MCK_S16Imm"},
- {"imm32xx16", "MCK_X16Imm"},
- {"imm64zx16", "MCK_U16Imm"},
- {"imm64zx32", "MCK_U32Imm"},
- {"imm64xx32", "MCK_X32Imm"},
- {"imm64zx48", "MCK_U48Imm"},
- {"bdxaddr12only", "MCK_BDXAddr64Disp12"},
- {"bdxaddr20only", "MCK_BDXAddr64Disp20"},
- {"bdaddr12only", "MCK_BDAddr64Disp12"},
- {"bdaddr20only", "MCK_BDAddr64Disp20"},
- {"bdvaddr12only", "MCK_BDVAddr64Disp12"},
- {"bdladdr12onlylen4", "MCK_BDLAddr64Disp12Len4"},
- {"bdladdr12onlylen8", "MCK_BDLAddr64Disp12Len8"},
- {"bdraddr12only", "MCK_BDRAddr64Disp12"}};
-
- StringRef ArgText;
- if (const DefInit *DefOp = dyn_cast<DefInit>(Arg))
- ArgText = DefOp->getDef()->getName();
- if (const DagInit *DagOp = dyn_cast<DagInit>(Arg))
- ArgText = DagOp->getOperatorAsDef(Def.getLoc())->getName();
-
- // Check registered mappings
- auto It = KindMap.find(ArgText);
- if (It != KindMap.end())
- return It->second;
+static std::string getMatchClassKind(const Record &Def, const Init *Arg,
+ unsigned OperandIndex) {
- PrintFatalError(&Def, "unsupported operand kind in .insn directive operand " +
- Twine(OperandIndex) + ": " + ArgText);
+ // Obtain record of operand.
+ const Record *OpRec;
+ if (const DefInit *DefOp = dyn_cast<DefInit>(Arg))
+ OpRec = DefOp->getDef();
+ else if (const DagInit *DagOp = dyn_cast<DagInit>(Arg))
+ OpRec = DagOp->getOperatorAsDef(Def.getLoc());
+ else
+ PrintFatalError(&Def, "Unexpected Init Type (neither def nor dag) in .insn "
+ "directive operand");
+
+ // Get name of ParserMatchClass associated with operand.
+ StringRef MC = OpRec->getValueAsDef("ParserMatchClass")->getName();
+
+ // Drop AsmOperandSuffix if present.
+ if (MC.ends_with("AsmOperand"))
+ MC = MC.drop_back(10);
+
+ // Prepend MCK_ and return.
+ return "MCK_" + std::string(MC);
}
static InsnMatchEntry buildInsnMatchEntry(const Record &Def) {
@@ -97,7 +73,7 @@ static InsnMatchEntry buildInsnMatchEntry(const Record &Def) {
for (unsigned I = 0; I < InOperands->getNumArgs(); ++I)
Entry.OperandKinds.push_back(
- getMatchClassKind(Def, InOperands->getArg(I), I).str());
+ getMatchClassKind(Def, InOperands->getArg(I), I));
return Entry;
}
>From ac4751237e138a2b87beea1c974711c136c77021 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Fri, 11 Sep 2026 14:24:07 +0200
Subject: [PATCH 06/11] Move enc handling to the format classes
assisted-by IBM Bob
---
.../lib/Target/SystemZ/SystemZInstrFormats.td | 371 ++++++-----
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 583 +++---------------
2 files changed, 322 insertions(+), 632 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 10d09ecd637f8..2c5f6e753499d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -188,28 +188,28 @@ def getTwoOperandOpcode : InstrMapping {
class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
-
- let Inst = op;
+ bits<16> enc;
+ let Inst = !if(!ne(op, 0), op, enc);
}
class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
-
+ bits<16> enc;
bits<8> I1;
- let Inst{15-8} = op;
+ let Inst{15-8} = !if(!ne(op, 0), op, enc{15-8});
let Inst{7-0} = I1;
}
class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
-
+ bits<32> enc;
bits<4> I1;
bits<4> I2;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-8} = 0;
let Inst{7-4} = I1;
let Inst{3-0} = I2;
@@ -218,12 +218,12 @@ class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
-
+ bits<48> enc;
bits<4> M1;
bits<12> RI2;
bits<24> RI3;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-36} = M1;
let Inst{35-24} = RI2;
let Inst{23-0} = RI3;
@@ -232,130 +232,136 @@ class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
-
+ bits<32> enc;
bits<4> R1;
bits<16> I2;
- let Inst{31-24} = op{11-4};
+ let Inst{31-24} = !if(!ne(op, 0), op{11-4}, enc{31-24});
let Inst{23-20} = R1;
- let Inst{19-16} = op{3-0};
+ let Inst{19-16} = !if(!ne(op, 0), op{3-0}, enc{19-16});
let Inst{15-0} = I2;
}
class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
-
+ bits<32> enc;
bits<4> R1;
bits<16> RI2;
- let Inst{31-24} = op{11-4};
+ let Inst{31-24} = !if(!ne(op, 0), op{11-4}, enc{31-24});
let Inst{23-20} = R1;
- let Inst{19-16} = op{3-0};
+ let Inst{19-16} = !if(!ne(op, 0), op{3-0}, enc{19-16});
let Inst{15-0} = RI2;
}
class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
-
+ bits<32> enc;
bits<4> M1;
bits<16> RI2;
- let Inst{31-24} = op{11-4};
+ let Inst{31-24} = !if(!ne(op, 0), op{11-4}, enc{31-24});
let Inst{23-20} = M1;
- let Inst{19-16} = op{3-0};
+ let Inst{19-16} = !if(!ne(op, 0), op{3-0}, enc{19-16});
let Inst{15-0} = RI2;
}
class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<16> I2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = 0;
let Inst{31-16} = I2;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R2;
bits<4> M3;
bits<16> RI4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31-16} = RI4;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<8> I2;
bits<4> M3;
bits<16> RI4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-16} = RI4;
let Inst{15-8} = I2;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R3;
bits<16> I2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-16} = I2;
let Inst{15-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R3;
bits<16> RI2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-16} = RI2;
let Inst{15-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R2;
@@ -363,7 +369,7 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<8> I4;
bits<8> I5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31} = !if(I3Or{7}, 1, I3{7});
@@ -383,67 +389,72 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
let Inst{17} = !if(I4Or{1}, 1, I4{1});
let Inst{16} = !if(I4Or{0}, 1, I4{0});
let Inst{15-8} = I5;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> M3;
bits<16> I2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-16} = I2;
let Inst{15-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<32> I2;
- let Inst{47-40} = op{11-4};
+ let Inst{47-40} = !if(!ne(op, 0), op{11-4}, enc{47-40});
let Inst{39-36} = R1;
- let Inst{35-32} = op{3-0};
+ let Inst{35-32} = !if(!ne(op, 0), op{3-0}, enc{35-32});
let Inst{31-0} = I2;
}
class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<32> RI2;
- let Inst{47-40} = op{11-4};
+ let Inst{47-40} = !if(!ne(op, 0), op{11-4}, enc{47-40});
let Inst{39-36} = R1;
- let Inst{35-32} = op{3-0};
+ let Inst{35-32} = !if(!ne(op, 0), op{3-0}, enc{35-32});
let Inst{31-0} = RI2;
}
class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> M1;
bits<32> RI2;
- let Inst{47-40} = op{11-4};
+ let Inst{47-40} = !if(!ne(op, 0), op{11-4}, enc{47-40});
let Inst{39-36} = M1;
- let Inst{35-32} = op{3-0};
+ let Inst{35-32} = !if(!ne(op, 0), op{3-0}, enc{35-32});
let Inst{31-0} = RI2;
}
class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<8> I2;
@@ -451,23 +462,24 @@ class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> B4;
bits<12> D4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-28} = B4;
let Inst{27-16} = D4;
let Inst{15-8} = I2;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
+ bits<16> enc;
bits<4> R1;
bits<4> R2;
- let Inst{15-8} = op;
+ let Inst{15-8} = !if(!ne(op, 0), op, enc{15-8});
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
@@ -475,12 +487,13 @@ class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R3;
bits<4> R2;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-12} = R1;
let Inst{11-8} = 0;
let Inst{7-4} = R3;
@@ -490,11 +503,12 @@ class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R2;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-8} = 0;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
@@ -503,13 +517,14 @@ class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R2;
bits<4> R3;
bits<4> M4;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-12} = R3;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
@@ -519,13 +534,14 @@ class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R2;
bits<4> R3;
bits<4> M4;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-12} = R3;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
@@ -535,12 +551,13 @@ class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R2;
bits<4> M3;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-4} = R1;
@@ -550,12 +567,13 @@ class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R2;
bits<4> M4;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-12} = 0;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
@@ -565,13 +583,14 @@ class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R2;
bits<4> M3;
bits<4> M4;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-12} = M3;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
@@ -581,6 +600,7 @@ class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R2;
@@ -588,26 +608,27 @@ class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> B4;
bits<12> D4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31-28} = B4;
let Inst{27-16} = D4;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> X2;
bits<4> B2;
bits<12> D2;
- let Inst{31-24} = op;
+ let Inst{31-24} = !if(!ne(op, 0), op, enc{31-24});
let Inst{23-20} = R1;
let Inst{19-16} = X2;
let Inst{15-12} = B2;
@@ -619,13 +640,14 @@ class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> M1;
bits<4> X2;
bits<4> B2;
bits<12> D2;
- let Inst{31-24} = op;
+ let Inst{31-24} = !if(!ne(op, 0), op, enc{31-24});
let Inst{23-20} = M1;
let Inst{19-16} = X2;
let Inst{15-12} = B2;
@@ -637,6 +659,7 @@ class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> X2;
@@ -644,14 +667,14 @@ class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = X2;
let Inst{31-28} = B2;
let Inst{27-16} = D2;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
let HasIndex = 1;
}
@@ -659,6 +682,7 @@ class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R3;
@@ -666,14 +690,14 @@ class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> B2;
bits<12> D2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R3;
let Inst{35-32} = X2;
let Inst{31-28} = B2;
let Inst{27-16} = D2;
let Inst{15-12} = R1;
let Inst{11-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
let HasIndex = 1;
}
@@ -681,19 +705,20 @@ class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> X2;
bits<4> B2;
bits<20> D2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = X2;
let Inst{31-28} = B2;
let Inst{27-16} = D2{11-0};
let Inst{15-8} = D2{19-12};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
let Has20BitOffset = 1;
let HasIndex = 1;
@@ -702,19 +727,20 @@ class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> M1;
bits<4> X2;
bits<4> B2;
bits<20> D2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = M1;
let Inst{35-32} = X2;
let Inst{31-28} = B2;
let Inst{27-16} = D2{11-0};
let Inst{15-8} = D2{19-12};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
let Has20BitOffset = 1;
let HasIndex = 1;
@@ -723,13 +749,14 @@ class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R3;
bits<4> B2;
bits<12> D2;
- let Inst{31-24} = op;
+ let Inst{31-24} = !if(!ne(op, 0), op, enc{31-24});
let Inst{23-20} = R1;
let Inst{19-16} = R3;
let Inst{15-12} = B2;
@@ -739,13 +766,14 @@ class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> M3;
bits<4> B2;
bits<12> D2;
- let Inst{31-24} = op;
+ let Inst{31-24} = !if(!ne(op, 0), op, enc{31-24});
let Inst{23-20} = R1;
let Inst{19-16} = M3;
let Inst{15-12} = B2;
@@ -755,30 +783,32 @@ class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRSEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R3;
bits<4> B2;
bits<12> D2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-28} = B2;
let Inst{27-16} = D2;
let Inst{15-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> R1;
bits<4> R3;
bits<16> RI2;
- let Inst{31-24} = op;
+ let Inst{31-24} = !if(!ne(op, 0), op, enc{31-24});
let Inst{23-20} = R1;
let Inst{19-16} = R3;
let Inst{15-0} = RI2;
@@ -787,23 +817,25 @@ class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
bits<4> L1;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = L1;
let Inst{35-32} = 0;
let Inst{31-28} = B1;
let Inst{27-16} = D1;
let Inst{15-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> B2;
@@ -811,31 +843,32 @@ class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<8> L2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-32} = L2;
let Inst{31-28} = B2;
let Inst{27-16} = D2;
let Inst{15-12} = R1;
let Inst{11-8} = M3;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> R3;
bits<4> B2;
bits<20> D2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-28} = B2;
let Inst{27-16} = D2{11-0};
let Inst{15-8} = D2{19-12};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
let Has20BitOffset = 1;
}
@@ -843,19 +876,20 @@ class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> M3;
bits<4> B2;
bits<20> D2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-28} = B2;
let Inst{27-16} = D2{11-0};
let Inst{15-8} = D2{19-12};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
let Has20BitOffset = 1;
}
@@ -863,12 +897,13 @@ class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> B1;
bits<12> D1;
bits<8> I2;
- let Inst{31-24} = op;
+ let Inst{31-24} = !if(!ne(op, 0), op, enc{31-24});
let Inst{23-16} = I2;
let Inst{15-12} = B1;
let Inst{11-0} = D1;
@@ -877,12 +912,13 @@ class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
bits<16> I2;
- let Inst{47-32} = op;
+ let Inst{47-32} = !if(!ne(op, 0), op, enc{47-32});
let Inst{31-28} = B1;
let Inst{27-16} = D1;
let Inst{15-0} = I2;
@@ -891,17 +927,18 @@ class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<20> D1;
bits<8> I2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-32} = I2;
let Inst{31-28} = B1;
let Inst{27-16} = D1{11-0};
let Inst{15-8} = D1{19-12};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
let Has20BitOffset = 1;
}
@@ -909,13 +946,14 @@ class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> M1;
bits<16> RI2;
bits<4> B3;
bits<12> D3;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-36} = M1;
let Inst{35-32} = 0;
let Inst{31-28} = B3;
@@ -926,6 +964,7 @@ class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
@@ -933,7 +972,7 @@ class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> B2;
bits<12> D2;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-32} = L1;
let Inst{31-28} = B1;
let Inst{27-16} = D1;
@@ -944,6 +983,7 @@ class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
@@ -952,7 +992,7 @@ class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<4> L2;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-36} = L1;
let Inst{35-32} = L2;
let Inst{31-28} = B1;
@@ -964,6 +1004,7 @@ class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
@@ -972,7 +1013,7 @@ class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<4> I3;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-36} = L1;
let Inst{35-32} = I3;
let Inst{31-28} = B1;
@@ -984,6 +1025,7 @@ class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> B1;
@@ -992,7 +1034,7 @@ class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<4> R3;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-28} = B1;
@@ -1004,6 +1046,7 @@ class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> B2;
@@ -1012,7 +1055,7 @@ class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> B4;
bits<12> D4;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-28} = B2;
@@ -1024,6 +1067,7 @@ class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
@@ -1031,7 +1075,7 @@ class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<8> L2;
- let Inst{47-40} = op;
+ let Inst{47-40} = !if(!ne(op, 0), op, enc{47-40});
let Inst{39-32} = L2;
let Inst{31-28} = B1;
let Inst{27-16} = D1;
@@ -1042,13 +1086,14 @@ class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
bits<4> B2;
bits<12> D2;
- let Inst{47-32} = op;
+ let Inst{47-32} = !if(!ne(op, 0), op, enc{47-32});
let Inst{31-28} = B1;
let Inst{27-16} = D1;
let Inst{15-12} = B2;
@@ -1058,6 +1103,7 @@ class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> B1;
bits<12> D1;
@@ -1065,9 +1111,9 @@ class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<4> R3;
- let Inst{47-40} = op{11-4};
+ let Inst{47-40} = !if(!ne(op, 0), op{11-4}, enc{47-40});
let Inst{39-36} = R3;
- let Inst{35-32} = op{3-0};
+ let Inst{35-32} = !if(!ne(op, 0), op{3-0}, enc{35-32});
let Inst{31-28} = B1;
let Inst{27-16} = D1;
let Inst{15-12} = B2;
@@ -1077,11 +1123,12 @@ class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
+ bits<32> enc;
bits<4> B2;
bits<12> D2;
- let Inst{31-16} = op;
+ let Inst{31-16} = !if(!ne(op, 0), op, enc{31-16});
let Inst{15-12} = B2;
let Inst{11-0} = D2;
}
@@ -1089,31 +1136,33 @@ class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<16> I2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = 0;
let Inst{31-16} = I2;
let Inst{15-12} = M3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<8> I2;
bits<8> I3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = 0;
let Inst{31-24} = I2;
@@ -1121,19 +1170,20 @@ class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V3;
bits<16> I2;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V3{3-0};
let Inst{31-16} = I2;
@@ -1141,12 +1191,13 @@ class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = V1{4};
let Inst{10} = V3{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1154,7 +1205,7 @@ class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<8> I4;
bits<4> M5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1165,12 +1216,13 @@ class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1178,7 +1230,7 @@ class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> M4;
bits<4> M5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-20} = I3;
@@ -1187,12 +1239,13 @@ class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1200,7 +1253,7 @@ class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<8> I4;
bits<4> M5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1211,12 +1264,13 @@ class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1224,7 +1278,7 @@ class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<8> I4;
bits<4> M5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-24} = I4;
@@ -1233,37 +1287,39 @@ class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<16> I2;
bits<4> I3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = 0;
let Inst{31-16} = I2;
let Inst{15-12} = I3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<4> R2;
bits<8> I3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = R2;
let Inst{31-24} = 0;
@@ -1271,19 +1327,20 @@ class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{19-12} = I3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
bits<8> I3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-24} = 0;
@@ -1292,12 +1349,13 @@ class InstVRIj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1305,7 +1363,7 @@ class InstVRIk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<5> V4;
bits<8> I5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1316,18 +1374,19 @@ class InstVRIk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = V4{4};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRIl<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
bits<16> I3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = 0;
let Inst{35-32} = V1{3-0};
let Inst{31-28} = V2{3-0};
@@ -1336,7 +1395,7 @@ class InstVRIl<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V1{4};
let Inst{9} = V2{4};
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
// Depending on the instruction mnemonic, certain bits may be or-ed into
@@ -1345,6 +1404,7 @@ class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> m4or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1352,7 +1412,7 @@ class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> M4;
bits<4> M5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-24} = 0;
@@ -1365,7 +1425,7 @@ class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
// Depending on the instruction mnemonic, certain bits may be or-ed into
@@ -1374,6 +1434,7 @@ class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> m5or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1381,7 +1442,7 @@ class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> M4;
bits<4> M5;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1396,12 +1457,13 @@ class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1410,7 +1472,7 @@ class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> M5;
bits<4> M6;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1422,7 +1484,7 @@ class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
// Depending on the instruction mnemonic, certain bits may be or-ed into
@@ -1431,6 +1493,7 @@ class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> m6or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1439,7 +1502,7 @@ class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> M5;
bits<4> M6;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1454,12 +1517,13 @@ class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = V4{4};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1468,7 +1532,7 @@ class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> M5;
bits<4> M6;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1480,35 +1544,37 @@ class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = V4{4};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<4> R2;
bits<4> R3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = R2;
let Inst{31-28} = R3;
let Inst{27-12} = 0;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<16> I2;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = 0;
let Inst{35-32} = V1{3-0};
let Inst{31-28} = 0;
@@ -1516,18 +1582,19 @@ class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = 0;
let Inst{10} = V1{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = 0;
let Inst{35-32} = V1{3-0};
let Inst{31-28} = V2{3-0};
@@ -1538,19 +1605,20 @@ class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V1{4};
let Inst{9} = V2{4};
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<5> V2;
bits<4> M3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = V2{3-0};
let Inst{31-24} = 0;
@@ -1560,19 +1628,20 @@ class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = 0;
let Inst{10} = V2{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
bits<5> V3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
@@ -1584,18 +1653,19 @@ class InstVRRj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRRk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = 0;
@@ -1607,12 +1677,13 @@ class InstVRRk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10} = V2{4};
let Inst{9} = 0;
let Inst{8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<4> B2;
@@ -1620,7 +1691,7 @@ class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<5> V3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V3{3-0};
let Inst{31-28} = B2;
@@ -1629,12 +1700,13 @@ class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = V1{4};
let Inst{10} = V3{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<4> B2;
@@ -1642,7 +1714,7 @@ class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<4> R3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = R3;
let Inst{31-28} = B2;
@@ -1650,12 +1722,13 @@ class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<4> R1;
bits<4> B2;
@@ -1663,7 +1736,7 @@ class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<5> V3;
bits<4> M4;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = R1;
let Inst{35-32} = V3{3-0};
let Inst{31-28} = B2;
@@ -1672,19 +1745,20 @@ class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = 0;
let Inst{10} = V3{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<4> B2;
bits<12> D2;
bits<4> R3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = 0;
let Inst{35-32} = R3;
let Inst{31-28} = B2;
@@ -1692,12 +1766,13 @@ class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{15-12} = V1{3-0};
let Inst{11-9} = 0;
let Inst{8} = V1{4};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<5> V2;
@@ -1705,7 +1780,7 @@ class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = B2;
@@ -1714,12 +1789,13 @@ class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<4> X2;
@@ -1727,7 +1803,7 @@ class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<12> D2;
bits<4> M3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-36} = V1{3-0};
let Inst{35-32} = X2;
let Inst{31-28} = B2;
@@ -1735,26 +1811,27 @@ class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{15-12} = M3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
+ bits<48> enc;
bits<5> V1;
bits<4> B2;
bits<12> D2;
bits<8> I3;
- let Inst{47-40} = op{15-8};
+ let Inst{47-40} = !if(!ne(op, 0), op{15-8}, enc{47-40});
let Inst{39-32} = I3;
let Inst{31-28} = B2;
let Inst{27-16} = D2;
let Inst{15-12} = V1{3-0};
let Inst{11-9} = 0;
let Inst{8} = V1{4};
- let Inst{7-0} = op{7-0};
+ let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index a2886e90ebc8e..d19691481440e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2276,879 +2276,492 @@ let hasSideEffects = 1 in {
//===----------------------------------------------------------------------===//
def InsnE : InstE<0, (outs), (ins imm64zx16:$enc), ".insn e,$enc", []>,
- InsnDirectiveBase {
- bits<16> enc;
- let Inst = enc;
-}
+ InsnDirectiveBase;
def InsnI : InstI<0, (outs), (ins imm64zx16:$enc, imm32zx8:$I1),
".insn i,$enc,$I1", []>,
- InsnDirectiveBase {
- bits<16> enc;
- let Inst{15-8} = enc{15-8};
-}
+ InsnDirectiveBase;
def InsnIE : InstIE<0, (outs), (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
".insn ie,$enc,$I1,$I2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnMII : InstMII<0, (outs),
(ins imm64zx48:$enc, imm32zx4:$M1, brtarget12bpp:$RI2,
brtarget24bpp:$RI3),
".insn mii,$enc,$M1,$RI2,$RI3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnRI : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
".insn ri,$enc,$R1,$I2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
- let Inst{19-16} = enc{19-16};
-}
+ InsnDirectiveBase;
def InsnRIa
: InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
".insn ri_a,$enc,$R1,$I2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
- let Inst{19-16} = enc{19-16};
-}
+ InsnDirectiveBase;
def InsnRIb
: InstRIb<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
".insn ri_b,$enc,$R1,$RI2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
- let Inst{19-16} = enc{19-16};
-}
+ InsnDirectiveBase;
def InsnRIc
: InstRIc<0, (outs), (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
".insn ri_c,$enc,$M1,$RI2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
- let Inst{19-16} = enc{19-16};
-}
+ InsnDirectiveBase;
// RIE base format - legacy operand order preserved
def InsnRIE
: InstRIEd<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$I2),
".insn rie,$enc,$R1,$R3,$I2", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIEa
: InstRIEa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32xx16:$I2, imm32zx4:$M3),
".insn rie_a,$enc,$R1,$I2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIEb : InstRIEb<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
imm32zx4:$M3, brtarget16:$RI4),
".insn rie_b,$enc,$R1,$R2,$M3,$RI4", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIEc : InstRIEc<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
imm32zx4:$M3, brtarget16:$RI4),
".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIEd
: InstRIEd<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
".insn rie_d,$enc,$R1,$I2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIEe
: InstRIEe<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, brtarget16:$RI2, AnyReg:$R3),
".insn rie_e,$enc,$R1,$RI2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIEf : InstRIEf<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
".insn rie_f,$enc,$R1,$R2,$I3,$I4,$I5", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIEg
: InstRIEg<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, imm32zx4:$M3),
".insn rie_g,$enc,$R1,$I2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRIL
: InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
".insn ril,$enc,$R1,$I2", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
+ InsnDirectiveBase;
def InsnRILa
: InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
".insn ril_a,$enc,$R1,$I2", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
+ InsnDirectiveBase;
def InsnRILb
: InstRILb<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
".insn ril_b,$enc,$R1,$RI2", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
+ InsnDirectiveBase;
def InsnRILc
: InstRILc<0, (outs), (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
".insn ril_c,$enc,$M1,$RI2", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
+ InsnDirectiveBase;
def InsnRILU : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
".insn rilu,$enc,$R1,$I2", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
+ InsnDirectiveBase;
def InsnRIS : InstRIS<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
".insn ris,$enc,$R1,$I2,$M3,$BD4", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRR : InstRR<0, (outs), (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
".insn rr,$enc,$R1,$R2", []>,
- InsnDirectiveBase {
- bits<16> enc;
-
- let Inst{15-8} = enc{15-8};
-}
+ InsnDirectiveBase;
def InsnRRD : InstRRD<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3),
".insn rrd,$enc,$R1,$R2,$R3", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnRRE : InstRRE<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2),
".insn rre,$enc,$R1,$R2", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
// Alias for rrf-a. Kept for backwards compatibility.
def InsnRRF : InstRRFa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
imm32zx4:$M4),
".insn rrf,$enc,$R1,$R2,$R3,$M4", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnRRFa : InstRRFa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
imm32zx4:$M4),
".insn rrf_a,$enc,$R1,$R2,$R3,$M4", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnRRFb : InstRRFb<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
imm32zx4:$M4),
".insn rrf_b,$enc,$R1,$R2,$R3,$M4", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnRRFc
: InstRRFc<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
".insn rrf_c,$enc,$R1,$R2,$M3", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnRRFd
: InstRRFd<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
".insn rrf_d,$enc,$R1,$R2,$M4", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnRRFe : InstRRFe<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
imm32zx4:$M3, imm32zx4:$M4),
".insn rrf_e,$enc,$R1,$R2,$M3,$M4", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnRRS : InstRRS<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3,
(bdaddr12only $B4, $D4):$BD4),
".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
// RS - legacy operand order preserved
def InsnRS : InstRSa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
(bdaddr12only $B2, $D2):$BD2),
".insn rs,$enc,$R1,$R3,$BD2", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
def InsnRSa : InstRSa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn rs_a,$enc,$R1,$BD2,$R3", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
def InsnRSb : InstRSb<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
(bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
".insn rs_b,$enc,$R1,$BD2,$M3", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
// RSE - legacy operand order preserved
-def InsnRSE : InstRSEa<6, (outs),
+def InsnRSE : InstRSEa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
(bdaddr12only $B2, $D2):$BD2),
".insn rse,$enc,$R1,$R3,$BD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
-
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
// RSI - legacy operand order preserved
def InsnRSI
: InstRSI<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
".insn rsi,$enc,$R1,$R3,$RI2", []>,
- InsnDirectiveBase {
- bits<32> enc;
-
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
def InsnRSLa
: InstRSLa<0, (outs),
(ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
".insn rsl_a,$enc,$BDL1", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRSLb
: InstRSLb<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
".insn rsl_b,$enc,$R1,$BDL2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
// RSY - legacy operand order preserved
def InsnRSY : InstRSYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
(bdaddr20only $B2, $D2):$BD2),
".insn rsy,$enc,$R1,$R3,$BD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRSYa : InstRSYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
".insn rsy_a,$enc,$R1,$BD2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRSYb : InstRSYb<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
".insn rsy_b,$enc,$R1,$BD2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
// Alias for rx-a. Kept for backwards compatibility.
def InsnRX : InstRXa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rx,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
def InsnRXa : InstRXa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rx_a,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
def InsnRXb : InstRXb<0, (outs),
(ins imm64zx32:$enc, imm32zx4:$M1,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rx_b,$enc,$M1,$XBD2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
def InsnRXE : InstRXE<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rxe,$enc,$R1,$XBD2", []>,
InsnDirectiveBase {
- bits<48> enc;
let M3 = 0;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
}
// RXF - legacy operand order preserved
def InsnRXF : InstRXF<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rxf,$enc,$R1,$R3,$XBD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRXY : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRXYa : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy_a,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnRXYb : InstRXYb<0, (outs),
(ins imm64zx48:$enc, imm32zx4:$M1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy_b,$enc,$M1,$XBD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
// There is no InstRXYc - it is identical to InstRXYa.
def InsnRXYc : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy_c,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnS : InstS<0, (outs), (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
".insn s,$enc,$BD2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-16} = enc{31-16};
-}
+ InsnDirectiveBase;
def InsnSI
: InstSI<0, (outs),
(ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
".insn si,$enc,$BD1,$I2", []>,
- InsnDirectiveBase {
- bits<32> enc;
- let Inst{31-24} = enc{31-24};
-}
+ InsnDirectiveBase;
def InsnSIY
: InstSIY<0, (outs),
(ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1, imm32xx8:$I2),
".insn siy,$enc,$BD1,$I2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnSIL
: InstSIL<0, (outs),
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx16:$I2),
".insn sil,$enc,$BD1,$I2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-32} = enc{47-32};
-}
+ InsnDirectiveBase;
def InsnSMI : InstSMI<0, (outs),
(ins imm64zx48:$enc, imm32zx4:$M1, brtarget16bpp:$RI2,
(bdaddr12only $B3, $D3):$BD3),
".insn smi,$enc,$M1,$RI2,$BD3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
// Alias for ss-. Kept for backwards compatibility.
def InsnSS : InstSSd<0, (outs),
(ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ss,$enc,$RBD1,$BD2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnSSa
: InstSSa<0, (outs),
(ins imm64zx48:$enc, (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
(bdaddr12only $B2, $D2):$BD2),
".insn ss_a,$enc,$BDL1,$BD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnSSb
: InstSSb<0, (outs),
(ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
(bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
".insn ss_b,$enc,$BDL1,$BDL2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnSSc
: InstSSc<0, (outs),
(ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
(bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
".insn ss_c,$enc,$BDL1,$BD2,$I3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnSSd : InstSSd<0, (outs),
(ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ss_d,$enc,$RBD1,$BD2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnSSe
: InstSSe<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
AnyReg:$R3, (bdaddr12only $B4, $D4):$BD4),
".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnSSf : InstSSf<0, (outs),
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
(bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
".insn ss_f,$enc,$BD1,$BDL2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
-}
+ InsnDirectiveBase;
def InsnSSE : InstSSE<0, (outs),
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
(bdaddr12only $B2, $D2):$BD2),
".insn sse,$enc,$BD1,$BD2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-32} = enc{47-32};
-}
+ InsnDirectiveBase;
def InsnSSF : InstSSF<0, (outs),
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ssf,$enc,$BD1,$BD2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{35-32} = enc{35-32};
-}
+ InsnDirectiveBase;
// Alias for vri-e. Kept for backwards compatibility.
def InsnVRI : InstVRIe<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx12:$I3,
imm32zx4:$M4, imm32zx4:$M5),
".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIa
: InstVRIa<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, imm32xx16:$I2, imm32zx4:$M3),
".insn vri_a,$enc,$V1,$I2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIb : InstVRIb<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, imm32zx8:$I2,
imm32zx8:$I3, imm32zx4:$M4),
".insn vri_b,$enc,$V1,$I2,$I3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIc : InstVRIc<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
VR128:$V3, imm32zx4:$M4),
".insn vri_c,$enc,$V1,$I2,$V3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRId : InstVRId<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx8:$I4, imm32zx4:$M5),
".insn vri_d,$enc,$V1,$V2,$V3,$I4,$M5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIe : InstVRIe<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
".insn vri_e,$enc,$V1,$V2,$I3,$M4,$M5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIf : InstVRIf<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx8:$I4, imm32zx4:$M5),
".insn vri_f,$enc,$V1,$V2,$V3,$I4,$M5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIg : InstVRIg<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
imm32zx8:$I4, imm32zx4:$M5),
".insn vri_g,$enc,$V1,$V2,$I3,$I4,$M5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIh : InstVRIh<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
imm32zx4:$I3, imm32zx4:$M4),
".insn vri_h,$enc,$V1,$I2,$I3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIi : InstVRIi<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2,
imm32zx8:$I3, imm32zx4:$M4),
".insn vri_i,$enc,$V1,$R2,$I3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIj : InstVRIj<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
imm32zx4:$M4),
".insn vri_j,$enc,$V1,$V2,$I3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIk : InstVRIk<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
VR128:$V4, imm32zx8:$I5),
".insn vri_k,$enc,$V1,$V2,$V3,$V4,$I5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRIl
: InstVRIl<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
".insn vri_l,$enc,$V1,$V2,$I3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
// Alias for vrr-c. Kept for backwards compatibility.
def InsnVRR : InstVRRc<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRa : InstVRRa<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3,
imm32zx4:$M4, imm32zx4:$M5),
".insn vrr_a,$enc,$V1,$V2,$M3,$M4,$M5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRb : InstVRRb<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx4:$M4, imm32zx4:$M5),
".insn vrr_b,$enc,$V1,$V2,$V3,$M4,$M5", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRc : InstVRRc<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
".insn vrr_c,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRd : InstVRRd<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
".insn vrr_d,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRe : InstVRRe<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
".insn vrr_e,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRf : InstVRRf<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2, AnyReg:$R3),
".insn vrr_f,$enc,$V1,$R2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRg
: InstVRRg<0, (outs), (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
".insn vrr_g,$enc,$V1,$I2", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRh
: InstVRRh<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
".insn vrr_h,$enc,$V1,$V2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRi : InstVRRi<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, VR128:$V2,
imm32zx4:$M3, imm32zx4:$M4),
".insn vrr_i,$enc,$R1,$V2,$M3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRj : InstVRRj<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx4:$M4),
".insn vrr_j,$enc,$V1,$V2,$V3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRRk
: InstVRRk<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
".insn vrr_k,$enc,$V1,$V2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
// VRS - legacy operand order preserved
def InsnVRS : InstVRSc<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
(bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRSa
: InstVRSa<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
VR128:$V3, imm32zx4:$M4),
".insn vrs_a,$enc,$V1,$BD2,$V3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRSb
: InstVRSb<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
AnyReg:$R3, imm32zx4:$M4),
".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRSc
: InstVRSc<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
VR128:$V3, imm32zx4:$M4),
".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRSd : InstVRSd<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn vrs_d,$enc,$V1,$BD2,$R3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRV : InstVRV<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
(bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
".insn vrv,$enc,$V1,$VBD2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVRX : InstVRX<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
(bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
".insn vrx,$enc,$V1,$XBD2,$M3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
def InsnVSI : InstVSI<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
(bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
".insn vsi,$enc,$V1,$BD2,$I3", []>,
- InsnDirectiveBase {
- bits<48> enc;
- let Inst{47-40} = enc{47-40};
- let Inst{7-0} = enc{7-0};
-}
+ InsnDirectiveBase;
//===----------------------------------------------------------------------===//
// Peepholes.
>From a4f3cbd4d2983b61d7df5d127c986f2af0fca003 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Fri, 11 Sep 2026 14:35:40 +0200
Subject: [PATCH 07/11] Replace Marker Class with Marker Bit
assisted-by IBM Bob
---
.../lib/Target/SystemZ/SystemZInstrFormats.td | 16 +-
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 852 ++++++++----------
.../TableGen/SystemZInsnDirectiveEmitter.cpp | 7 +-
3 files changed, 385 insertions(+), 490 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 2c5f6e753499d..df32a7c345dbb 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -99,6 +99,10 @@ class InstSystemZ<int size, dag outs, dag ins, string asmstr,
// result against zero, but only if the 'nsw' flag is set.
bit CCIfNoSignedWrap = 0;
+ // Indicates that the instruction is a helper for an .insn directive
+ // instead of an actual instruction
+ bit IsInsnDirective = 0;
+
let TSFlags{0} = SimpleBDXLoad;
let TSFlags{1} = SimpleBDXStore;
let TSFlags{2} = Has20BitOffset;
@@ -1834,18 +1838,6 @@ class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
}
-//===----------------------------------------------------------------------===//
-// Base class for all .insn directive instructions
-//===----------------------------------------------------------------------===//
-// This marker class is used to identify .insn directive instructions
-// for the SystemZInsnDirectiveEmitter. It must be the rightmost parent
-// in the inheritance list to ensure these properties take precedence over
-// the ones set by the InstFoo base classes.
-class InsnDirectiveBase {
- bit isCodeGenOnly = 1;
- bit hasSideEffects = 1;
-}
-
//===----------------------------------------------------------------------===//
// Variants of instructions with condition mask
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index d19691481440e..f9b17965d5d36 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2274,495 +2274,397 @@ let hasSideEffects = 1 in {
//===----------------------------------------------------------------------===//
// .insn directive instructions
//===----------------------------------------------------------------------===//
-
-def InsnE : InstE<0, (outs), (ins imm64zx16:$enc), ".insn e,$enc", []>,
- InsnDirectiveBase;
-def InsnI : InstI<0, (outs), (ins imm64zx16:$enc, imm32zx8:$I1),
- ".insn i,$enc,$I1", []>,
- InsnDirectiveBase;
-def InsnIE : InstIE<0, (outs), (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
- ".insn ie,$enc,$I1,$I2", []>,
- InsnDirectiveBase;
-def InsnMII : InstMII<0, (outs),
- (ins imm64zx48:$enc, imm32zx4:$M1, brtarget12bpp:$RI2,
- brtarget24bpp:$RI3),
- ".insn mii,$enc,$M1,$RI2,$RI3", []>,
- InsnDirectiveBase;
-def InsnRI : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
- ".insn ri,$enc,$R1,$I2", []>,
- InsnDirectiveBase;
-def InsnRIa
- : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
- ".insn ri_a,$enc,$R1,$I2", []>,
- InsnDirectiveBase;
-def InsnRIb
- : InstRIb<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
- ".insn ri_b,$enc,$R1,$RI2", []>,
- InsnDirectiveBase;
-def InsnRIc
- : InstRIc<0, (outs), (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
- ".insn ri_c,$enc,$M1,$RI2", []>,
- InsnDirectiveBase;
-// RIE base format - legacy operand order preserved
-def InsnRIE
- : InstRIEd<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$I2),
- ".insn rie,$enc,$R1,$R3,$I2", []>,
- InsnDirectiveBase;
-def InsnRIEa
- : InstRIEa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32xx16:$I2, imm32zx4:$M3),
- ".insn rie_a,$enc,$R1,$I2,$M3", []>,
- InsnDirectiveBase;
-def InsnRIEb : InstRIEb<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx4:$M3, brtarget16:$RI4),
- ".insn rie_b,$enc,$R1,$R2,$M3,$RI4", []>,
- InsnDirectiveBase;
-def InsnRIEc : InstRIEc<0, (outs),
+let isCodeGenOnly = 1, hasSideEffects = 1, IsInsnDirective = 1 in {
+ def InsnE : InstE<0, (outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
+ def InsnI : InstI<0, (outs), (ins imm64zx16:$enc, imm32zx8:$I1),
+ ".insn i,$enc,$I1", []>;
+ def InsnIE : InstIE<0, (outs), (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
+ ".insn ie,$enc,$I1,$I2", []>;
+ def InsnMII : InstMII<0, (outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1, brtarget12bpp:$RI2,
+ brtarget24bpp:$RI3),
+ ".insn mii,$enc,$M1,$RI2,$RI3", []>;
+ def InsnRI : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
+ ".insn ri,$enc,$R1,$I2", []>;
+ def InsnRIa
+ : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
+ ".insn ri_a,$enc,$R1,$I2", []>;
+ def InsnRIb
+ : InstRIb<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
+ ".insn ri_b,$enc,$R1,$RI2", []>;
+ def InsnRIc
+ : InstRIc<0, (outs), (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
+ ".insn ri_c,$enc,$M1,$RI2", []>;
+ // RIE base format - legacy operand order preserved
+ def InsnRIE
+ : InstRIEd<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$I2),
+ ".insn rie,$enc,$R1,$R3,$I2", []>;
+ def InsnRIEa
+ : InstRIEa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx16:$I2, imm32zx4:$M3),
+ ".insn rie_a,$enc,$R1,$I2,$M3", []>;
+ def InsnRIEb : InstRIEb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx4:$M3, brtarget16:$RI4),
+ ".insn rie_b,$enc,$R1,$R2,$M3,$RI4", []>;
+ def InsnRIEc : InstRIEc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
+ imm32zx4:$M3, brtarget16:$RI4),
+ ".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>;
+ def InsnRIEd
+ : InstRIEd<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
+ ".insn rie_d,$enc,$R1,$I2,$R3", []>;
+ def InsnRIEe
+ : InstRIEe<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, brtarget16:$RI2, AnyReg:$R3),
+ ".insn rie_e,$enc,$R1,$RI2,$R3", []>;
+ def InsnRIEf : InstRIEf<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
+ ".insn rie_f,$enc,$R1,$R2,$I3,$I4,$I5", []>;
+ def InsnRIEg
+ : InstRIEg<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, imm32zx4:$M3),
+ ".insn rie_g,$enc,$R1,$I2,$M3", []>;
+ def InsnRIL
+ : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
+ ".insn ril,$enc,$R1,$I2", []>;
+ def InsnRILa
+ : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
+ ".insn ril_a,$enc,$R1,$I2", []>;
+ def InsnRILb
+ : InstRILb<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
+ ".insn ril_b,$enc,$R1,$RI2", []>;
+ def InsnRILc
+ : InstRILc<0, (outs), (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
+ ".insn ril_c,$enc,$M1,$RI2", []>;
+ def InsnRILU : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
+ ".insn rilu,$enc,$R1,$I2", []>;
+ def InsnRIS : InstRIS<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
- imm32zx4:$M3, brtarget16:$RI4),
- ".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>,
- InsnDirectiveBase;
-def InsnRIEd
- : InstRIEd<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
- ".insn rie_d,$enc,$R1,$I2,$R3", []>,
- InsnDirectiveBase;
-def InsnRIEe
- : InstRIEe<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, brtarget16:$RI2, AnyReg:$R3),
- ".insn rie_e,$enc,$R1,$RI2,$R3", []>,
- InsnDirectiveBase;
-def InsnRIEf : InstRIEf<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
- ".insn rie_f,$enc,$R1,$R2,$I3,$I4,$I5", []>,
- InsnDirectiveBase;
-def InsnRIEg
- : InstRIEg<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, imm32zx4:$M3),
- ".insn rie_g,$enc,$R1,$I2,$M3", []>,
- InsnDirectiveBase;
-def InsnRIL
- : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
- ".insn ril,$enc,$R1,$I2", []>,
- InsnDirectiveBase;
-def InsnRILa
- : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
- ".insn ril_a,$enc,$R1,$I2", []>,
- InsnDirectiveBase;
-def InsnRILb
- : InstRILb<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
- ".insn ril_b,$enc,$R1,$RI2", []>,
- InsnDirectiveBase;
-def InsnRILc
- : InstRILc<0, (outs), (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
- ".insn ril_c,$enc,$M1,$RI2", []>,
- InsnDirectiveBase;
-def InsnRILU : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
- ".insn rilu,$enc,$R1,$I2", []>,
- InsnDirectiveBase;
-def InsnRIS : InstRIS<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
- imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
- ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>,
- InsnDirectiveBase;
-def InsnRR : InstRR<0, (outs), (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
- ".insn rr,$enc,$R1,$R2", []>,
- InsnDirectiveBase;
-def InsnRRD : InstRRD<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3),
- ".insn rrd,$enc,$R1,$R2,$R3", []>,
- InsnDirectiveBase;
-def InsnRRE : InstRRE<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2),
- ".insn rre,$enc,$R1,$R2", []>,
- InsnDirectiveBase;
-// Alias for rrf-a. Kept for backwards compatibility.
-def InsnRRF : InstRRFa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
- imm32zx4:$M4),
- ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>,
- InsnDirectiveBase;
-def InsnRRFa : InstRRFa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
- imm32zx4:$M4),
- ".insn rrf_a,$enc,$R1,$R2,$R3,$M4", []>,
- InsnDirectiveBase;
-def InsnRRFb : InstRRFb<0, (outs),
+ imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
+ ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
+ def InsnRR : InstRR<0, (outs), (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
+ ".insn rr,$enc,$R1,$R2", []>;
+ def InsnRRD : InstRRD<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3),
+ ".insn rrd,$enc,$R1,$R2,$R3", []>;
+ def InsnRRE : InstRRE<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2),
+ ".insn rre,$enc,$R1,$R2", []>;
+ // Alias for rrf-a. Kept for backwards compatibility.
+ def InsnRRF : InstRRFa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
imm32zx4:$M4),
- ".insn rrf_b,$enc,$R1,$R2,$R3,$M4", []>,
- InsnDirectiveBase;
-def InsnRRFc
- : InstRRFc<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
- ".insn rrf_c,$enc,$R1,$R2,$M3", []>,
- InsnDirectiveBase;
-def InsnRRFd
- : InstRRFd<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
- ".insn rrf_d,$enc,$R1,$R2,$M4", []>,
- InsnDirectiveBase;
-def InsnRRFe : InstRRFe<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx4:$M3, imm32zx4:$M4),
- ".insn rrf_e,$enc,$R1,$R2,$M3,$M4", []>,
- InsnDirectiveBase;
-def InsnRRS : InstRRS<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3,
- (bdaddr12only $B4, $D4):$BD4),
- ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>,
- InsnDirectiveBase;
-// RS - legacy operand order preserved
-def InsnRS : InstRSa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn rs,$enc,$R1,$R3,$BD2", []>,
- InsnDirectiveBase;
-def InsnRSa : InstRSa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn rs_a,$enc,$R1,$BD2,$R3", []>,
- InsnDirectiveBase;
-def InsnRSb : InstRSb<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
- ".insn rs_b,$enc,$R1,$BD2,$M3", []>,
- InsnDirectiveBase;
-// RSE - legacy operand order preserved
-def InsnRSE : InstRSEa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn rse,$enc,$R1,$R3,$BD2", []>,
- InsnDirectiveBase;
-// RSI - legacy operand order preserved
-def InsnRSI
- : InstRSI<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
- ".insn rsi,$enc,$R1,$R3,$RI2", []>,
- InsnDirectiveBase;
-def InsnRSLa
- : InstRSLa<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
- ".insn rsl_a,$enc,$BDL1", []>,
- InsnDirectiveBase;
-def InsnRSLb
- : InstRSLb<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
- ".insn rsl_b,$enc,$R1,$BDL2,$M3", []>,
- InsnDirectiveBase;
-// RSY - legacy operand order preserved
-def InsnRSY : InstRSYa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr20only $B2, $D2):$BD2),
- ".insn rsy,$enc,$R1,$R3,$BD2", []>,
- InsnDirectiveBase;
-def InsnRSYa : InstRSYa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn rsy_a,$enc,$R1,$BD2,$R3", []>,
- InsnDirectiveBase;
-def InsnRSYb : InstRSYb<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
- ".insn rsy_b,$enc,$R1,$BD2,$M3", []>,
- InsnDirectiveBase;
-// Alias for rx-a. Kept for backwards compatibility.
-def InsnRX : InstRXa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase;
-def InsnRXa : InstRXa<0, (outs),
+ ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
+ def InsnRRFa : InstRRFa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
+ imm32zx4:$M4),
+ ".insn rrf_a,$enc,$R1,$R2,$R3,$M4", []>;
+ def InsnRRFb : InstRRFb<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
+ imm32zx4:$M4),
+ ".insn rrf_b,$enc,$R1,$R2,$R3,$M4", []>;
+ def InsnRRFc
+ : InstRRFc<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
+ ".insn rrf_c,$enc,$R1,$R2,$M3", []>;
+ def InsnRRFd
+ : InstRRFd<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
+ ".insn rrf_d,$enc,$R1,$R2,$M4", []>;
+ def InsnRRFe : InstRRFe<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
+ imm32zx4:$M3, imm32zx4:$M4),
+ ".insn rrf_e,$enc,$R1,$R2,$M3,$M4", []>;
+ def InsnRRS : InstRRS<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3,
+ (bdaddr12only $B4, $D4):$BD4),
+ ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
+ // RS - legacy operand order preserved
+ def InsnRS : InstRSa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn rs,$enc,$R1,$R3,$BD2", []>;
+ def InsnRSa : InstRSa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn rs_a,$enc,$R1,$BD2,$R3", []>;
+ def InsnRSb : InstRSb<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
+ ".insn rs_b,$enc,$R1,$BD2,$M3", []>;
+ // RSE - legacy operand order preserved
+ def InsnRSE : InstRSEa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn rse,$enc,$R1,$R3,$BD2", []>;
+ // RSI - legacy operand order preserved
+ def InsnRSI
+ : InstRSI<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
+ ".insn rsi,$enc,$R1,$R3,$RI2", []>;
+ def InsnRSLa
+ : InstRSLa<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
+ ".insn rsl_a,$enc,$BDL1", []>;
+ def InsnRSLb
+ : InstRSLb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
+ ".insn rsl_b,$enc,$R1,$BDL2,$M3", []>;
+ // RSY - legacy operand order preserved
+ def InsnRSY : InstRSYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr20only $B2, $D2):$BD2),
+ ".insn rsy,$enc,$R1,$R3,$BD2", []>;
+ def InsnRSYa : InstRSYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn rsy_a,$enc,$R1,$BD2,$R3", []>;
+ def InsnRSYb : InstRSYb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
+ ".insn rsy_b,$enc,$R1,$BD2,$M3", []>;
+ // Alias for rx-a. Kept for backwards compatibility.
+ def InsnRX : InstRXa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
(bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx_a,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase;
-def InsnRXb : InstRXb<0, (outs),
- (ins imm64zx32:$enc, imm32zx4:$M1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx_b,$enc,$M1,$XBD2", []>,
- InsnDirectiveBase;
-def InsnRXE : InstRXE<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxe,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase {
- let M3 = 0;
-}
-// RXF - legacy operand order preserved
-def InsnRXF : InstRXF<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxf,$enc,$R1,$R3,$XBD2", []>,
- InsnDirectiveBase;
-
-def InsnRXY : InstRXYa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase;
-def InsnRXYa : InstRXYa<0, (outs),
+ ".insn rx,$enc,$R1,$XBD2", []>;
+ def InsnRXa : InstRXa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx_a,$enc,$R1,$XBD2", []>;
+ def InsnRXb : InstRXb<0, (outs),
+ (ins imm64zx32:$enc, imm32zx4:$M1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx_b,$enc,$M1,$XBD2", []>;
+ def InsnRXE : InstRXE<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy_a,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase;
-def InsnRXYb : InstRXYb<0, (outs),
- (ins imm64zx48:$enc, imm32zx4:$M1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy_b,$enc,$M1,$XBD2", []>,
- InsnDirectiveBase;
-// There is no InstRXYc - it is identical to InstRXYa.
-def InsnRXYc : InstRXYa<0, (outs),
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rxe,$enc,$R1,$XBD2", []> {
+ let M3 = 0;
+ }
+ // RXF - legacy operand order preserved
+ def InsnRXF : InstRXF<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
+
+ def InsnRXY : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy_c,$enc,$R1,$XBD2", []>,
- InsnDirectiveBase;
-def InsnS : InstS<0, (outs), (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
- ".insn s,$enc,$BD2", []>,
- InsnDirectiveBase;
-def InsnSI
- : InstSI<0, (outs),
- (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
- ".insn si,$enc,$BD1,$I2", []>,
- InsnDirectiveBase;
-def InsnSIY
- : InstSIY<0, (outs),
- (ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1, imm32xx8:$I2),
- ".insn siy,$enc,$BD1,$I2", []>,
- InsnDirectiveBase;
-def InsnSIL
- : InstSIL<0, (outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx16:$I2),
- ".insn sil,$enc,$BD1,$I2", []>,
- InsnDirectiveBase;
-def InsnSMI : InstSMI<0, (outs),
- (ins imm64zx48:$enc, imm32zx4:$M1, brtarget16bpp:$RI2,
- (bdaddr12only $B3, $D3):$BD3),
- ".insn smi,$enc,$M1,$RI2,$BD3", []>,
- InsnDirectiveBase;
-// Alias for ss-. Kept for backwards compatibility.
-def InsnSS : InstSSd<0, (outs),
- (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ss,$enc,$RBD1,$BD2,$R3", []>,
- InsnDirectiveBase;
-def InsnSSa
- : InstSSa<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn ss_a,$enc,$BDL1,$BD2", []>,
- InsnDirectiveBase;
-def InsnSSb
- : InstSSb<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
- (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
- ".insn ss_b,$enc,$BDL1,$BDL2", []>,
- InsnDirectiveBase;
-def InsnSSc
- : InstSSc<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
- ".insn ss_c,$enc,$BDL1,$BD2,$I3", []>,
- InsnDirectiveBase;
-def InsnSSd : InstSSd<0, (outs),
+ ".insn rxy,$enc,$R1,$XBD2", []>;
+ def InsnRXYa : InstRXYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_a,$enc,$R1,$XBD2", []>;
+ def InsnRXYb : InstRXYb<0, (outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_b,$enc,$M1,$XBD2", []>;
+ // There is no InstRXYc - it is identical to InstRXYa.
+ def InsnRXYc : InstRXYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy_c,$enc,$R1,$XBD2", []>;
+ def InsnS : InstS<0, (outs), (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
+ ".insn s,$enc,$BD2", []>;
+ def InsnSI
+ : InstSI<0, (outs),
+ (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
+ ".insn si,$enc,$BD1,$I2", []>;
+ def InsnSIY
+ : InstSIY<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1, imm32xx8:$I2),
+ ".insn siy,$enc,$BD1,$I2", []>;
+ def InsnSIL
+ : InstSIL<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx16:$I2),
+ ".insn sil,$enc,$BD1,$I2", []>;
+ def InsnSMI : InstSMI<0, (outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1, brtarget16bpp:$RI2,
+ (bdaddr12only $B3, $D3):$BD3),
+ ".insn smi,$enc,$M1,$RI2,$BD3", []>;
+ // Alias for ss-. Kept for backwards compatibility.
+ def InsnSS : InstSSd<0, (outs),
(ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
(bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ss_d,$enc,$RBD1,$BD2,$R3", []>,
- InsnDirectiveBase;
-def InsnSSe
- : InstSSe<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
- AnyReg:$R3, (bdaddr12only $B4, $D4):$BD4),
- ".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>,
- InsnDirectiveBase;
-def InsnSSf : InstSSf<0, (outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
- ".insn ss_f,$enc,$BD1,$BDL2", []>,
- InsnDirectiveBase;
-def InsnSSE : InstSSE<0, (outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn sse,$enc,$BD1,$BD2", []>,
- InsnDirectiveBase;
-def InsnSSF : InstSSF<0, (outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ssf,$enc,$BD1,$BD2,$R3", []>,
- InsnDirectiveBase;
-// Alias for vri-e. Kept for backwards compatibility.
-def InsnVRI : InstVRIe<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx12:$I3,
- imm32zx4:$M4, imm32zx4:$M5),
- ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>,
- InsnDirectiveBase;
-def InsnVRIa
- : InstVRIa<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32xx16:$I2, imm32zx4:$M3),
- ".insn vri_a,$enc,$V1,$I2,$M3", []>,
- InsnDirectiveBase;
-def InsnVRIb : InstVRIb<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32zx8:$I2,
- imm32zx8:$I3, imm32zx4:$M4),
- ".insn vri_b,$enc,$V1,$I2,$I3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRIc : InstVRIc<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
- VR128:$V3, imm32zx4:$M4),
- ".insn vri_c,$enc,$V1,$I2,$V3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRId : InstVRId<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx8:$I4, imm32zx4:$M5),
- ".insn vri_d,$enc,$V1,$V2,$V3,$I4,$M5", []>,
- InsnDirectiveBase;
-def InsnVRIe : InstVRIe<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
- ".insn vri_e,$enc,$V1,$V2,$I3,$M4,$M5", []>,
- InsnDirectiveBase;
-def InsnVRIf : InstVRIf<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx8:$I4, imm32zx4:$M5),
- ".insn vri_f,$enc,$V1,$V2,$V3,$I4,$M5", []>,
- InsnDirectiveBase;
-def InsnVRIg : InstVRIg<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
- imm32zx8:$I4, imm32zx4:$M5),
- ".insn vri_g,$enc,$V1,$V2,$I3,$I4,$M5", []>,
- InsnDirectiveBase;
-def InsnVRIh : InstVRIh<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
- imm32zx4:$I3, imm32zx4:$M4),
- ".insn vri_h,$enc,$V1,$I2,$I3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRIi : InstVRIi<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2,
- imm32zx8:$I3, imm32zx4:$M4),
- ".insn vri_i,$enc,$V1,$R2,$I3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRIj : InstVRIj<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
- imm32zx4:$M4),
- ".insn vri_j,$enc,$V1,$V2,$I3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRIk : InstVRIk<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx8:$I5),
- ".insn vri_k,$enc,$V1,$V2,$V3,$V4,$I5", []>,
- InsnDirectiveBase;
-def InsnVRIl
- : InstVRIl<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
- ".insn vri_l,$enc,$V1,$V2,$I3", []>,
- InsnDirectiveBase;
-// Alias for vrr-c. Kept for backwards compatibility.
-def InsnVRR : InstVRRc<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>,
- InsnDirectiveBase;
-def InsnVRRa : InstVRRa<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3,
- imm32zx4:$M4, imm32zx4:$M5),
- ".insn vrr_a,$enc,$V1,$V2,$M3,$M4,$M5", []>,
- InsnDirectiveBase;
-def InsnVRRb : InstVRRb<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
+ def InsnSSa
+ : InstSSa<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn ss_a,$enc,$BDL1,$BD2", []>;
+ def InsnSSb
+ : InstSSb<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
+ ".insn ss_b,$enc,$BDL1,$BDL2", []>;
+ def InsnSSc
+ : InstSSc<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
+ ".insn ss_c,$enc,$BDL1,$BD2,$I3", []>;
+ def InsnSSd : InstSSd<0, (outs),
+ (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn ss_d,$enc,$RBD1,$BD2,$R3", []>;
+ def InsnSSe
+ : InstSSe<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
+ AnyReg:$R3, (bdaddr12only $B4, $D4):$BD4),
+ ".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>;
+ def InsnSSf : InstSSf<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
+ ".insn ss_f,$enc,$BD1,$BDL2", []>;
+ def InsnSSE : InstSSE<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn sse,$enc,$BD1,$BD2", []>;
+ def InsnSSF : InstSSF<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn ssf,$enc,$BD1,$BD2,$R3", []>;
+ // Alias for vri-e. Kept for backwards compatibility.
+ def InsnVRI : InstVRIe<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx12:$I3,
imm32zx4:$M4, imm32zx4:$M5),
- ".insn vrr_b,$enc,$V1,$V2,$V3,$M4,$M5", []>,
- InsnDirectiveBase;
-def InsnVRRc : InstVRRc<0, (outs),
+ ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
+ def InsnVRIa
+ : InstVRIa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32xx16:$I2, imm32zx4:$M3),
+ ".insn vri_a,$enc,$V1,$I2,$M3", []>;
+ def InsnVRIb : InstVRIb<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx8:$I2,
+ imm32zx8:$I3, imm32zx4:$M4),
+ ".insn vri_b,$enc,$V1,$I2,$I3,$M4", []>;
+ def InsnVRIc : InstVRIc<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vri_c,$enc,$V1,$I2,$V3,$M4", []>;
+ def InsnVRId : InstVRId<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_d,$enc,$V1,$V2,$V3,$I4,$M5", []>;
+ def InsnVRIe : InstVRIe<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
+ imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vri_e,$enc,$V1,$V2,$I3,$M4,$M5", []>;
+ def InsnVRIf : InstVRIf<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_f,$enc,$V1,$V2,$V3,$I4,$M5", []>;
+ def InsnVRIg : InstVRIg<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
+ imm32zx8:$I4, imm32zx4:$M5),
+ ".insn vri_g,$enc,$V1,$V2,$I3,$I4,$M5", []>;
+ def InsnVRIh : InstVRIh<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
+ imm32zx4:$I3, imm32zx4:$M4),
+ ".insn vri_h,$enc,$V1,$I2,$I3,$M4", []>;
+ def InsnVRIi : InstVRIi<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2,
+ imm32zx8:$I3, imm32zx4:$M4),
+ ".insn vri_i,$enc,$V1,$R2,$I3,$M4", []>;
+ def InsnVRIj : InstVRIj<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
+ imm32zx4:$M4),
+ ".insn vri_j,$enc,$V1,$V2,$I3,$M4", []>;
+ def InsnVRIk : InstVRIk<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx8:$I5),
+ ".insn vri_k,$enc,$V1,$V2,$V3,$V4,$I5", []>;
+ def InsnVRIl
+ : InstVRIl<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
+ ".insn vri_l,$enc,$V1,$V2,$I3", []>;
+ // Alias for vrr-c. Kept for backwards compatibility.
+ def InsnVRR : InstVRRc<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr_c,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>,
- InsnDirectiveBase;
-def InsnVRRd : InstVRRd<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr_d,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>,
- InsnDirectiveBase;
-def InsnVRRe : InstVRRe<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr_e,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>,
- InsnDirectiveBase;
-def InsnVRRf : InstVRRf<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2, AnyReg:$R3),
- ".insn vrr_f,$enc,$V1,$R2,$R3", []>,
- InsnDirectiveBase;
-def InsnVRRg
- : InstVRRg<0, (outs), (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
- ".insn vrr_g,$enc,$V1,$I2", []>,
- InsnDirectiveBase;
-def InsnVRRh
- : InstVRRh<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
- ".insn vrr_h,$enc,$V1,$V2,$M3", []>,
- InsnDirectiveBase;
-def InsnVRRi : InstVRRi<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V2,
- imm32zx4:$M3, imm32zx4:$M4),
- ".insn vrr_i,$enc,$R1,$V2,$M3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRRj : InstVRRj<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4),
- ".insn vrr_j,$enc,$V1,$V2,$V3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRRk
- : InstVRRk<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
- ".insn vrr_k,$enc,$V1,$V2,$M3", []>,
- InsnDirectiveBase;
-// VRS - legacy operand order preserved
-def InsnVRS : InstVRSc<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
- ".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>,
- InsnDirectiveBase;
-def InsnVRSa
- : InstVRSa<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
- VR128:$V3, imm32zx4:$M4),
- ".insn vrs_a,$enc,$V1,$BD2,$V3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRSb
- : InstVRSb<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
- AnyReg:$R3, imm32zx4:$M4),
- ".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRSc
- : InstVRSc<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
- VR128:$V3, imm32zx4:$M4),
- ".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>,
- InsnDirectiveBase;
-def InsnVRSd : InstVRSd<0, (outs),
+ ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
+ def InsnVRRa : InstVRRa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3,
+ imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vrr_a,$enc,$V1,$V2,$M3,$M4,$M5", []>;
+ def InsnVRRb : InstVRRb<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vrr_b,$enc,$V1,$V2,$V3,$M4,$M5", []>;
+ def InsnVRRc : InstVRRc<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_c,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
+ def InsnVRRd : InstVRRd<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_d,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
+ def InsnVRRe : InstVRRe<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr_e,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
+ def InsnVRRf : InstVRRf<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2, AnyReg:$R3),
+ ".insn vrr_f,$enc,$V1,$R2,$R3", []>;
+ def InsnVRRg
+ : InstVRRg<0, (outs), (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
+ ".insn vrr_g,$enc,$V1,$I2", []>;
+ def InsnVRRh
+ : InstVRRh<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_h,$enc,$V1,$V2,$M3", []>;
+ def InsnVRRi : InstVRRi<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V2,
+ imm32zx4:$M3, imm32zx4:$M4),
+ ".insn vrr_i,$enc,$R1,$V2,$M3,$M4", []>;
+ def InsnVRRj : InstVRRj<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4),
+ ".insn vrr_j,$enc,$V1,$V2,$V3,$M4", []>;
+ def InsnVRRk
+ : InstVRRk<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_k,$enc,$V1,$V2,$M3", []>;
+ // VRS - legacy operand order preserved
+ def InsnVRS : InstVRSc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
+ ".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>;
+ def InsnVRSa
+ : InstVRSa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vrs_a,$enc,$V1,$BD2,$V3,$M4", []>;
+ def InsnVRSb
+ : InstVRSb<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
+ AnyReg:$R3, imm32zx4:$M4),
+ ".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>;
+ def InsnVRSc
+ : InstVRSc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>;
+ def InsnVRSd : InstVRSd<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn vrs_d,$enc,$V1,$BD2,$R3", []>;
+ def InsnVRV : InstVRV<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn vrs_d,$enc,$V1,$BD2,$R3", []>,
- InsnDirectiveBase;
-def InsnVRV : InstVRV<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
- ".insn vrv,$enc,$V1,$VBD2,$M3", []>,
- InsnDirectiveBase;
-def InsnVRX : InstVRX<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
- ".insn vrx,$enc,$V1,$XBD2,$M3", []>,
- InsnDirectiveBase;
-def InsnVSI : InstVSI<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
- ".insn vsi,$enc,$V1,$BD2,$I3", []>,
- InsnDirectiveBase;
-
+ (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
+ ".insn vrv,$enc,$V1,$VBD2,$M3", []>;
+ def InsnVRX : InstVRX<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
+ ".insn vrx,$enc,$V1,$XBD2,$M3", []>;
+ def InsnVSI : InstVSI<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
+ ".insn vsi,$enc,$V1,$BD2,$I3", []>;
+}
//===----------------------------------------------------------------------===//
// Peepholes.
//===----------------------------------------------------------------------===//
diff --git a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
index 22aef8325e2bb..9238f4b9759ec 100644
--- a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
@@ -84,9 +84,10 @@ static void emitInsnDirectiveMatchTable(const RecordKeeper &RK,
OS);
// This will hold all .insn directive definitions (~100 plus margin).
SmallVector<InsnMatchEntry, 128> Entries;
- // All .insn directive instructions inherit from InsnDirectiveBase.
- for (const Record *Def : RK.getAllDerivedDefinitions("InsnDirectiveBase"))
- Entries.push_back(buildInsnMatchEntry(*Def));
+ // Collect all InstSystemZ records that have IsInsnDirective set to 1.
+ for (const Record *Def : RK.getAllDerivedDefinitions("InstSystemZ"))
+ if (Def->getValueAsBit("IsInsnDirective"))
+ Entries.push_back(buildInsnMatchEntry(*Def));
llvm::sort(Entries, [](const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
return LHS.Format < RHS.Format;
>From 16c9d9ec1fd20ccd9097491b16f1c9e20f481290 Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Fri, 11 Sep 2026 14:37:35 +0200
Subject: [PATCH 08/11] Revert unintended whitespace change
---
llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index bb0a409f2e71e..893efded1c8e7 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -1267,6 +1267,7 @@ bool SystemZAsmParser::parseDirectiveInsn(SMLoc L) {
// Expect immediate expression.
if (Parser.parseExpression(Expr))
return Error(StartLoc, "unexpected token in directive");
+
SMLoc EndLoc =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
>From 3a6212607c3b3bcc2d786927f9bbf8a98dd65adc Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Mon, 14 Sep 2026 11:26:30 +0200
Subject: [PATCH 09/11] Incorporate Review comments
- improved ParserMatchClass name fetching
- cleaned up and standardized formatting in SystemZInstrInfo.td
and SystemZInstrFormats.td
- consolidated legacy instruction formats in their own section
- Renamed InstRSEa to InstRSE
- Made M3 parm to InsnRXE settable
---
.../lib/Target/SystemZ/SystemZInstrFormats.td | 9 +-
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 459 +++++++++---------
llvm/lib/Target/SystemZ/SystemZOperands.td | 2 +-
llvm/test/MC/SystemZ/directive-insn-z14.s | 2 +-
llvm/test/MC/SystemZ/directive-insn.s | 2 +-
.../TableGen/SystemZInsnDirectiveEmitter.cpp | 7 +-
6 files changed, 230 insertions(+), 251 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index df32a7c345dbb..608f215bc94ce 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -193,6 +193,7 @@ class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
bits<16> enc;
+
let Inst = !if(!ne(op, 0), op, enc);
}
@@ -200,6 +201,7 @@ class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
bits<16> enc;
+
bits<8> I1;
let Inst{15-8} = !if(!ne(op, 0), op, enc{15-8});
@@ -210,6 +212,7 @@ class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
bits<32> enc;
+
bits<4> I1;
bits<4> I2;
@@ -223,6 +226,7 @@ class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
bits<48> enc;
+
bits<4> M1;
bits<12> RI2;
bits<24> RI3;
@@ -237,6 +241,7 @@ class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
bits<32> enc;
+
bits<4> R1;
bits<16> I2;
@@ -250,6 +255,7 @@ class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
bits<32> enc;
+
bits<4> R1;
bits<16> RI2;
@@ -263,6 +269,7 @@ class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
bits<32> enc;
+
bits<4> M1;
bits<16> RI2;
@@ -784,7 +791,7 @@ class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11-0} = D2;
}
-class InstRSEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+class InstRSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
bits<48> enc;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index f9b17965d5d36..fe1cab4c314be 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2275,396 +2275,371 @@ let hasSideEffects = 1 in {
// .insn directive instructions
//===----------------------------------------------------------------------===//
let isCodeGenOnly = 1, hasSideEffects = 1, IsInsnDirective = 1 in {
- def InsnE : InstE<0, (outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
- def InsnI : InstI<0, (outs), (ins imm64zx16:$enc, imm32zx8:$I1),
+ def InsnE : InstE<0, (outs),
+ (ins imm64zx16:$enc), ".insn e,$enc", []>;
+ def InsnI : InstI<0, (outs),
+ (ins imm64zx16:$enc, imm32zx8:$I1),
".insn i,$enc,$I1", []>;
- def InsnIE : InstIE<0, (outs), (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
+ def InsnIE : InstIE<0, (outs),
+ (ins imm64zx32:$enc, imm32zx4:$I1, imm32zx4:$I2),
".insn ie,$enc,$I1,$I2", []>;
def InsnMII : InstMII<0, (outs),
(ins imm64zx48:$enc, imm32zx4:$M1, brtarget12bpp:$RI2,
- brtarget24bpp:$RI3),
+ brtarget24bpp:$RI3),
".insn mii,$enc,$M1,$RI2,$RI3", []>;
- def InsnRI : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
- ".insn ri,$enc,$R1,$I2", []>;
- def InsnRIa
- : InstRIa<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
+ def InsnRI : InstRIa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, imm32sx16:$I2),
+ ".insn ri,$enc,$R1,$I2", []>;
+ def InsnRIa : InstRIa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, imm32xx16:$I2),
".insn ri_a,$enc,$R1,$I2", []>;
- def InsnRIb
- : InstRIb<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
- ".insn ri_b,$enc,$R1,$RI2", []>;
- def InsnRIc
- : InstRIc<0, (outs), (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
- ".insn ri_c,$enc,$M1,$RI2", []>;
- // RIE base format - legacy operand order preserved
- def InsnRIE
- : InstRIEd<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$I2),
- ".insn rie,$enc,$R1,$R3,$I2", []>;
- def InsnRIEa
- : InstRIEa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32xx16:$I2, imm32zx4:$M3),
- ".insn rie_a,$enc,$R1,$I2,$M3", []>;
+ def InsnRIb : InstRIb<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, brtarget16:$RI2),
+ ".insn ri_b,$enc,$R1,$RI2", []>;
+ def InsnRIc : InstRIc<0, (outs),
+ (ins imm64zx32:$enc, imm32zx4:$M1, brtarget16:$RI2),
+ ".insn ri_c,$enc,$M1,$RI2", []>;
+ def InsnRIEa : InstRIEa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32xx16:$I2, imm32zx4:$M3),
+ ".insn rie_a,$enc,$R1,$I2,$M3", []>;
def InsnRIEb : InstRIEb<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx4:$M3, brtarget16:$RI4),
+ imm32zx4:$M3, brtarget16:$RI4),
".insn rie_b,$enc,$R1,$R2,$M3,$RI4", []>;
def InsnRIEc : InstRIEc<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
- imm32zx4:$M3, brtarget16:$RI4),
- ".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>;
- def InsnRIEd
- : InstRIEd<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
- ".insn rie_d,$enc,$R1,$I2,$R3", []>;
- def InsnRIEe
- : InstRIEe<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, brtarget16:$RI2, AnyReg:$R3),
- ".insn rie_e,$enc,$R1,$RI2,$R3", []>;
+ imm32zx4:$M3, brtarget16:$RI4),
+ ".insn rie_c,$enc,$R1,$I2,$M3,$RI4", []>;
+ def InsnRIEd : InstRIEd<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, AnyReg:$R3),
+ ".insn rie_d,$enc,$R1,$I2,$R3", []>;
+ def InsnRIEe : InstRIEe<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, brtarget16:$RI2, AnyReg:$R3),
+ ".insn rie_e,$enc,$R1,$RI2,$R3", []>;
def InsnRIEf : InstRIEf<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
+ imm32zx8:$I3, imm32zx8:$I4, imm32zx8:$I5),
".insn rie_f,$enc,$R1,$R2,$I3,$I4,$I5", []>;
- def InsnRIEg
- : InstRIEg<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, imm32zx4:$M3),
- ".insn rie_g,$enc,$R1,$I2,$M3", []>;
- def InsnRIL
- : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
- ".insn ril,$enc,$R1,$I2", []>;
- def InsnRILa
- : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
- ".insn ril_a,$enc,$R1,$I2", []>;
- def InsnRILb
- : InstRILb<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
- ".insn ril_b,$enc,$R1,$RI2", []>;
- def InsnRILc
- : InstRILc<0, (outs), (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
- ".insn ril_c,$enc,$M1,$RI2", []>;
- def InsnRILU : InstRILa<0, (outs), (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
- ".insn rilu,$enc,$R1,$I2", []>;
+ def InsnRIEg : InstRIEg<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm32sx16:$I2, imm32zx4:$M3),
+ ".insn rie_g,$enc,$R1,$I2,$M3", []>;
+ def InsnRIL : InstRILa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$I2),
+ ".insn ril,$enc,$R1,$I2", []>;
+ def InsnRILa : InstRILa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, imm64xx32:$I2),
+ ".insn ril_a,$enc,$R1,$I2", []>;
+ def InsnRILb : InstRILb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, brtarget32:$RI2),
+ ".insn ril_b,$enc,$R1,$RI2", []>;
+ def InsnRILc : InstRILc<0, (outs),
+ (ins imm64zx48:$enc, imm32zx4:$M1, brtarget32:$RI2),
+ ".insn ril_c,$enc,$M1,$RI2", []>;
def InsnRIS : InstRIS<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, imm32xx8:$I2,
- imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
+ imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
- def InsnRR : InstRR<0, (outs), (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
+ def InsnRR : InstRR<0, (outs),
+ (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
".insn rr,$enc,$R1,$R2", []>;
def InsnRRD : InstRRD<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3),
".insn rrd,$enc,$R1,$R2,$R3", []>;
- def InsnRRE : InstRRE<0, (outs), (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2),
+ def InsnRRE : InstRRE<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2),
".insn rre,$enc,$R1,$R2", []>;
- // Alias for rrf-a. Kept for backwards compatibility.
- def InsnRRF : InstRRFa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
- imm32zx4:$M4),
- ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
def InsnRRFa : InstRRFa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
- imm32zx4:$M4),
+ imm32zx4:$M4),
".insn rrf_a,$enc,$R1,$R2,$R3,$M4", []>;
def InsnRRFb : InstRRFb<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
imm32zx4:$M4),
".insn rrf_b,$enc,$R1,$R2,$R3,$M4", []>;
- def InsnRRFc
- : InstRRFc<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
- ".insn rrf_c,$enc,$R1,$R2,$M3", []>;
- def InsnRRFd
- : InstRRFd<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
- ".insn rrf_d,$enc,$R1,$R2,$M4", []>;
+ def InsnRRFc : InstRRFc<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3),
+ ".insn rrf_c,$enc,$R1,$R2,$M3", []>;
+ def InsnRRFd : InstRRFd<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M4),
+ ".insn rrf_d,$enc,$R1,$R2,$M4", []>;
def InsnRRFe : InstRRFe<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- imm32zx4:$M3, imm32zx4:$M4),
+ imm32zx4:$M3, imm32zx4:$M4),
".insn rrf_e,$enc,$R1,$R2,$M3,$M4", []>;
def InsnRRS : InstRRS<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R2, imm32zx4:$M3,
- (bdaddr12only $B4, $D4):$BD4),
+ (bdaddr12only $B4, $D4):$BD4),
".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
- // RS - legacy operand order preserved
- def InsnRS : InstRSa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn rs,$enc,$R1,$R3,$BD2", []>;
def InsnRSa : InstRSa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn rs_a,$enc,$R1,$BD2,$R3", []>;
def InsnRSb : InstRSb<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M3),
".insn rs_b,$enc,$R1,$BD2,$M3", []>;
- // RSE - legacy operand order preserved
- def InsnRSE : InstRSEa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn rse,$enc,$R1,$R3,$BD2", []>;
- // RSI - legacy operand order preserved
- def InsnRSI
- : InstRSI<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
- ".insn rsi,$enc,$R1,$R3,$RI2", []>;
- def InsnRSLa
- : InstRSLa<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
- ".insn rsl_a,$enc,$BDL1", []>;
- def InsnRSLb
- : InstRSLb<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
- ".insn rsl_b,$enc,$R1,$BDL2,$M3", []>;
- // RSY - legacy operand order preserved
- def InsnRSY : InstRSYa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdaddr20only $B2, $D2):$BD2),
- ".insn rsy,$enc,$R1,$R3,$BD2", []>;
+ def InsnRSLa : InstRSLa<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
+ ".insn rsl_a,$enc,$BDL1", []>;
+ def InsnRSLb : InstRSLb<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
+ ".insn rsl_b,$enc,$R1,$BDL2,$M3", []>;
def InsnRSYa : InstRSYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
+ (bdaddr20only $B2, $D2):$BD2, AnyReg:$R3),
".insn rsy_a,$enc,$R1,$BD2,$R3", []>;
def InsnRSYb : InstRSYb<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
+ (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
".insn rsy_b,$enc,$R1,$BD2,$M3", []>;
- // Alias for rx-a. Kept for backwards compatibility.
- def InsnRX : InstRXa<0, (outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx,$enc,$R1,$XBD2", []>;
def InsnRXa : InstRXa<0, (outs),
(ins imm64zx32:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rx_a,$enc,$R1,$XBD2", []>;
def InsnRXb : InstRXb<0, (outs),
(ins imm64zx32:$enc, imm32zx4:$M1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
".insn rx_b,$enc,$M1,$XBD2", []>;
def InsnRXE : InstRXE<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxe,$enc,$R1,$XBD2", []> {
- let M3 = 0;
- }
- // RXF - legacy operand order preserved
- def InsnRXF : InstRXF<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
-
+ (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
+ ".insn rxe,$enc,$R1,$XBD2,$M3", []>;
def InsnRXY : InstRXYa<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy,$enc,$R1,$XBD2", []>;
+ (ins imm64zx48:$enc, AnyReg:$R1,
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ ".insn rxy,$enc,$R1,$XBD2", []>;
def InsnRXYa : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy_a,$enc,$R1,$XBD2", []>;
def InsnRXYb : InstRXYb<0, (outs),
(ins imm64zx48:$enc, imm32zx4:$M1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy_b,$enc,$M1,$XBD2", []>;
// There is no InstRXYc - it is identical to InstRXYa.
def InsnRXYc : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
+ (bdxaddr20only $B2, $D2, $X2):$XBD2),
".insn rxy_c,$enc,$R1,$XBD2", []>;
- def InsnS : InstS<0, (outs), (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
+ def InsnS : InstS<0, (outs),
+ (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
".insn s,$enc,$BD2", []>;
- def InsnSI
- : InstSI<0, (outs),
- (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
- ".insn si,$enc,$BD1,$I2", []>;
- def InsnSIY
- : InstSIY<0, (outs),
- (ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1, imm32xx8:$I2),
- ".insn siy,$enc,$BD1,$I2", []>;
- def InsnSIL
- : InstSIL<0, (outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx16:$I2),
- ".insn sil,$enc,$BD1,$I2", []>;
+ def InsnSI : InstSI<0, (outs),
+ (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx8:$I2),
+ ".insn si,$enc,$BD1,$I2", []>;
+ def InsnSIY : InstSIY<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr20only $B1, $D1):$BD1, imm32xx8:$I2),
+ ".insn siy,$enc,$BD1,$I2", []>;
+ def InsnSIL : InstSIL<0, (outs),
+ (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, imm32xx16:$I2),
+ ".insn sil,$enc,$BD1,$I2", []>;
def InsnSMI : InstSMI<0, (outs),
(ins imm64zx48:$enc, imm32zx4:$M1, brtarget16bpp:$RI2,
- (bdaddr12only $B3, $D3):$BD3),
+ (bdaddr12only $B3, $D3):$BD3),
".insn smi,$enc,$M1,$RI2,$BD3", []>;
- // Alias for ss-. Kept for backwards compatibility.
- def InsnSS : InstSSd<0, (outs),
- (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
- def InsnSSa
- : InstSSa<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
- (bdaddr12only $B2, $D2):$BD2),
- ".insn ss_a,$enc,$BDL1,$BD2", []>;
- def InsnSSb
- : InstSSb<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
- (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
- ".insn ss_b,$enc,$BDL1,$BDL2", []>;
- def InsnSSc
- : InstSSc<0, (outs),
- (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
- ".insn ss_c,$enc,$BDL1,$BD2,$I3", []>;
+ def InsnSSa : InstSSa<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn ss_a,$enc,$BDL1,$BD2", []>;
+ def InsnSSb : InstSSb<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
+ ".insn ss_b,$enc,$BDL1,$BDL2", []>;
+ def InsnSSc : InstSSc<0, (outs),
+ (ins imm64zx48:$enc, (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$I3),
+ ".insn ss_c,$enc,$BDL1,$BD2,$I3", []>;
def InsnSSd : InstSSd<0, (outs),
(ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ss_d,$enc,$RBD1,$BD2,$R3", []>;
- def InsnSSe
- : InstSSe<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
- AnyReg:$R3, (bdaddr12only $B4, $D4):$BD4),
- ".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>;
+ def InsnSSe : InstSSe<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
+ AnyReg:$R3, (bdaddr12only $B4, $D4):$BD4),
+ ".insn ss_e,$enc,$R1,$BD2,$R3,$BD4", []>;
def InsnSSf : InstSSf<0, (outs),
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
+ (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
".insn ss_f,$enc,$BD1,$BDL2", []>;
def InsnSSE : InstSSE<0, (outs),
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdaddr12only $B2, $D2):$BD2),
+ (bdaddr12only $B2, $D2):$BD2),
".insn sse,$enc,$BD1,$BD2", []>;
def InsnSSF : InstSSF<0, (outs),
(ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn ssf,$enc,$BD1,$BD2,$R3", []>;
- // Alias for vri-e. Kept for backwards compatibility.
- def InsnVRI : InstVRIe<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx12:$I3,
- imm32zx4:$M4, imm32zx4:$M5),
- ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
- def InsnVRIa
- : InstVRIa<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, imm32xx16:$I2, imm32zx4:$M3),
- ".insn vri_a,$enc,$V1,$I2,$M3", []>;
+ def InsnVRIa : InstVRIa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32xx16:$I2, imm32zx4:$M3),
+ ".insn vri_a,$enc,$V1,$I2,$M3", []>;
def InsnVRIb : InstVRIb<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, imm32zx8:$I2,
- imm32zx8:$I3, imm32zx4:$M4),
+ imm32zx8:$I3, imm32zx4:$M4),
".insn vri_b,$enc,$V1,$I2,$I3,$M4", []>;
def InsnVRIc : InstVRIc<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
- VR128:$V3, imm32zx4:$M4),
+ VR128:$V3, imm32zx4:$M4),
".insn vri_c,$enc,$V1,$I2,$V3,$M4", []>;
def InsnVRId : InstVRId<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx8:$I4, imm32zx4:$M5),
+ imm32zx8:$I4, imm32zx4:$M5),
".insn vri_d,$enc,$V1,$V2,$V3,$I4,$M5", []>;
def InsnVRIe : InstVRIe<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
+ imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
".insn vri_e,$enc,$V1,$V2,$I3,$M4,$M5", []>;
def InsnVRIf : InstVRIf<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx8:$I4, imm32zx4:$M5),
+ imm32zx8:$I4, imm32zx4:$M5),
".insn vri_f,$enc,$V1,$V2,$V3,$I4,$M5", []>;
def InsnVRIg : InstVRIg<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
- imm32zx8:$I4, imm32zx4:$M5),
+ imm32zx8:$I4, imm32zx4:$M5),
".insn vri_g,$enc,$V1,$V2,$I3,$I4,$M5", []>;
def InsnVRIh : InstVRIh<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2,
- imm32zx4:$I3, imm32zx4:$M4),
- ".insn vri_h,$enc,$V1,$I2,$I3,$M4", []>;
+ imm32zx4:$I3),
+ ".insn vri_h,$enc,$V1,$I2,$I3", []>;
def InsnVRIi : InstVRIi<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2,
- imm32zx8:$I3, imm32zx4:$M4),
+ imm32zx8:$I3, imm32zx4:$M4),
".insn vri_i,$enc,$V1,$R2,$I3,$M4", []>;
def InsnVRIj : InstVRIj<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx8:$I3,
- imm32zx4:$M4),
+ imm32zx4:$M4),
".insn vri_j,$enc,$V1,$V2,$I3,$M4", []>;
def InsnVRIk : InstVRIk<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx8:$I5),
+ VR128:$V4, imm32zx8:$I5),
".insn vri_k,$enc,$V1,$V2,$V3,$V4,$I5", []>;
- def InsnVRIl
- : InstVRIl<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
- ".insn vri_l,$enc,$V1,$V2,$I3", []>;
- // Alias for vrr-c. Kept for backwards compatibility.
- def InsnVRR : InstVRRc<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
- ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
+ def InsnVRIl : InstVRIl<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx16:$I3),
+ ".insn vri_l,$enc,$V1,$V2,$I3", []>;
def InsnVRRa : InstVRRa<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3,
- imm32zx4:$M4, imm32zx4:$M5),
+ imm32zx4:$M4, imm32zx4:$M5),
".insn vrr_a,$enc,$V1,$V2,$M3,$M4,$M5", []>;
def InsnVRRb : InstVRRb<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4, imm32zx4:$M5),
+ imm32zx4:$M4, imm32zx4:$M5),
".insn vrr_b,$enc,$V1,$V2,$V3,$M4,$M5", []>;
def InsnVRRc : InstVRRc<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
+ imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
".insn vrr_c,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
def InsnVRRd : InstVRRd<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
".insn vrr_d,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
def InsnVRRe : InstVRRe<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
+ VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
".insn vrr_e,$enc,$V1,$V2,$V3,$V4,$M5,$M6", []>;
def InsnVRRf : InstVRRf<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, AnyReg:$R2, AnyReg:$R3),
".insn vrr_f,$enc,$V1,$R2,$R3", []>;
- def InsnVRRg
- : InstVRRg<0, (outs), (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
- ".insn vrr_g,$enc,$V1,$I2", []>;
- def InsnVRRh
- : InstVRRh<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
- ".insn vrr_h,$enc,$V1,$V2,$M3", []>;
+ def InsnVRRg : InstVRRg<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, imm32zx16:$I2),
+ ".insn vrr_g,$enc,$V1,$I2", []>;
+ def InsnVRRh : InstVRRh<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_h,$enc,$V1,$V2,$M3", []>;
def InsnVRRi : InstVRRi<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1, VR128:$V2,
- imm32zx4:$M3, imm32zx4:$M4),
+ imm32zx4:$M3, imm32zx4:$M4),
".insn vrr_i,$enc,$R1,$V2,$M3,$M4", []>;
def InsnVRRj : InstVRRj<0, (outs),
(ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
- imm32zx4:$M4),
+ imm32zx4:$M4),
".insn vrr_j,$enc,$V1,$V2,$V3,$M4", []>;
- def InsnVRRk
- : InstVRRk<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
- ".insn vrr_k,$enc,$V1,$V2,$M3", []>;
- // VRS - legacy operand order preserved
- def InsnVRS : InstVRSc<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
- ".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>;
- def InsnVRSa
- : InstVRSa<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
- VR128:$V3, imm32zx4:$M4),
- ".insn vrs_a,$enc,$V1,$BD2,$V3,$M4", []>;
- def InsnVRSb
- : InstVRSb<0, (outs),
- (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
- AnyReg:$R3, imm32zx4:$M4),
- ".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>;
- def InsnVRSc
- : InstVRSc<0, (outs),
- (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
- VR128:$V3, imm32zx4:$M4),
- ".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>;
+ def InsnVRRk : InstVRRk<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx4:$M3),
+ ".insn vrr_k,$enc,$V1,$V2,$M3", []>;
+ def InsnVRSa : InstVRSa<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vrs_a,$enc,$V1,$BD2,$V3,$M4", []>;
+ def InsnVRSb : InstVRSb<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, (bdaddr12only $B2, $D2):$BD2,
+ AnyReg:$R3, imm32zx4:$M4),
+ ".insn vrs_b,$enc,$V1,$BD2,$R3,$M4", []>;
+ def InsnVRSc : InstVRSc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, (bdaddr12only $B2, $D2):$BD2,
+ VR128:$V3, imm32zx4:$M4),
+ ".insn vrs_c,$enc,$R1,$BD2,$V3,$M4", []>;
def InsnVRSd : InstVRSd<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
".insn vrs_d,$enc,$V1,$BD2,$R3", []>;
def InsnVRV : InstVRV<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
- (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
+ (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
".insn vrv,$enc,$V1,$VBD2,$M3", []>;
def InsnVRX : InstVRX<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
+ (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
".insn vrx,$enc,$V1,$XBD2,$M3", []>;
def InsnVSI : InstVSI<0, (outs),
(ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
+ (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
".insn vsi,$enc,$V1,$BD2,$I3", []>;
+
+ // The following .insn directive definitions do not follow the rule for
+ // operand order, and/or reference the base instruction format even where
+ // that format has subformats. They are kept for backwards compatibility.
+
+ def InsnRIE : InstRIEd<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$I2),
+ ".insn rie,$enc,$R1,$R3,$I2", []>;
+ def InsnRILU : InstRILa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, uimm32:$I2),
+ ".insn rilu,$enc,$R1,$I2", []>;
+ def InsnRRF : InstRRFa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, AnyReg:$R3,
+ imm32zx4:$M4),
+ ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
+ def InsnRS : InstRSa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn rs,$enc,$R1,$R3,$BD2", []>;
+ def InsnRSE : InstRSE<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr12only $B2, $D2):$BD2),
+ ".insn rse,$enc,$R1,$R3,$BD2", []>;
+ def InsnRSI : InstRSI<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R3, brtarget16:$RI2),
+ ".insn rsi,$enc,$R1,$R3,$RI2", []>;
+ def InsnRSY : InstRSYa<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdaddr20only $B2, $D2):$BD2),
+ ".insn rsy,$enc,$R1,$R3,$BD2", []>;
+ def InsnRX : InstRXa<0, (outs),
+ (ins imm64zx32:$enc, AnyReg:$R1,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rx,$enc,$R1,$XBD2", []>;
+ def InsnRXF : InstRXF<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, AnyReg:$R3,
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
+ def InsnSS : InstSSd<0, (outs),
+ (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
+ (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
+ ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
+ def InsnVRI : InstVRIe<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, imm32zx12:$I3,
+ imm32zx4:$M4, imm32zx4:$M5),
+ ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
+ def InsnVRR : InstVRRc<0, (outs),
+ (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, VR128:$V3,
+ imm32zx4:$M4, imm32zx4:$M5, imm32zx4:$M6),
+ ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
+ def InsnVRS : InstVRSc<0, (outs),
+ (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
+ (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
+ ".insn vrs,$enc,$R1,$V3,$BD2,$M4", []>;
}
+
//===----------------------------------------------------------------------===//
// Peepholes.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td
index f0ab67e421149..17bdd2fdb6a5d 100644
--- a/llvm/lib/Target/SystemZ/SystemZOperands.td
+++ b/llvm/lib/Target/SystemZ/SystemZOperands.td
@@ -302,7 +302,7 @@ def U3Imm : ImmediateAsmOperand<"U3Imm">;
def U4Imm : ImmediateAsmOperand<"U4Imm">;
def S8Imm : ImmediateAsmOperand<"S8Imm">;
def U8Imm : ImmediateAsmOperand<"U8Imm">;
-def X8Imm : ImmediateAsmOperand<"X8Imm">;
+def X8Imm : ImmediateAsmOperand<"X8Imm">;
def U12Imm : ImmediateAsmOperand<"U12Imm">;
def S16Imm : ImmediateAsmOperand<"S16Imm">;
def U16Imm : ImmediateAsmOperand<"U16Imm">;
diff --git a/llvm/test/MC/SystemZ/directive-insn-z14.s b/llvm/test/MC/SystemZ/directive-insn-z14.s
index af0a549d78ecf..92bf5806ecf78 100644
--- a/llvm/test/MC/SystemZ/directive-insn-z14.s
+++ b/llvm/test/MC/SystemZ/directive-insn-z14.s
@@ -14,7 +14,7 @@ label.START:
.insn vri_g,0xe6000000005b,%v1,%v2,103,52,5
#CHECK: e6 10 34 56 70 49 vlip %v1, 13398, 7
- .insn vri_h,0xe60000000049,%v1,13398,7,0
+ .insn vri_h,0xe60000000049,%v1,13398,7
#CHECK: e6 12 00 34 50 58 vcvd %v1, %r2, 69, 3
.insn vri_i,0xe60000000058,%v1,%r2,69,3
diff --git a/llvm/test/MC/SystemZ/directive-insn.s b/llvm/test/MC/SystemZ/directive-insn.s
index caa8899b3e7ab..7021d88d5522d 100644
--- a/llvm/test/MC/SystemZ/directive-insn.s
+++ b/llvm/test/MC/SystemZ/directive-insn.s
@@ -75,7 +75,7 @@ label.rsi:
.insn rx,0x59000000,%r1,160(%r3,%r15)
#CHECK: ed 13 f0 a0 00 19 cdb %f1, 160(%r3,%r15)
- .insn rxe,0xed0000000019,%f1,160(%r3,%r15)
+ .insn rxe,0xed0000000019,%f1,160(%r3,%r15),0
#CHECK: ed 23 f0 a0 10 1e madb %f1, %f2, 160(%r3,%r15)
.insn rxf,0xed000000001e,%f1,%f2,160(%r3,%r15)
diff --git a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
index 9238f4b9759ec..40d83b824589c 100644
--- a/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/SystemZInsnDirectiveEmitter.cpp
@@ -49,11 +49,8 @@ static std::string getMatchClassKind(const Record &Def, const Init *Arg,
"directive operand");
// Get name of ParserMatchClass associated with operand.
- StringRef MC = OpRec->getValueAsDef("ParserMatchClass")->getName();
-
- // Drop AsmOperandSuffix if present.
- if (MC.ends_with("AsmOperand"))
- MC = MC.drop_back(10);
+ StringRef MC =
+ OpRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name");
// Prepend MCK_ and return.
return "MCK_" + std::string(MC);
>From e7f96e46eceeb076661963f56f87c1dbdbab50fa Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Mon, 14 Sep 2026 13:52:06 +0200
Subject: [PATCH 10/11] Clarifying comment for insn directive defs
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index fe1cab4c314be..db1db21ff6892 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2273,6 +2273,18 @@ let hasSideEffects = 1 in {
//===----------------------------------------------------------------------===//
// .insn directive instructions
+//
+// Enables encoding of instructions not directly supported by the assembler:
+// .insn <format>, <opcode encoding>, <operands>
+//
+// Rules for these definitions:
+// - Each subformat has its own .insn directive.
+// - Operands are ordered by index (e.g. V1, I2, V3 not V1, V3, I2), since
+// individual instructions within a format may use a different order.
+// - When instructions in a format interpret the same immediate field with
+// different signedness, the directive uses an 'X'-type immediate, whose
+// range is the union of the signed and unsigned cases (e.g. -128..255
+// for imm32xx8).
//===----------------------------------------------------------------------===//
let isCodeGenOnly = 1, hasSideEffects = 1, IsInsnDirective = 1 in {
def InsnE : InstE<0, (outs),
>From 66308fb6fbb67ac24b8b78e8fc52c8cbb844a0bd Mon Sep 17 00:00:00 2001
From: Dominik Steenken <dost at de.ibm.com>
Date: Mon, 14 Sep 2026 15:56:26 +0200
Subject: [PATCH 11/11] Pass M3 in enc field for RXE
This is in accordance with similar behavior in gas.
---
llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 3 ++-
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 4 ++--
llvm/test/MC/SystemZ/directive-insn-z13.s | 6 ++++++
llvm/test/MC/SystemZ/directive-insn.s | 2 +-
4 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 608f215bc94ce..2b0a2a163ad96 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -683,7 +683,8 @@ class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{35-32} = X2;
let Inst{31-28} = B2;
let Inst{27-16} = D2;
- let Inst{15-12} = M3;
+ // Allow M3 to be sourced from enc operand in the .insn directive
+ let Inst{15-12} = !if(!ne(op, 0), M3, enc{15-12});
let Inst{11-8} = 0;
let Inst{7-0} = !if(!ne(op, 0), op{7-0}, enc{7-0});
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index db1db21ff6892..f95f6fa05ddcf 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2415,8 +2415,8 @@ let isCodeGenOnly = 1, hasSideEffects = 1, IsInsnDirective = 1 in {
".insn rx_b,$enc,$M1,$XBD2", []>;
def InsnRXE : InstRXE<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
- ".insn rxe,$enc,$R1,$XBD2,$M3", []>;
+ (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ ".insn rxe,$enc,$R1,$XBD2", []>;
def InsnRXY : InstRXYa<0, (outs),
(ins imm64zx48:$enc, AnyReg:$R1,
(bdxaddr20only $B2, $D2, $X2):$XBD2),
diff --git a/llvm/test/MC/SystemZ/directive-insn-z13.s b/llvm/test/MC/SystemZ/directive-insn-z13.s
index 29b7659d7a02f..54bc2ae6dc15b 100644
--- a/llvm/test/MC/SystemZ/directive-insn-z13.s
+++ b/llvm/test/MC/SystemZ/directive-insn-z13.s
@@ -61,4 +61,10 @@ label.START:
#CHECK: e7 12 30 00 00 62 vlvgp %v1, %r2, %r3
.insn vrr_f,0xe70000000062,%v1,%r2,%r3
+# Tested here because the resulting lcbb instruction
+# requires the vector extension. Tests M3 passing in
+# the enc field for the RXE format.
+#CHECK: e7 13 f0 a0 60 27 lcbb %r1, 160(%r3,%r15), 6
+ .insn rxe,0xe70000006027,%r1,160(%r3,%r15)
+
diff --git a/llvm/test/MC/SystemZ/directive-insn.s b/llvm/test/MC/SystemZ/directive-insn.s
index 7021d88d5522d..caa8899b3e7ab 100644
--- a/llvm/test/MC/SystemZ/directive-insn.s
+++ b/llvm/test/MC/SystemZ/directive-insn.s
@@ -75,7 +75,7 @@ label.rsi:
.insn rx,0x59000000,%r1,160(%r3,%r15)
#CHECK: ed 13 f0 a0 00 19 cdb %f1, 160(%r3,%r15)
- .insn rxe,0xed0000000019,%f1,160(%r3,%r15),0
+ .insn rxe,0xed0000000019,%f1,160(%r3,%r15)
#CHECK: ed 23 f0 a0 10 1e madb %f1, %f2, 160(%r3,%r15)
.insn rxf,0xed000000001e,%f1,%f2,160(%r3,%r15)
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