[llvm] [VectorCombine] fold partial interleaved load (PR #219201)

Kamlesh Kumar via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 14 03:32:12 PDT 2026 

https://github.com/kamleshbhalui updated https://github.com/llvm/llvm-project/pull/219201

>From 9354b8209b25d8e087addd9ae59d7c3caa3de6ca Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Mon, 14 Sep 2026 10:09:15 +0000
Subject: [PATCH 1/2] add test

---
 .../AArch64/partial-deinterleave.ll           | 829 ++++++++++++++++++
 .../PowerPC/partial-deinterleave.ll           | 829 ++++++++++++++++++
 .../RISCV/partial-deinterleave.ll             | 829 ++++++++++++++++++
 .../VectorCombine/X86/partial-deinterleave.ll | 829 ++++++++++++++++++
 4 files changed, 3316 insertions(+)
 create mode 100644 llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll

diff --git a/llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll
new file mode 100644
index 0000000000000..242a963956b21
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll
@@ -0,0 +1,829 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+
+; RUN: opt -mtriple=aarch64-unknown-linux-gnu -passes=vector-combine -S %s | FileCheck %s
+
+define <2 x i32> @factor2_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor2_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor3_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor4_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor4_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor5_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor5_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor5_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor6_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor6_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor6_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor6_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor7_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor7_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor7_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor7_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor7_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor8_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor8_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor8_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor8_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor8_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor8_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts8(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts8(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[FIELD7:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 7
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    [[SUM7:%.*]] = add <2 x i32> [[SUM6]], [[FIELD7]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM7]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %field7 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 7
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  %sum7 = add <2 x i32> %sum6, %field7
+  ret <2 x i32> %sum7
+}
diff --git a/llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll
new file mode 100644
index 0000000000000..d215de97ba166
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll
@@ -0,0 +1,829 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+
+; RUN: opt -mtriple=powerpc64le-unknown-linux-gnu -passes=vector-combine -S %s | FileCheck %s
+
+define <2 x i32> @factor2_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor2_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor3_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor4_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor4_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor5_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor5_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor5_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor6_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor6_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor6_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor6_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor7_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor7_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor7_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor7_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor7_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor8_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor8_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor8_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor8_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor8_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor8_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts8(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts8(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[FIELD7:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 7
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    [[SUM7:%.*]] = add <2 x i32> [[SUM6]], [[FIELD7]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM7]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %field7 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 7
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  %sum7 = add <2 x i32> %sum6, %field7
+  ret <2 x i32> %sum7
+}
diff --git a/llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll
new file mode 100644
index 0000000000000..ca627ab4a0a52
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll
@@ -0,0 +1,829 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+
+; RUN: opt -mtriple=riscv64-unknown-linux-gnu -mattr=+v -passes=vector-combine -S %s | FileCheck %s
+
+define <2 x i32> @factor2_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor2_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor3_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor4_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor4_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor5_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor5_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor5_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor6_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor6_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor6_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor6_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor7_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor7_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor7_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor7_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor7_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor8_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor8_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor8_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor8_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor8_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor8_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts8(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts8(
+; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[FIELD7:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 7
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    [[SUM7:%.*]] = add <2 x i32> [[SUM6]], [[FIELD7]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM7]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %field7 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 7
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  %sum7 = add <2 x i32> %sum6, %field7
+  ret <2 x i32> %sum7
+}
diff --git a/llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll
new file mode 100644
index 0000000000000..f613173cf7ccf
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll
@@ -0,0 +1,829 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -passes=vector-combine -S %s | FileCheck %s
+
+define <2 x i32> @factor2_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor2_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor2_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <4 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor3_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor3_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor3_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <6 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor4_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor4_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor4_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor4_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <8 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor5_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor5_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor5_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor5_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor5_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <10 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor6_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor6_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor6_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor6_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor6_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor6_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <12 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor7_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor7_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor7_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor7_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor7_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor7_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor7_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <14 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts1(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts1(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  ret <2 x i32> %field0
+}
+
+define <2 x i32> @factor8_extracts2(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts2(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %sum1 = add <2 x i32> %field0, %field1
+  ret <2 x i32> %sum1
+}
+
+define <2 x i32> @factor8_extracts3(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts3(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  ret <2 x i32> %sum2
+}
+
+define <2 x i32> @factor8_extracts4(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts4(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM3]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  ret <2 x i32> %sum3
+}
+
+define <2 x i32> @factor8_extracts5(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts5(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM4]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  ret <2 x i32> %sum4
+}
+
+define <2 x i32> @factor8_extracts6(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts6(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM5]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  ret <2 x i32> %sum5
+}
+
+define <2 x i32> @factor8_extracts7(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts7(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM6]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  ret <2 x i32> %sum6
+}
+
+define <2 x i32> @factor8_extracts8(ptr %src) {
+; CHECK-LABEL: define <2 x i32> @factor8_extracts8(
+; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
+; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[FIELD7:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 7
+; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
+; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
+; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
+; CHECK-NEXT:    [[SUM4:%.*]] = add <2 x i32> [[SUM3]], [[FIELD4]]
+; CHECK-NEXT:    [[SUM5:%.*]] = add <2 x i32> [[SUM4]], [[FIELD5]]
+; CHECK-NEXT:    [[SUM6:%.*]] = add <2 x i32> [[SUM5]], [[FIELD6]]
+; CHECK-NEXT:    [[SUM7:%.*]] = add <2 x i32> [[SUM6]], [[FIELD7]]
+; CHECK-NEXT:    ret <2 x i32> [[SUM7]]
+;
+  %wide = load <16 x i32>, ptr %src, align 4
+  %deinterleaved = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> %wide)
+  %field0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 0
+  %field1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 1
+  %field2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 2
+  %field3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 3
+  %field4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 4
+  %field5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 5
+  %field6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 6
+  %field7 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %deinterleaved, 7
+  %sum1 = add <2 x i32> %field0, %field1
+  %sum2 = add <2 x i32> %sum1, %field2
+  %sum3 = add <2 x i32> %sum2, %field3
+  %sum4 = add <2 x i32> %sum3, %field4
+  %sum5 = add <2 x i32> %sum4, %field5
+  %sum6 = add <2 x i32> %sum5, %field6
+  %sum7 = add <2 x i32> %sum6, %field7
+  ret <2 x i32> %sum7
+}

>From 73db8c3b89c5967ea5127017cf15427d225992db Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Mon, 14 Sep 2026 10:12:55 +0000
Subject: [PATCH 2/2] [VectorCombine] fold Partial interleaved load to shuffle

Full interleaved load coule be unprofitable particularly when
not all results are used, transform it to a plain load plus shuffle.
---
 .../Transforms/Vectorize/VectorCombine.cpp    |  98 ++++++
 .../AArch64/partial-deinterleave.ll           | 124 ++++----
 .../PowerPC/partial-deinterleave.ll           | 163 +++++-----
 .../RISCV/partial-deinterleave.ll             |  30 +-
 .../VectorCombine/X86/partial-deinterleave.ll | 300 ++++++++----------
 .../deinterleave-extract-to-shuffle.ll        | 122 +++++++
 ...deinterleave-interleave-multiple-inputs.ll | 172 ++++++++++
 .../deinterleave-interleave-reverse-chain.ll  |  60 ++++
 .../VectorCombine/interleave-elementwise.ll   | 126 ++++++++
 .../interleave-identical-operands.ll          |  76 +++++
 10 files changed, 924 insertions(+), 347 deletions(-)
 create mode 100644 llvm/test/Transforms/VectorCombine/deinterleave-extract-to-shuffle.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/deinterleave-interleave-multiple-inputs.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/deinterleave-interleave-reverse-chain.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/interleave-elementwise.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/interleave-identical-operands.ll

diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index e8c5885f9b1e3..077c87e0d0496 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -164,6 +164,7 @@ class VectorCombine {
   bool shrinkLoadForShuffles(Instruction &I);
   bool shrinkPhiOfShuffles(Instruction &I);
   bool foldDeinterleaveInterleavePair(Instruction &I);
+  bool foldPartialDeinterleave(Instruction &I);
 
   void replaceValue(Instruction &Old, Value &New, bool Erase = true) {
     LLVM_DEBUG(dbgs() << "VC: Replacing: " << Old << '\n');
@@ -6032,6 +6033,101 @@ bool VectorCombine::foldInsExtVectorToShuffle(Instruction &I) {
   return true;
 }
 
+static unsigned getAlignedNumElements(unsigned MaxIdx, FixedVectorType *LoadTy,
+                                      const TargetTransformInfo &TTI,
+                                      const DataLayout &DL);
+
+/// Replace a partially used deinterleaved load with load + shuffles,
+/// when it is profitable.
+bool VectorCombine::foldPartialDeinterleave(Instruction &I) {
+  auto *Deinterleave = dyn_cast<IntrinsicInst>(&I);
+  if (!Deinterleave)
+    return false;
+
+  unsigned Factor =
+      getDeinterleaveIntrinsicFactor(Deinterleave->getIntrinsicID());
+  if (!Factor)
+    return false;
+
+  auto *Load = dyn_cast<LoadInst>(Deinterleave->getArgOperand(0));
+  auto *LoadTy = dyn_cast<FixedVectorType>(Load->getType());
+  if (!LoadTy || !Load->hasOneUse() || !Load->isSimple())
+    return false;
+
+  auto *ResultTy = dyn_cast<FixedVectorType>(
+      Deinterleave->getType()->getStructElementType(0));
+
+  SmallVector<ExtractValueInst *, 8> Extracts;
+  SmallVector<unsigned, 8> UsedIndices;
+  for (User *U : Deinterleave->users()) {
+    auto *Extract = dyn_cast<ExtractValueInst>(U);
+    if (!Extract || Extract->getNumIndices() != 1)
+      return false;
+    unsigned Index = *Extract->idx_begin();
+    Extracts.push_back(Extract);
+    if (!is_contained(UsedIndices, Index))
+      UsedIndices.push_back(Index);
+  }
+
+  if (Extracts.empty())
+    return false;
+  llvm::sort(UsedIndices);
+
+  SmallVector<SmallVector<int, 8>, 8> Masks(Factor);
+  for (unsigned Index : UsedIndices)
+    for (unsigned Lane = 0; Lane != ResultTy->getNumElements(); ++Lane)
+      Masks[Index].push_back(Index + Lane * Factor);
+
+  // shrink the load size when possible
+  unsigned MaxUsedIndex =
+      UsedIndices.back() + (ResultTy->getNumElements() - 1) * Factor;
+  unsigned NewNumElements =
+      std::min(LoadTy->getNumElements(),
+               getAlignedNumElements(MaxUsedIndex, LoadTy, TTI, *DL));
+  auto *NewLoadTy =
+      FixedVectorType::get(LoadTy->getElementType(), NewNumElements);
+
+  SmallVector<unsigned, 8> AllIndices(Factor);
+  std::iota(AllIndices.begin(), AllIndices.end(), 0);
+  InstructionCost OldCost = TTI.getInterleavedMemoryOpCost(
+      Instruction::Load, LoadTy, Factor, AllIndices, Load->getAlign(),
+      Load->getPointerAddressSpace(), CostKind);
+
+  InstructionCost NewCost =
+      TTI.getMemoryOpCost(Instruction::Load, NewLoadTy, Load->getAlign(),
+                          Load->getPointerAddressSpace(), CostKind);
+  for (unsigned Index : UsedIndices)
+    NewCost += TTI.getShuffleCost(TTI::SK_PermuteSingleSrc, ResultTy, NewLoadTy,
+                                  CostKind, Masks[Index]);
+
+  LLVM_DEBUG(dbgs() << "VC: Found partially used deinterleave: " << I
+                    << "\n  OldCost: " << OldCost << " vs NewCost: " << NewCost
+                    << "\n");
+  if (!OldCost.isValid() || !NewCost.isValid() || NewCost > OldCost)
+    return false;
+
+  Value *ShuffleInput = Load;
+  if (NewLoadTy != LoadTy) {
+    IRBuilder<> LoadBuilder(Load);
+    LoadBuilder.SetCurrentDebugLocation(Load->getDebugLoc());
+    auto *NewLoad = cast<LoadInst>(LoadBuilder.CreateAlignedLoad(
+        NewLoadTy, Load->getPointerOperand(), Load->getAlign()));
+    NewLoad->copyMetadata(*Load);
+    NewLoad->takeName(Load);
+    ShuffleInput = NewLoad;
+  }
+
+  IRBuilder<> ShuffleBuilder(Deinterleave);
+  ShuffleBuilder.SetCurrentDebugLocation(Deinterleave->getDebugLoc());
+  SmallVector<Value *, 8> Shuffles(Factor);
+  for (unsigned Index : UsedIndices)
+    Shuffles[Index] =
+        ShuffleBuilder.CreateShuffleVector(ShuffleInput, Masks[Index]);
+  for (ExtractValueInst *Extract : Extracts)
+    replaceValue(*Extract, *Shuffles[*Extract->idx_begin()], false);
+  return true;
+}
+
 /// Fold away a matched pair of vector.deinterleave/interleave intrinsics
 /// with a chain of elementwise operations on each between the
 /// deinterleave and interleave.
@@ -6334,6 +6430,8 @@ bool VectorCombine::foldInterleaveIntrinsics(Instruction &I) {
 /// %merge1 = bitcast <vscale x 16 x i16> %f1 to <vscale x 8 x i32>
 /// ```
 bool VectorCombine::foldDeinterleaveIntrinsics(Instruction &I) {
+  if (foldPartialDeinterleave(I))
+    return true;
   if (foldDeinterleaveInterleavePair(I))
     return true;
 
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll
index 242a963956b21..125d86b8f68a8 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/partial-deinterleave.ll
@@ -171,9 +171,8 @@ define <2 x i32> @factor4_extracts4(ptr %src) {
 define <2 x i32> @factor5_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <10 x i32>, ptr %src, align 4
@@ -185,10 +184,9 @@ define <2 x i32> @factor5_extracts1(ptr %src) {
 define <2 x i32> @factor5_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 6>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -203,11 +201,10 @@ define <2 x i32> @factor5_extracts2(ptr %src) {
 define <2 x i32> @factor5_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 6>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 2, i32 7>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -281,9 +278,8 @@ define <2 x i32> @factor5_extracts5(ptr %src) {
 define <2 x i32> @factor6_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 6>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <12 x i32>, ptr %src, align 4
@@ -295,10 +291,9 @@ define <2 x i32> @factor6_extracts1(ptr %src) {
 define <2 x i32> @factor6_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 7>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -314,10 +309,9 @@ define <2 x i32> @factor6_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -336,11 +330,10 @@ define <2 x i32> @factor6_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -425,9 +418,8 @@ define <2 x i32> @factor6_extracts6(ptr %src) {
 define <2 x i32> @factor7_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <14 x i32>, ptr %src, align 4
@@ -439,10 +431,9 @@ define <2 x i32> @factor7_extracts1(ptr %src) {
 define <2 x i32> @factor7_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -457,11 +448,10 @@ define <2 x i32> @factor7_extracts2(ptr %src) {
 define <2 x i32> @factor7_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -479,12 +469,11 @@ define <2 x i32> @factor7_extracts3(ptr %src) {
 define <2 x i32> @factor7_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 10>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -607,9 +596,8 @@ define <2 x i32> @factor7_extracts7(ptr %src) {
 define <2 x i32> @factor8_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <16 x i32>, ptr %src, align 4
@@ -621,10 +609,9 @@ define <2 x i32> @factor8_extracts1(ptr %src) {
 define <2 x i32> @factor8_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -639,11 +626,10 @@ define <2 x i32> @factor8_extracts2(ptr %src) {
 define <2 x i32> @factor8_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 10>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -661,12 +647,11 @@ define <2 x i32> @factor8_extracts3(ptr %src) {
 define <2 x i32> @factor8_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 11>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -688,12 +673,11 @@ define <2 x i32> @factor8_extracts5(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts5(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 3, i32 11>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 4, i32 12>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
diff --git a/llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll
index d215de97ba166..48d0da240ed70 100644
--- a/llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll
+++ b/llvm/test/Transforms/VectorCombine/PowerPC/partial-deinterleave.ll
@@ -37,9 +37,8 @@ define <2 x i32> @factor2_extracts2(ptr %src) {
 define <2 x i32> @factor3_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor3_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <4 x i32> [[WIDE]], <4 x i32> poison, <2 x i32> <i32 0, i32 3>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <6 x i32>, ptr %src, align 4
@@ -92,8 +91,7 @@ define <2 x i32> @factor4_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor4_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 4>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <8 x i32>, ptr %src, align 4
@@ -106,9 +104,8 @@ define <2 x i32> @factor4_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor4_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 4>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 5>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -171,9 +168,8 @@ define <2 x i32> @factor4_extracts4(ptr %src) {
 define <2 x i32> @factor5_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <10 x i32>, ptr %src, align 4
@@ -185,10 +181,9 @@ define <2 x i32> @factor5_extracts1(ptr %src) {
 define <2 x i32> @factor5_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 6>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -203,11 +198,10 @@ define <2 x i32> @factor5_extracts2(ptr %src) {
 define <2 x i32> @factor5_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 6>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 2, i32 7>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -281,9 +275,8 @@ define <2 x i32> @factor5_extracts5(ptr %src) {
 define <2 x i32> @factor6_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 6>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <12 x i32>, ptr %src, align 4
@@ -295,10 +288,9 @@ define <2 x i32> @factor6_extracts1(ptr %src) {
 define <2 x i32> @factor6_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 7>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -314,10 +306,9 @@ define <2 x i32> @factor6_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -336,11 +327,10 @@ define <2 x i32> @factor6_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -425,9 +415,8 @@ define <2 x i32> @factor6_extracts6(ptr %src) {
 define <2 x i32> @factor7_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <14 x i32>, ptr %src, align 4
@@ -439,10 +428,9 @@ define <2 x i32> @factor7_extracts1(ptr %src) {
 define <2 x i32> @factor7_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -457,11 +445,10 @@ define <2 x i32> @factor7_extracts2(ptr %src) {
 define <2 x i32> @factor7_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -479,12 +466,11 @@ define <2 x i32> @factor7_extracts3(ptr %src) {
 define <2 x i32> @factor7_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 10>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -505,13 +491,12 @@ define <2 x i32> @factor7_extracts4(ptr %src) {
 define <2 x i32> @factor7_extracts5(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts5(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 10>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 4, i32 11>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -607,9 +592,8 @@ define <2 x i32> @factor7_extracts7(ptr %src) {
 define <2 x i32> @factor8_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <16 x i32>, ptr %src, align 4
@@ -621,10 +605,9 @@ define <2 x i32> @factor8_extracts1(ptr %src) {
 define <2 x i32> @factor8_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -639,11 +622,10 @@ define <2 x i32> @factor8_extracts2(ptr %src) {
 define <2 x i32> @factor8_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 10>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -661,12 +643,11 @@ define <2 x i32> @factor8_extracts3(ptr %src) {
 define <2 x i32> @factor8_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 11>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -688,12 +669,11 @@ define <2 x i32> @factor8_extracts5(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts5(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 3, i32 11>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 4, i32 12>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -718,13 +698,12 @@ define <2 x i32> @factor8_extracts6(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts6(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
-; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 3, i32 11>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 4, i32 12>
+; CHECK-NEXT:    [[FIELD5:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 5, i32 13>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
diff --git a/llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll
index ca627ab4a0a52..401b18454c7e4 100644
--- a/llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll
+++ b/llvm/test/Transforms/VectorCombine/RISCV/partial-deinterleave.ll
@@ -5,9 +5,8 @@
 define <2 x i32> @factor2_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor2_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <3 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <3 x i32> [[WIDE]], <3 x i32> poison, <2 x i32> <i32 0, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <4 x i32>, ptr %src, align 4
@@ -20,9 +19,8 @@ define <2 x i32> @factor2_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor2_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <4 x i32> [[WIDE]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <4 x i32> [[WIDE]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -37,9 +35,8 @@ define <2 x i32> @factor2_extracts2(ptr %src) {
 define <2 x i32> @factor3_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor3_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <4 x i32> [[WIDE]], <4 x i32> poison, <2 x i32> <i32 0, i32 3>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <6 x i32>, ptr %src, align 4
@@ -171,9 +168,8 @@ define <2 x i32> @factor4_extracts4(ptr %src) {
 define <2 x i32> @factor5_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <6 x i32> [[WIDE]], <6 x i32> poison, <2 x i32> <i32 0, i32 5>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <10 x i32>, ptr %src, align 4
@@ -281,9 +277,8 @@ define <2 x i32> @factor5_extracts5(ptr %src) {
 define <2 x i32> @factor6_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <7 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <7 x i32> [[WIDE]], <7 x i32> poison, <2 x i32> <i32 0, i32 6>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <12 x i32>, ptr %src, align 4
@@ -425,9 +420,8 @@ define <2 x i32> @factor6_extracts6(ptr %src) {
 define <2 x i32> @factor7_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <14 x i32>, ptr %src, align 4
diff --git a/llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll b/llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll
index f613173cf7ccf..ae0dd5bc64097 100644
--- a/llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/partial-deinterleave.ll
@@ -20,9 +20,8 @@ define <2 x i32> @factor2_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor2_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <4 x i32> [[WIDE]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <4 x i32> [[WIDE]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -37,9 +36,8 @@ define <2 x i32> @factor2_extracts2(ptr %src) {
 define <2 x i32> @factor3_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor3_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <4 x i32> [[WIDE]], <4 x i32> poison, <2 x i32> <i32 0, i32 3>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <6 x i32>, ptr %src, align 4
@@ -52,9 +50,8 @@ define <2 x i32> @factor3_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor3_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <6 x i32> [[WIDE]], <6 x i32> poison, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <6 x i32> [[WIDE]], <6 x i32> poison, <2 x i32> <i32 1, i32 4>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -70,10 +67,9 @@ define <2 x i32> @factor3_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor3_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <6 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <6 x i32> [[WIDE]], <6 x i32> poison, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <6 x i32> [[WIDE]], <6 x i32> poison, <2 x i32> <i32 1, i32 4>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <6 x i32> [[WIDE]], <6 x i32> poison, <2 x i32> <i32 2, i32 5>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -92,8 +88,7 @@ define <2 x i32> @factor4_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor4_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 4>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <8 x i32>, ptr %src, align 4
@@ -106,9 +101,8 @@ define <2 x i32> @factor4_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor4_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 4>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 5>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -124,10 +118,9 @@ define <2 x i32> @factor4_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor4_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 4>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 5>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 2, i32 6>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -146,11 +139,10 @@ define <2 x i32> @factor4_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor4_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4.v8i32(<8 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 4>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 5>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 2, i32 6>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 3, i32 7>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -171,9 +163,8 @@ define <2 x i32> @factor4_extracts4(ptr %src) {
 define <2 x i32> @factor5_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <10 x i32>, ptr %src, align 4
@@ -185,10 +176,9 @@ define <2 x i32> @factor5_extracts1(ptr %src) {
 define <2 x i32> @factor5_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 6>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -203,11 +193,10 @@ define <2 x i32> @factor5_extracts2(ptr %src) {
 define <2 x i32> @factor5_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 6>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 2, i32 7>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -226,11 +215,10 @@ define <2 x i32> @factor5_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 1, i32 6>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 2, i32 7>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 3, i32 8>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -252,12 +240,11 @@ define <2 x i32> @factor5_extracts5(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor5_extracts5(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <10 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave5.v10i32(<10 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 0, i32 5>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 1, i32 6>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 2, i32 7>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 3, i32 8>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <10 x i32> [[WIDE]], <10 x i32> poison, <2 x i32> <i32 4, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -281,9 +268,8 @@ define <2 x i32> @factor5_extracts5(ptr %src) {
 define <2 x i32> @factor6_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 6>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <12 x i32>, ptr %src, align 4
@@ -295,10 +281,9 @@ define <2 x i32> @factor6_extracts1(ptr %src) {
 define <2 x i32> @factor6_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 1, i32 7>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -314,10 +299,9 @@ define <2 x i32> @factor6_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -336,11 +320,10 @@ define <2 x i32> @factor6_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -362,12 +345,11 @@ define <2 x i32> @factor6_extracts5(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts5(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 9>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 4, i32 10>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -392,13 +374,12 @@ define <2 x i32> @factor6_extracts6(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor6_extracts6(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6.v12i32(<12 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
-; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 6>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 7>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 8>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 9>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 4, i32 10>
+; CHECK-NEXT:    [[FIELD5:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 5, i32 11>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -425,9 +406,8 @@ define <2 x i32> @factor6_extracts6(ptr %src) {
 define <2 x i32> @factor7_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <8 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <8 x i32> [[WIDE]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <14 x i32>, ptr %src, align 4
@@ -439,10 +419,9 @@ define <2 x i32> @factor7_extracts1(ptr %src) {
 define <2 x i32> @factor7_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -457,11 +436,10 @@ define <2 x i32> @factor7_extracts2(ptr %src) {
 define <2 x i32> @factor7_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -479,12 +457,11 @@ define <2 x i32> @factor7_extracts3(ptr %src) {
 define <2 x i32> @factor7_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 10>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -505,13 +482,12 @@ define <2 x i32> @factor7_extracts4(ptr %src) {
 define <2 x i32> @factor7_extracts5(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts5(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 9>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 10>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 4, i32 11>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -536,13 +512,12 @@ define <2 x i32> @factor7_extracts6(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts6(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
-; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 2, i32 9>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 3, i32 10>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 4, i32 11>
+; CHECK-NEXT:    [[FIELD5:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 5, i32 12>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -570,14 +545,13 @@ define <2 x i32> @factor7_extracts7(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor7_extracts7(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <14 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave7.v14i32(<14 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
-; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
-; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 0, i32 7>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 1, i32 8>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 2, i32 9>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 3, i32 10>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 4, i32 11>
+; CHECK-NEXT:    [[FIELD5:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 5, i32 12>
+; CHECK-NEXT:    [[FIELD6:%.*]] = shufflevector <14 x i32> [[WIDE]], <14 x i32> poison, <2 x i32> <i32 6, i32 13>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -607,9 +581,8 @@ define <2 x i32> @factor7_extracts7(ptr %src) {
 define <2 x i32> @factor8_extracts1(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts1(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
 ; CHECK-NEXT:    ret <2 x i32> [[FIELD0]]
 ;
   %wide = load <16 x i32>, ptr %src, align 4
@@ -621,10 +594,9 @@ define <2 x i32> @factor8_extracts1(ptr %src) {
 define <2 x i32> @factor8_extracts2(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts2(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM1]]
 ;
@@ -639,11 +611,10 @@ define <2 x i32> @factor8_extracts2(ptr %src) {
 define <2 x i32> @factor8_extracts3(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts3(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 10>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUM2]]
@@ -661,12 +632,11 @@ define <2 x i32> @factor8_extracts3(ptr %src) {
 define <2 x i32> @factor8_extracts4(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts4(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
-; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
+; CHECK-NEXT:    [[WIDE:%.*]] = load <12 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <12 x i32> [[WIDE]], <12 x i32> poison, <2 x i32> <i32 3, i32 11>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -688,12 +658,11 @@ define <2 x i32> @factor8_extracts5(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts5(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 3, i32 11>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 4, i32 12>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -718,13 +687,12 @@ define <2 x i32> @factor8_extracts6(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts6(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
-; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 3, i32 11>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 4, i32 12>
+; CHECK-NEXT:    [[FIELD5:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 5, i32 13>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -752,14 +720,13 @@ define <2 x i32> @factor8_extracts7(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts7(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
-; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
-; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 3, i32 11>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 4, i32 12>
+; CHECK-NEXT:    [[FIELD5:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 5, i32 13>
+; CHECK-NEXT:    [[FIELD6:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 6, i32 14>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
@@ -790,15 +757,14 @@ define <2 x i32> @factor8_extracts8(ptr %src) {
 ; CHECK-LABEL: define <2 x i32> @factor8_extracts8(
 ; CHECK-SAME: ptr [[SRC:%.*]]) {
 ; CHECK-NEXT:    [[WIDE:%.*]] = load <16 x i32>, ptr [[SRC]], align 4
-; CHECK-NEXT:    [[DEINTERLEAVED:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8.v16i32(<16 x i32> [[WIDE]])
-; CHECK-NEXT:    [[FIELD0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 0
-; CHECK-NEXT:    [[FIELD1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 1
-; CHECK-NEXT:    [[FIELD2:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 2
-; CHECK-NEXT:    [[FIELD3:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 3
-; CHECK-NEXT:    [[FIELD4:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 4
-; CHECK-NEXT:    [[FIELD5:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 5
-; CHECK-NEXT:    [[FIELD6:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 6
-; CHECK-NEXT:    [[FIELD7:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[DEINTERLEAVED]], 7
+; CHECK-NEXT:    [[FIELD0:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    [[FIELD1:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 1, i32 9>
+; CHECK-NEXT:    [[FIELD2:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 2, i32 10>
+; CHECK-NEXT:    [[FIELD3:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 3, i32 11>
+; CHECK-NEXT:    [[FIELD4:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 4, i32 12>
+; CHECK-NEXT:    [[FIELD5:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 5, i32 13>
+; CHECK-NEXT:    [[FIELD6:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 6, i32 14>
+; CHECK-NEXT:    [[FIELD7:%.*]] = shufflevector <16 x i32> [[WIDE]], <16 x i32> poison, <2 x i32> <i32 7, i32 15>
 ; CHECK-NEXT:    [[SUM1:%.*]] = add <2 x i32> [[FIELD0]], [[FIELD1]]
 ; CHECK-NEXT:    [[SUM2:%.*]] = add <2 x i32> [[SUM1]], [[FIELD2]]
 ; CHECK-NEXT:    [[SUM3:%.*]] = add <2 x i32> [[SUM2]], [[FIELD3]]
diff --git a/llvm/test/Transforms/VectorCombine/deinterleave-extract-to-shuffle.ll b/llvm/test/Transforms/VectorCombine/deinterleave-extract-to-shuffle.ll
new file mode 100644
index 0000000000000..74f4b483cc9f3
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/deinterleave-extract-to-shuffle.ll
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mtriple=aarch64 -passes=vector-combine -S %s | FileCheck %s
+
+define <2 x double> @extract_field0(<6 x double> %v) {
+; CHECK-LABEL: define <2 x double> @extract_field0(
+; CHECK-SAME: <6 x double> [[V:%.*]]) {
+; CHECK-NEXT:    [[F0:%.*]] = shufflevector <6 x double> [[V]], <6 x double> poison, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    ret <2 x double> [[F0]]
+;
+  %d = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %v)
+  %f0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 0
+  ret <2 x double> %f0
+}
+
+define <2 x double> @extract_field2(<6 x double> %v) {
+; CHECK-LABEL: define <2 x double> @extract_field2(
+; CHECK-SAME: <6 x double> [[V:%.*]]) {
+; CHECK-NEXT:    [[F2:%.*]] = shufflevector <6 x double> [[V]], <6 x double> poison, <2 x i32> <i32 2, i32 5>
+; CHECK-NEXT:    ret <2 x double> [[F2]]
+;
+  %d = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %v)
+  %f2 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 2
+  ret <2 x double> %f2
+}
+
+define <2 x double> @extract_two_fields(<6 x double> %v) {
+; CHECK-LABEL: define <2 x double> @extract_two_fields(
+; CHECK-SAME: <6 x double> [[V:%.*]]) {
+; CHECK-NEXT:    [[F0:%.*]] = shufflevector <6 x double> [[V]], <6 x double> poison, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[F2:%.*]] = shufflevector <6 x double> [[V]], <6 x double> poison, <2 x i32> <i32 2, i32 5>
+; CHECK-NEXT:    [[SUM:%.*]] = fadd <2 x double> [[F0]], [[F2]]
+; CHECK-NEXT:    ret <2 x double> [[SUM]]
+;
+  %d = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %v)
+  %f0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 0
+  %f2 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 2
+  %sum = fadd <2 x double> %f0, %f2
+  ret <2 x double> %sum
+}
+
+define <2 x double> @all_fields_used(<6 x double> %v) {
+; CHECK-LABEL: define <2 x double> @all_fields_used(
+; CHECK-SAME: <6 x double> [[V:%.*]]) {
+; CHECK-NEXT:    [[D:%.*]] = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> [[V]])
+; CHECK-NEXT:    [[F0:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[D]], 0
+; CHECK-NEXT:    [[F1:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[D]], 1
+; CHECK-NEXT:    [[F2:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[D]], 2
+; CHECK-NEXT:    [[SUM01:%.*]] = fadd <2 x double> [[F0]], [[F1]]
+; CHECK-NEXT:    [[SUM:%.*]] = fadd <2 x double> [[SUM01]], [[F2]]
+; CHECK-NEXT:    ret <2 x double> [[SUM]]
+;
+  %d = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %v)
+  %f0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 0
+  %f1 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 1
+  %f2 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 2
+  %sum01 = fadd <2 x double> %f0, %f1
+  %sum = fadd <2 x double> %sum01, %f2
+  ret <2 x double> %sum
+}
+
+define void @square_field0(ptr %p0, ptr %p1, ptr %r0, ptr %r1) {
+; CHECK-LABEL: define void @square_field0(
+; CHECK-SAME: ptr [[P0:%.*]], ptr [[P1:%.*]], ptr [[R0:%.*]], ptr [[R1:%.*]]) {
+; CHECK-NEXT:    [[WIDE0:%.*]] = load <6 x double>, ptr [[P0]], align 8
+; CHECK-NEXT:    [[F0:%.*]] = shufflevector <6 x double> [[WIDE0]], <6 x double> poison, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[WIDE1:%.*]] = load <6 x double>, ptr [[P1]], align 8
+; CHECK-NEXT:    [[F1:%.*]] = shufflevector <6 x double> [[WIDE1]], <6 x double> poison, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[SQUARE0:%.*]] = fmul <2 x double> [[F0]], [[F0]]
+; CHECK-NEXT:    [[SQUARE1:%.*]] = fmul <2 x double> [[F1]], [[F1]]
+; CHECK-NEXT:    store <2 x double> [[SQUARE0]], ptr [[R0]], align 8
+; CHECK-NEXT:    store <2 x double> [[SQUARE1]], ptr [[R1]], align 8
+; CHECK-NEXT:    ret void
+;
+  %wide0 = load <6 x double>, ptr %p0, align 8
+  %d0 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %wide0)
+  %f0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d0, 0
+  %wide1 = load <6 x double>, ptr %p1, align 8
+  %d1 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %wide1)
+  %f1 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d1, 0
+  %square0 = fmul <2 x double> %f0, %f0
+  %square1 = fmul <2 x double> %f1, %f1
+  store <2 x double> %square0, ptr %r0, align 8
+  store <2 x double> %square1, ptr %r1, align 8
+  ret void
+}
+
+define <vscale x 2 x double> @scalable(<vscale x 6 x double> %v) {
+; CHECK-LABEL: define <vscale x 2 x double> @scalable(
+; CHECK-SAME: <vscale x 6 x double> [[V:%.*]]) {
+; CHECK-NEXT:    [[D:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.vector.deinterleave3.nxv6f64(<vscale x 6 x double> [[V]])
+; CHECK-NEXT:    [[F0:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[D]], 0
+; CHECK-NEXT:    ret <vscale x 2 x double> [[F0]]
+;
+  %d = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.vector.deinterleave3.nxv6f64(<vscale x 6 x double> %v)
+  %f0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %d, 0
+  ret <vscale x 2 x double> %f0
+}
+
+define <2 x double> @operand_bundle(<6 x double> %v) {
+; CHECK-LABEL: define <2 x double> @operand_bundle(
+; CHECK-SAME: <6 x double> [[V:%.*]]) {
+; CHECK-NEXT:    [[D:%.*]] = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> [[V]]) [ "deopt"(i32 0) ]
+; CHECK-NEXT:    [[F0:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[D]], 0
+; CHECK-NEXT:    ret <2 x double> [[F0]]
+;
+  %d = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %v) [ "deopt"(i32 0) ]
+  %f0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %d, 0
+  ret <2 x double> %f0
+}
+
+define { <2 x double>, <2 x double>, <2 x double> } @non_extract_use(<6 x double> %v) {
+; CHECK-LABEL: define { <2 x double>, <2 x double>, <2 x double> } @non_extract_use(
+; CHECK-SAME: <6 x double> [[V:%.*]]) {
+; CHECK-NEXT:    [[D:%.*]] = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> [[V]])
+; CHECK-NEXT:    ret { <2 x double>, <2 x double>, <2 x double> } [[D]]
+;
+  %d = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %v)
+  ret { <2 x double>, <2 x double>, <2 x double> } %d
+}
+
+declare { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double>)
+declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.vector.deinterleave3.nxv6f64(<vscale x 6 x double>)
diff --git a/llvm/test/Transforms/VectorCombine/deinterleave-interleave-multiple-inputs.ll b/llvm/test/Transforms/VectorCombine/deinterleave-interleave-multiple-inputs.ll
new file mode 100644
index 0000000000000..15ad95fb8f9e3
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/deinterleave-interleave-multiple-inputs.ll
@@ -0,0 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes=vector-combine %s | FileCheck %s
+
+define <6 x double> @deinterleave3_fmuladd_two_inputs(
+; CHECK-LABEL: define <6 x double> @deinterleave3_fmuladd_two_inputs(
+; CHECK-SAME: <6 x double> [[X:%.*]], <6 x double> [[Y:%.*]], double [[SCALE:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <6 x double> poison, double [[SCALE]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <6 x double> [[TMP1]], <6 x double> poison, <6 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = call <6 x double> @llvm.fmuladd.v6f64(<6 x double> [[TMP2]], <6 x double> [[X]], <6 x double> [[Y]])
+; CHECK-NEXT:    ret <6 x double> [[R]]
+;
+  <6 x double> %x, <6 x double> %y, double %scale) {
+  %splat.insert = insertelement <2 x double> poison, double %scale, i64 0
+  %splat = shufflevector <2 x double> %splat.insert, <2 x double> poison, <2 x i32> zeroinitializer
+  %dx = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %x)
+  %x0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dx, 0
+  %x1 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dx, 1
+  %x2 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dx, 2
+  %dy = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %y)
+  %y0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dy, 0
+  %y1 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dy, 1
+  %y2 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dy, 2
+  %r0 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %splat, <2 x double> %x0, <2 x double> %y0)
+  %r1 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %splat, <2 x double> %x1, <2 x double> %y1)
+  %r2 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %splat, <2 x double> %x2, <2 x double> %y2)
+  %r = call <6 x double> @llvm.vector.interleave3.v6f64(<2 x double> %r0, <2 x double> %r1, <2 x double> %r2)
+  ret <6 x double> %r
+}
+
+define <vscale x 4 x i32> @scalable_deinterleave2_add_two_inputs(
+; CHECK-LABEL: define <vscale x 4 x i32> @scalable_deinterleave2_add_two_inputs(
+; CHECK-SAME: <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> [[Y:%.*]]) {
+; CHECK-NEXT:    [[R:%.*]] = add <vscale x 4 x i32> [[X]], [[Y]]
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+  %dx = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %x)
+  %x0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %dx, 0
+  %x1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %dx, 1
+  %dy = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %y)
+  %y0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %dy, 0
+  %y1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %dy, 1
+  %r0 = add <vscale x 2 x i32> %x0, %y0
+  %r1 = add <vscale x 2 x i32> %x1, %y1
+  %r = call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %r0, <vscale x 2 x i32> %r1)
+  ret <vscale x 4 x i32> %r
+}
+
+; Fields from another deinterleave must be in matching order.
+define <6 x double> @negative_deinterleave3_reordered_operand(
+; CHECK-LABEL: define <6 x double> @negative_deinterleave3_reordered_operand(
+; CHECK-SAME: <6 x double> [[X:%.*]], <6 x double> [[Y:%.*]], double [[SCALE:%.*]]) {
+; CHECK-NEXT:    [[SPLAT_INSERT:%.*]] = insertelement <2 x double> poison, double [[SCALE]], i64 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <2 x double> [[SPLAT_INSERT]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[DX:%.*]] = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> [[X]])
+; CHECK-NEXT:    [[X0:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[DX]], 0
+; CHECK-NEXT:    [[X1:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[DX]], 1
+; CHECK-NEXT:    [[X2:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[DX]], 2
+; CHECK-NEXT:    [[DY:%.*]] = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> [[Y]])
+; CHECK-NEXT:    [[Y0:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[DY]], 0
+; CHECK-NEXT:    [[Y1:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[DY]], 1
+; CHECK-NEXT:    [[Y2:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[DY]], 2
+; CHECK-NEXT:    [[R0:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[SPLAT]], <2 x double> [[X0]], <2 x double> [[Y1]])
+; CHECK-NEXT:    [[R1:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[SPLAT]], <2 x double> [[X1]], <2 x double> [[Y0]])
+; CHECK-NEXT:    [[R2:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[SPLAT]], <2 x double> [[X2]], <2 x double> [[Y2]])
+; CHECK-NEXT:    [[R:%.*]] = call <6 x double> @llvm.vector.interleave3.v6f64(<2 x double> [[R0]], <2 x double> [[R1]], <2 x double> [[R2]])
+; CHECK-NEXT:    ret <6 x double> [[R]]
+;
+  <6 x double> %x, <6 x double> %y, double %scale) {
+  %splat.insert = insertelement <2 x double> poison, double %scale, i64 0
+  %splat = shufflevector <2 x double> %splat.insert, <2 x double> poison, <2 x i32> zeroinitializer
+  %dx = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %x)
+  %x0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dx, 0
+  %x1 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dx, 1
+  %x2 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dx, 2
+  %dy = call { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double> %y)
+  %y0 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dy, 0
+  %y1 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dy, 1
+  %y2 = extractvalue { <2 x double>, <2 x double>, <2 x double> } %dy, 2
+  %r0 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %splat, <2 x double> %x0, <2 x double> %y1)
+  %r1 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %splat, <2 x double> %x1, <2 x double> %y0)
+  %r2 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %splat, <2 x double> %x2, <2 x double> %y2)
+  %r = call <6 x double> @llvm.vector.interleave3.v6f64(<2 x double> %r0, <2 x double> %r1, <2 x double> %r2)
+  ret <6 x double> %r
+}
+
+define <4 x i32> @negative_mismatched_factors(
+; CHECK-LABEL: define <4 x i32> @negative_mismatched_factors(
+; CHECK-SAME: <4 x i32> [[X:%.*]], <6 x i32> [[Y:%.*]]) {
+; CHECK-NEXT:    [[DX:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT:    [[X0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DX]], 0
+; CHECK-NEXT:    [[X1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DX]], 1
+; CHECK-NEXT:    [[DY:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> [[Y]])
+; CHECK-NEXT:    [[Y0:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DY]], 0
+; CHECK-NEXT:    [[Y1:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[DY]], 1
+; CHECK-NEXT:    [[R0:%.*]] = add <2 x i32> [[X0]], [[Y0]]
+; CHECK-NEXT:    [[R1:%.*]] = add <2 x i32> [[X1]], [[Y1]]
+; CHECK-NEXT:    [[R:%.*]] = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> [[R0]], <2 x i32> [[R1]])
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  <4 x i32> %x, <6 x i32> %y) {
+  %dx = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %x)
+  %x0 = extractvalue { <2 x i32>, <2 x i32> } %dx, 0
+  %x1 = extractvalue { <2 x i32>, <2 x i32> } %dx, 1
+  %dy = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32> %y)
+  %y0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %dy, 0
+  %y1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %dy, 1
+  %r0 = add <2 x i32> %x0, %y0
+  %r1 = add <2 x i32> %x1, %y1
+  %r = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %r0, <2 x i32> %r1)
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @negative_secondary_deinterleave_bundle(
+; CHECK-LABEL: define <4 x i32> @negative_secondary_deinterleave_bundle(
+; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]) {
+; CHECK-NEXT:    [[DX:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[X]])
+; CHECK-NEXT:    [[X0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DX]], 0
+; CHECK-NEXT:    [[X1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DX]], 1
+; CHECK-NEXT:    [[DY:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> [[Y]]) [ "deopt"(i32 0) ]
+; CHECK-NEXT:    [[Y0:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DY]], 0
+; CHECK-NEXT:    [[Y1:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[DY]], 1
+; CHECK-NEXT:    [[R0:%.*]] = add <2 x i32> [[X0]], [[Y0]]
+; CHECK-NEXT:    [[R1:%.*]] = add <2 x i32> [[X1]], [[Y1]]
+; CHECK-NEXT:    [[R:%.*]] = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> [[R0]], <2 x i32> [[R1]])
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  <4 x i32> %x, <4 x i32> %y) {
+  %dx = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %x)
+  %x0 = extractvalue { <2 x i32>, <2 x i32> } %dx, 0
+  %x1 = extractvalue { <2 x i32>, <2 x i32> } %dx, 1
+  %dy = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %y) [ "deopt"(i32 0) ]
+  %y0 = extractvalue { <2 x i32>, <2 x i32> } %dy, 0
+  %y1 = extractvalue { <2 x i32>, <2 x i32> } %dy, 1
+  %r0 = add <2 x i32> %x0, %y0
+  %r1 = add <2 x i32> %x1, %y1
+  %r = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %r0, <2 x i32> %r1)
+  ret <4 x i32> %r
+}
+
+define <4 x float> @negative_convergent_intrinsic(<4 x float> %x) {
+; CHECK-LABEL: define <4 x float> @negative_convergent_intrinsic(
+; CHECK-SAME: <4 x float> [[X:%.*]]) {
+; CHECK-NEXT:    [[DX:%.*]] = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> [[X]])
+; CHECK-NEXT:    [[X0:%.*]] = extractvalue { <2 x float>, <2 x float> } [[DX]], 0
+; CHECK-NEXT:    [[X1:%.*]] = extractvalue { <2 x float>, <2 x float> } [[DX]], 1
+; CHECK-NEXT:    [[R0:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X0]]) #[[ATTR2:[0-9]+]]
+; CHECK-NEXT:    [[R1:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X1]]) #[[ATTR2]]
+; CHECK-NEXT:    [[R:%.*]] = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> [[R0]], <2 x float> [[R1]])
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %dx = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %x)
+  %x0 = extractvalue { <2 x float>, <2 x float> } %dx, 0
+  %x1 = extractvalue { <2 x float>, <2 x float> } %dx, 1
+  %r0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %x0) convergent
+  %r1 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %x1) convergent
+  %r = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %r0, <2 x float> %r1)
+  ret <4 x float> %r
+}
+
+declare { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float>)
+declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
+declare <4 x float> @llvm.vector.interleave2.v4f32(<2 x float>, <2 x float>)
+
+declare { <2 x double>, <2 x double>, <2 x double> } @llvm.vector.deinterleave3.v6f64(<6 x double>)
+declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>)
+declare <6 x double> @llvm.vector.interleave3.v6f64(<2 x double>, <2 x double>, <2 x double>)
+declare { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32>)
+declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3.v6i32(<6 x i32>)
+declare <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32>, <2 x i32>)
diff --git a/llvm/test/Transforms/VectorCombine/deinterleave-interleave-reverse-chain.ll b/llvm/test/Transforms/VectorCombine/deinterleave-interleave-reverse-chain.ll
new file mode 100644
index 0000000000000..71918370c80ed
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/deinterleave-interleave-reverse-chain.ll
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mtriple=aarch64-linux-gnu -S -passes=vector-combine < %s | FileCheck %s
+
+define <16 x float> @shuffle_reverse_fneg(<16 x float> %x) {
+; CHECK-LABEL: define <16 x float> @shuffle_reverse_fneg(
+; CHECK-SAME: <16 x float> [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = fneg <16 x float> [[X]]
+; CHECK-NEXT:    [[R:%.*]] = call <16 x float> @llvm.vector.reverse.v16f32(<16 x float> [[TMP1]])
+; CHECK-NEXT:    ret <16 x float> [[R]]
+;
+  %d = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave4.v16f32(<16 x float> %x)
+  %f0 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %d, 0
+  %f1 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %d, 1
+  %f2 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %d, 2
+  %f3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %d, 3
+  %n0 = fneg <4 x float> %f0
+  %n1 = fneg <4 x float> %f1
+  %n2 = fneg <4 x float> %f2
+  %n3 = fneg <4 x float> %f3
+  %r0 = shufflevector <4 x float> %n0, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r1 = shufflevector <4 x float> %n1, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r2 = shufflevector <4 x float> %n2, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r3 = shufflevector <4 x float> %n3, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r = call <16 x float> @llvm.vector.interleave4.v16f32(<4 x float> %r3, <4 x float> %r2, <4 x float> %r1, <4 x float> %r0)
+  ret <16 x float> %r
+}
+
+define <vscale x 8 x float> @intrinsic_reverse_fneg(<vscale x 8 x float> %x) {
+; CHECK-LABEL: define <vscale x 8 x float> @intrinsic_reverse_fneg(
+; CHECK-SAME: <vscale x 8 x float> [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = fneg <vscale x 8 x float> [[X]]
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 8 x float> @llvm.vector.reverse.nxv8f32(<vscale x 8 x float> [[TMP1]])
+; CHECK-NEXT:    ret <vscale x 8 x float> [[R]]
+;
+  %d = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %x)
+  %f0 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %d, 0
+  %f1 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %d, 1
+  %n0 = fneg <vscale x 4 x float> %f0
+  %n1 = fneg <vscale x 4 x float> %f1
+  %r0 = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %n0)
+  %r1 = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %n1)
+  %r = call <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %r1, <vscale x 4 x float> %r0)
+  ret <vscale x 8 x float> %r
+}
+
+define <8 x float> @negative_same_field_order(<8 x float> %x) {
+; CHECK-LABEL: define <8 x float> @negative_same_field_order(
+; CHECK-SAME: <8 x float> [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x float> @llvm.vector.reverse.v8f32(<8 x float> [[X]])
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+; CHECK-NEXT:    ret <8 x float> [[R]]
+;
+  %d = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %x)
+  %f0 = extractvalue { <4 x float>, <4 x float> } %d, 0
+  %f1 = extractvalue { <4 x float>, <4 x float> } %d, 1
+  %r0 = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %f0)
+  %r1 = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %f1)
+  %r = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %r0, <4 x float> %r1)
+  ret <8 x float> %r
+}
diff --git a/llvm/test/Transforms/VectorCombine/interleave-elementwise.ll b/llvm/test/Transforms/VectorCombine/interleave-elementwise.ll
new file mode 100644
index 0000000000000..ed7e24b7f1fbd
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/interleave-elementwise.ll
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes=vector-combine %s | FileCheck %s
+
+define { <4 x float>, <4 x float> } @shared_interleave_dag(
+; CHECK-LABEL: define { <4 x float>, <4 x float> } @shared_interleave_dag(
+; CHECK-SAME: <4 x float> [[CHANGE:%.*]], <4 x float> [[WEIGHT:%.*]], <4 x float> [[CUMULATIVE:%.*]], <2 x float> [[MID:%.*]], <2 x float> [[ERROR:%.*]]) {
+; CHECK-NEXT:    [[CHANGE_PARTS:%.*]] = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> [[CHANGE]])
+; CHECK-NEXT:    [[CHANGE_0:%.*]] = extractvalue { <2 x float>, <2 x float> } [[CHANGE_PARTS]], 0
+; CHECK-NEXT:    [[CHANGE_1:%.*]] = extractvalue { <2 x float>, <2 x float> } [[CHANGE_PARTS]], 1
+; CHECK-NEXT:    [[WEIGHT_PARTS:%.*]] = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> [[WEIGHT]])
+; CHECK-NEXT:    [[WEIGHT_0:%.*]] = extractvalue { <2 x float>, <2 x float> } [[WEIGHT_PARTS]], 0
+; CHECK-NEXT:    [[WEIGHT_1:%.*]] = extractvalue { <2 x float>, <2 x float> } [[WEIGHT_PARTS]], 1
+; CHECK-NEXT:    [[CUMULATIVE_PARTS:%.*]] = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> [[CUMULATIVE]])
+; CHECK-NEXT:    [[CUMULATIVE_0:%.*]] = extractvalue { <2 x float>, <2 x float> } [[CUMULATIVE_PARTS]], 0
+; CHECK-NEXT:    [[CUMULATIVE_1:%.*]] = extractvalue { <2 x float>, <2 x float> } [[CUMULATIVE_PARTS]], 1
+; CHECK-NEXT:    [[SCALED_ERROR:%.*]] = fmul <2 x float> [[ERROR]], splat (float 2.000000e+00)
+; CHECK-NEXT:    [[MID_0:%.*]] = shufflevector <2 x float> [[MID]], <2 x float> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[MID_1:%.*]] = shufflevector <2 x float> [[MID]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT:    [[BASE_0:%.*]] = fmul <2 x float> [[MID_0]], [[SCALED_ERROR]]
+; CHECK-NEXT:    [[BASE_1:%.*]] = fmul <2 x float> [[MID_1]], [[SCALED_ERROR]]
+; CHECK-NEXT:    [[DELTA_0:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[CHANGE_0]], <2 x float> splat (float 2.000000e+00), <2 x float> [[BASE_0]])
+; CHECK-NEXT:    [[DELTA_1:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[CHANGE_1]], <2 x float> splat (float 2.000000e+00), <2 x float> [[BASE_1]])
+; CHECK-NEXT:    [[NEW_WEIGHT_0:%.*]] = fadd <2 x float> [[WEIGHT_0]], [[DELTA_0]]
+; CHECK-NEXT:    [[NEW_WEIGHT_1:%.*]] = fadd <2 x float> [[WEIGHT_1]], [[DELTA_1]]
+; CHECK-NEXT:    [[NEW_WEIGHT:%.*]] = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> [[NEW_WEIGHT_0]], <2 x float> [[NEW_WEIGHT_1]])
+; CHECK-NEXT:    [[NEW_CUMULATIVE_0:%.*]] = fadd <2 x float> [[CUMULATIVE_0]], [[DELTA_0]]
+; CHECK-NEXT:    [[NEW_CUMULATIVE_1:%.*]] = fadd <2 x float> [[CUMULATIVE_1]], [[DELTA_1]]
+; CHECK-NEXT:    [[NEW_CUMULATIVE:%.*]] = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> [[NEW_CUMULATIVE_0]], <2 x float> [[NEW_CUMULATIVE_1]])
+; CHECK-NEXT:    [[RESULT_0:%.*]] = insertvalue { <4 x float>, <4 x float> } poison, <4 x float> [[NEW_WEIGHT]], 0
+; CHECK-NEXT:    [[RESULT_1:%.*]] = insertvalue { <4 x float>, <4 x float> } [[RESULT_0]], <4 x float> [[NEW_CUMULATIVE]], 1
+; CHECK-NEXT:    ret { <4 x float>, <4 x float> } [[RESULT_1]]
+;
+  <4 x float> %change, <4 x float> %weight, <4 x float> %cumulative,
+  <2 x float> %mid, <2 x float> %error) {
+  %change.parts = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %change)
+  %change.0 = extractvalue { <2 x float>, <2 x float> } %change.parts, 0
+  %change.1 = extractvalue { <2 x float>, <2 x float> } %change.parts, 1
+  %weight.parts = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %weight)
+  %weight.0 = extractvalue { <2 x float>, <2 x float> } %weight.parts, 0
+  %weight.1 = extractvalue { <2 x float>, <2 x float> } %weight.parts, 1
+  %cumulative.parts = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %cumulative)
+  %cumulative.0 = extractvalue { <2 x float>, <2 x float> } %cumulative.parts, 0
+  %cumulative.1 = extractvalue { <2 x float>, <2 x float> } %cumulative.parts, 1
+  %scaled.error = fmul <2 x float> %error, splat (float 2.0)
+  %mid.0 = shufflevector <2 x float> %mid, <2 x float> poison, <2 x i32> zeroinitializer
+  %mid.1 = shufflevector <2 x float> %mid, <2 x float> poison, <2 x i32> splat (i32 1)
+  %base.0 = fmul <2 x float> %mid.0, %scaled.error
+  %base.1 = fmul <2 x float> %mid.1, %scaled.error
+  %delta.0 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %change.0, <2 x float> splat (float 2.0), <2 x float> %base.0)
+  %delta.1 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %change.1, <2 x float> splat (float 2.0), <2 x float> %base.1)
+  %new.weight.0 = fadd <2 x float> %weight.0, %delta.0
+  %new.weight.1 = fadd <2 x float> %weight.1, %delta.1
+  %new.weight = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %new.weight.0, <2 x float> %new.weight.1)
+  %new.cumulative.0 = fadd <2 x float> %cumulative.0, %delta.0
+  %new.cumulative.1 = fadd <2 x float> %cumulative.1, %delta.1
+  %new.cumulative = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %new.cumulative.0, <2 x float> %new.cumulative.1)
+  %result.0 = insertvalue { <4 x float>, <4 x float> } poison, <4 x float> %new.weight, 0
+  %result.1 = insertvalue { <4 x float>, <4 x float> } %result.0, <4 x float> %new.cumulative, 1
+  ret { <4 x float>, <4 x float> } %result.1
+}
+
+define { <vscale x 4 x i32>, <vscale x 4 x i32> } @scalable_shared_interleave_dag(
+; CHECK-LABEL: define { <vscale x 4 x i32>, <vscale x 4 x i32> } @scalable_shared_interleave_dag(
+; CHECK-SAME: <vscale x 4 x i32> [[CHANGE:%.*]], <vscale x 4 x i32> [[WEIGHT:%.*]], <vscale x 4 x i32> [[CUMULATIVE:%.*]]) {
+; CHECK-NEXT:    [[CHANGE_PARTS:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> [[CHANGE]])
+; CHECK-NEXT:    [[CHANGE_0:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[CHANGE_PARTS]], 0
+; CHECK-NEXT:    [[CHANGE_1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[CHANGE_PARTS]], 1
+; CHECK-NEXT:    [[WEIGHT_PARTS:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> [[WEIGHT]])
+; CHECK-NEXT:    [[WEIGHT_0:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[WEIGHT_PARTS]], 0
+; CHECK-NEXT:    [[WEIGHT_1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[WEIGHT_PARTS]], 1
+; CHECK-NEXT:    [[CUMULATIVE_PARTS:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> [[CUMULATIVE]])
+; CHECK-NEXT:    [[CUMULATIVE_0:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[CUMULATIVE_PARTS]], 0
+; CHECK-NEXT:    [[CUMULATIVE_1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[CUMULATIVE_PARTS]], 1
+; CHECK-NEXT:    [[DELTA_0:%.*]] = add <vscale x 2 x i32> [[CHANGE_0]], splat (i32 7)
+; CHECK-NEXT:    [[DELTA_1:%.*]] = add <vscale x 2 x i32> [[CHANGE_1]], splat (i32 7)
+; CHECK-NEXT:    [[NEW_WEIGHT_0:%.*]] = add <vscale x 2 x i32> [[WEIGHT_0]], [[DELTA_0]]
+; CHECK-NEXT:    [[NEW_WEIGHT_1:%.*]] = add <vscale x 2 x i32> [[WEIGHT_1]], [[DELTA_1]]
+; CHECK-NEXT:    [[NEW_WEIGHT:%.*]] = call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> [[NEW_WEIGHT_0]], <vscale x 2 x i32> [[NEW_WEIGHT_1]])
+; CHECK-NEXT:    [[NEW_CUMULATIVE_0:%.*]] = add <vscale x 2 x i32> [[CUMULATIVE_0]], [[DELTA_0]]
+; CHECK-NEXT:    [[NEW_CUMULATIVE_1:%.*]] = add <vscale x 2 x i32> [[CUMULATIVE_1]], [[DELTA_1]]
+; CHECK-NEXT:    [[NEW_CUMULATIVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> [[NEW_CUMULATIVE_0]], <vscale x 2 x i32> [[NEW_CUMULATIVE_1]])
+; CHECK-NEXT:    [[RESULT_0:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> [[NEW_WEIGHT]], 0
+; CHECK-NEXT:    [[RESULT_1:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[RESULT_0]], <vscale x 4 x i32> [[NEW_CUMULATIVE]], 1
+; CHECK-NEXT:    ret { <vscale x 4 x i32>, <vscale x 4 x i32> } [[RESULT_1]]
+;
+  <vscale x 4 x i32> %change, <vscale x 4 x i32> %weight,
+  <vscale x 4 x i32> %cumulative) {
+  %change.parts = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %change)
+  %change.0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %change.parts, 0
+  %change.1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %change.parts, 1
+  %weight.parts = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %weight)
+  %weight.0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %weight.parts, 0
+  %weight.1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %weight.parts, 1
+  %cumulative.parts = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %cumulative)
+  %cumulative.0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %cumulative.parts, 0
+  %cumulative.1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %cumulative.parts, 1
+  %delta.0 = add <vscale x 2 x i32> %change.0, splat (i32 7)
+  %delta.1 = add <vscale x 2 x i32> %change.1, splat (i32 7)
+  %new.weight.0 = add <vscale x 2 x i32> %weight.0, %delta.0
+  %new.weight.1 = add <vscale x 2 x i32> %weight.1, %delta.1
+  %new.weight = call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %new.weight.0, <vscale x 2 x i32> %new.weight.1)
+  %new.cumulative.0 = add <vscale x 2 x i32> %cumulative.0, %delta.0
+  %new.cumulative.1 = add <vscale x 2 x i32> %cumulative.1, %delta.1
+  %new.cumulative = call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %new.cumulative.0, <vscale x 2 x i32> %new.cumulative.1)
+  %result.0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %new.weight, 0
+  %result.1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %result.0, <vscale x 4 x i32> %new.cumulative, 1
+  ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %result.1
+}
+
+; Do not introduce two new operand interleaves just to widen an operation.
+define <4 x i32> @negative_two_new_interleaves(<2 x i32> %a0,
+; CHECK-LABEL: define <4 x i32> @negative_two_new_interleaves(
+; CHECK-SAME: <2 x i32> [[A0:%.*]], <2 x i32> [[A1:%.*]], <2 x i32> [[B0:%.*]], <2 x i32> [[B1:%.*]]) {
+; CHECK-NEXT:    [[X0:%.*]] = add <2 x i32> [[A0]], [[B0]]
+; CHECK-NEXT:    [[X1:%.*]] = add <2 x i32> [[A1]], [[B1]]
+; CHECK-NEXT:    [[R:%.*]] = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> [[X0]], <2 x i32> [[X1]])
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  <2 x i32> %a1,
+  <2 x i32> %b0,
+  <2 x i32> %b1) {
+  %x0 = add <2 x i32> %a0, %b0
+  %x1 = add <2 x i32> %a1, %b1
+  %r = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %x0, <2 x i32> %x1)
+  ret <4 x i32> %r
+}
diff --git a/llvm/test/Transforms/VectorCombine/interleave-identical-operands.ll b/llvm/test/Transforms/VectorCombine/interleave-identical-operands.ll
new file mode 100644
index 0000000000000..971ff1d98a51e
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/interleave-identical-operands.ll
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes=vector-combine %s | FileCheck %s
+
+define <8 x i32> @interleave2_same_operand(<4 x i32> %x) {
+; CHECK-LABEL: define <8 x i32> @interleave2_same_operand(
+; CHECK-SAME: <4 x i32> [[X:%.*]]) {
+; CHECK-NEXT:    [[R:%.*]] = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> [[X]], <4 x i32> [[X]])
+; CHECK-NEXT:    ret <8 x i32> [[R]]
+;
+  %r = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %x, <4 x i32> %x)
+  ret <8 x i32> %r
+}
+
+define <16 x double> @interleave8_same_fmul_operand(<2 x double> %x) {
+; CHECK-LABEL: define <16 x double> @interleave8_same_fmul_operand(
+; CHECK-SAME: <2 x double> [[X:%.*]]) {
+; CHECK-NEXT:    [[MUL:%.*]] = fmul <2 x double> [[X]], splat (double f0x3FB70A3D70A3D70A)
+; CHECK-NEXT:    [[R:%.*]] = call <16 x double> @llvm.vector.interleave8.v16f64(<2 x double> [[MUL]], <2 x double> [[MUL]], <2 x double> [[MUL]], <2 x double> [[MUL]], <2 x double> [[MUL]], <2 x double> [[MUL]], <2 x double> [[MUL]], <2 x double> [[MUL]])
+; CHECK-NEXT:    ret <16 x double> [[R]]
+;
+  %mul = fmul <2 x double> %x, splat (double 0x3FB70A3D70A3D70A)
+  %r = call <16 x double> @llvm.vector.interleave8.v16f64(
+  <2 x double> %mul, <2 x double> %mul, <2 x double> %mul,
+  <2 x double> %mul, <2 x double> %mul, <2 x double> %mul,
+  <2 x double> %mul, <2 x double> %mul)
+  ret <16 x double> %r
+}
+
+define <16 x double> @interleave_splats(<4 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: define <16 x double> @interleave_splats(
+; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) {
+; CHECK-NEXT:    [[A0:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[A1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT:    [[A2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
+; CHECK-NEXT:    [[A3:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <2 x i32> <i32 3, i32 3>
+; CHECK-NEXT:    [[B0:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[B1:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT:    [[B2:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
+; CHECK-NEXT:    [[B3:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <2 x i32> <i32 3, i32 3>
+; CHECK-NEXT:    [[R:%.*]] = call <16 x double> @llvm.vector.interleave8.v16f64(<2 x double> [[A0]], <2 x double> [[A1]], <2 x double> [[A2]], <2 x double> [[A3]], <2 x double> [[B0]], <2 x double> [[B1]], <2 x double> [[B2]], <2 x double> [[B3]])
+; CHECK-NEXT:    ret <16 x double> [[R]]
+;
+  %a0 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> zeroinitializer
+  %a1 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> splat (i32 1)
+  %a2 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> splat (i32 2)
+  %a3 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> splat (i32 3)
+  %b0 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> zeroinitializer
+  %b1 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> splat (i32 1)
+  %b2 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> splat (i32 2)
+  %b3 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> splat (i32 3)
+  %r = call <16 x double> @llvm.vector.interleave8.v16f64(
+  <2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3,
+  <2 x double> %b0, <2 x double> %b1, <2 x double> %b2, <2 x double> %b3)
+  ret <16 x double> %r
+}
+
+define <4 x i32> @negative_interleave_partial_splats(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: define <4 x i32> @negative_interleave_partial_splats(
+; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]]) {
+; CHECK-NEXT:    [[A0:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> poison, <2 x i32> <i32 0, i32 poison>
+; CHECK-NEXT:    [[B0:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> [[A0]], <2 x i32> [[B0]])
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = shufflevector <2 x i32> %a, <2 x i32> poison, <2 x i32> <i32 0, i32 poison>
+  %b0 = shufflevector <2 x i32> %b, <2 x i32> poison, <2 x i32> zeroinitializer
+  %r = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a0, <2 x i32> %b0)
+  ret <4 x i32> %r
+}
+
+declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32>, <2 x i32>)
+declare <16 x double> @llvm.vector.interleave8.v16f64(<2 x double>, <2 x double>,
+  <2 x double>, <2 x double>,
+  <2 x double>, <2 x double>,
+  <2 x double>, <2 x double>)

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