[llvm] [AArch64][SelectionDAG] Fold SVE interleaves of splat vectors (PR #219146)

[Serval MARTINOT-LAGARDE via llvm-commits]

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@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
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Serval6 wrote:

Thanks, I removed this line

https://github.com/llvm/llvm-project/pull/219146