[llvm] [RISCV][GlobalISel] Fix fptosi/fptoui from half to i64 on RV32 (PR #222316)

[Kane Wang via llvm-commits]

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@@ -630,6 +630,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
       .customFor(ST.is64Bit() && ST.hasStdExtZfh(), {{s32, s16}})
       .widenScalarToNextPow2(0)
       .minScalar(0, s32)
+      // The magnitude of a half is at most 65504, so with Zfh use fcvt.w[u].h
+      // and extend the i32 result. Without Zfh, use the libcalls.
+      .libcallFor(!ST.hasStdExtZfh(), {{s64, s16}})
+      .narrowScalarFor({{s64, s16}}, changeTo(0, s32))
       .libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
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ReVe1uv wrote:

Currently bfloat values fail in the IRTranslator, so they never reach this rule and the s16 is always a half, but once bf16 is supported these rules would decode it as half and produce wrong code. I think it's best to revisit this once extended LLTs can express float types, and rewrite the s16 float rules here accordingly.

https://github.com/llvm/llvm-project/pull/222316