[llvm] [DAGCombiner] Fold anyext of a truncating build vector by recreating a wider build vector. (PR #214005)
Usman Nadeem via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 13 18:23:51 PDT 2026
https://github.com/UsmanNadeem updated https://github.com/llvm/llvm-project/pull/214005
>From da37fa9c37e18f5c6b08608bfd5fa1b909fb28f0 Mon Sep 17 00:00:00 2001
From: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: Tue, 4 Aug 2026 09:35:20 -0700
Subject: [PATCH] [DAGCombiner] Fold anyext of a truncating build vector by
recreating a wider build vector
Fixes some of the regressions from https://github.com/llvm/llvm-project/pull/212156
There is a reverse transfrom in AArch64 if the target is unable to create a valid shuffle from the build vector.
Change-Id: I0b9c56665369809a32318605c0610c4cdd907ab1
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 15 ++++
.../Target/AArch64/AArch64ISelLowering.cpp | 34 +++++++
.../CodeGen/AArch64/combine-storetomstore.ll | 60 ++++++-------
llvm/test/CodeGen/AArch64/sext.ll | 64 ++++++-------
.../AArch64/sve-masked-compressstore.ll | 90 +++++++++----------
...streaming-mode-fixed-length-masked-load.ll | 14 ++-
...treaming-mode-fixed-length-masked-store.ll | 12 ++-
llvm/test/CodeGen/AArch64/vector-compress.ll | 7 +-
llvm/test/CodeGen/X86/avx512-mask-op.ll | 34 +++----
9 files changed, 175 insertions(+), 155 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ca292fc81afa6..32f5a757d7adf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16818,6 +16818,21 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
return SCC;
}
+ // ty1 aext(ty2 build_vector()) -> ty1 build_vector().
+ // If a build vector is implicitly truncating its elements we can do the build
+ // vector in a wider type and get rid of the any extend. Since a build vector
+ // cannot be implicitly extending, the final type size must be <= size of the
+ // build vector's operands.
+ if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.hasOneUse() &&
+ VT.getScalarSizeInBits() <= N0.getOperand(0).getScalarValueSizeInBits() &&
+ (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))) {
+ // First try to see if the build vector can be optimized to something else.
+ if (SDValue SD = visitBUILD_VECTOR(N0.getNode()))
+ return DAG.getAnyExtOrTrunc(SD, DL, VT);
+
+ return DAG.getBuildVector(VT, DL, N0->ops());
+ }
+
if (SDValue NewCtPop = widenCtPop(N, DAG, DL))
return NewCtPop;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 99bcb5f50c134..fea4948fe3f97 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17145,6 +17145,34 @@ SDValue AArch64TargetLowering::LowerFixedLengthBuildVectorToSVE(
return convertFromScalableVector(DAG, VT, Vec);
}
+/// Try to recreate this build vector in half sized integer VT without losing
+/// data. This can work if all the extracts are from a smaller typed source
+/// vector.
+static SDValue getTruncatedBUILD_VECTOR(SDValue N, SelectionDAG &DAG) {
+ if (N.getOpcode() != ISD::BUILD_VECTOR)
+ return SDValue();
+
+ EVT VT = N.getValueType();
+ if (!VT.isInteger())
+ return SDValue();
+
+ EVT TruncatedTy = VT.changeElementType(
+ *DAG.getContext(),
+ VT.getVectorElementType().getHalfSizedIntegerVT(*DAG.getContext()));
+ if (!DAG.getTargetLoweringInfo().isTypeLegal(TruncatedTy))
+ return SDValue();
+
+ unsigned TruncEltSizeInBits = TruncatedTy.getScalarSizeInBits();
+ if (all_of(N->ops(), [&](SDValue Elem) {
+ return Elem.isUndef() ||
+ (Elem.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+ Elem.getOperand(0).getValueType().getScalarSizeInBits() <=
+ TruncEltSizeInBits);
+ }))
+ return DAG.getBuildVector(TruncatedTy, SDLoc(N), N->ops());
+ return SDValue();
+}
+
SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
@@ -17514,6 +17542,12 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
if (NumElts >= 4) {
if (SDValue Shuffle = ReconstructShuffle(Op, DAG))
return Shuffle;
+ else if (SDValue TruncBV = getTruncatedBUILD_VECTOR(Op, DAG)) {
+ // Try to see if we can get a valid shuffle from the build vector
+ // recreated in a smaller type.
+ if (SDValue Shuffle = ReconstructShuffle(TruncBV, DAG))
+ return DAG.getAnyExtOrTrunc(Shuffle, DL, VT);
+ }
if (SDValue Shuffle = ReconstructShuffleWithRuntimeMask(Op, DAG))
return Shuffle;
diff --git a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
index 35e1f3ea3020c..75d185fd6377f 100644
--- a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
@@ -472,64 +472,60 @@ define void @test_masked_store_success_v32i16(<32 x i16> %x, ptr %ptr, <32 x i1>
; SVE-NEXT: fmov s4, w9
; SVE-NEXT: ldr w9, [sp, #8]
; SVE-NEXT: fmov s5, w11
-; SVE-NEXT: mov v7.b[1], w2
+; SVE-NEXT: mov v7.h[1], w2
; SVE-NEXT: // kill: def $q2 killed $q2 def $z2
; SVE-NEXT: // kill: def $q3 killed $q3 def $z3
; SVE-NEXT: // kill: def $q1 killed $q1 def $z1
; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
; SVE-NEXT: fmov s6, w9
; SVE-NEXT: ldr w9, [sp, #152]
-; SVE-NEXT: mov v4.b[1], w8
+; SVE-NEXT: mov v4.h[1], w8
; SVE-NEXT: ldr w8, [sp, #16]
-; SVE-NEXT: mov v5.b[1], w10
-; SVE-NEXT: mov v6.b[1], w8
+; SVE-NEXT: mov v5.h[1], w10
+; SVE-NEXT: mov v6.h[1], w8
; SVE-NEXT: ldr w8, [sp, #88]
-; SVE-NEXT: mov v7.b[2], w3
-; SVE-NEXT: mov v4.b[2], w8
+; SVE-NEXT: mov v7.h[2], w3
+; SVE-NEXT: mov v4.h[2], w8
; SVE-NEXT: ldr w8, [sp, #24]
-; SVE-NEXT: mov v5.b[2], w9
+; SVE-NEXT: mov v5.h[2], w9
; SVE-NEXT: ldr w9, [sp, #160]
-; SVE-NEXT: mov v6.b[2], w8
+; SVE-NEXT: mov v6.h[2], w8
; SVE-NEXT: ldr w8, [sp, #96]
-; SVE-NEXT: mov v7.b[3], w4
-; SVE-NEXT: mov v4.b[3], w8
+; SVE-NEXT: mov v7.h[3], w4
+; SVE-NEXT: mov v4.h[3], w8
; SVE-NEXT: ldr w8, [sp, #32]
-; SVE-NEXT: mov v5.b[3], w9
+; SVE-NEXT: mov v5.h[3], w9
; SVE-NEXT: ldr w9, [sp, #168]
-; SVE-NEXT: mov v6.b[3], w8
+; SVE-NEXT: mov v6.h[3], w8
; SVE-NEXT: ldr w8, [sp, #104]
-; SVE-NEXT: mov v7.b[4], w5
-; SVE-NEXT: mov v4.b[4], w8
+; SVE-NEXT: mov v7.h[4], w5
+; SVE-NEXT: mov v4.h[4], w8
; SVE-NEXT: ldr w8, [sp, #40]
-; SVE-NEXT: mov v5.b[4], w9
+; SVE-NEXT: mov v5.h[4], w9
; SVE-NEXT: ldr w9, [sp, #176]
-; SVE-NEXT: mov v6.b[4], w8
+; SVE-NEXT: mov v6.h[4], w8
; SVE-NEXT: ldr w8, [sp, #112]
-; SVE-NEXT: mov v7.b[5], w6
-; SVE-NEXT: mov v4.b[5], w8
+; SVE-NEXT: mov v7.h[5], w6
+; SVE-NEXT: mov v4.h[5], w8
; SVE-NEXT: ldr w8, [sp, #48]
-; SVE-NEXT: mov v5.b[5], w9
+; SVE-NEXT: mov v5.h[5], w9
; SVE-NEXT: ldr w9, [sp, #184]
-; SVE-NEXT: mov v6.b[5], w8
+; SVE-NEXT: mov v6.h[5], w8
; SVE-NEXT: ldr w8, [sp, #120]
-; SVE-NEXT: mov v7.b[6], w7
-; SVE-NEXT: mov v4.b[6], w8
+; SVE-NEXT: mov v7.h[6], w7
+; SVE-NEXT: mov v4.h[6], w8
; SVE-NEXT: ldr w8, [sp, #56]
-; SVE-NEXT: mov v5.b[6], w9
+; SVE-NEXT: mov v5.h[6], w9
; SVE-NEXT: ldr w9, [sp, #192]
-; SVE-NEXT: mov v6.b[6], w8
+; SVE-NEXT: mov v6.h[6], w8
; SVE-NEXT: ldr w8, [sp, #128]
-; SVE-NEXT: mov v4.b[7], w8
+; SVE-NEXT: mov v4.h[7], w8
; SVE-NEXT: ldr w8, [sp, #64]
-; SVE-NEXT: mov v5.b[7], w9
+; SVE-NEXT: mov v5.h[7], w9
; SVE-NEXT: ldr w9, [sp]
-; SVE-NEXT: mov v6.b[7], w8
+; SVE-NEXT: mov v6.h[7], w8
; SVE-NEXT: mov x8, #16 // =0x10
-; SVE-NEXT: mov v7.b[7], w9
-; SVE-NEXT: ushll v4.8h, v4.8b, #0
-; SVE-NEXT: ushll v5.8h, v5.8b, #0
-; SVE-NEXT: ushll v6.8h, v6.8b, #0
-; SVE-NEXT: ushll v7.8h, v7.8b, #0
+; SVE-NEXT: mov v7.h[7], w9
; SVE-NEXT: shl v4.8h, v4.8h, #15
; SVE-NEXT: shl v5.8h, v5.8h, #15
; SVE-NEXT: shl v6.8h, v6.8h, #15
diff --git a/llvm/test/CodeGen/AArch64/sext.ll b/llvm/test/CodeGen/AArch64/sext.ll
index 278731ad0663a..f1fae4aafd26a 100644
--- a/llvm/test/CodeGen/AArch64/sext.ll
+++ b/llvm/test/CodeGen/AArch64/sext.ll
@@ -239,9 +239,8 @@ define <3 x i32> @sext_v3i8_v3i32(<3 x i8> %a) {
; CHECK-SD-LABEL: sext_v3i8_v3i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: mov v0.h[1], w1
-; CHECK-SD-NEXT: mov v0.h[2], w2
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: mov v0.s[1], w1
+; CHECK-SD-NEXT: mov v0.s[2], w2
; CHECK-SD-NEXT: shl v0.4s, v0.4s, #24
; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #24
; CHECK-SD-NEXT: ret
@@ -398,9 +397,8 @@ define <3 x i32> @sext_v3i10_v3i32(<3 x i10> %a) {
; CHECK-SD-LABEL: sext_v3i10_v3i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: mov v0.h[1], w1
-; CHECK-SD-NEXT: mov v0.h[2], w2
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: mov v0.s[1], w1
+; CHECK-SD-NEXT: mov v0.s[2], w2
; CHECK-SD-NEXT: shl v0.4s, v0.4s, #22
; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #22
; CHECK-SD-NEXT: ret
@@ -1055,42 +1053,36 @@ entry:
define <16 x i32> @sext_v16i10_v16i32(<16 x i10> %a) {
; CHECK-SD-LABEL: sext_v16i10_v16i32:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ldr w8, [sp, #32]
-; CHECK-SD-NEXT: ldr w9, [sp]
; CHECK-SD-NEXT: fmov s0, w0
; CHECK-SD-NEXT: fmov s1, w4
-; CHECK-SD-NEXT: ldr w10, [sp, #40]
-; CHECK-SD-NEXT: ldr w11, [sp, #8]
-; CHECK-SD-NEXT: fmov s2, w9
-; CHECK-SD-NEXT: fmov s3, w8
-; CHECK-SD-NEXT: ldr w8, [sp, #48]
-; CHECK-SD-NEXT: mov v0.h[1], w1
-; CHECK-SD-NEXT: ldr w9, [sp, #16]
-; CHECK-SD-NEXT: mov v1.h[1], w5
-; CHECK-SD-NEXT: mov v2.h[1], w11
-; CHECK-SD-NEXT: mov v3.h[1], w10
-; CHECK-SD-NEXT: mov v0.h[2], w2
-; CHECK-SD-NEXT: mov v1.h[2], w6
-; CHECK-SD-NEXT: mov v2.h[2], w9
-; CHECK-SD-NEXT: mov v3.h[2], w8
-; CHECK-SD-NEXT: ldr w8, [sp, #56]
-; CHECK-SD-NEXT: ldr w9, [sp, #24]
-; CHECK-SD-NEXT: mov v0.h[3], w3
-; CHECK-SD-NEXT: mov v1.h[3], w7
-; CHECK-SD-NEXT: mov v2.h[3], w9
-; CHECK-SD-NEXT: mov v3.h[3], w8
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #0
-; CHECK-SD-NEXT: ushll v3.4s, v3.4h, #0
-; CHECK-SD-NEXT: shl v0.4s, v0.4s, #22
-; CHECK-SD-NEXT: shl v1.4s, v1.4s, #22
+; CHECK-SD-NEXT: ldr s2, [sp]
+; CHECK-SD-NEXT: ldr s3, [sp, #32]
+; CHECK-SD-NEXT: add x8, sp, #8
+; CHECK-SD-NEXT: add x9, sp, #40
+; CHECK-SD-NEXT: ld1 { v2.s }[1], [x8]
+; CHECK-SD-NEXT: add x8, sp, #16
+; CHECK-SD-NEXT: mov v0.s[1], w1
+; CHECK-SD-NEXT: mov v1.s[1], w5
+; CHECK-SD-NEXT: ld1 { v3.s }[1], [x9]
+; CHECK-SD-NEXT: add x9, sp, #48
+; CHECK-SD-NEXT: ld1 { v2.s }[2], [x8]
+; CHECK-SD-NEXT: add x8, sp, #24
+; CHECK-SD-NEXT: ld1 { v3.s }[2], [x9]
+; CHECK-SD-NEXT: add x9, sp, #56
+; CHECK-SD-NEXT: mov v0.s[2], w2
+; CHECK-SD-NEXT: mov v1.s[2], w6
+; CHECK-SD-NEXT: ld1 { v2.s }[3], [x8]
+; CHECK-SD-NEXT: ld1 { v3.s }[3], [x9]
+; CHECK-SD-NEXT: mov v0.s[3], w3
+; CHECK-SD-NEXT: mov v1.s[3], w7
; CHECK-SD-NEXT: shl v2.4s, v2.4s, #22
; CHECK-SD-NEXT: shl v3.4s, v3.4s, #22
-; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #22
-; CHECK-SD-NEXT: sshr v1.4s, v1.4s, #22
; CHECK-SD-NEXT: sshr v2.4s, v2.4s, #22
+; CHECK-SD-NEXT: shl v0.4s, v0.4s, #22
+; CHECK-SD-NEXT: shl v1.4s, v1.4s, #22
; CHECK-SD-NEXT: sshr v3.4s, v3.4s, #22
+; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #22
+; CHECK-SD-NEXT: sshr v1.4s, v1.4s, #22
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sext_v16i10_v16i32:
diff --git a/llvm/test/CodeGen/AArch64/sve-masked-compressstore.ll b/llvm/test/CodeGen/AArch64/sve-masked-compressstore.ll
index b6fa9ea943c75..03bb81498be92 100644
--- a/llvm/test/CodeGen/AArch64/sve-masked-compressstore.ll
+++ b/llvm/test/CodeGen/AArch64/sve-masked-compressstore.ll
@@ -423,42 +423,41 @@ define void @test_compressstore_v8i32(ptr %p, <8 x i32> %vec, <8 x i1> %mask) {
; CHECK-SME2p2-STREAMING: // %bb.0:
; CHECK-SME2p2-STREAMING-NEXT: sub sp, sp, #16
; CHECK-SME2p2-STREAMING-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SME2p2-STREAMING-NEXT: mov z3.b, z2.b[7]
-; CHECK-SME2p2-STREAMING-NEXT: mov z4.b, z2.b[6]
-; CHECK-SME2p2-STREAMING-NEXT: mov z5.b, z2.b[5]
-; CHECK-SME2p2-STREAMING-NEXT: mov z6.b, z2.b[4]
-; CHECK-SME2p2-STREAMING-NEXT: mov z7.b, z2.b[1]
-; CHECK-SME2p2-STREAMING-NEXT: mov z16.b, z2.b[2]
-; CHECK-SME2p2-STREAMING-NEXT: mov z17.b, z2.b[3]
+; CHECK-SME2p2-STREAMING-NEXT: mov z3.b, z2.b[1]
+; CHECK-SME2p2-STREAMING-NEXT: mov z4.b, z2.b[2]
+; CHECK-SME2p2-STREAMING-NEXT: mov z5.b, z2.b[3]
+; CHECK-SME2p2-STREAMING-NEXT: mov z6.b, z2.b[7]
+; CHECK-SME2p2-STREAMING-NEXT: mov z7.b, z2.b[6]
+; CHECK-SME2p2-STREAMING-NEXT: mov z16.b, z2.b[5]
+; CHECK-SME2p2-STREAMING-NEXT: mov z17.b, z2.b[4]
; CHECK-SME2p2-STREAMING-NEXT: fmov w8, s2
; CHECK-SME2p2-STREAMING-NEXT: ptrue p0.s, vl4
-; CHECK-SME2p2-STREAMING-NEXT: zip1 z3.h, z4.h, z3.h
-; CHECK-SME2p2-STREAMING-NEXT: zip1 z4.h, z6.h, z5.h
-; CHECK-SME2p2-STREAMING-NEXT: zip1 z6.h, z2.h, z7.h
-; CHECK-SME2p2-STREAMING-NEXT: fmov w9, s7
+; CHECK-SME2p2-STREAMING-NEXT: zip1 z18.h, z4.h, z5.h
+; CHECK-SME2p2-STREAMING-NEXT: zip1 z19.h, z2.h, z3.h
+; CHECK-SME2p2-STREAMING-NEXT: fmov w9, s3
+; CHECK-SME2p2-STREAMING-NEXT: zip1 z6.s, z7.s, z6.s
; CHECK-SME2p2-STREAMING-NEXT: and w8, w8, #0x1
-; CHECK-SME2p2-STREAMING-NEXT: zip1 z5.h, z16.h, z17.h
-; CHECK-SME2p2-STREAMING-NEXT: zip1 z3.s, z4.s, z3.s
+; CHECK-SME2p2-STREAMING-NEXT: zip1 z7.s, z17.s, z16.s
; CHECK-SME2p2-STREAMING-NEXT: bfi w8, w9, #1, #1
-; CHECK-SME2p2-STREAMING-NEXT: fmov w9, s16
-; CHECK-SME2p2-STREAMING-NEXT: zip1 z4.s, z6.s, z5.s
-; CHECK-SME2p2-STREAMING-NEXT: uunpklo z3.s, z3.h
+; CHECK-SME2p2-STREAMING-NEXT: zip1 z16.s, z19.s, z18.s
+; CHECK-SME2p2-STREAMING-NEXT: fmov w9, s4
+; CHECK-SME2p2-STREAMING-NEXT: zip1 z6.d, z7.d, z6.d
+; CHECK-SME2p2-STREAMING-NEXT: uunpklo z7.s, z16.h
; CHECK-SME2p2-STREAMING-NEXT: bfi w8, w9, #2, #1
-; CHECK-SME2p2-STREAMING-NEXT: fmov w9, s17
-; CHECK-SME2p2-STREAMING-NEXT: uunpklo z4.s, z4.h
+; CHECK-SME2p2-STREAMING-NEXT: fmov w9, s5
+; CHECK-SME2p2-STREAMING-NEXT: lsl z6.s, z6.s, #31
; CHECK-SME2p2-STREAMING-NEXT: orr w8, w8, w9, lsl #3
-; CHECK-SME2p2-STREAMING-NEXT: lsl z3.s, z3.s, #31
-; CHECK-SME2p2-STREAMING-NEXT: lsl z4.s, z4.s, #31
+; CHECK-SME2p2-STREAMING-NEXT: lsl z7.s, z7.s, #31
+; CHECK-SME2p2-STREAMING-NEXT: asr z2.s, z6.s, #31
; CHECK-SME2p2-STREAMING-NEXT: and w8, w8, #0xf
-; CHECK-SME2p2-STREAMING-NEXT: asr z2.s, z3.s, #31
-; CHECK-SME2p2-STREAMING-NEXT: asr z3.s, z4.s, #31
+; CHECK-SME2p2-STREAMING-NEXT: asr z3.s, z7.s, #31
; CHECK-SME2p2-STREAMING-NEXT: cmpne p1.s, p0/z, z2.s, #0
; CHECK-SME2p2-STREAMING-NEXT: fmov s2, w8
; CHECK-SME2p2-STREAMING-NEXT: cmpne p2.s, p0/z, z3.s, #0
; CHECK-SME2p2-STREAMING-NEXT: ptrue p0.s
-; CHECK-SME2p2-STREAMING-NEXT: cnt z2.s, p0/z, z2.s
; CHECK-SME2p2-STREAMING-NEXT: cntp x9, p1, p1.s
; CHECK-SME2p2-STREAMING-NEXT: compact z1.s, p1, z1.s
+; CHECK-SME2p2-STREAMING-NEXT: cnt z2.s, p0/z, z2.s
; CHECK-SME2p2-STREAMING-NEXT: fmov w10, s2
; CHECK-SME2p2-STREAMING-NEXT: cntp x8, p2, p2.s
; CHECK-SME2p2-STREAMING-NEXT: compact z0.s, p2, z0.s
@@ -474,44 +473,43 @@ define void @test_compressstore_v8i32(ptr %p, <8 x i32> %vec, <8 x i1> %mask) {
; CHECK-STREAMING-COMPAT-NEXT: sub sp, sp, #16
; CHECK-STREAMING-COMPAT-NEXT: .cfi_def_cfa_offset 16
; CHECK-STREAMING-COMPAT-NEXT: // kill: def $d2 killed $d2 def $z2
-; CHECK-STREAMING-COMPAT-NEXT: mov z3.b, z2.b[7]
-; CHECK-STREAMING-COMPAT-NEXT: mov z4.b, z2.b[6]
+; CHECK-STREAMING-COMPAT-NEXT: mov z3.b, z2.b[1]
+; CHECK-STREAMING-COMPAT-NEXT: mov z4.b, z2.b[2]
; CHECK-STREAMING-COMPAT-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-STREAMING-COMPAT-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-STREAMING-COMPAT-NEXT: mov z5.b, z2.b[5]
-; CHECK-STREAMING-COMPAT-NEXT: mov z6.b, z2.b[4]
-; CHECK-STREAMING-COMPAT-NEXT: mov z7.b, z2.b[1]
-; CHECK-STREAMING-COMPAT-NEXT: mov z16.b, z2.b[2]
-; CHECK-STREAMING-COMPAT-NEXT: mov z17.b, z2.b[3]
+; CHECK-STREAMING-COMPAT-NEXT: mov z5.b, z2.b[3]
+; CHECK-STREAMING-COMPAT-NEXT: mov z6.b, z2.b[7]
+; CHECK-STREAMING-COMPAT-NEXT: mov z7.b, z2.b[6]
+; CHECK-STREAMING-COMPAT-NEXT: mov z16.b, z2.b[5]
+; CHECK-STREAMING-COMPAT-NEXT: mov z17.b, z2.b[4]
; CHECK-STREAMING-COMPAT-NEXT: fmov w8, s2
; CHECK-STREAMING-COMPAT-NEXT: ptrue p0.s, vl4
-; CHECK-STREAMING-COMPAT-NEXT: zip1 z3.h, z4.h, z3.h
-; CHECK-STREAMING-COMPAT-NEXT: zip1 z4.h, z6.h, z5.h
-; CHECK-STREAMING-COMPAT-NEXT: zip1 z6.h, z2.h, z7.h
-; CHECK-STREAMING-COMPAT-NEXT: fmov w9, s7
+; CHECK-STREAMING-COMPAT-NEXT: zip1 z18.h, z4.h, z5.h
+; CHECK-STREAMING-COMPAT-NEXT: zip1 z19.h, z2.h, z3.h
+; CHECK-STREAMING-COMPAT-NEXT: fmov w9, s3
+; CHECK-STREAMING-COMPAT-NEXT: zip1 z6.s, z7.s, z6.s
; CHECK-STREAMING-COMPAT-NEXT: and w8, w8, #0x1
-; CHECK-STREAMING-COMPAT-NEXT: zip1 z5.h, z16.h, z17.h
-; CHECK-STREAMING-COMPAT-NEXT: zip1 z3.s, z4.s, z3.s
+; CHECK-STREAMING-COMPAT-NEXT: zip1 z7.s, z17.s, z16.s
; CHECK-STREAMING-COMPAT-NEXT: bfi w8, w9, #1, #1
-; CHECK-STREAMING-COMPAT-NEXT: fmov w9, s16
-; CHECK-STREAMING-COMPAT-NEXT: zip1 z4.s, z6.s, z5.s
-; CHECK-STREAMING-COMPAT-NEXT: uunpklo z3.s, z3.h
+; CHECK-STREAMING-COMPAT-NEXT: zip1 z16.s, z19.s, z18.s
+; CHECK-STREAMING-COMPAT-NEXT: fmov w9, s4
+; CHECK-STREAMING-COMPAT-NEXT: zip1 z6.d, z7.d, z6.d
+; CHECK-STREAMING-COMPAT-NEXT: uunpklo z7.s, z16.h
; CHECK-STREAMING-COMPAT-NEXT: bfi w8, w9, #2, #1
-; CHECK-STREAMING-COMPAT-NEXT: fmov w9, s17
-; CHECK-STREAMING-COMPAT-NEXT: uunpklo z4.s, z4.h
+; CHECK-STREAMING-COMPAT-NEXT: fmov w9, s5
+; CHECK-STREAMING-COMPAT-NEXT: lsl z6.s, z6.s, #31
; CHECK-STREAMING-COMPAT-NEXT: orr w8, w8, w9, lsl #3
-; CHECK-STREAMING-COMPAT-NEXT: lsl z3.s, z3.s, #31
-; CHECK-STREAMING-COMPAT-NEXT: lsl z4.s, z4.s, #31
+; CHECK-STREAMING-COMPAT-NEXT: lsl z7.s, z7.s, #31
+; CHECK-STREAMING-COMPAT-NEXT: asr z2.s, z6.s, #31
; CHECK-STREAMING-COMPAT-NEXT: and w8, w8, #0xf
-; CHECK-STREAMING-COMPAT-NEXT: asr z2.s, z3.s, #31
-; CHECK-STREAMING-COMPAT-NEXT: asr z3.s, z4.s, #31
+; CHECK-STREAMING-COMPAT-NEXT: asr z3.s, z7.s, #31
; CHECK-STREAMING-COMPAT-NEXT: cmpne p1.s, p0/z, z2.s, #0
; CHECK-STREAMING-COMPAT-NEXT: fmov s2, w8
; CHECK-STREAMING-COMPAT-NEXT: cmpne p2.s, p0/z, z3.s, #0
; CHECK-STREAMING-COMPAT-NEXT: ptrue p0.s
-; CHECK-STREAMING-COMPAT-NEXT: cnt z2.s, p0/z, z2.s
; CHECK-STREAMING-COMPAT-NEXT: cntp x9, p1, p1.s
; CHECK-STREAMING-COMPAT-NEXT: compact z1.s, p1, z1.s
+; CHECK-STREAMING-COMPAT-NEXT: cnt z2.s, p0/z, z2.s
; CHECK-STREAMING-COMPAT-NEXT: fmov w10, s2
; CHECK-STREAMING-COMPAT-NEXT: cntp x8, p2, p2.s
; CHECK-STREAMING-COMPAT-NEXT: compact z0.s, p2, z0.s
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
index 583dde21d054d..4bbc79d7f0c41 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
@@ -2323,14 +2323,12 @@ define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) {
; CHECK-NEXT: mov z6.b, z0.b[5]
; CHECK-NEXT: mov z7.b, z0.b[4]
; CHECK-NEXT: ptrue p0.s, vl4
-; CHECK-NEXT: zip1 z1.h, z2.h, z1.h
-; CHECK-NEXT: zip1 z0.h, z0.h, z3.h
-; CHECK-NEXT: zip1 z2.h, z5.h, z4.h
-; CHECK-NEXT: zip1 z3.h, z7.h, z6.h
-; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-NEXT: zip1 z1.s, z3.s, z2.s
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: zip1 z1.s, z2.s, z1.s
+; CHECK-NEXT: zip1 z0.s, z0.s, z3.s
+; CHECK-NEXT: zip1 z2.s, z5.s, z4.s
+; CHECK-NEXT: zip1 z3.s, z7.s, z6.s
+; CHECK-NEXT: zip1 z0.d, z0.d, z1.d
+; CHECK-NEXT: zip1 z1.d, z3.d, z2.d
; CHECK-NEXT: lsl z0.s, z0.s, #31
; CHECK-NEXT: lsl z1.s, z1.s, #31
; CHECK-NEXT: asr z0.s, z0.s, #31
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
index 0fa6fca1065c6..afc7e5b22fb5b 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
@@ -1020,14 +1020,12 @@ define void @masked_store_v8f32(ptr %dst, <8 x i1> %mask) {
; CHECK-NEXT: mov z6.b, z0.b[2]
; CHECK-NEXT: mov z7.b, z0.b[1]
; CHECK-NEXT: ptrue p0.s, vl4
-; CHECK-NEXT: zip1 z1.h, z2.h, z1.h
-; CHECK-NEXT: zip1 z2.h, z4.h, z3.h
-; CHECK-NEXT: zip1 z3.h, z6.h, z5.h
-; CHECK-NEXT: zip1 z0.h, z0.h, z7.h
; CHECK-NEXT: zip1 z1.s, z2.s, z1.s
-; CHECK-NEXT: zip1 z0.s, z0.s, z3.s
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: zip1 z2.s, z4.s, z3.s
+; CHECK-NEXT: zip1 z3.s, z6.s, z5.s
+; CHECK-NEXT: zip1 z0.s, z0.s, z7.s
+; CHECK-NEXT: zip1 z1.d, z2.d, z1.d
+; CHECK-NEXT: zip1 z0.d, z0.d, z3.d
; CHECK-NEXT: lsl z1.s, z1.s, #31
; CHECK-NEXT: lsl z0.s, z0.s, #31
; CHECK-NEXT: asr z1.s, z1.s, #31
diff --git a/llvm/test/CodeGen/AArch64/vector-compress.ll b/llvm/test/CodeGen/AArch64/vector-compress.ll
index 55c343164a1b8..74f38884fe9f6 100644
--- a/llvm/test/CodeGen/AArch64/vector-compress.ll
+++ b/llvm/test/CodeGen/AArch64/vector-compress.ll
@@ -413,10 +413,9 @@ define <3 x i32> @test_compress_narrow(<3 x i32> %vec, <3 x i1> %mask) {
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: mov x11, sp
; CHECK-NEXT: str s0, [sp]
-; CHECK-NEXT: mov.h v1[0], w0
-; CHECK-NEXT: mov.h v1[1], w1
-; CHECK-NEXT: mov.h v1[2], w2
-; CHECK-NEXT: ushll.4s v1, v1, #0
+; CHECK-NEXT: mov.s v1[0], w0
+; CHECK-NEXT: mov.s v1[1], w1
+; CHECK-NEXT: mov.s v1[2], w2
; CHECK-NEXT: shl.4s v1, v1, #31
; CHECK-NEXT: cmlt.4s v1, v1, #0
; CHECK-NEXT: mov.s w8, v1[1]
diff --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll
index 68ca43b05eaa6..bada3532502d8 100644
--- a/llvm/test/CodeGen/X86/avx512-mask-op.ll
+++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll
@@ -4356,22 +4356,18 @@ define <64 x i1> @mask64_insert(i32 %a) {
;
; SKX-LABEL: mask64_insert:
; SKX: ## %bb.0:
-; SKX-NEXT: andb $1, %dil
-; SKX-NEXT: cmpb $1, %dil
-; SKX-NEXT: movabsq $-562958543486980, %rax ## imm = 0xFFFDFFFDFFFDFFFC
-; SKX-NEXT: sbbq $-1, %rax
-; SKX-NEXT: kmovq %rax, %k0
-; SKX-NEXT: vpmovm2b %k0, %zmm0
+; SKX-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; SKX-NEXT: ## zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
+; SKX-NEXT: vpinsrb $0, %edi, %xmm0, %xmm1
+; SKX-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0
; SKX-NEXT: retq
;
; AVX512BW-LABEL: mask64_insert:
; AVX512BW: ## %bb.0:
-; AVX512BW-NEXT: andb $1, %dil
-; AVX512BW-NEXT: cmpb $1, %dil
-; AVX512BW-NEXT: movabsq $-562958543486980, %rax ## imm = 0xFFFDFFFDFFFDFFFC
-; AVX512BW-NEXT: sbbq $-1, %rax
-; AVX512BW-NEXT: kmovq %rax, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
+; AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; AVX512BW-NEXT: ## zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
+; AVX512BW-NEXT: vpinsrb $0, %edi, %xmm0, %xmm1
+; AVX512BW-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: mask64_insert:
@@ -4388,16 +4384,10 @@ define <64 x i1> @mask64_insert(i32 %a) {
;
; X86-LABEL: mask64_insert:
; X86: ## %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: andb $1, %al
-; X86-NEXT: cmpb $1, %al
-; X86-NEXT: movl $-131076, %eax ## imm = 0xFFFDFFFC
-; X86-NEXT: sbbl $-1, %eax
-; X86-NEXT: kmovd %eax, %k0
-; X86-NEXT: movl $-131075, %eax ## imm = 0xFFFDFFFD
-; X86-NEXT: kmovd %eax, %k1
-; X86-NEXT: kunpckdq %k0, %k1, %k0
-; X86-NEXT: vpmovm2b %k0, %zmm0
+; X86-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 = [1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; X86-NEXT: ## zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
+; X86-NEXT: vpinsrb $0, {{[0-9]+}}(%esp), %xmm0, %xmm1
+; X86-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0
; X86-NEXT: retl
%a_i = trunc i32 %a to i1
%maskv = insertelement <64 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0
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