[llvm] [AArch64] Make ImmInsnModel operands optional. NFC (PR #223280)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 13 14:32:57 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/223280
This helps make sure we do not use them incorrectly, and should allow them to
be checked for values in the future.
>From bb2544499c8d26b59e89e96726dfecbbd8acfb3a Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 13 Sep 2026 22:32:45 +0100
Subject: [PATCH] [AArch64] Make ImmInsnModel operands optional. NFC
This helps make sure we do not use them incorrectly, and should allow them to
be checked for values in the future.
---
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 16 ++++-----
llvm/lib/Target/AArch64/AArch64ExpandImm.cpp | 8 ++---
llvm/lib/Target/AArch64/AArch64ExpandImm.h | 4 +--
.../AArch64/AArch64ExpandPseudoInsts.cpp | 35 ++++++++++---------
.../Target/AArch64/AArch64ISelLowering.cpp | 4 +--
5 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index 9f88f4768a441..2a39aa63554d9 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -158,16 +158,16 @@ static InstructionListType createMOVImm(MCPhysReg DstReg, unsigned BitSize,
case AArch64::ORRXri:
case AArch64::ANDXri:
case AArch64::EORXri:
- if (I->Op1 == 0)
+ if (*I->Op1 == 0)
Insts.emplace_back(
MCInstBuilder(I->Opcode)
.addReg(DstReg)
.addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
- .addImm(I->Op2));
+ .addImm(*I->Op2));
else
Insts.emplace_back(
MCInstBuilder(I->Opcode).addReg(DstReg).addReg(DstReg).addImm(
- I->Op2));
+ *I->Op2));
break;
case AArch64::EORXrs:
case AArch64::EONXrs:
@@ -177,23 +177,23 @@ static InstructionListType createMOVImm(MCPhysReg DstReg, unsigned BitSize,
.addReg(DstReg)
.addReg(DstReg)
.addReg(DstReg)
- .addImm(I->Op2));
+ .addImm(*I->Op2));
break;
case AArch64::MOVNWi:
case AArch64::MOVNXi:
case AArch64::MOVZWi:
case AArch64::MOVZXi:
Insts.emplace_back(
- MCInstBuilder(I->Opcode).addReg(DstReg).addImm(I->Op1).addImm(
- I->Op2));
+ MCInstBuilder(I->Opcode).addReg(DstReg).addImm(*I->Op1).addImm(
+ *I->Op2));
break;
case AArch64::MOVKWi:
case AArch64::MOVKXi:
Insts.emplace_back(MCInstBuilder(I->Opcode)
.addReg(DstReg)
.addReg(DstReg)
- .addImm(I->Op1)
- .addImm(I->Op2));
+ .addImm(*I->Op1)
+ .addImm(*I->Op2));
break;
default:
llvm_unreachable("Unhandled! Please refer to expandMOVImm in llvm");
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp b/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
index 04c217ca34f00..a4ee6224f2861 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
@@ -232,9 +232,9 @@ static bool trySequenceOfOnes(uint64_t UImm,
return true;
// Create the second MOVK instruction.
- Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
- AArch64_AM::getShifterImm(AArch64_AM::LSL,
- SecondMovkIdx * 16) });
+ Insn.push_back(
+ {AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
+ AArch64_AM::getShifterImm(AArch64_AM::LSL, SecondMovkIdx * 16)});
return true;
}
@@ -285,7 +285,7 @@ static bool tryCopyWithNegation(uint64_t Imm, bool AllowThreeSequence,
Insn.push_back({AArch64::MOVNXi, Imm16 ^ Mask, 16});
}
- Insn.push_back({Opc, 0, N});
+ Insn.push_back({Opc, std::nullopt, N});
return true;
};
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandImm.h b/llvm/lib/Target/AArch64/AArch64ExpandImm.h
index c3376520eb410..f3ca35627ab6c 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandImm.h
+++ b/llvm/lib/Target/AArch64/AArch64ExpandImm.h
@@ -21,8 +21,8 @@ namespace AArch64_IMM {
struct ImmInsnModel {
unsigned Opcode;
- uint64_t Op1;
- uint64_t Op2;
+ std::optional<uint32_t> Op1;
+ std::optional<uint32_t> Op2;
};
struct AddrInsnModel {
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 3965ff1783bc5..bcd61e191e17f 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -172,7 +172,7 @@ bool AArch64ExpandPseudoImpl::expandMOVImm(MachineBasicBlock &MBB,
MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
.add(MI.getOperand(0))
.addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
- .addImm(I->Op2));
+ .addImm(*I->Op2));
} else {
Register DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
@@ -182,7 +182,7 @@ bool AArch64ExpandPseudoImpl::expandMOVImm(MachineBasicBlock &MBB,
getDeadRegState(DstIsDead && LastItem) |
RenamableState)
.addReg(DstReg)
- .addImm(I->Op2));
+ .addImm(*I->Op2));
}
break;
case AArch64::EONXrs:
@@ -198,32 +198,33 @@ bool AArch64ExpandPseudoImpl::expandMOVImm(MachineBasicBlock &MBB,
RenamableState)
.addReg(DstReg)
.addReg(DstReg)
- .addImm(I->Op2));
+ .addImm(*I->Op2));
} break;
case AArch64::MOVNWi:
case AArch64::MOVNXi:
case AArch64::MOVZWi:
case AArch64::MOVZXi: {
bool DstIsDead = MI.getOperand(0).isDead();
- MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
- .addReg(DstReg, RegState::Define |
- getDeadRegState(DstIsDead && LastItem) |
- RenamableState)
- .addImm(I->Op1)
- .addImm(I->Op2));
+ MIBS.push_back(
+ BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
+ .addReg(DstReg, RegState::Define |
+ getDeadRegState(DstIsDead && LastItem) |
+ RenamableState)
+ .addImm(*I->Op1)
+ .addImm(*I->Op2));
} break;
case AArch64::MOVKWi:
case AArch64::MOVKXi: {
Register DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
- MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
- .addReg(DstReg,
- RegState::Define |
- getDeadRegState(DstIsDead && LastItem) |
- RenamableState)
- .addReg(DstReg)
- .addImm(I->Op1)
- .addImm(I->Op2));
+ MIBS.push_back(
+ BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
+ .addReg(DstReg, RegState::Define |
+ getDeadRegState(DstIsDead && LastItem) |
+ RenamableState)
+ .addReg(DstReg)
+ .addImm(*I->Op1)
+ .addImm(*I->Op2));
} break;
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 99bcb5f50c134..26ca67ed132e5 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -14034,8 +14034,8 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
for (unsigned I = 0; I + 1 < Insn.size(); ++I) {
const AArch64_IMM::ImmInsnModel &First = Insn[I];
const AArch64_IMM::ImmInsnModel &Second = Insn[I + 1];
- if (Subtarget->fusesMOVImmPair(First.Opcode, First.Op2, Second.Opcode,
- Second.Op2)) {
+ if (Subtarget->fusesMOVImmPair(First.Opcode, First.Op2.value_or(0),
+ Second.Opcode, Second.Op2.value_or(0))) {
++Limit;
// An instruction can only be fused once, so the 2nd one of the pair
// cannot start another pair and is skipped.
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