[llvm] 89c4368 - [VPlan] Don't create no-op casts in truncateToMinimalBitwidths. (#223271)
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Sun Sep 13 13:53:51 PDT 2026
Author: Florian Hahn
Date: 2026-09-13T21:53:46+01:00
New Revision: 89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
URL: https://github.com/llvm/llvm-project/commit/89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
DIFF: https://github.com/llvm/llvm-project/commit/89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f.diff
LOG: [VPlan] Don't create no-op casts in truncateToMinimalBitwidths. (#223271)
No-op casts get folded to the input operand, which caused applyFlags to
crash if that was not a cast. Fix by avoiding creating such trivial
casts in the first place.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
index 0d43d7a8f0cca..9b6f0f37008a6 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
@@ -471,6 +471,8 @@ class VPBuilder {
VPWidenCastRecipe *createWidenCast(Instruction::CastOps Opcode, VPValue *Op,
Type *ResultTy) {
+ assert(Op->getScalarType() != ResultTy &&
+ "must not create a no-op cast recipe");
return tryInsertInstruction(new VPWidenCastRecipe(
Opcode, Op, ResultTy, nullptr, VPIRFlags::getDefaultFlags(Opcode)));
}
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index dd29d99a58e16..a8321e3ca0e22 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -2553,17 +2553,10 @@ void VPlanTransforms::truncateToMinimalBitwidths(
"Only ICmps should not need extending the result.");
assert(!isa<VPWidenStoreRecipe>(&R) && "stores cannot be narrowed");
- // For loads/intrinsics we don't recreate the recipe; just wrap the
- // original wide result in a ZExt to OldResTy.
- if (isa<VPWidenLoadRecipe, VPWidenIntrinsicRecipe>(&R)) {
- if (OldResSizeInBits != NewResSizeInBits) {
- auto *Ext = VPBuilder::getToInsertAfter(&R).createWidenCast(
- Instruction::ZExt, ResultVPV, OldResTy);
- ResultVPV->replaceAllUsesWith(Ext);
- Ext->setOperand(0, ResultVPV);
- }
+ // Loads/intrinsics are not recreated; they keep producing their original
+ // wide result and narrowed users will truncate it as needed below.
+ if (isa<VPWidenLoadRecipe, VPWidenIntrinsicRecipe>(&R))
continue;
- }
// Shrink operands by introducing truncates as needed.
unsigned StartIdx =
@@ -2591,9 +2584,10 @@ void VPlanTransforms::truncateToMinimalBitwidths(
NWR->insertBefore(&R);
// Wrap NWR in a ZExt to preserve the original wide type for downstream
- // users (unless this is an ICmp, which produces i1 regardless).
+ // users. Not needed for ICmps, whose result type is i1 irrespective of
+ // the narrowing of their operands.
VPValue *Replacement = NWR->getVPSingleValue();
- if (OldResSizeInBits != NewResSizeInBits)
+ if (Replacement->getScalarType() != OldResTy)
Replacement =
VPBuilder::getToInsertAfter(NWR)
.createWidenCast(Instruction::ZExt, Replacement, OldResTy)
diff --git a/llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll b/llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
index 8a162930ffd99..0f1b8a2540ff4 100644
--- a/llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
+++ b/llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
@@ -158,6 +158,53 @@ loop:
%ec = icmp eq i64 %iv.next, 1000
br i1 %ec, label %exit, label %loop
+exit:
+ ret void
+}
+
+; The narrowed %cmp keeps its i1 result type when truncating to minimal bitwidth.
+define void @narrowed_icmp_used_by_ext(ptr noalias %src, ptr noalias %dst) {
+; CHECK-LABEL: define void @narrowed_icmp_used_by_ext(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
+; CHECK: vector.ph:
+; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
+; CHECK: vector.body:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i64> [[WIDE_LOAD]] to <4 x i32>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sle <4 x i32> [[TMP1]], splat (i32 1)
+; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP2]] to <4 x i32>
+; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i32> splat (i32 1), [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[INDEX]]
+; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[TMP5]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK: middle.block:
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.src = getelementptr inbounds i64, ptr %src, i64 %iv
+ %l = load i64, ptr %gep.src
+ %cmp = icmp sle i64 %l, 1
+ %ext = zext i1 %cmp to i64
+ %or = or i64 1, %ext
+ %or.trunc = trunc i64 %or to i32
+ %gep.dst = getelementptr inbounds i32, ptr %dst, i64 %iv
+ store i32 %or.trunc, ptr %gep.dst, align 4
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1024
+ br i1 %ec, label %exit, label %loop
+
exit:
ret void
}
@@ -169,4 +216,5 @@ exit:
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
;.
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