[llvm] [WebAssembly][GlobalISel] Implement control flow ops. (PR #218857)

[Matt Arsenault via llvm-commits]

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@@ -175,6 +176,19 @@ bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetLowering &TLI = *STI.getTargetLowering();
 
+  if (I.isPHI()) {
+    const Register DefReg = I.getOperand(0).getReg();
+
+    const TargetRegisterClass *DefRC =
+        TRI.getConstrainedRegClassForOperand(I.getOperand(0), MRI);
+
+    if (!DefRC)
+      return false;
+
+    I.setDesc(TII.get(TargetOpcode::PHI));
+    return RBI.constrainGenericRegister(DefReg, *DefRC, MRI) != nullptr;
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arsenm wrote:

This also needs to constrain all the inputs. It just happens to usually work out if you don't based on the processing of the def instructions, but not always 

https://github.com/llvm/llvm-project/pull/218857