[llvm] [SDAG] Promote extract subvector in more cases without falling back to build vectors. (PR #212156)

[Matt Arsenault via llvm-commits]

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@@ -1119,42 +1123,54 @@ entry:
 define <16 x i64> @zext_v16i10_v16i64(<16 x i10> %a) {
 ; CHECK-SD-LABEL: zext_v16i10_v16i64:
 ; CHECK-SD:       // %bb.0: // %entry
-; CHECK-SD-NEXT:    fmov s0, w6
+; CHECK-SD-NEXT:    ldr w9, [sp, #32]
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arsenm wrote:

Really big looking regression 

https://github.com/llvm/llvm-project/pull/212156