[llvm] [AMDGPU] Fix mode register intersection across predecessors (PR #222244)

[Matt Arsenault via llvm-commits]

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@@ -372,37 +372,32 @@ void SIModeRegister::processBlockPhase2(MachineBasicBlock &MBB,
     // Mask bits (which represent the Mode bits with a known value) can only be
     // added by explicit SETREG instructions or the initial default value -
     // the intersection process may remove Mask bits.
-    // If we find a predecessor that has not yet had an exit value determined
-    // (this can happen for example if a block is its own predecessor) we defer
-    // use of that value as the Mask will be all zero, and we will revisit this
-    // block again later (unless the only predecessor without an exit value is
-    // this block).
-    MachineBasicBlock::pred_iterator P = MBB.pred_begin(), E = MBB.pred_end();
-    MachineBasicBlock &PB = *(*P);
-    unsigned PredBlock = PB.getNumber();
-    if ((ThisBlock == PredBlock) && (std::next(P) == E)) {
-      BlockInfo[ThisBlock]->Pred = DefaultStatus;
+    BlockData &Info = *BlockInfo[ThisBlock];
+    bool SelfPredPending = false;
+    // An entry block is also entered from the function entry, so the default
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arsenm wrote:

It's only entered from the function entry, and cannot have predecessors. You can skip the loop 

https://github.com/llvm/llvm-project/pull/222244