[llvm] [Mips] Handle division by zero trap on MIPS1 (PR #201133)

[via llvm-commits]

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@@ -1280,19 +1287,68 @@ addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
   return VReg;
 }
 
-static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
-                                              MachineBasicBlock &MBB,
-                                              const TargetInstrInfo &TII,
-                                              bool Is64Bit, bool IsMicroMips) {
+static MachineBasicBlock *
+insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock &MBB,
+                    const TargetInstrInfo &TII, bool Is64Bit,
+                    const DivByZeroTrapKind TrapKind) {
   if (NoZeroDivCheck)
     return &MBB;
 
-  // Insert instruction "teq $divisor_reg, $zero, 7".
   MachineBasicBlock::iterator I(MI);
-  MachineInstrBuilder MIB;
   MachineOperand &Divisor = MI.getOperand(2);
+
+  if (TrapKind == DivByZeroTrapKind::Break) {
+    // Build instructions:
+    // MBB:
+    //   bnez     $divisor, $zero, SinkMBB
+    //   MI       $dst, $dividend, $divisor (delay slot)
+    //
+    // BreakMBB:
+    //   break    7
+    //
+    // SinkMBB:
+    //   fallthrough
+    const DebugLoc DL = MI.getDebugLoc();
+    const BasicBlock *BB = MBB.getBasicBlock();
+    const auto It = std::next(MachineFunction::iterator(&MBB));
+
+    MachineFunction *MF = MBB.getParent();
+    MachineBasicBlock *BreakMBB = MF->CreateMachineBasicBlock(BB);
+    MachineBasicBlock *SinkMBB = MF->CreateMachineBasicBlock(BB);
+    MF->insert(It, BreakMBB);
+    MF->insert(It, SinkMBB);
+
+    // Place all instructions after MI into SinkMBB.
+    SinkMBB->splice(SinkMBB->begin(), &MBB, std::next(I), MBB.end());
+    SinkMBB->transferSuccessorsAndUpdatePHIs(&MBB);
+
+    // Place the branch at the end of the block. Since MI is defined as having
+    // no side effects in TableGen, the filler will place it in the branch delay
+    // slot.
+    BuildMI(&MBB, DL, TII.get(Mips::BNE))
+        .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
+        .addReg(Mips::ZERO)
+        .addMBB(SinkMBB);
+    MBB.addSuccessor(BreakMBB);
+    MBB.addSuccessor(SinkMBB);
+
+    // BreakMBB: break 7
+    BuildMI(BreakMBB, DL, TII.get(Mips::BREAK)).addImm(7).addImm(0);
+    BreakMBB->addSuccessor(SinkMBB);
+
+    LivePhysRegs LiveRegs;
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neoto wrote:

I think I managed to do what you're asking. I updated the checks and also ran `llvm-lit`, and it seems like it's still lowered the same. BTW, thank you for the review!

https://github.com/llvm/llvm-project/pull/201133