[llvm] [CodeGen][AMDGPU] Allow elementwise atomic load/store at element alignment (PR #219906)

[Shilei Tian via llvm-commits]

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@@ -230,6 +230,37 @@ static unsigned getAtomicOpSize(AtomicCmpXchgInst *CASI) {
   return DL.getTypeStoreSize(CASI->getCompareOperand()->getType());
 }
 
+static unsigned getAtomicOpElementSize(const DataLayout &DL, LoadInst *LI) {
+  Type *Ty = LI->getType();
+  return DL.getTypeStoreSize(LI->isElementwise() ? Ty->getScalarType() : Ty);
+}
+
+static unsigned getAtomicOpElementSize(const DataLayout &DL, StoreInst *SI) {
+  Type *Ty = SI->getValueOperand()->getType();
+  return DL.getTypeStoreSize(SI->isElementwise() ? Ty->getScalarType() : Ty);
+}
+
+// TODO: atomicrmw can be elementwise too, cmpxchg has no elementwise form.
+template <typename Inst>
+static unsigned getAtomicOpElementSize(const DataLayout &, Inst *I) {
+  return getAtomicOpSize(I);
+}
+
+/// Return the size \p I has to be aligned to. The element size is smaller than
+/// the whole access only for elementwise atomics, and only counts if the target
+/// can issue them at element alignment.
+template <typename Inst>
+static unsigned getRequiredAtomicSize(const TargetLowering *TLI,
+                                      const DataLayout &DL, Inst *I) {
+  unsigned Size = getAtomicOpSize(I);
+  unsigned ElementSize = getAtomicOpElementSize(DL, I);
+  if (ElementSize != Size &&
+      TLI->isAtomicAlignmentSupported(I->getAlign(), Size, ElementSize,
+                                      I->getPointerAddressSpace()))
+    return ElementSize;
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shiltian wrote:

This is worth a note in comment.

https://github.com/llvm/llvm-project/pull/219906