[llvm] [SLP]Model copyable lanes of idempotent binops as op(V, V) when the operand column has a constant lane (PR #220252)
Alexey Bataev via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 13 08:04:28 PDT 2026
https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/220252
>From e47fab540e0bc3be6802fe1a77fd54f8c5badc42 Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bataev at outlook.com>
Date: Tue, 1 Sep 2026 06:44:45 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
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Created using spr 1.3.7
---
.../Transforms/Vectorize/SLPVectorizer.cpp | 122 +++++++++++++-----
.../X86/and-neg-pow2-copyable.ll | 33 ++---
2 files changed, 105 insertions(+), 50 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 8c51e2fc1ce3a..88f293c6c2dfe 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -4845,12 +4845,20 @@ class slpvectorizer::BoUpSLP {
.insert(CD);
// Remove extra deps for users, becoming non-immediate users of the
// instruction. It may happen, if the chain of same copyable elements
- // appears in the tree.
+ // appears in the tree. With the self-operand modeling (op(V, V)) the
+ // user node has the value on more than one operand column, so its
+ // copyable data releases the instruction's schedule data directly
+ // and must stay a counted user.
if (In == I) {
- EdgeInfo UserEI = EI.UserTE->UserTreeIndex;
- if (ScheduleCopyableData *UserCD =
- getScheduleCopyableData(UserEI, In))
- ScheduleCopyableDataMapByUsers[I].remove(UserCD);
+ unsigned NumCols = 0;
+ for (unsigned OpIdx : seq<unsigned>(EI.UserTE->getNumOperands()))
+ NumCols += EI.UserTE->getOperand(OpIdx)[Lane] == I;
+ if (NumCols <= 1) {
+ EdgeInfo UserEI = EI.UserTE->UserTreeIndex;
+ if (ScheduleCopyableData *UserCD =
+ getScheduleCopyableData(UserEI, In))
+ ScheduleCopyableDataMapByUsers[I].remove(UserCD);
+ }
}
It = find(make_range(std::next(It), Op.end()), I);
} while (It != Op.end());
@@ -11422,8 +11430,11 @@ class InstructionsCompatibilityAnalysis {
/// Returns the value and operands for the \p V, considering if it is original
/// instruction and its actual operands should be returned, or it is a
/// copyable element and its should be represented as idempotent instruction.
- SmallVector<Value *> getOperands(const InstructionsState &S, Value *V) const {
- if (isa<PoisonValue>(V))
+ /// \p SelfOp selects the op(V, V) modeling for a copyable lane instead of
+ /// op(V, identity).
+ SmallVector<Value *> getOperands(const InstructionsState &S, Value *V,
+ bool SelfOp) const {
+ if (isa<PoisonValue>(V) || SelfOp)
return {V, V};
if (!S.isCopyableElement(V))
return convertTo(cast<Instruction>(V), S).second;
@@ -11449,6 +11460,59 @@ class InstructionsCompatibilityAnalysis {
return {V, selectBestIdempotentValue()};
}
+ /// Returns the copyable lanes of an idempotent binop to be modeled as
+ /// op(V, V) == V instead of op(V, identity): when the operand column the
+ /// lane joins also holds a constant lane, the reorder would align that
+ /// column as constants and move the lane out, breaking the opcode-peer
+ /// node, while the symmetric form is reorder-proof. The other column must
+ /// be an instruction node so the lane is absorbed there as a copyable
+ /// rather than breaking a constant column.
+ SmallVector<const Value *> findSelfOpLanes(const InstructionsState &S,
+ ArrayRef<Value *> VL,
+ const BoUpSLP &R) const {
+ SmallVector<const Value *> SelfOpLanes;
+ if (!Instruction::isIdempotent(MainOpcode) || none_of(VL, [&](Value *V) {
+ if (isa<PoisonValue>(V))
+ return false;
+ if (S.isCopyableElement(V))
+ return isa<Constant>(V);
+ return isa<Constant>(cast<Instruction>(V)->getOperand(0));
+ }))
+ return SelfOpLanes;
+ // Index the instruction operands of the non-copyable lanes by opcode
+ // and block, so the copyable lanes find their opcode peers without a
+ // quadratic scan.
+ SmallDenseMap<std::pair<unsigned, BasicBlock *>, SmallVector<Value *>>
+ PeerOps;
+ for (Value *RV : VL) {
+ if (isa<PoisonValue>(RV) || S.isCopyableElement(RV))
+ continue;
+ auto *RI = cast<Instruction>(RV);
+ assert(RI->getNumOperands() == 2 && "Expected binary operation.");
+ for (unsigned OpIdx : seq<unsigned>(RI->getNumOperands())) {
+ auto *OpI = dyn_cast<Instruction>(RI->getOperand(OpIdx));
+ if (OpI &&
+ isa<Instruction>(RI->getOperand(RI->getNumOperands() - 1 - OpIdx)))
+ PeerOps[{OpI->getOpcode(), OpI->getParent()}].push_back(OpI);
+ }
+ }
+ SmallVector<std::pair<Value *, Value *>> Candidates;
+ for (Value *V : VL) {
+ auto *I = dyn_cast<Instruction>(V);
+ if (!I || !S.isCopyableElement(I))
+ continue;
+ auto It = PeerOps.find({I->getOpcode(), I->getParent()});
+ if (It == PeerOps.end())
+ continue;
+ for (Value *OpI : It->second)
+ Candidates.emplace_back(V, OpI);
+ }
+ if (R.findBestRootPair(Candidates).first)
+ for (const auto &P : Candidates)
+ SelfOpLanes.push_back(P.first);
+ return SelfOpLanes;
+ }
+
/// Builds operands for the original instructions.
void
buildOriginalOperands(const InstructionsState &S, ArrayRef<Value *> VL,
@@ -11754,7 +11818,7 @@ class InstructionsCompatibilityAnalysis {
SmallVector<BoUpSLP::ValueList> VOps;
buildOriginalOperands(S, I == SMain ? MainOp : I, VOps);
SmallVector<Value *> CopyableOps =
- getOperands(CopyableS, I == MainOp ? SMain : I);
+ getOperands(CopyableS, I == MainOp ? SMain : I, /*SelfOp=*/false);
if (CopyableOps.size() == VOps.size() &&
all_of(zip(CopyableOps, VOps), [&](const auto &P) {
return std::get<0>(P) == std::get<1>(P)[0];
@@ -11921,7 +11985,7 @@ class InstructionsCompatibilityAnalysis {
if (RecurrenceDescriptor::isFMulAddIntrinsic(MainOp) &&
AbsorbCopyableFMulOrFAdds)
S.setAbsorbCopyableFMulOrFAdd(true);
- SmallVector<BoUpSLP::ValueList> Operands = buildOperands(S, VL);
+ SmallVector<BoUpSLP::ValueList> Operands = buildOperands(S, VL, R);
auto BuildCandidates =
[](SmallVectorImpl<std::pair<Value *, Value *>> &Candidates, Value *V1,
Value *V2) {
@@ -12083,7 +12147,7 @@ class InstructionsCompatibilityAnalysis {
return OrigS;
// Retry with the copyable modeled as the first multiplicand.
S.setCopyableOpIdx(0);
- Operands = buildOperands(S, VL);
+ Operands = buildOperands(S, VL, R);
if (!CheckOperand(Operands[S.getCopyableOpIdx()]))
return OrigS;
}
@@ -12092,7 +12156,8 @@ class InstructionsCompatibilityAnalysis {
}
SmallVector<BoUpSLP::ValueList> buildOperands(const InstructionsState &S,
- ArrayRef<Value *> VL) {
+ ArrayRef<Value *> VL,
+ const BoUpSLP &R) {
assert(S && "Invalid state!");
SmallVector<BoUpSLP::ValueList> Operands;
if (S.areInstructionsWithCopyableElements()) {
@@ -12116,9 +12181,11 @@ class InstructionsCompatibilityAnalysis {
isCommutative(MainOp) && NumMainOpOperands == 2;
Operands.assign(NumMainOpOperands,
BoUpSLP::ValueList(VL.size(), nullptr));
+ SmallVector<const Value *> SelfOpLanes = findSelfOpLanes(S, VL, R);
// Populate operands for every lane.
for (auto [Idx, V] : enumerate(VL)) {
- SmallVector<Value *> OperandsForValue = getOperands(S, V);
+ SmallVector<Value *> OperandsForValue =
+ getOperands(S, V, is_contained(SelfOpLanes, V));
for (auto [OperandIdx, Operand] : enumerate(OperandsForValue))
Operands[OperandIdx][Idx] = Operand;
}
@@ -12630,7 +12697,7 @@ static void scanAssociativeOperands(
}
BoUpSLP::ValueList Column = std::move(Columns[Idx].Col);
SmallVector<BoUpSLP::ValueList> SubOperands =
- Analysis.buildOperands(ColS, Column);
+ Analysis.buildOperands(ColS, Column, R);
assert(SubOperands.size() == 2 && "Expected 2 operand columns.");
// Poison and copyable lanes have no real instruction left to erase
// later: a copyable V is used as-is, not subsumed by the flattened
@@ -13054,7 +13121,7 @@ void BoUpSLP::buildTreeRec(ArrayRef<Value *> VLRef, unsigned Depth,
return;
}
InstructionsCompatibilityAnalysis Analysis(*DT, *DL, *TTI, *TLI);
- SmallVector<ValueList> Operands = Analysis.buildOperands(S, VL);
+ SmallVector<ValueList> Operands = Analysis.buildOperands(S, VL, *this);
// Flatten associative binary chains into operand columns. Only the peeled
// chain links are required to be single-use (they are erased); the root
// being flattened may have other uses. Skip lanes that are neither chain
@@ -13845,7 +13912,7 @@ static InstructionCost canConvertToFMA(ArrayRef<Value *> VL,
DominatorTree &DT, const DataLayout &DL,
TargetTransformInfo &TTI,
const TargetLibraryInfo &TLI,
- const TTI::TargetCostKind CostKind);
+ const BoUpSLP &R);
uint64_t BoUpSLP::getNumScalarInsts(bool HasTreeLoop) {
uint64_t Total = 0;
@@ -13926,7 +13993,7 @@ uint64_t BoUpSLP::getNumScalarInsts(bool HasTreeLoop) {
I->getOpcode() != Instruction::FSub))
continue;
if (canConvertToFMA(I, InstructionsState(I, I), *DT, *DL, *TTI, *TLI,
- CostKind)
+ *this)
.isValid()) {
assert(Count > 0 && "Underflow in scalar inst count (fma)");
--Count;
@@ -14649,13 +14716,14 @@ static InstructionCost canConvertToFMA(ArrayRef<Value *> VL,
DominatorTree &DT, const DataLayout &DL,
TargetTransformInfo &TTI,
const TargetLibraryInfo &TLI,
- const TTI::TargetCostKind CostKind) {
+ const BoUpSLP &R) {
assert(all_of(VL,
[](Value *V) {
return V->getType()->getScalarType()->isFloatingPointTy();
}) &&
"Can only convert to FMA for floating point types");
assert(S.isAddSubLikeOp() && "Can only convert to FMA for add/sub");
+ const TTI::TargetCostKind CostKind = R.getCostKind();
auto CheckForContractable = [](ArrayRef<Value *> VL,
const InstructionsState &S) {
@@ -14679,7 +14747,7 @@ static InstructionCost canConvertToFMA(ArrayRef<Value *> VL,
return InstructionCost::getInvalid();
// fmul also should be contractable
InstructionsCompatibilityAnalysis Analysis(DT, DL, TTI, TLI);
- SmallVector<BoUpSLP::ValueList> Operands = Analysis.buildOperands(S, VL);
+ SmallVector<BoUpSLP::ValueList> Operands = Analysis.buildOperands(S, VL, R);
InstructionsState OpS = getSameOpcode(Operands.front(), TLI);
if (!OpS.valid())
@@ -15539,7 +15607,7 @@ void BoUpSLP::transformNodes() {
!IsOneUseVectorFMulOperand(RHS)))
break;
if (!canConvertToFMA(E.Scalars, E.getOperations(), *DT, *DL, *TTI, *TLI,
- CostKind)
+ *this)
.isValid())
break;
// This node is a fmuladd node.
@@ -17261,8 +17329,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
};
auto GetFMulAddCost = [&, &TTI = *TTI](const InstructionsState &S,
Instruction *VI) {
- InstructionCost Cost =
- canConvertToFMA(VI, S, *DT, *DL, TTI, *TLI, CostKind);
+ InstructionCost Cost = canConvertToFMA(VI, S, *DT, *DL, TTI, *TLI, *this);
return Cost;
};
switch (ShuffleOrOp) {
@@ -32455,9 +32522,8 @@ class HorizontalReduction {
auto *RdxOp = cast<Instruction>(U);
if (hasRequiredNumberOfUses(IsCmpSelMinMax, RdxOp)) {
if (RdxKind == RecurKind::FAdd) {
- InstructionCost FMACost =
- canConvertToFMA(RdxOp, getSameOpcode(RdxOp, TLI), DT, DL,
- *TTI, TLI, CostKind);
+ InstructionCost FMACost = canConvertToFMA(
+ RdxOp, getSameOpcode(RdxOp, TLI), DT, DL, *TTI, TLI, R);
if (FMACost.isValid()) {
LLVM_DEBUG(dbgs() << "FMA cost: " << FMACost << "\n");
if (auto *I = dyn_cast<Instruction>(RdxVal)) {
@@ -32583,7 +32649,7 @@ class HorizontalReduction {
}
if (!Ops.empty()) {
FMACost = canConvertToFMA(Ops, getSameOpcode(Ops, TLI), DT, DL,
- *TTI, TLI, CostKind);
+ *TTI, TLI, R);
if (FMACost.isValid()) {
// Calculate actual FMAD cost.
IntrinsicCostAttributes ICA(Intrinsic::fmuladd, RVecTy,
@@ -33390,8 +33456,7 @@ bool SLPVectorizerPass::tryToVectorize(
if (!AllowFMACandidates &&
(I->getOpcode() == Instruction::FAdd ||
I->getOpcode() == Instruction::FSub) &&
- canConvertToFMA(I, getSameOpcode(I, *TLI), *DT, *DL, *TTI, *TLI,
- R.getCostKind())
+ canConvertToFMA(I, getSameOpcode(I, *TLI), *DT, *DL, *TTI, *TLI, R)
.isValid()) {
FMACandidates.insert(I);
return false;
@@ -34667,8 +34732,7 @@ bool SLPVectorizerPass::vectorizeOnceUsedSeeds(BasicBlock *BB, BoUpSLP &R) {
auto *U = cast<Instruction>(I.user_back());
if (InstructionsState S = getSameOpcode(U, *TLI);
S && S.isAddSubLikeOp() &&
- canConvertToFMA(U, S, *DT, *DL, *TTI, *TLI, R.getCostKind())
- .isValid())
+ canConvertToFMA(U, S, *DT, *DL, *TTI, *TLI, R).isValid())
continue;
}
// The keys are hashes, so the groups are numbered by the first seed to
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll b/llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
index 80e7bdc4ea4e6..17d7374d5385e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
@@ -12,31 +12,22 @@ define void @and_neg_pow2_copyable_16(ptr %out, ptr %y) {
; CHECK-SAME: ptr [[OUT:%.*]], ptr [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 4
-; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 12
-; CHECK-NEXT: [[P10:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 24
-; CHECK-NEXT: [[P9:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 36
-; CHECK-NEXT: [[Y9:%.*]] = load i32, ptr [[P9]], align 4
-; CHECK-NEXT: [[P11:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 40
-; CHECK-NEXT: [[P4:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 48
-; CHECK-NEXT: [[TMP0:%.*]] = call <3 x i32> @llvm.masked.load.v3i32.p0(ptr align 4 [[P3]], <3 x i1> <i1 true, i1 false, i1 true>, <3 x i32> poison)
-; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr [[P10]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 [[P1]], <8 x i1> <i1 true, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison)
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 3, i32 7>
-; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> <i32 1, i32 4, i32 16, i32 64>, [[TMP3]]
+; CHECK-NEXT: [[Y1:%.*]] = load i32, ptr [[P1]], align 4
+; CHECK-NEXT: [[P11:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 8
+; CHECK-NEXT: [[P4:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 16
+; CHECK-NEXT: [[P8:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 32
; CHECK-NEXT: [[TMP16:%.*]] = load <2 x i32>, ptr [[P11]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P4]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i32> [[TMP7]], <16 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 5, i32 poison, i32 poison, i32 24, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i32> [[TMP8]], i32 [[Y9]], i64 9
+; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr [[P8]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[Y1]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <16 x i32> [[TMP3]], <16 x i32> [[TMP4]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <16 x i32> [[TMP9]], <16 x i32> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
-; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <16 x i32> [[TMP18]], <16 x i32> [[TMP21]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <16 x i32> [[TMP5]], <16 x i32> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <2 x i32> [[TMP16]], <2 x i32> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <16 x i32> [[TMP19]], <16 x i32> [[TMP20]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 16, i32 17, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: [[TMP10:%.*]] = shl <16 x i32> <i32 0, i32 -1, i32 -1, i32 9, i32 -1, i32 25, i32 36, i32 49, i32 -1, i32 81, i32 100, i32 121, i32 144, i32 169, i32 196, i32 225>, [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i32> [[TMP17]], <16 x i32> <i32 -1, i32 poison, i32 poison, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> <i32 16, i32 0, i32 1, i32 19, i32 2, i32 21, i32 22, i32 23, i32 3, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i32> [[TMP7]], <16 x i32> [[TMP20]], <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP10:%.*]] = shl <16 x i32> <i32 0, i32 1, i32 4, i32 9, i32 16, i32 25, i32 36, i32 49, i32 64, i32 81, i32 100, i32 121, i32 144, i32 169, i32 196, i32 225>, [[TMP9]]
+; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i32> [[TMP10]], <16 x i32> <i32 -1, i32 poison, i32 poison, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> <i32 16, i32 1, i32 2, i32 19, i32 4, i32 21, i32 22, i32 23, i32 8, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i32> [[TMP10]], <16 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP11:%.*]] = sub nsw <16 x i32> [[TMP13]], [[TMP14]]
; CHECK-NEXT: [[TMP12:%.*]] = and <16 x i32> [[TMP10]], [[TMP11]]
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