[llvm] [SelectionDAG] Avoid redundant comparisons in bit-test switch lowering (PR #222626)

[Matt Arsenault via llvm-commits]

================
@@ -0,0 +1,171 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -O2 -verify-machineinstrs < %s | FileCheck %s
----------------
arsenm wrote:

```suggestion
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
```

https://github.com/llvm/llvm-project/pull/222626