[llvm] [AMDGPU][MC] Diagnose bf16 inline constants without op_sel in the ass… (PR #223035)

[Matt Arsenault via llvm-commits]

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@@ -4866,6 +4868,56 @@ bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,
   return false;
 }
 
+// On subtargets with FeatureBF16InlineConstFromUpperFP32 the hardware generates
+// a bf16 inline constant in the high half of the corresponding fp32 inline
+// constant. A VOP1 bf16 opcode (v_cvt_f32_bf16 and the bf16 transcendentals)
+// reads the low half of its source, so it must use the VOP3 encoding with
+// op_sel[0] set in order to see the constant at all.
+bool AMDGPUAsmParser::validateBF16InlineConst(const MCInst &Inst,
+                                              const OperandVector &Operands) {
+  if (!getFeatureBits()[AMDGPU::FeatureBF16InlineConstFromUpperFP32])
+    return true;
+
+  const unsigned Opc = Inst.getOpcode();
+  const MCInstrDesc &Desc = MII.get(Opc);
+  const bool IsVOP3 =
+      SIInstrFlags::isVOP3(Desc) && !SIInstrFlags::isVOP3P(Desc);
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arsenm wrote:

We probably should fix isVOP3 to mean literally VOP3, and not VOP3 + VOP3P 

https://github.com/llvm/llvm-project/pull/223035