[llvm] [AMDGPU] Legalize 64bit elements for BUILD_VECTOR (PR #145052)

[Matt Arsenault via llvm-commits]

================
@@ -19121,6 +19163,92 @@ SDValue SITargetLowering::performSelectCombine(SDNode *N,
                          SelectLHS, SelectRHS);
 }
 
+SDValue
+SITargetLowering::performBuildVectorCombine(SDNode *N,
+                                            DAGCombinerInfo &DCI) const {
+  // TODO: Perform for all targets instead of just v_mov_b64 enabled ones,
+  // lower could still enable s_mov_b64 which is supported on all targets.
+  const GCNSubtarget *ST = getSubtarget();
+  if (DCI.Level < AfterLegalizeDAG || !ST->hasVMovB64Inst())
+    return SDValue();
+
+  SelectionDAG &DAG = DCI.DAG;
+  SDLoc SL(N);
+
+  EVT VT = N->getValueType(0);
+  EVT EltVT = VT.getVectorElementType();
+  unsigned SizeBits = VT.getSizeInBits();
+  unsigned EltSize = EltVT.getSizeInBits();
+
+  // Skip if:
+  //  - Value type isn't multiple of 64 bit (e.g., v3i32), or
+  //  - Element type has already been combined into 64b elements
+  if ((SizeBits % 64) != 0 || EltSize == 64)
+    return SDValue();
+
+  SmallVector<APInt, 8> SrcBits;
+  BitVector SrcUndef(N->getNumOperands(), false);
+  for (SDValue Operand : N->ops()) {
+    // Build_vector with constants only.
+    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand);
+    ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Operand);
+    BuildVectorSDNode *BV =
+        dyn_cast<BuildVectorSDNode>(peekThroughBitcasts(Operand));
+
----------------
arsenm wrote:

Also handle undef? Can't you filter out the simple constants below here?

(Now that I think of it, do you really need this combine on the scalar cases? I'd expect the generic combiner to catch those as-is)

https://github.com/llvm/llvm-project/pull/145052