[llvm] [GlobalISel] [AArch64] Skip redundant shift amount masking during isel (PR #223136)

[Matt Arsenault via llvm-commits]

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@@ -3158,6 +3158,35 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
         MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
         I.getOperand(2).setReg(Trunc.getReg(0));
       }
+
+      // Mirror tryShiftAmountMod from AArch64DAGToDAGISel.
+      // AArch64 shift instructions only use the low 5 bits (i32) or 6 bits
+      // (i64) of the shift amount. If the shift amount is zero-extended or
+      // masked with an AND that covers enough bits, we can skip the operation.
+      if (!SrcTy.isVector()) {
+        Register ZExtSrc;
+        int64_t MaskImm;
+        Register MaskSrc;
+        // Skip G_ZEXT of the shift amount.
+        if (mi_match(I.getOperand(2).getReg(), MRI,
+                     m_OneNonDBGUse(m_GZExt(m_Reg(ZExtSrc)))))
+          I.getOperand(2).setReg(ZExtSrc);
+        // Skip G_AND that was introduced by legalizing a G_ZEXT of a narrow
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arsenm wrote:

Use braces and/or move the comment. this is weirdly splitting the if and else if with a long comment 

https://github.com/llvm/llvm-project/pull/223136