[llvm] [GlobalISel] Use G_ANYEXT instead of G_ZEXT for shift amount widening (PR #223136)

[Matt Arsenault via llvm-commits]

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@@ -3158,6 +3158,36 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
         MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
         I.getOperand(2).setReg(Trunc.getReg(0));
       }
+
+      // Mirror tryShiftAmountMod from AArch64DAGToDAGISel.
+      // AArch64 shift instructions only use the low 5 bits (i32) or 6 bits
+      // (i64) of the shift amount. If the shift amount is zero-extended from
+      // a narrower type, or masked with an AND that covers enough bits, we
+      // can remove the redundant operation.
+      if (!SrcTy.isVector()) {
+        int Bits = SrcTy.getSizeInBits() == 32 ? 5 : 6;
+        Register NewShiftReg = I.getOperand(2).getReg();
+
+        // Skip over G_ZEXT of the shift amount.
+        MachineInstr *ShiftAmtDef = MRI.getVRegDef(NewShiftReg);
+        if (ShiftAmtDef && ShiftAmtDef->getOpcode() == TargetOpcode::G_ZEXT &&
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arsenm wrote:

Don't use getVRegDef directly, use mi_match 

https://github.com/llvm/llvm-project/pull/223136