[llvm] [GlobalISel] Use G_ANYEXT instead of G_ZEXT for shift amount widening (PR #223136)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index b44e00271..8488e13a1 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -3158,7 +3158,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
         MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
         I.getOperand(2).setReg(Trunc.getReg(0));
       }
-      
+
       // NEW: Mirror tryShiftAmountMod from AArch64DAGToDAGISel.
       // AArch64 shift instructions only use the low 5 bits (i32) or 6 bits
       // (i64) of the shift amount. If the shift amount is zero-extended from
@@ -3170,21 +3170,18 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
 
         // Skip over G_ZEXT of the shift amount.
         MachineInstr *ShiftAmtDef = MRI.getVRegDef(NewShiftReg);
-        if (ShiftAmtDef &&
-            ShiftAmtDef->getOpcode() == TargetOpcode::G_ZEXT &&
+        if (ShiftAmtDef && ShiftAmtDef->getOpcode() == TargetOpcode::G_ZEXT &&
             MRI.hasOneNonDBGUse(NewShiftReg)) {
           NewShiftReg = ShiftAmtDef->getOperand(1).getReg();
           ShiftAmtDef = MRI.getVRegDef(NewShiftReg);
         }
 
         // Skip over G_AND with a mask that covers at least Bits bits.
-        if (ShiftAmtDef &&
-            ShiftAmtDef->getOpcode() == TargetOpcode::G_AND &&
+        if (ShiftAmtDef && ShiftAmtDef->getOpcode() == TargetOpcode::G_AND &&
             MRI.hasOneNonDBGUse(NewShiftReg)) {
           Register MaskReg = ShiftAmtDef->getOperand(2).getReg();
           auto MaskVal = getIConstantVRegVal(MaskReg, MRI);
-          if (MaskVal &&
-              llvm::countr_one(MaskVal->getZExtValue()) >= Bits)
+          if (MaskVal && llvm::countr_one(MaskVal->getZExtValue()) >= Bits)
             NewShiftReg = ShiftAmtDef->getOperand(1).getReg();
         }
 

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https://github.com/llvm/llvm-project/pull/223136