[llvm] [LV][CSSPGO] Don't let pseudo probes block early-exit vectorization (PR #220149)

[chandan singh via llvm-commits]

================
@@ -1208,6 +1209,13 @@ bool VPlanTransforms::areAllLoadsDereferenceable(VPBasicBlock *HeaderVPBB,
   const DataLayout &DL = TheLoop->getHeader()->getDataLayout();
   for (VPBasicBlock *VPBB : vp_rpo_plain_cfg_loop_body(HeaderVPBB)) {
     for (VPRecipeBase &R : *VPBB) {
+      // Pseudo-probes are profiling placeholders with side effects but no real
+      // memory access. They are modeled as reading inaccessible memory, so skip
+      // them here to stay consistent with isReadOnlyLoop(), which classifies
+      // such loops as read-only.
+      if (auto *SDR = dyn_cast<VPSingleDefRecipe>(&R))
+        if (isa_and_nonnull<PseudoProbeInst>(SDR->getUnderlyingValue()))
+          continue;
----------------
chandankds wrote:

Done. `areAllLoadsDereferenceable()` now matches the probe with VPlan pattern matching:

```
if (match(&R, m_Intrinsic<Intrinsic::pseudoprobe>()))
  continue;
```

https://github.com/llvm/llvm-project/pull/220149