[llvm] [X86] Fold FMSUBADD + FADD into VFCMADDC for fp16 (PR #222896)
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Sat Sep 12 08:29:06 PDT 2026
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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/X86/X86ISelLowering.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5d540a8d3..258a54118 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -56082,15 +56082,16 @@ static bool isCFMulFromFMSUBADD(SDValue N, SelectionDAG &DAG, SDValue &A,
SDValue Op2 = N.getOperand(2);
SmallVector<SDValue, 2> Inputs;
- auto matchShufflePattern = [&DAG, &Inputs](SDValue V, ArrayRef<int> Pat) -> bool {
+ auto matchShufflePattern = [&DAG, &Inputs](SDValue V,
+ ArrayRef<int> Pat) -> bool {
SmallVector<int, 32> Mask;
SmallVector<int, 8> RepeatedMask;
Inputs.clear();
if (!getTargetShuffleInputs(V, Inputs, Mask, DAG))
return false;
MVT VT = V.getSimpleValueType();
- return is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask)
- && isShuffleEquivalent(RepeatedMask, Pat, Inputs[0]);
+ return is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask) &&
+ isShuffleEquivalent(RepeatedMask, Pat, Inputs[0]);
};
auto matchFMSUBADDPattern = [&](SDValue X, SDValue OpA) -> bool {
@@ -56103,10 +56104,9 @@ static bool isCFMulFromFMSUBADD(SDValue N, SelectionDAG &DAG, SDValue &A,
SDValue P = Op2.getOperand(0);
SDValue Q = Op2.getOperand(1);
auto matchFMulPattern = [&](SDValue P, SDValue Q) {
- return matchShufflePattern(P, {1, 0, 3, 2, 5, 4, 7, 6})
- && Inputs[0] == A
- && matchShufflePattern(Q, {1, 1, 3, 3, 5, 5, 7, 7})
- && Inputs[0] == B;
+ return matchShufflePattern(P, {1, 0, 3, 2, 5, 4, 7, 6}) &&
+ Inputs[0] == A &&
+ matchShufflePattern(Q, {1, 1, 3, 3, 5, 5, 7, 7}) && Inputs[0] == B;
};
return matchFMulPattern(P, Q) || matchFMulPattern(Q, P);
};
``````````
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https://github.com/llvm/llvm-project/pull/222896
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