[llvm] [AArch64] Codegen for AArch64 Return Address Signing Hardening (PR #176187)

[Anatoly Trosinenko via llvm-commits]

================
@@ -234,6 +238,18 @@ static void emitAUTCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
   }
 }
 
+static inline void emitMOV(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator &MBBI, DebugLoc DL,
+                           const AArch64InstrInfo *TII, Register Dst,
+                           Register Src) {
+  assert(&MBB == MBBI->getParent());
+  BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrs), Dst)
+      .addReg(AArch64::XZR)
+      .addReg(Src)
+      .addImm(0)
+      .setMIFlag(MachineInstr::FrameDestroy);
----------------
atrosinenko wrote:

Sounds reasonably, thanks. Let's postpone the decision until someone actually wants to use `emitMOV` in the prologue.

https://github.com/llvm/llvm-project/pull/176187