[llvm] [GlobalISel] Use G_ANYEXT instead of G_ZEXT for shift amount widening (PR #223136)
Deepak Shirke via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 12 05:54:05 PDT 2026
https://github.com/deepakshirkem updated https://github.com/llvm/llvm-project/pull/223136
>From ac299764d0630a020bb2237c2606b9b0e055938c Mon Sep 17 00:00:00 2001
From: deepakshirkem <deepakshirke509 at gmail.com>
Date: Sat, 12 Sep 2026 16:25:00 +0530
Subject: [PATCH 1/2] [GlobalISel] Use G_ANYEXT instead of G_ZEXT for shift
amount widening
When widening the shift amount type for G_SHL, G_LSHR, and G_ASHR,
use G_ANYEXT instead of G_ZEXT. The shift amount is undefined behavior
for values >= the type width, so we don't need to zero-extend it.
Using G_ANYEXT avoids generating a redundant AND instruction.
Before (GlobalISel):
and w8, w1, #0xff
lsl w0, w0, w8
After (GlobalISel, matches SelectionDAG):
lsl w0, w0, w1
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 14 ++-
.../AArch64/GlobalISel/shift-amount-anyext.ll | 34 ++++++
llvm/test/CodeGen/AArch64/shift.ll | 107 ++++++------------
3 files changed, 74 insertions(+), 81 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/shift-amount-anyext.ll
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a109d984c3e25..3533f550150a0 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3044,9 +3044,10 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
widenScalarDst(MI, WideTy);
} else {
assert(TypeIdx == 1);
- // The "number of bits to shift" operand must preserve its value as an
- // unsigned integer:
- widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
+ // The shift amount is undefined behavior for values >= type width,
+ // so we can use G_ANYEXT instead of G_ZEXT to avoid generating
+ // a redundant AND instruction.
+ widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
}
Observer.changedInstr(MI);
@@ -3096,9 +3097,10 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
widenScalarDst(MI, WideTy);
} else {
assert(TypeIdx == 1);
- // The "number of bits to shift" operand must preserve its value as an
- // unsigned integer:
- widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
+ // The shift amount is undefined behavior for values >= type width,
+ // so we can use G_ANYEXT instead of G_ZEXT to avoid generating
+ // a redundant AND instruction.
+ widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
}
Observer.changedInstr(MI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/shift-amount-anyext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/shift-amount-anyext.ll
new file mode 100644
index 0000000000000..363957a6c2b62
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/shift-amount-anyext.ll
@@ -0,0 +1,34 @@
+; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+
+; Check that shift amount is not masked with AND for small types
+; GlobalISel should match SelectionDAG behavior
+
+; CHECK-LABEL: shl_i8
+; CHECK: lsl w0, w0, w1
+; CHECK-NOT: and
+define i8 @shl_i8(i8 %a, i8 %b) {
+ %r = shl i8 %a, %b
+ ret i8 %r
+}
+
+; CHECK-LABEL: shl_i16
+; CHECK: lsl w0, w0, w1
+; CHECK-NOT: and
+define i16 @shl_i16(i16 %a, i16 %b) {
+ %r = shl i16 %a, %b
+ ret i16 %r
+}
+
+; CHECK-LABEL: lshr_i8
+; CHECK-NOT: and w{{[0-9]+}}, w1
+define i8 @lshr_i8(i8 %a, i8 %b) {
+ %r = lshr i8 %a, %b
+ ret i8 %r
+}
+
+; CHECK-LABEL: ashr_i8
+; CHECK-NOT: and w{{[0-9]+}}, w1
+define i8 @ashr_i8(i8 %a, i8 %b) {
+ %r = ashr i8 %a, %b
+ ret i8 %r
+}
diff --git a/llvm/test/CodeGen/AArch64/shift.ll b/llvm/test/CodeGen/AArch64/shift.ll
index 5d7935474c903..1fb0377e00fc4 100644
--- a/llvm/test/CodeGen/AArch64/shift.ll
+++ b/llvm/test/CodeGen/AArch64/shift.ll
@@ -10,8 +10,7 @@ define i1 @shl_i1(i1 %0, i1 %1){
;
; CHECK-GI-LABEL: shl_i1:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w8, w1, #0x1
-; CHECK-GI-NEXT: lsl w8, w0, w8
+; CHECK-GI-NEXT: lsl w8, w0, w1
; CHECK-GI-NEXT: and w0, w8, #0x1
; CHECK-GI-NEXT: ret
%3 = shl i1 %0, %1
@@ -19,31 +18,19 @@ define i1 @shl_i1(i1 %0, i1 %1){
}
define i8 @shl_i8(i8 %0, i8 %1){
-; CHECK-SD-LABEL: shl_i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: lsl w0, w0, w1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: shl_i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w8, w1, #0xff
-; CHECK-GI-NEXT: lsl w0, w0, w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: shl_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsl w0, w0, w1
+; CHECK-NEXT: ret
%3 = shl i8 %0, %1
ret i8 %3
}
define i16 @shl_i16(i16 %0, i16 %1){
-; CHECK-SD-LABEL: shl_i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: lsl w0, w0, w1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: shl_i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w8, w1, #0xffff
-; CHECK-GI-NEXT: lsl w0, w0, w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: shl_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsl w0, w0, w1
+; CHECK-NEXT: ret
%3 = shl i16 %0, %1
ret i16 %3
}
@@ -109,8 +96,7 @@ define i1 @ashr_i1(i1 %0, i1 %1){
; CHECK-GI-LABEL: ashr_i1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sbfx w8, w0, #0, #1
-; CHECK-GI-NEXT: and w9, w1, #0x1
-; CHECK-GI-NEXT: asr w8, w8, w9
+; CHECK-GI-NEXT: asr w8, w8, w1
; CHECK-GI-NEXT: and w0, w8, #0x1
; CHECK-GI-NEXT: ret
%3 = ashr i1 %0, %1
@@ -118,35 +104,21 @@ define i1 @ashr_i1(i1 %0, i1 %1){
}
define i8 @ashr_i8(i8 %0, i8 %1){
-; CHECK-SD-LABEL: ashr_i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sxtb w8, w0
-; CHECK-SD-NEXT: asr w0, w8, w1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ashr_i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sxtb w8, w0
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: asr w0, w8, w9
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ashr_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sxtb w8, w0
+; CHECK-NEXT: asr w0, w8, w1
+; CHECK-NEXT: ret
%3 = ashr i8 %0, %1
ret i8 %3
}
define i16 @ashr_i16(i16 %0, i16 %1){
-; CHECK-SD-LABEL: ashr_i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sxth w8, w0
-; CHECK-SD-NEXT: asr w0, w8, w1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ashr_i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sxth w8, w0
-; CHECK-GI-NEXT: and w9, w1, #0xffff
-; CHECK-GI-NEXT: asr w0, w8, w9
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ashr_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sxth w8, w0
+; CHECK-NEXT: asr w0, w8, w1
+; CHECK-NEXT: ret
%3 = ashr i16 %0, %1
ret i16 %3
}
@@ -214,44 +186,29 @@ define i1 @lshr_i1(i1 %0, i1 %1){
;
; CHECK-GI-LABEL: lshr_i1:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w8, w1, #0x1
-; CHECK-GI-NEXT: and w9, w0, #0x1
-; CHECK-GI-NEXT: lsr w0, w9, w8
+; CHECK-GI-NEXT: and w8, w0, #0x1
+; CHECK-GI-NEXT: lsr w0, w8, w1
; CHECK-GI-NEXT: ret
%3 = lshr i1 %0, %1
ret i1 %3
}
define i8 @lshr_i8(i8 %0, i8 %1){
-; CHECK-SD-LABEL: lshr_i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: and w8, w0, #0xff
-; CHECK-SD-NEXT: lsr w0, w8, w1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: lshr_i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w8, w1, #0xff
-; CHECK-GI-NEXT: and w9, w0, #0xff
-; CHECK-GI-NEXT: lsr w0, w9, w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: lshr_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and w8, w0, #0xff
+; CHECK-NEXT: lsr w0, w8, w1
+; CHECK-NEXT: ret
%3 = lshr i8 %0, %1
ret i8 %3
}
define i16 @lshr_i16(i16 %0, i16 %1){
-; CHECK-SD-LABEL: lshr_i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: and w8, w0, #0xffff
-; CHECK-SD-NEXT: lsr w0, w8, w1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: lshr_i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w8, w1, #0xffff
-; CHECK-GI-NEXT: and w9, w0, #0xffff
-; CHECK-GI-NEXT: lsr w0, w9, w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: lshr_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and w8, w0, #0xffff
+; CHECK-NEXT: lsr w0, w8, w1
+; CHECK-NEXT: ret
%3 = lshr i16 %0, %1
ret i16 %3
}
>From 6244840ca62502b2fce0037431c4bdb040609070 Mon Sep 17 00:00:00 2001
From: deepakshirkem <deepakshirke509 at gmail.com>
Date: Sat, 12 Sep 2026 18:23:43 +0530
Subject: [PATCH 2/2] Update tests for G_ANYEXT shift amount widening across
all targets
---
.../AArch64/GlobalISel/legalize-bitcast.mir | 65 +-
.../AArch64/GlobalISel/legalize-fshl.mir | 109 +-
.../AArch64/GlobalISel/legalize-fshr.mir | 106 +-
.../AArch64/GlobalISel/legalize-inserts.mir | 177 +-
.../AArch64/GlobalISel/legalize-saddsat.mir | 34 +-
.../AArch64/GlobalISel/legalize-shift.mir | 25 +-
.../AArch64/GlobalISel/legalize-ssubsat.mir | 34 +-
.../legalize-store-vector-bools.mir | 48 +-
.../GlobalISel/legalize-unmerge-values.mir | 4 +-
llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll | 12 +-
.../AArch64/aarch64-matrix-umull-smull.ll | 6 +-
llvm/test/CodeGen/AArch64/combine-sdiv.ll | 41 +-
llvm/test/CodeGen/AArch64/funnel-shift.ll | 4 -
...st-and-by-const-from-lshr-in-eqcmp-zero.ll | 47 +-
...ist-and-by-const-from-shl-in-eqcmp-zero.ll | 24 +-
llvm/test/CodeGen/AArch64/neon-dotreduce.ll | 2194 +++++++++--------
llvm/test/CodeGen/AArch64/overflow-vec.ll | 73 +-
llvm/test/CodeGen/AArch64/rem-by-const.ll | 8 +-
llvm/test/CodeGen/AArch64/sadd_sat.ll | 47 +-
llvm/test/CodeGen/AArch64/sadd_sat_plus.ll | 13 +-
llvm/test/CodeGen/AArch64/sadd_sat_vec.ll | 10 +-
llvm/test/CodeGen/AArch64/select_const.ll | 3 -
llvm/test/CodeGen/AArch64/sext.ll | 24 +-
.../AArch64/signed-truncation-check.ll | 4 +-
llvm/test/CodeGen/AArch64/smul_fix.ll | 4 +-
llvm/test/CodeGen/AArch64/smul_fix_sat.ll | 16 +-
llvm/test/CodeGen/AArch64/ssub_sat.ll | 47 +-
llvm/test/CodeGen/AArch64/ssub_sat_plus.ll | 13 +-
llvm/test/CodeGen/AArch64/ssub_sat_vec.ll | 10 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 265 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 107 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 74 +-
.../AMDGPU/GlobalISel/legalize-ashr.mir | 144 +-
.../AMDGPU/GlobalISel/legalize-fshl.mir | 188 +-
.../AMDGPU/GlobalISel/legalize-fshr.mir | 164 +-
.../AMDGPU/GlobalISel/legalize-lshr.mir | 135 +-
.../AMDGPU/GlobalISel/legalize-rotl-rotr.mir | 63 +-
.../AMDGPU/GlobalISel/legalize-shl.mir | 120 +-
.../GlobalISel/legalize-vector-args-gfx7.mir | 10 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 169 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll | 113 +-
.../test/CodeGen/RISCV/GlobalISel/bitmanip.ll | 80 +-
.../legalizer/legalize-ashr-rv32.mir | 30 +-
.../legalizer/legalize-ashr-rv64.mir | 34 +-
.../legalizer/legalize-bitreverse-rv32.mir | 6 +-
.../legalizer/legalize-bitreverse-rv64.mir | 6 +-
.../legalizer/legalize-lshr-rv32.mir | 15 +-
.../legalizer/legalize-lshr-rv64.mir | 18 +-
.../legalizer/legalize-rotate-rv32.mir | 36 +-
.../legalizer/legalize-rotate-rv64.mir | 36 +-
.../legalizer/legalize-shl-rv32.mir | 12 +-
.../legalizer/legalize-shl-rv64.mir | 16 +-
.../GlobalISel/instructions/ashr.ll | 56 +-
.../GlobalISel/instructions/ashr.mir | 12 +-
.../GlobalISel/instructions/fshl.mir | 24 +-
.../GlobalISel/instructions/fshr.mir | 22 +-
.../GlobalISel/instructions/lshr.ll | 24 +-
.../GlobalISel/instructions/lshr.mir | 12 +-
.../GlobalISel/instructions/shl.ll | 16 +-
.../GlobalISel/instructions/shl.mir | 12 +-
.../CodeGen/X86/GlobalISel/lshr-scalar.ll | 1 -
.../X86/GlobalISel/shl-scalar-widening.ll | 1 -
62 files changed, 2561 insertions(+), 2662 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
index b418d9e224b46..0eafaf603647b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
@@ -58,53 +58,60 @@ body: |
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i8)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C]](i64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C1]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C1]], [[SHL]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C3]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](i8)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C3]](i64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[COPY]](i32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C4]](i64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC2]](i8)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C4]](i64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C5]](i32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C5]](i64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C6]](i64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](i8)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C1]]
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C5]](i64)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C2]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C7]](i32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C6]](i64)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C8]](i64)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC4]](i8)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT4]], [[C1]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C6]](i64)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT4]], [[C2]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C9]](i32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C7]](i64)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C10]](i64)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](i8)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT5]], [[C1]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C7]](i64)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT5]], [[C2]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C11]](i32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C8]](i64)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C12]](i64)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC6]](i8)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ANYEXT6]], [[C1]]
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C8]](i64)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ANYEXT6]], [[C2]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C13]](i32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C9]](i64)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C14]](i64)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC7]](i8)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT7]], [[C1]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT7]], [[C2]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C15]](i32)
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[OR7]](i32)
; CHECK-NEXT: G_STORE [[TRUNC]](i8), [[FRAME_INDEX]](p0) :: (store (i8) into %stack.0)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
index 2a020b5990235..741b13e24fe78 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
@@ -22,11 +22,11 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[XOR]], [[COPY3]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[AND]](i32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND2]], [[C3]](i64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND2]], [[C2]](i32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C3]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[AND3]], [[AND1]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR1]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
@@ -65,11 +65,11 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[XOR]], [[COPY3]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[AND]](i32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND2]], [[C3]](i64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND2]], [[C2]](i32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C3]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[AND3]], [[AND1]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR1]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
@@ -170,11 +170,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C]](i32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[COPY2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -203,12 +205,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -237,15 +240,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[AND1]], [[C3]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C3]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[AND1]], [[C4]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR1]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -274,12 +278,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -308,12 +313,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -342,15 +348,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[AND1]], [[C3]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C3]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[AND1]], [[C4]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR1]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
index 5e76c8bce8c28..a002415271df0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
@@ -21,11 +21,12 @@ body: |
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[COPY2]], [[C1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[XOR]], [[COPY3]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C2]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C3]](i64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[SHL]], [[AND1]](i32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C4]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND2]], [[AND]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL1]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
@@ -63,11 +64,12 @@ body: |
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[COPY2]], [[C1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[XOR]], [[COPY3]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C2]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C3]](i64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[SHL]], [[AND1]](i32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C4]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND2]], [[AND]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL1]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
@@ -169,12 +171,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -203,12 +206,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -237,14 +241,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[SHL]], [[C1]](i64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C3]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[SHL]], [[C3]](i64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C5]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C4]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL1]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -273,12 +279,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 11
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 11
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -307,12 +314,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C2]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -341,14 +349,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C]](i64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[SHL]], [[C1]](i64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C3]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[SHL]], [[C3]](i64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C5]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[C4]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL1]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index 62e074681d877..184cab4814107 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -66,198 +66,247 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x2
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[COPY2]](i32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[C1]](i32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[COPY3]](i32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[COPY4]](i32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY [[C3]](i32)
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[COPY5]](i32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[COPY6]](i32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY [[C5]](i32)
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[COPY7]](i32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY [[C6]](i32)
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[COPY8]](i32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[OR6]](i32)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND8]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND8]], [[COPY9]](i32)
; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[AND9]], [[SHL7]]
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY [[C1]](i32)
; CHECK-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(i32) = G_SHL [[AND10]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(i32) = G_SHL [[AND10]], [[COPY10]](i32)
; CHECK-NEXT: [[OR8:%[0-9]+]]:_(i32) = G_OR [[OR7]], [[SHL8]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[AND11:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[COPY11]](i32)
; CHECK-NEXT: [[OR9:%[0-9]+]]:_(i32) = G_OR [[OR8]], [[SHL9]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY [[C3]](i32)
; CHECK-NEXT: [[AND12:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(i32) = G_SHL [[AND12]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(i32) = G_SHL [[AND12]], [[COPY12]](i32)
; CHECK-NEXT: [[OR10:%[0-9]+]]:_(i32) = G_OR [[OR9]], [[SHL10]]
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[AND13:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(i32) = G_SHL [[AND13]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(i32) = G_SHL [[AND13]], [[COPY13]](i32)
; CHECK-NEXT: [[OR11:%[0-9]+]]:_(i32) = G_OR [[OR10]], [[SHL11]]
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY [[C5]](i32)
; CHECK-NEXT: [[AND14:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(i32) = G_SHL [[AND14]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(i32) = G_SHL [[AND14]], [[COPY14]](i32)
; CHECK-NEXT: [[OR12:%[0-9]+]]:_(i32) = G_OR [[OR11]], [[SHL12]]
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[C6]](i32)
; CHECK-NEXT: [[AND15:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(i32) = G_SHL [[AND15]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(i32) = G_SHL [[AND15]], [[COPY15]](i32)
; CHECK-NEXT: [[OR13:%[0-9]+]]:_(i32) = G_OR [[OR12]], [[SHL13]]
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i8) = G_TRUNC [[OR13]](i32)
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND16:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(i32) = G_SHL [[AND16]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(i32) = G_SHL [[AND16]], [[COPY16]](i32)
; CHECK-NEXT: [[AND17:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[OR14:%[0-9]+]]:_(i32) = G_OR [[AND17]], [[SHL14]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[C1]](i32)
; CHECK-NEXT: [[AND18:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(i32) = G_SHL [[AND18]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(i32) = G_SHL [[AND18]], [[COPY17]](i32)
; CHECK-NEXT: [[OR15:%[0-9]+]]:_(i32) = G_OR [[OR14]], [[SHL15]]
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[AND19:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(i32) = G_SHL [[AND19]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(i32) = G_SHL [[AND19]], [[COPY18]](i32)
; CHECK-NEXT: [[OR16:%[0-9]+]]:_(i32) = G_OR [[OR15]], [[SHL16]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[C3]](i32)
; CHECK-NEXT: [[AND20:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(i32) = G_SHL [[AND20]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(i32) = G_SHL [[AND20]], [[COPY19]](i32)
; CHECK-NEXT: [[OR17:%[0-9]+]]:_(i32) = G_OR [[OR16]], [[SHL17]]
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[AND21:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(i32) = G_SHL [[AND21]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(i32) = G_SHL [[AND21]], [[COPY20]](i32)
; CHECK-NEXT: [[OR18:%[0-9]+]]:_(i32) = G_OR [[OR17]], [[SHL18]]
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY [[C5]](i32)
; CHECK-NEXT: [[AND22:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(i32) = G_SHL [[AND22]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(i32) = G_SHL [[AND22]], [[COPY21]](i32)
; CHECK-NEXT: [[OR19:%[0-9]+]]:_(i32) = G_OR [[OR18]], [[SHL19]]
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY [[C6]](i32)
; CHECK-NEXT: [[AND23:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(i32) = G_SHL [[AND23]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(i32) = G_SHL [[AND23]], [[COPY22]](i32)
; CHECK-NEXT: [[OR20:%[0-9]+]]:_(i32) = G_OR [[OR19]], [[SHL20]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[OR20]](i32)
+ ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND24:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(i32) = G_SHL [[AND24]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(i32) = G_SHL [[AND24]], [[COPY23]](i32)
; CHECK-NEXT: [[AND25:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[OR21:%[0-9]+]]:_(i32) = G_OR [[AND25]], [[SHL21]]
+ ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(i32) = COPY [[C1]](i32)
; CHECK-NEXT: [[AND26:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(i32) = G_SHL [[AND26]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(i32) = G_SHL [[AND26]], [[COPY24]](i32)
; CHECK-NEXT: [[OR22:%[0-9]+]]:_(i32) = G_OR [[OR21]], [[SHL22]]
+ ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[AND27:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(i32) = G_SHL [[AND27]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(i32) = G_SHL [[AND27]], [[COPY25]](i32)
; CHECK-NEXT: [[OR23:%[0-9]+]]:_(i32) = G_OR [[OR22]], [[SHL23]]
+ ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(i32) = COPY [[C3]](i32)
; CHECK-NEXT: [[AND28:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(i32) = G_SHL [[AND28]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(i32) = G_SHL [[AND28]], [[COPY26]](i32)
; CHECK-NEXT: [[OR24:%[0-9]+]]:_(i32) = G_OR [[OR23]], [[SHL24]]
+ ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[AND29:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(i32) = G_SHL [[AND29]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(i32) = G_SHL [[AND29]], [[COPY27]](i32)
; CHECK-NEXT: [[OR25:%[0-9]+]]:_(i32) = G_OR [[OR24]], [[SHL25]]
+ ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(i32) = COPY [[C5]](i32)
; CHECK-NEXT: [[AND30:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(i32) = G_SHL [[AND30]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(i32) = G_SHL [[AND30]], [[COPY28]](i32)
; CHECK-NEXT: [[OR26:%[0-9]+]]:_(i32) = G_OR [[OR25]], [[SHL26]]
+ ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(i32) = COPY [[C6]](i32)
; CHECK-NEXT: [[AND31:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(i32) = G_SHL [[AND31]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(i32) = G_SHL [[AND31]], [[COPY29]](i32)
; CHECK-NEXT: [[OR27:%[0-9]+]]:_(i32) = G_OR [[OR26]], [[SHL27]]
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i8) = G_TRUNC [[OR27]](i32)
+ ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND32:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(i32) = G_SHL [[AND32]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(i32) = G_SHL [[AND32]], [[COPY30]](i32)
; CHECK-NEXT: [[AND33:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[OR28:%[0-9]+]]:_(i32) = G_OR [[AND33]], [[SHL28]]
+ ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(i32) = COPY [[C1]](i32)
; CHECK-NEXT: [[AND34:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(i32) = G_SHL [[AND34]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(i32) = G_SHL [[AND34]], [[COPY31]](i32)
; CHECK-NEXT: [[OR29:%[0-9]+]]:_(i32) = G_OR [[OR28]], [[SHL29]]
+ ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[AND35:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(i32) = G_SHL [[AND35]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(i32) = G_SHL [[AND35]], [[COPY32]](i32)
; CHECK-NEXT: [[OR30:%[0-9]+]]:_(i32) = G_OR [[OR29]], [[SHL30]]
+ ; CHECK-NEXT: [[COPY33:%[0-9]+]]:_(i32) = COPY [[C3]](i32)
; CHECK-NEXT: [[AND36:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(i32) = G_SHL [[AND36]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(i32) = G_SHL [[AND36]], [[COPY33]](i32)
; CHECK-NEXT: [[OR31:%[0-9]+]]:_(i32) = G_OR [[OR30]], [[SHL31]]
+ ; CHECK-NEXT: [[COPY34:%[0-9]+]]:_(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[AND37:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(i32) = G_SHL [[AND37]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(i32) = G_SHL [[AND37]], [[COPY34]](i32)
; CHECK-NEXT: [[OR32:%[0-9]+]]:_(i32) = G_OR [[OR31]], [[SHL32]]
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]]:_(i32) = COPY [[C5]](i32)
; CHECK-NEXT: [[AND38:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(i32) = G_SHL [[AND38]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(i32) = G_SHL [[AND38]], [[COPY35]](i32)
; CHECK-NEXT: [[OR33:%[0-9]+]]:_(i32) = G_OR [[OR32]], [[SHL33]]
+ ; CHECK-NEXT: [[COPY36:%[0-9]+]]:_(i32) = COPY [[C6]](i32)
; CHECK-NEXT: [[AND39:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(i32) = G_SHL [[AND39]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(i32) = G_SHL [[AND39]], [[COPY36]](i32)
; CHECK-NEXT: [[OR34:%[0-9]+]]:_(i32) = G_OR [[OR33]], [[SHL34]]
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i8) = G_TRUNC [[OR34]](i32)
+ ; CHECK-NEXT: [[COPY37:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND40:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(i32) = G_SHL [[AND40]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(i32) = G_SHL [[AND40]], [[COPY37]](i32)
; CHECK-NEXT: [[AND41:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[OR35:%[0-9]+]]:_(i32) = G_OR [[AND41]], [[SHL35]]
+ ; CHECK-NEXT: [[COPY38:%[0-9]+]]:_(i32) = COPY [[C1]](i32)
; CHECK-NEXT: [[AND42:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL36:%[0-9]+]]:_(i32) = G_SHL [[AND42]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL36:%[0-9]+]]:_(i32) = G_SHL [[AND42]], [[COPY38]](i32)
; CHECK-NEXT: [[OR36:%[0-9]+]]:_(i32) = G_OR [[OR35]], [[SHL36]]
+ ; CHECK-NEXT: [[COPY39:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[AND43:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(i32) = G_SHL [[AND43]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(i32) = G_SHL [[AND43]], [[COPY39]](i32)
; CHECK-NEXT: [[OR37:%[0-9]+]]:_(i32) = G_OR [[OR36]], [[SHL37]]
+ ; CHECK-NEXT: [[COPY40:%[0-9]+]]:_(i32) = COPY [[C3]](i32)
; CHECK-NEXT: [[AND44:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL38:%[0-9]+]]:_(i32) = G_SHL [[AND44]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL38:%[0-9]+]]:_(i32) = G_SHL [[AND44]], [[COPY40]](i32)
; CHECK-NEXT: [[OR38:%[0-9]+]]:_(i32) = G_OR [[OR37]], [[SHL38]]
+ ; CHECK-NEXT: [[COPY41:%[0-9]+]]:_(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[AND45:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL39:%[0-9]+]]:_(i32) = G_SHL [[AND45]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL39:%[0-9]+]]:_(i32) = G_SHL [[AND45]], [[COPY41]](i32)
; CHECK-NEXT: [[OR39:%[0-9]+]]:_(i32) = G_OR [[OR38]], [[SHL39]]
+ ; CHECK-NEXT: [[COPY42:%[0-9]+]]:_(i32) = COPY [[C5]](i32)
; CHECK-NEXT: [[AND46:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL40:%[0-9]+]]:_(i32) = G_SHL [[AND46]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL40:%[0-9]+]]:_(i32) = G_SHL [[AND46]], [[COPY42]](i32)
; CHECK-NEXT: [[OR40:%[0-9]+]]:_(i32) = G_OR [[OR39]], [[SHL40]]
+ ; CHECK-NEXT: [[COPY43:%[0-9]+]]:_(i32) = COPY [[C6]](i32)
; CHECK-NEXT: [[AND47:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL41:%[0-9]+]]:_(i32) = G_SHL [[AND47]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL41:%[0-9]+]]:_(i32) = G_SHL [[AND47]], [[COPY43]](i32)
; CHECK-NEXT: [[OR41:%[0-9]+]]:_(i32) = G_OR [[OR40]], [[SHL41]]
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i8) = G_TRUNC [[OR41]](i32)
+ ; CHECK-NEXT: [[COPY44:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND48:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(i32) = G_SHL [[AND48]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(i32) = G_SHL [[AND48]], [[COPY44]](i32)
; CHECK-NEXT: [[AND49:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[OR42:%[0-9]+]]:_(i32) = G_OR [[AND49]], [[SHL42]]
+ ; CHECK-NEXT: [[COPY45:%[0-9]+]]:_(i32) = COPY [[C1]](i32)
; CHECK-NEXT: [[AND50:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL43:%[0-9]+]]:_(i32) = G_SHL [[AND50]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL43:%[0-9]+]]:_(i32) = G_SHL [[AND50]], [[COPY45]](i32)
; CHECK-NEXT: [[OR43:%[0-9]+]]:_(i32) = G_OR [[OR42]], [[SHL43]]
+ ; CHECK-NEXT: [[COPY46:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[AND51:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL44:%[0-9]+]]:_(i32) = G_SHL [[AND51]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL44:%[0-9]+]]:_(i32) = G_SHL [[AND51]], [[COPY46]](i32)
; CHECK-NEXT: [[OR44:%[0-9]+]]:_(i32) = G_OR [[OR43]], [[SHL44]]
+ ; CHECK-NEXT: [[COPY47:%[0-9]+]]:_(i32) = COPY [[C3]](i32)
; CHECK-NEXT: [[AND52:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL45:%[0-9]+]]:_(i32) = G_SHL [[AND52]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL45:%[0-9]+]]:_(i32) = G_SHL [[AND52]], [[COPY47]](i32)
; CHECK-NEXT: [[OR45:%[0-9]+]]:_(i32) = G_OR [[OR44]], [[SHL45]]
+ ; CHECK-NEXT: [[COPY48:%[0-9]+]]:_(i32) = COPY [[C4]](i32)
; CHECK-NEXT: [[AND53:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL46:%[0-9]+]]:_(i32) = G_SHL [[AND53]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL46:%[0-9]+]]:_(i32) = G_SHL [[AND53]], [[COPY48]](i32)
; CHECK-NEXT: [[OR46:%[0-9]+]]:_(i32) = G_OR [[OR45]], [[SHL46]]
+ ; CHECK-NEXT: [[COPY49:%[0-9]+]]:_(i32) = COPY [[C5]](i32)
; CHECK-NEXT: [[AND54:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL47:%[0-9]+]]:_(i32) = G_SHL [[AND54]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL47:%[0-9]+]]:_(i32) = G_SHL [[AND54]], [[COPY49]](i32)
; CHECK-NEXT: [[OR47:%[0-9]+]]:_(i32) = G_OR [[OR46]], [[SHL47]]
+ ; CHECK-NEXT: [[COPY50:%[0-9]+]]:_(i32) = COPY [[C6]](i32)
; CHECK-NEXT: [[AND55:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL48:%[0-9]+]]:_(i32) = G_SHL [[AND55]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL48:%[0-9]+]]:_(i32) = G_SHL [[AND55]], [[COPY50]](i32)
; CHECK-NEXT: [[OR48:%[0-9]+]]:_(i32) = G_OR [[OR47]], [[SHL48]]
; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i8) = G_TRUNC [[OR48]](i32)
+ ; CHECK-NEXT: [[COPY51:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[AND56:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL49:%[0-9]+]]:_(i32) = G_SHL [[AND56]], [[C1]](i64)
+ ; CHECK-NEXT: [[SHL49:%[0-9]+]]:_(i32) = G_SHL [[AND56]], [[COPY51]](i32)
; CHECK-NEXT: [[AND57:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[OR49:%[0-9]+]]:_(i32) = G_OR [[AND57]], [[SHL49]]
; CHECK-NEXT: [[AND58:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(i32) = G_SHL [[AND58]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(i32) = G_SHL [[AND58]], [[C1]](i32)
; CHECK-NEXT: [[OR50:%[0-9]+]]:_(i32) = G_OR [[OR49]], [[SHL50]]
; CHECK-NEXT: [[AND59:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL51:%[0-9]+]]:_(i32) = G_SHL [[AND59]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL51:%[0-9]+]]:_(i32) = G_SHL [[AND59]], [[C2]](i32)
; CHECK-NEXT: [[OR51:%[0-9]+]]:_(i32) = G_OR [[OR50]], [[SHL51]]
; CHECK-NEXT: [[AND60:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(i32) = G_SHL [[AND60]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(i32) = G_SHL [[AND60]], [[C3]](i32)
; CHECK-NEXT: [[OR52:%[0-9]+]]:_(i32) = G_OR [[OR51]], [[SHL52]]
; CHECK-NEXT: [[AND61:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(i32) = G_SHL [[AND61]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(i32) = G_SHL [[AND61]], [[C4]](i32)
; CHECK-NEXT: [[OR53:%[0-9]+]]:_(i32) = G_OR [[OR52]], [[SHL53]]
; CHECK-NEXT: [[AND62:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(i32) = G_SHL [[AND62]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(i32) = G_SHL [[AND62]], [[C5]](i32)
; CHECK-NEXT: [[OR54:%[0-9]+]]:_(i32) = G_OR [[OR53]], [[SHL54]]
; CHECK-NEXT: [[AND63:%[0-9]+]]:_(i32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(i32) = G_SHL [[AND63]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(i32) = G_SHL [[AND63]], [[C6]](i32)
; CHECK-NEXT: [[OR55:%[0-9]+]]:_(i32) = G_OR [[OR54]], [[SHL55]]
; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[OR55]](i32)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[TRUNC1]](i8), [[TRUNC2]](i8), [[TRUNC3]](i8), [[TRUNC4]](i8), [[TRUNC5]](i8), [[TRUNC6]](i8), [[TRUNC7]](i8), [[TRUNC8]](i8)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
index c31ce19084b0d..29776f31a758b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
@@ -71,9 +71,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[ADD]], 16
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ne), [[ADD]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG2]](i32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 -32768
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](i32), [[ADD1]], [[ADD]]
@@ -106,9 +106,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[ADD]], 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ne), [[ADD]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG2]](i32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](i32), [[ADD1]], [[ADD]]
@@ -141,9 +141,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[ADD]], 3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ne), [[ADD]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG2]](i32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](i32), [[ADD1]], [[ADD]]
@@ -206,7 +206,8 @@ body: |
; CHECK-NEXT: %copy_1:_(i128) = COPY $q0
; CHECK-NEXT: %copy_2:_(i128) = COPY $q1
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(i64) = G_EXTRACT %copy_1(i128), 0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES %copy_1(i128)
; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(i64) = G_EXTRACT %copy_2(i128), 0
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES %copy_2(i128)
@@ -222,13 +223,22 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[MV:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[UV4]](i8), [[UV5]](i8), [[UV6]](i8), [[DEF]](i8)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 87
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[MV]](i32), [[MV1]](i32)
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(i64) = G_SEXT_INREG [[MV2]], 24
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[SEXT_INREG3]], [[C1]](i64)
- ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(i64), [[UADDO3:%[0-9]+]]:_(i32) = G_UADDO [[ASHR]], [[C]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](i32), [[UADDO2]], [[UADDO]]
- ; CHECK-NEXT: $x0 = COPY [[SELECT]](i64)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[C2]], [[C]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(i64) = G_SUB [[C]], [[C2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[C2]](i64), [[C]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[C2]](i64), [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[UADDO]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[SEXT_INREG3]], [[SUB1]](i64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[SEXT_INREG3]], [[SUB]](i64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](i32), [[OR]], [[ASHR]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP2]](i32), [[UADDO]], [[SELECT]]
+ ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(i64), [[UADDO3:%[0-9]+]]:_(i32) = G_UADDO [[SELECT1]], [[C1]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](i32), [[UADDO2]], [[UADDO]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT2]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(i128) = COPY $q0
%x:_(i88) = G_TRUNC %copy_1(i128)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index bf3e812e22ba6..c448fa37fb588 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -8,22 +8,19 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](i64)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(i32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[SEXT_INREG]], [[AND]](i32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[SEXT_INREG]], [[TRUNC]](i32)
; CHECK-NEXT: $w0 = COPY [[ASHR]](i32)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[TRUNC2]], [[C]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](i64)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[TRUNC3]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND2]], [[AND1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC3]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[AND]], [[TRUNC2]](i32)
; CHECK-NEXT: $w0 = COPY [[LSHR]](i32)
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[TRUNC4]], [[C]]
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](i64)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[TRUNC5]], [[AND3]](i32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[TRUNC5]], [[TRUNC4]](i32)
; CHECK-NEXT: $w0 = COPY [[SHL]](i32)
%0:_(i64) = COPY $x0
%1:_(i64) = COPY $x1
@@ -47,8 +44,8 @@ body: |
; CHECK-LABEL: name: test_shl_i64_i32
; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](i32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[COPY]], [[ZEXT]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[COPY]], [[ANYEXT]](i64)
; CHECK-NEXT: $x0 = COPY [[SHL]](i64)
%0:_(i64) = COPY $x0
%1:_(i32) = COPY $w1
@@ -63,8 +60,8 @@ body: |
; CHECK-LABEL: name: test_ashr_i64_i32
; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](i32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[COPY]], [[ZEXT]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[COPY]], [[ANYEXT]](i64)
; CHECK-NEXT: $x0 = COPY [[ASHR]](i64)
%0:_(i64) = COPY $x0
%1:_(i32) = COPY $w1
@@ -79,8 +76,8 @@ body: |
; CHECK-LABEL: name: test_lshr_i64_i32
; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](i32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY]], [[ZEXT]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY]], [[ANYEXT]](i64)
; CHECK-NEXT: $x0 = COPY [[LSHR]](i64)
%0:_(i64) = COPY $x0
%1:_(i32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
index 4799956694d81..fdefe8f991ff5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
@@ -71,9 +71,9 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[SUB]], 16
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ne), [[SUB]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG2]](i32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 -32768
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](i32), [[ADD]], [[SUB]]
@@ -106,9 +106,9 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[SUB]], 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ne), [[SUB]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG2]](i32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](i32), [[ADD]], [[SUB]]
@@ -141,9 +141,9 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[SUB]], 3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ne), [[SUB]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG2]](i32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i32) = G_ASHR [[COPY]], [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[ASHR]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](i32), [[ADD]], [[SUB]]
@@ -206,7 +206,8 @@ body: |
; CHECK-NEXT: %copy_1:_(i128) = COPY $q0
; CHECK-NEXT: %copy_2:_(i128) = COPY $q1
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(i64) = G_EXTRACT %copy_1(i128), 0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES %copy_1(i128)
; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(i64) = G_EXTRACT %copy_2(i128), 0
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES %copy_2(i128)
@@ -222,13 +223,22 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[MV:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[UV4]](i8), [[UV5]](i8), [[UV6]](i8), [[DEF]](i8)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 87
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[MV]](i32), [[MV1]](i32)
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(i64) = G_SEXT_INREG [[MV2]], 24
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[SEXT_INREG3]], [[C1]](i64)
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(i64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[ASHR]], [[C]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](i32), [[UADDO]], [[USUBO]]
- ; CHECK-NEXT: $x0 = COPY [[SELECT]](i64)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[C2]], [[C]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(i64) = G_SUB [[C]], [[C2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[C2]](i64), [[C]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[C2]](i64), [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[USUBO]], [[C2]](i64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[SEXT_INREG3]], [[SUB1]](i64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i64) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[SEXT_INREG3]], [[SUB]](i64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](i32), [[OR]], [[ASHR]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP2]](i32), [[USUBO]], [[SELECT]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(i64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[SELECT1]], [[C1]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](i32), [[UADDO]], [[USUBO]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT2]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(i128) = COPY $q0
%x:_(i88) = G_TRUNC %copy_1(i128)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
index 72158d3d75cd1..8468c5758b6c2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
@@ -23,53 +23,61 @@ body: |
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x i8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x i16>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C1]](i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C]](i32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i8)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C1]](i64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C]](i32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY2]], [[SHL]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[C]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY3]], [[SHL]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C3]](i64)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](i8)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C3]](i64)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[COPY4]](i32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C4]](i64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC2]](i8)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C2]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C4]](i64)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C5]](i32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C5]](i64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C6]](i64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](i8)
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C2]]
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C5]](i64)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C7]](i32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C6]](i64)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C8]](i64)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC4]](i8)
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT4]], [[C2]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C6]](i64)
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C9]](i32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C7]](i64)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C10]](i64)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](i8)
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT5]], [[C2]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C7]](i64)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C11]](i32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C8]](i64)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C12]](i64)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC6]](i8)
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ANYEXT6]], [[C2]]
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C8]](i64)
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C13]](i32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C9]](i64)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x i8>), [[C14]](i64)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC7]](i8)
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT7]], [[C2]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C9]](i64)
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C15]](i32)
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[OR7]](i32)
; CHECK-NEXT: G_STORE [[TRUNC3]](i8), %ptr(p0) :: (store (i8))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
index a4a6a13fb1f1c..a4b44ab453d22 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
@@ -33,9 +33,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[COPY]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[UV]](i8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[ZEXT]], [[C]](i64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[ZEXT]], [[C]](i32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[UV]](i8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i64) = G_ANYEXT [[LSHR]](i32)
; CHECK-NEXT: $x0 = COPY [[ANYEXT]](i64)
diff --git a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
index 2334e0603ee43..5f51f7f5aaacf 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
@@ -14,7 +14,9 @@ define <8 x i16> @dupsext_v8i8_v8i16(i8 %src, <8 x i8> %b) {
; CHECK-GI-LABEL: dupsext_v8i8_v8i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: lsl w8, w0, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: mov w9, #8 // =0x8
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: dup v1.8h, w8
; CHECK-GI-NEXT: xtn v1.8b, v1.8h
; CHECK-GI-NEXT: smull v0.8h, v1.8b, v0.8b
@@ -304,9 +306,11 @@ define <2 x i16> @dupsext_v2i8_v2i16(i8 %src, <2 x i8> %b) {
; CHECK-GI-LABEL: dupsext_v2i8_v2i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: lsl w8, w0, #8
+; CHECK-GI-NEXT: mov w9, #8 // =0x8
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #24
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: sxth w8, w8
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #24
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: dup v1.4h, w8
; CHECK-GI-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-GI-NEXT: mul v0.2s, v1.2s, v0.2s
@@ -377,8 +381,10 @@ define <8 x i16> @nonsplat_shuffleinsert(i8 %src, <8 x i8> %b) {
; CHECK-GI-LABEL: nonsplat_shuffleinsert:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: lsl w8, w0, #8
+; CHECK-GI-NEXT: mov w9, #8 // =0x8
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: mov v1.h[1], w8
; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #4
; CHECK-GI-NEXT: mul v0.8h, v1.8h, v0.8h
diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
index 66606ba4bad59..e8d4b5510ff31 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
@@ -642,11 +642,13 @@ define i16 @red_mla_dup_ext_u8_s8_s16(ptr noalias nocapture noundef readonly %A,
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB5_4: // %vector.ph
; CHECK-GI-NEXT: lsl w9, w1, #8
+; CHECK-GI-NEXT: mov w10, #8 // =0x8
; CHECK-GI-NEXT: movi v0.2d, #0000000000000000
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: add x10, x0, #8
; CHECK-GI-NEXT: and x11, x8, #0xfffffff0
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: asr w9, w9, w10
+; CHECK-GI-NEXT: add x10, x0, #8
; CHECK-GI-NEXT: dup v2.8h, w9
; CHECK-GI-NEXT: and x9, x8, #0xfffffff0
; CHECK-GI-NEXT: .LBB5_5: // %vector.body
diff --git a/llvm/test/CodeGen/AArch64/combine-sdiv.ll b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
index b160333edb487..ada0a97072876 100644
--- a/llvm/test/CodeGen/AArch64/combine-sdiv.ll
+++ b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
@@ -1307,10 +1307,14 @@ define i8 @combine_i8_sdiv_pow2(i8 %x) {
;
; CHECK-GI-LABEL: combine_i8_sdiv_pow2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w8, w0, #7, #1
+; CHECK-GI-NEXT: sxtb w8, w0
+; CHECK-GI-NEXT: mov w9, #7 // =0x7
+; CHECK-GI-NEXT: asr w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #4 // =0x4
; CHECK-GI-NEXT: ubfx w8, w8, #4, #4
; CHECK-GI-NEXT: add w8, w0, w8
-; CHECK-GI-NEXT: sbfx w0, w8, #4, #4
+; CHECK-GI-NEXT: sxtb w8, w8
+; CHECK-GI-NEXT: asr w0, w8, w9
; CHECK-GI-NEXT: ret
%1 = sdiv i8 %x, 16
ret i8 %1
@@ -1328,7 +1332,9 @@ define i8 @combine_i8_sdiv_negpow2(i8 %x) {
;
; CHECK-GI-LABEL: combine_i8_sdiv_negpow2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w8, w0, #7, #1
+; CHECK-GI-NEXT: sxtb w8, w0
+; CHECK-GI-NEXT: mov w9, #7 // =0x7
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: ubfx w8, w8, #2, #6
; CHECK-GI-NEXT: add w8, w0, w8
; CHECK-GI-NEXT: sxtb w8, w8
@@ -1349,10 +1355,14 @@ define i16 @combine_i16_sdiv_pow2(i16 %x) {
;
; CHECK-GI-LABEL: combine_i16_sdiv_pow2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w8, w0, #15, #1
+; CHECK-GI-NEXT: sxth w8, w0
+; CHECK-GI-NEXT: mov w9, #15 // =0xf
+; CHECK-GI-NEXT: asr w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #4 // =0x4
; CHECK-GI-NEXT: ubfx w8, w8, #12, #4
; CHECK-GI-NEXT: add w8, w0, w8
-; CHECK-GI-NEXT: sbfx w0, w8, #4, #12
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: asr w0, w8, w9
; CHECK-GI-NEXT: ret
%1 = sdiv i16 %x, 16
ret i16 %1
@@ -1370,7 +1380,9 @@ define i16 @combine_i16_sdiv_negpow2(i16 %x) {
;
; CHECK-GI-LABEL: combine_i16_sdiv_negpow2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w8, w0, #15, #1
+; CHECK-GI-NEXT: sxth w8, w0
+; CHECK-GI-NEXT: mov w9, #15 // =0xf
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: ubfx w8, w8, #8, #8
; CHECK-GI-NEXT: add w8, w0, w8
; CHECK-GI-NEXT: sxth w8, w8
@@ -1476,10 +1488,11 @@ define i5 @combine_i5_sdiv_const7(i5 %x) {
; CHECK-GI-NEXT: sbfx w9, w0, #0, #5
; CHECK-GI-NEXT: sbfx w8, w8, #0, #5
; CHECK-GI-NEXT: mul w8, w9, w8
+; CHECK-GI-NEXT: mov w9, #2 // =0x2
; CHECK-GI-NEXT: sbfx w8, w8, #0, #10
; CHECK-GI-NEXT: add w8, w0, w8, asr #5
; CHECK-GI-NEXT: sbfx w8, w8, #0, #5
-; CHECK-GI-NEXT: asr w8, w8, #2
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: ubfx w9, w8, #4, #1
; CHECK-GI-NEXT: add w0, w8, w9
; CHECK-GI-NEXT: ret
@@ -1499,11 +1512,13 @@ define i5 @combine_i5_sdiv_const100(i5 %x) {
; CHECK-GI-LABEL: combine_i5_sdiv_const100:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sbfx w8, w0, #0, #5
-; CHECK-GI-NEXT: asr w8, w8, #4
+; CHECK-GI-NEXT: mov w9, #4 // =0x4
+; CHECK-GI-NEXT: asr w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #2 // =0x2
; CHECK-GI-NEXT: ubfx w8, w8, #3, #2
; CHECK-GI-NEXT: add w8, w0, w8
; CHECK-GI-NEXT: sbfx w8, w8, #0, #5
-; CHECK-GI-NEXT: asr w0, w8, #2
+; CHECK-GI-NEXT: asr w0, w8, w9
; CHECK-GI-NEXT: ret
%1 = sdiv i5 %x, 100
ret i5 %1
@@ -1526,9 +1541,11 @@ define i8 @combine_i8_sdiv_const7(i8 %x) {
; CHECK-GI-NEXT: sxtb w8, w0
; CHECK-GI-NEXT: mov w9, #-109 // =0xffffff93
; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #2 // =0x2
; CHECK-GI-NEXT: sxth w8, w8
; CHECK-GI-NEXT: add w8, w0, w8, asr #8
-; CHECK-GI-NEXT: sbfx w8, w8, #2, #6
+; CHECK-GI-NEXT: sxtb w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: ubfx w9, w8, #7, #1
; CHECK-GI-NEXT: add w0, w8, w9
; CHECK-GI-NEXT: ret
@@ -1551,7 +1568,9 @@ define i8 @combine_i8_sdiv_const100(i8 %x) {
; CHECK-GI-NEXT: sxtb w8, w0
; CHECK-GI-NEXT: mov w9, #41 // =0x29
; CHECK-GI-NEXT: mul w8, w8, w9
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: mov w9, #8 // =0x8
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: asr w8, w8, #4
; CHECK-GI-NEXT: ubfx w9, w8, #7, #1
; CHECK-GI-NEXT: add w0, w8, w9
diff --git a/llvm/test/CodeGen/AArch64/funnel-shift.ll b/llvm/test/CodeGen/AArch64/funnel-shift.ll
index c4e4d3c7dcd2b..dc5b2cdcaa485 100644
--- a/llvm/test/CodeGen/AArch64/funnel-shift.ll
+++ b/llvm/test/CodeGen/AArch64/funnel-shift.ll
@@ -153,8 +153,6 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-GI-NEXT: mov w9, #36 // =0x24
; CHECK-GI-NEXT: ubfx x10, x1, #1, #36
; CHECK-GI-NEXT: sub x9, x9, x8
-; CHECK-GI-NEXT: and x8, x8, #0x1fffffffff
-; CHECK-GI-NEXT: and x9, x9, #0x1fffffffff
; CHECK-GI-NEXT: lsl x8, x0, x8
; CHECK-GI-NEXT: lsr x9, x10, x9
; CHECK-GI-NEXT: orr x0, x8, x9
@@ -368,8 +366,6 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-GI-NEXT: mov w9, #36 // =0x24
; CHECK-GI-NEXT: lsl x10, x0, #1
; CHECK-GI-NEXT: sub x9, x9, x8
-; CHECK-GI-NEXT: and x8, x8, #0x1fffffffff
-; CHECK-GI-NEXT: and x9, x9, #0x1fffffffff
; CHECK-GI-NEXT: lsr x8, x11, x8
; CHECK-GI-NEXT: lsl x9, x10, x9
; CHECK-GI-NEXT: orr x0, x9, x8
diff --git a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index 7d8ff9ac11e30..78efedb0c9317 100644
--- a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -24,8 +24,7 @@ define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_signbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #128 // =0x80
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: lsr w8, w8, w1
; CHECK-GI-NEXT: tst w8, w0
; CHECK-GI-NEXT: cset w0, eq
; CHECK-GI-NEXT: ret
@@ -46,8 +45,7 @@ define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_lowestbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: lsr w8, w8, w1
; CHECK-GI-NEXT: tst w8, w0
; CHECK-GI-NEXT: cset w0, eq
; CHECK-GI-NEXT: ret
@@ -68,8 +66,7 @@ define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_bitsinmiddle_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #24 // =0x18
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: lsr w8, w8, w1
; CHECK-GI-NEXT: tst w8, w0
; CHECK-GI-NEXT: cset w0, eq
; CHECK-GI-NEXT: ret
@@ -92,8 +89,7 @@ define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
; CHECK-GI-LABEL: scalar_i16_signbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #32768 // =0x8000
-; CHECK-GI-NEXT: and w9, w1, #0xffff
-; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: lsr w8, w8, w1
; CHECK-GI-NEXT: tst w8, w0
; CHECK-GI-NEXT: cset w0, eq
; CHECK-GI-NEXT: ret
@@ -114,8 +110,7 @@ define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
; CHECK-GI-LABEL: scalar_i16_lowestbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: and w9, w1, #0xffff
-; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: lsr w8, w8, w1
; CHECK-GI-NEXT: tst w8, w0
; CHECK-GI-NEXT: cset w0, eq
; CHECK-GI-NEXT: ret
@@ -136,8 +131,7 @@ define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
; CHECK-GI-LABEL: scalar_i16_bitsinmiddle_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #4080 // =0xff0
-; CHECK-GI-NEXT: and w9, w1, #0xffff
-; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: lsr w8, w8, w1
; CHECK-GI-NEXT: tst w8, w0
; CHECK-GI-NEXT: cset w0, eq
; CHECK-GI-NEXT: ret
@@ -425,8 +419,7 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_signbit_ne:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #128 // =0x80
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: lsr w8, w8, w1
; CHECK-GI-NEXT: tst w8, w0
; CHECK-GI-NEXT: cset w0, ne
; CHECK-GI-NEXT: ret
@@ -480,24 +473,14 @@ define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
}
define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
-; CHECK-SD-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: mov w8, #128 // =0x80
-; CHECK-SD-NEXT: lsr w8, w8, w1
-; CHECK-SD-NEXT: and w8, w8, w0
-; CHECK-SD-NEXT: cmp w8, #1
-; CHECK-SD-NEXT: cset w0, eq
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #128 // =0x80
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsr w8, w8, w9
-; CHECK-GI-NEXT: and w8, w8, w0
-; CHECK-GI-NEXT: cmp w8, #1
-; CHECK-GI-NEXT: cset w0, eq
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #128 // =0x80
+; CHECK-NEXT: lsr w8, w8, w1
+; CHECK-NEXT: and w8, w8, w0
+; CHECK-NEXT: cmp w8, #1
+; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: ret
%t0 = lshr i8 128, %y
%t1 = and i8 %t0, %x
%res = icmp eq i8 %t1, 1 ; should be comparing with 0
diff --git a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index f61e4303ca2be..b55efeb580ee7 100644
--- a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -25,8 +25,7 @@ define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_signbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff80
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: tst w8, #0xff
; CHECK-GI-NEXT: cset w0, eq
@@ -49,8 +48,7 @@ define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_lowestbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: tst w8, #0xff
; CHECK-GI-NEXT: cset w0, eq
@@ -73,8 +71,7 @@ define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_bitsinmiddle_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #24 // =0x18
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: tst w8, #0xff
; CHECK-GI-NEXT: cset w0, eq
@@ -99,8 +96,7 @@ define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
; CHECK-GI-LABEL: scalar_i16_signbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #-32768 // =0xffff8000
-; CHECK-GI-NEXT: and w9, w1, #0xffff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: tst w8, #0xffff
; CHECK-GI-NEXT: cset w0, eq
@@ -123,8 +119,7 @@ define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
; CHECK-GI-LABEL: scalar_i16_lowestbit_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: and w9, w1, #0xffff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: tst w8, #0xffff
; CHECK-GI-NEXT: cset w0, eq
@@ -147,8 +142,7 @@ define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
; CHECK-GI-LABEL: scalar_i16_bitsinmiddle_eq:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #4080 // =0xff0
-; CHECK-GI-NEXT: and w9, w1, #0xffff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: tst w8, #0xffff
; CHECK-GI-NEXT: cset w0, eq
@@ -430,8 +424,7 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_signbit_ne:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff80
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: tst w8, #0xff
; CHECK-GI-NEXT: cset w0, ne
@@ -488,8 +481,7 @@ define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
; CHECK-GI-LABEL: scalar_i8_bitsinmiddle_slt:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #24 // =0x18
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: lsl w8, w8, w1
; CHECK-GI-NEXT: and w8, w8, w0
; CHECK-GI-NEXT: sxtb w8, w8
; CHECK-GI-NEXT: cmp w8, #0
diff --git a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
index f5312828cfd78..eb5d30b9a0e2c 100644
--- a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -3285,493 +3285,589 @@ define i32 @test_sdot_v25i8_double(<25 x i8> %a, <25 x i8> %b, <25 x i8> %c, <25
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
; CHECK-GI-NEXT: .cfi_offset w29, -16
; CHECK-GI-NEXT: lsl w8, w0, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #16]
-; CHECK-GI-NEXT: lsl w10, w1, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #24]
-; CHECK-GI-NEXT: lsl w12, w4, #8
-; CHECK-GI-NEXT: ldr w13, [sp, #56]
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #64]
-; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: lsl w8, w11, #8
+; CHECK-GI-NEXT: lsl w9, w1, #8
; CHECK-GI-NEXT: lsl w11, w2, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: fmov s4, w9
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: ldr w16, [sp, #112]
-; CHECK-GI-NEXT: mov v2.h[1], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #32]
-; CHECK-GI-NEXT: sbfx w9, w11, #8, #8
-; CHECK-GI-NEXT: lsl w11, w3, #8
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
+; CHECK-GI-NEXT: ldr w12, [sp, #80]
+; CHECK-GI-NEXT: ldr w13, [sp, #152]
+; CHECK-GI-NEXT: lsl w14, w4, #8
+; CHECK-GI-NEXT: sxth w10, w8
+; CHECK-GI-NEXT: mov w8, #8 // =0x8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: ldr w16, [sp, #168]
; CHECK-GI-NEXT: movi d1, #0000000000000000
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v4.h[1], w8
-; CHECK-GI-NEXT: ldr w8, [sp, #152]
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: asr w9, w9, w8
; CHECK-GI-NEXT: movi d0, #0000000000000000
-; CHECK-GI-NEXT: mov v2.h[2], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #40]
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: lsl w8, w8, #8
+; CHECK-GI-NEXT: fmov s2, w10
+; CHECK-GI-NEXT: sxth w10, w11
+; CHECK-GI-NEXT: ldr w11, [sp, #16]
; CHECK-GI-NEXT: mov v1.s[1], wzr
-; CHECK-GI-NEXT: mov v4.h[2], w10
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #160]
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: asr w10, w10, w8
; CHECK-GI-NEXT: mov v0.s[1], wzr
-; CHECK-GI-NEXT: mov v2.h[3], w11
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #48]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: fmov s3, w8
+; CHECK-GI-NEXT: mov v2.h[1], w9
+; CHECK-GI-NEXT: lsl w9, w3, #8
+; CHECK-GI-NEXT: sxth w9, w9
; CHECK-GI-NEXT: mov v1.s[2], wzr
-; CHECK-GI-NEXT: mov v4.h[3], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #80]
-; CHECK-GI-NEXT: lsl w8, w11, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #168]
; CHECK-GI-NEXT: mov v0.s[2], wzr
+; CHECK-GI-NEXT: mov v2.h[2], w10
+; CHECK-GI-NEXT: lsl w10, w11, #8
+; CHECK-GI-NEXT: lsl w11, w12, #8
+; CHECK-GI-NEXT: lsl w12, w13, #8
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: ldr w13, [sp, #24]
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: mov v1.s[3], wzr
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: mov v0.s[3], wzr
+; CHECK-GI-NEXT: mov v2.h[3], w9
+; CHECK-GI-NEXT: ldr w9, [sp, #88]
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: asr w15, w11, w8
+; CHECK-GI-NEXT: asr w11, w12, w8
+; CHECK-GI-NEXT: asr w12, w14, w8
+; CHECK-GI-NEXT: fmov s3, w10
+; CHECK-GI-NEXT: lsl w10, w9, #8
+; CHECK-GI-NEXT: sxth w9, w13
+; CHECK-GI-NEXT: lsl w13, w5, #8
+; CHECK-GI-NEXT: fmov s4, w11
+; CHECK-GI-NEXT: ldr w11, [sp, #32]
; CHECK-GI-NEXT: mov v2.h[4], w12
-; CHECK-GI-NEXT: lsl w12, w5, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: mov v3.h[1], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #88]
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: lsl w14, w6, #8
+; CHECK-GI-NEXT: sxth w13, w13
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v4.h[4], w8
-; CHECK-GI-NEXT: lsl w8, w10, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #176]
-; CHECK-GI-NEXT: mov v2.h[5], w12
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: lsl w12, w6, #8
-; CHECK-GI-NEXT: fmov s6, w9
-; CHECK-GI-NEXT: sbfx w15, w8, #8, #8
-; CHECK-GI-NEXT: lsl w9, w10, #8
-; CHECK-GI-NEXT: mov v3.h[2], w11
-; CHECK-GI-NEXT: sbfx w11, w12, #8, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #96]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v4.h[5], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #224]
-; CHECK-GI-NEXT: mov v6.h[1], w15
-; CHECK-GI-NEXT: mov v2.h[6], w11
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: mov v3.h[1], w9
+; CHECK-GI-NEXT: ldr w9, [sp, #40]
+; CHECK-GI-NEXT: fmov s6, w15
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: ldr w12, [sp, #96]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: mov v2.h[5], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #160]
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: lsl w15, w7, #8
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: mov v6.h[1], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #48]
+; CHECK-GI-NEXT: mov v3.h[2], w11
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v2.h[6], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #104]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w9, w9, w8
; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #184]
-; CHECK-GI-NEXT: ldr w12, [sp, #104]
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
; CHECK-GI-NEXT: mov v3.h[3], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #216]
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: mov v6.h[2], w12
+; CHECK-GI-NEXT: mov v4.h[1], w13
+; CHECK-GI-NEXT: sxth w13, w14
+; CHECK-GI-NEXT: lsl w14, w16, #8
+; CHECK-GI-NEXT: mov v2.h[7], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #112]
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: ldr w11, [sp, #56]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: ldr w12, [sp, #64]
+; CHECK-GI-NEXT: mov v3.h[4], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #176]
+; CHECK-GI-NEXT: mov v6.h[3], w13
+; CHECK-GI-NEXT: asr w13, w14, w8
+; CHECK-GI-NEXT: ldr w14, [sp, #120]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: lsl w10, w10, #8
; CHECK-GI-NEXT: lsl w11, w11, #8
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v2.h[7], w15
-; CHECK-GI-NEXT: lsl w15, w9, #8
-; CHECK-GI-NEXT: mov v4.h[6], w14
-; CHECK-GI-NEXT: mov v6.h[2], w10
-; CHECK-GI-NEXT: lsl w10, w13, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: sbfx w13, w15, #8, #8
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #288]
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: mov v3.h[4], w11
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: mov v4.h[2], w13
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: ldr w13, [sp, #184]
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: mov v6.h[4], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #216]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v4.h[3], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #224]
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v6.h[5], w14
+; CHECK-GI-NEXT: sxth w14, w15
+; CHECK-GI-NEXT: ldr w15, [sp, #232]
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: mov v3.h[5], w11
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: ldr w11, [sp, #192]
-; CHECK-GI-NEXT: fmov s5, w13
-; CHECK-GI-NEXT: ldr w13, [sp, #232]
-; CHECK-GI-NEXT: ldr w9, [sp, #120]
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: mov v4.h[4], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #280]
+; CHECK-GI-NEXT: fmov s5, w14
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: mov v6.h[3], w12
-; CHECK-GI-NEXT: ldr w8, [sp, #72]
+; CHECK-GI-NEXT: ldr w14, [sp, #288]
+; CHECK-GI-NEXT: asr w10, w10, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: mov v1.s[3], wzr
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: lsl w14, w14, #8
; CHECK-GI-NEXT: mov v5.h[1], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #280]
-; CHECK-GI-NEXT: sbfx w15, w11, #8, #8
-; CHECK-GI-NEXT: sbfx w12, w13, #8, #8
-; CHECK-GI-NEXT: lsl w13, w14, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #240]
+; CHECK-GI-NEXT: ldr w10, [sp, #240]
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: mov v3.h[6], w12
+; CHECK-GI-NEXT: ldr w12, [sp, #200]
+; CHECK-GI-NEXT: asr w11, w11, w8
; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v3.h[5], w15
-; CHECK-GI-NEXT: lsl w15, w16, #8
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: mov v5.h[2], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #296]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: lsl w8, w8, #8
-; CHECK-GI-NEXT: fmov s7, w10
-; CHECK-GI-NEXT: ldr w10, [sp, #200]
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w14, w14
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v6.h[4], w15
-; CHECK-GI-NEXT: ldr w15, [sp, #304]
-; CHECK-GI-NEXT: ldr w11, [sp, #128]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v5.h[3], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #208]
-; CHECK-GI-NEXT: mov v7.h[1], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #248]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
+; CHECK-GI-NEXT: ldr w9, [sp, #72]
+; CHECK-GI-NEXT: mov v5.h[2], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #296]
+; CHECK-GI-NEXT: mov v4.h[5], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #248]
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: fmov s7, w13
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v6.h[5], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #272]
-; CHECK-GI-NEXT: mov v3.h[6], w10
-; CHECK-GI-NEXT: lsl w10, w14, #8
-; CHECK-GI-NEXT: sbfx w14, w15, #8, #8
-; CHECK-GI-NEXT: mov v7.h[2], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #256]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: ldr w15, [sp, #320]
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: mov v5.h[4], w13
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: ldr w13, [sp, #312]
-; CHECK-GI-NEXT: mov v3.h[7], w10
+; CHECK-GI-NEXT: ldr w13, [sp, #208]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: asr w10, w10, w8
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: mov v4.h[7], w8
-; CHECK-GI-NEXT: mov v7.h[3], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #264]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
+; CHECK-GI-NEXT: mov v7.h[1], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #304]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: mov v5.h[3], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #256]
+; CHECK-GI-NEXT: sxth w11, w11
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w8, w9, #8, #8
-; CHECK-GI-NEXT: ldr w16, [sp, #136]
+; CHECK-GI-NEXT: asr w15, w15, w8
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: mov v5.h[5], w12
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mul v16.8h, v2.8h, v3.8h
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: sbfx w12, w14, #8, #8
+; CHECK-GI-NEXT: mov v4.h[6], w12
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v7.h[2], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #312]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: ldr w12, [sp, #264]
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: mov v5.h[4], w11
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: asr w11, w14, w8
; CHECK-GI-NEXT: lsl w14, w15, #8
-; CHECK-GI-NEXT: mov v6.h[6], w11
-; CHECK-GI-NEXT: mov v7.h[4], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #328]
-; CHECK-GI-NEXT: ldr w10, [sp, #144]
-; CHECK-GI-NEXT: mov v5.h[6], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #336]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: smov w9, v16.h[0]
-; CHECK-GI-NEXT: smov w15, v16.h[4]
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: mov v4.h[7], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #272]
+; CHECK-GI-NEXT: mov v7.h[3], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #320]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v5.h[5], w10
+; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: lsl w15, w11, #8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: smov w17, v16.h[5]
-; CHECK-GI-NEXT: sxtb w10, w10
-; CHECK-GI-NEXT: mov v0.s[3], wzr
-; CHECK-GI-NEXT: sbfx w11, w13, #8, #8
-; CHECK-GI-NEXT: smov w13, v16.h[1]
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: mul v17.8h, v2.8h, v4.8h
+; CHECK-GI-NEXT: ldr w16, [sp, #128]
+; CHECK-GI-NEXT: mov v7.h[4], w14
+; CHECK-GI-NEXT: sxth w14, w15
+; CHECK-GI-NEXT: mov v5.h[6], w12
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: ldr w12, [sp, #328]
+; CHECK-GI-NEXT: lsl w15, w16, #8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: mov v3.h[7], w9
+; CHECK-GI-NEXT: smov w9, v17.h[0]
+; CHECK-GI-NEXT: ldr w10, [sp, #136]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: lsl w12, w12, #8
; CHECK-GI-NEXT: mov v7.h[5], w14
-; CHECK-GI-NEXT: mov v5.h[7], w8
-; CHECK-GI-NEXT: ldr w14, [sp, #344]
-; CHECK-GI-NEXT: ldr w8, [sp, #352]
+; CHECK-GI-NEXT: ldr w14, [sp, #336]
+; CHECK-GI-NEXT: mov v5.h[7], w13
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: lsl w13, w14, #8
+; CHECK-GI-NEXT: smov w14, v17.h[1]
; CHECK-GI-NEXT: fmov s2, w9
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: mov v6.h[6], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #344]
+; CHECK-GI-NEXT: sxth w16, w10
+; CHECK-GI-NEXT: mul v18.8h, v3.8h, v5.8h
+; CHECK-GI-NEXT: ldr w11, [sp, #144]
+; CHECK-GI-NEXT: mov v7.h[6], w12
+; CHECK-GI-NEXT: sxth w12, w13
+; CHECK-GI-NEXT: sxtb w17, w15
+; CHECK-GI-NEXT: asr w13, w16, w8
+; CHECK-GI-NEXT: smov w16, v17.h[2]
+; CHECK-GI-NEXT: mov v2.s[1], w14
+; CHECK-GI-NEXT: smov w15, v17.h[4]
+; CHECK-GI-NEXT: ldr w10, [sp, #352]
+; CHECK-GI-NEXT: sxtb w14, w11
+; CHECK-GI-NEXT: mov v6.h[7], w13
+; CHECK-GI-NEXT: smov w11, v17.h[5]
+; CHECK-GI-NEXT: smov w13, v18.h[0]
+; CHECK-GI-NEXT: asr w9, w12, w8
+; CHECK-GI-NEXT: ldr w12, [sp, #360]
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: mov v2.s[2], w16
+; CHECK-GI-NEXT: smov w16, v18.h[4]
; CHECK-GI-NEXT: fmov s3, w15
-; CHECK-GI-NEXT: lsl w9, w12, #8
-; CHECK-GI-NEXT: sbfx w12, w16, #8, #8
-; CHECK-GI-NEXT: sxtb w14, w14
-; CHECK-GI-NEXT: lsl w8, w8, #8
-; CHECK-GI-NEXT: mov v7.h[6], w11
-; CHECK-GI-NEXT: ldr w11, [sp, #360]
-; CHECK-GI-NEXT: smov w15, v16.h[3]
-; CHECK-GI-NEXT: mov v2.s[1], w13
-; CHECK-GI-NEXT: smov w13, v16.h[2]
-; CHECK-GI-NEXT: mov v6.h[7], w12
-; CHECK-GI-NEXT: smov w12, v16.h[6]
-; CHECK-GI-NEXT: mov v3.s[1], w17
-; CHECK-GI-NEXT: mul v18.8h, v4.8h, v5.8h
-; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: sbfx w16, w9, #8, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #368]
-; CHECK-GI-NEXT: mov v2.s[2], w13
-; CHECK-GI-NEXT: smov w13, v16.h[7]
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v3.s[2], w12
-; CHECK-GI-NEXT: sbfx w12, w8, #8, #8
-; CHECK-GI-NEXT: mul w8, w10, w14
-; CHECK-GI-NEXT: smov w10, v18.h[0]
-; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: lsl w15, w12, #8
+; CHECK-GI-NEXT: mov v7.h[7], w9
+; CHECK-GI-NEXT: fmov s4, w13
+; CHECK-GI-NEXT: smov w13, v18.h[5]
+; CHECK-GI-NEXT: mul w9, w14, w17
+; CHECK-GI-NEXT: smov w14, v18.h[1]
+; CHECK-GI-NEXT: sxth w17, w15
+; CHECK-GI-NEXT: ldr w12, [sp, #368]
+; CHECK-GI-NEXT: mov v3.s[1], w11
+; CHECK-GI-NEXT: sxth w11, w10
+; CHECK-GI-NEXT: smov w10, v17.h[6]
+; CHECK-GI-NEXT: fmov s5, w16
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: mul v7.8h, v6.8h, v7.8h
+; CHECK-GI-NEXT: asr w15, w11, w8
+; CHECK-GI-NEXT: smov w11, v18.h[2]
+; CHECK-GI-NEXT: ldr w16, [sp, #520]
+; CHECK-GI-NEXT: mov v4.s[1], w14
+; CHECK-GI-NEXT: asr w14, w17, w8
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: fmov s16, w15
+; CHECK-GI-NEXT: smov w15, v17.h[3]
+; CHECK-GI-NEXT: mov v5.s[1], w13
+; CHECK-GI-NEXT: smov w13, v18.h[6]
+; CHECK-GI-NEXT: mov v3.s[2], w10
+; CHECK-GI-NEXT: smov w10, v17.h[7]
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: mov v16.h[1], w14
; CHECK-GI-NEXT: ldr w14, [sp, #376]
-; CHECK-GI-NEXT: fmov s16, w12
-; CHECK-GI-NEXT: smov w12, v18.h[1]
-; CHECK-GI-NEXT: mov v7.h[7], w16
+; CHECK-GI-NEXT: mov v4.s[2], w11
; CHECK-GI-NEXT: mov v2.s[3], w15
-; CHECK-GI-NEXT: smov w15, v18.h[4]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v3.s[3], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #416]
+; CHECK-GI-NEXT: smov w15, v18.h[7]
+; CHECK-GI-NEXT: smov w11, v18.h[3]
+; CHECK-GI-NEXT: mov v5.s[2], w13
+; CHECK-GI-NEXT: mov v3.s[3], w10
+; CHECK-GI-NEXT: smov w10, v7.h[0]
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: fmov s4, w10
-; CHECK-GI-NEXT: mov v16.h[1], w11
-; CHECK-GI-NEXT: ldr w10, [sp, #424]
+; CHECK-GI-NEXT: ldr w13, [sp, #384]
+; CHECK-GI-NEXT: mov v16.h[2], w12
+; CHECK-GI-NEXT: ldr w12, [sp, #416]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: mov v4.s[3], w11
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #384]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: fmov s5, w15
+; CHECK-GI-NEXT: mov v5.s[3], w15
+; CHECK-GI-NEXT: smov w15, v7.h[1]
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: fmov s6, w10
+; CHECK-GI-NEXT: ldr w10, [sp, #480]
+; CHECK-GI-NEXT: asr w11, w14, w8
+; CHECK-GI-NEXT: ldr w14, [sp, #424]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: sxth w13, w13
; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: ldr w15, [sp, #432]
-; CHECK-GI-NEXT: mov v4.s[1], w12
-; CHECK-GI-NEXT: smov w12, v18.h[5]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mov v16.h[2], w9
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
+; CHECK-GI-NEXT: mov v16.h[3], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #392]
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: mov v6.s[1], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #488]
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w14, w14
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: fmov s17, w13
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: mul v7.8h, v6.8h, v7.8h
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #392]
+; CHECK-GI-NEXT: fmov s17, w12
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: ldr w12, [sp, #432]
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: mov v16.h[4], w13
+; CHECK-GI-NEXT: fmov s18, w10
; CHECK-GI-NEXT: ldr w13, [sp, #400]
-; CHECK-GI-NEXT: mov v5.s[1], w12
-; CHECK-GI-NEXT: smov w12, v18.h[2]
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v17.h[1], w10
-; CHECK-GI-NEXT: mov v16.h[3], w14
-; CHECK-GI-NEXT: ldr w10, [sp, #440]
-; CHECK-GI-NEXT: smov w14, v18.h[6]
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: ldr w16, [sp, #456]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: sxth w8, w8
-; CHECK-GI-NEXT: add v2.4s, v2.4s, v3.4s
-; CHECK-GI-NEXT: mov v4.s[2], w12
-; CHECK-GI-NEXT: smov w12, v18.h[3]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v17.h[2], w15
-; CHECK-GI-NEXT: mov v16.h[4], w11
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: mov v5.s[2], w14
-; CHECK-GI-NEXT: smov w14, v18.h[7]
-; CHECK-GI-NEXT: ldr w15, [sp, #448]
-; CHECK-GI-NEXT: ldr w11, [sp, #408]
-; CHECK-GI-NEXT: mov v4.s[3], w12
-; CHECK-GI-NEXT: smov w12, v7.h[0]
-; CHECK-GI-NEXT: mov v17.h[3], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #480]
-; CHECK-GI-NEXT: mov v16.h[5], w9
-; CHECK-GI-NEXT: lsl w9, w13, #8
-; CHECK-GI-NEXT: lsl w13, w15, #8
-; CHECK-GI-NEXT: mov v5.s[3], w14
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: smov w14, v7.h[1]
-; CHECK-GI-NEXT: lsl w15, w16, #8
-; CHECK-GI-NEXT: fmov s6, w12
-; CHECK-GI-NEXT: ldr w12, [sp, #488]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v17.h[4], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #496]
-; CHECK-GI-NEXT: fmov s18, w10
-; CHECK-GI-NEXT: ldr w10, [sp, #552]
-; CHECK-GI-NEXT: mov v6.s[1], w14
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #464]
-; CHECK-GI-NEXT: mov v16.h[6], w9
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: mov v17.h[1], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #496]
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: sxth w12, w12
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v18.h[1], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #560]
-; CHECK-GI-NEXT: mov v17.h[5], w15
-; CHECK-GI-NEXT: sbfx w15, w10, #8, #8
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #512]
-; CHECK-GI-NEXT: fmov s19, w15
-; CHECK-GI-NEXT: ldr w15, [sp, #616]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v16.h[7], w11
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: ldr w10, [sp, #408]
+; CHECK-GI-NEXT: mov v18.h[1], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #440]
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: mov v16.h[5], w11
; CHECK-GI-NEXT: ldr w11, [sp, #504]
-; CHECK-GI-NEXT: mov v18.h[2], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #568]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: mov v17.h[6], w14
-; CHECK-GI-NEXT: lsl w14, w15, #8
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v17.h[2], w12
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: ldr w15, [sp, #576]
-; CHECK-GI-NEXT: mov v19.h[1], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #624]
+; CHECK-GI-NEXT: ldr w12, [sp, #448]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: mov v18.h[2], w14
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: mov v16.h[6], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #512]
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: ldr w14, [sp, #456]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v17.h[3], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #552]
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: sbfx w16, w11, #8, #8
+; CHECK-GI-NEXT: mov v18.h[3], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #560]
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: add v2.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT: mov v17.h[4], w12
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: ldr w12, [sp, #568]
+; CHECK-GI-NEXT: mov v18.h[4], w13
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: sxth w13, w14
+; CHECK-GI-NEXT: lsl w14, w16, #8
+; CHECK-GI-NEXT: mov v16.h[7], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #464]
+; CHECK-GI-NEXT: fmov s19, w15
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: asr w13, w13, w8
; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
+; CHECK-GI-NEXT: ldr w15, [sp, #528]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: add v3.4s, v4.4s, v5.4s
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: mov v19.h[1], w11
+; CHECK-GI-NEXT: mov v17.h[5], w13
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: mov v18.h[5], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #616]
+; CHECK-GI-NEXT: ldr w11, [sp, #576]
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: ldr w13, [sp, #584]
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: mov v19.h[2], w12
+; CHECK-GI-NEXT: ldr w12, [sp, #624]
+; CHECK-GI-NEXT: mov v17.h[6], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #680]
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: sxth w14, w14
; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: mov v18.h[6], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #688]
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: sxth w10, w10
; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: lsl w13, w13, #8
; CHECK-GI-NEXT: fmov s20, w14
-; CHECK-GI-NEXT: ldr w14, [sp, #680]
-; CHECK-GI-NEXT: mov v18.h[3], w16
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: mov v19.h[2], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #632]
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: ldr w14, [sp, #632]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: mov v19.h[3], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #592]
+; CHECK-GI-NEXT: sxth w13, w13
; CHECK-GI-NEXT: mov v20.h[1], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #688]
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v18.h[4], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #584]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
+; CHECK-GI-NEXT: ldr w12, [sp, #696]
+; CHECK-GI-NEXT: fmov s21, w10
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v19.h[3], w15
-; CHECK-GI-NEXT: fmov s21, w14
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: ldr w10, [sp, #600]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: mov v21.h[1], w15
; CHECK-GI-NEXT: ldr w15, [sp, #640]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v20.h[2], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #696]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #520]
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v19.h[4], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #704]
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: asr w12, w12, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v21.h[1], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #592]
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: mov v19.h[4], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #704]
-; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: mov v20.h[2], w14
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: mov v21.h[2], w12
+; CHECK-GI-NEXT: ldr w12, [sp, #648]
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: mov v19.h[5], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #712]
; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: ldr w14, [sp, #608]
+; CHECK-GI-NEXT: asr w13, w13, w8
; CHECK-GI-NEXT: mov v20.h[3], w15
-; CHECK-GI-NEXT: ldr w15, [sp, #648]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v21.h[2], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #600]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
+; CHECK-GI-NEXT: ldr w15, [sp, #656]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: mov v21.h[3], w13
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: mov v18.h[5], w11
-; CHECK-GI-NEXT: ldr w11, [sp, #712]
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: mov v19.h[6], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #720]
+; CHECK-GI-NEXT: ldr w13, [sp, #664]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: mov v20.h[4], w12
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v19.h[5], w12
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: ldr w12, [sp, #656]
+; CHECK-GI-NEXT: mov v21.h[4], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #728]
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: ldr w12, [sp, #472]
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v20.h[5], w15
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: mov v21.h[3], w10
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #608]
-; CHECK-GI-NEXT: mov v20.h[4], w15
+; CHECK-GI-NEXT: mov v19.h[7], w14
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: ldr w14, [sp, #672]
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #528]
-; CHECK-GI-NEXT: ldr w15, [sp, #664]
-; CHECK-GI-NEXT: mov v19.h[6], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #720]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: mov v21.h[4], w11
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: ldr w15, [sp, #536]
+; CHECK-GI-NEXT: mov v21.h[5], w10
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w16, w10, #8, #8
-; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: mov v20.h[5], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #728]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mov v19.h[7], w16
-; CHECK-GI-NEXT: ldr w9, [sp, #472]
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v18.h[6], w14
-; CHECK-GI-NEXT: sbfx w14, w15, #8, #8
-; CHECK-GI-NEXT: mov v21.h[5], w13
-; CHECK-GI-NEXT: ldr w15, [sp, #672]
-; CHECK-GI-NEXT: ldr w11, [sp, #536]
-; CHECK-GI-NEXT: ldr w13, [sp, #736]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: mov v20.h[6], w14
+; CHECK-GI-NEXT: ldr w10, [sp, #736]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v20.h[6], w13
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: sxth w14, w14
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: lsl w16, w10, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: smov w13, v7.h[2]
; CHECK-GI-NEXT: mul v19.8h, v16.8h, v19.8h
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v21.h[6], w12
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: smov w14, v7.h[2]
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
+; CHECK-GI-NEXT: mov v21.h[6], w11
+; CHECK-GI-NEXT: asr w11, w14, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: sxth w14, w16
+; CHECK-GI-NEXT: mov v17.h[7], w12
; CHECK-GI-NEXT: smov w12, v7.h[4]
-; CHECK-GI-NEXT: mov v17.h[7], w9
-; CHECK-GI-NEXT: mov v20.h[7], w15
-; CHECK-GI-NEXT: smov w9, v7.h[5]
-; CHECK-GI-NEXT: mov v18.h[7], w11
-; CHECK-GI-NEXT: smov w11, v19.h[4]
-; CHECK-GI-NEXT: ldr w15, [sp, #744]
-; CHECK-GI-NEXT: mov v21.h[7], w13
-; CHECK-GI-NEXT: mov v6.s[2], w14
-; CHECK-GI-NEXT: smov w14, v19.h[0]
+; CHECK-GI-NEXT: mov v20.h[7], w11
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: ldr w10, [sp, #544]
+; CHECK-GI-NEXT: asr w8, w14, w8
+; CHECK-GI-NEXT: smov w14, v7.h[5]
+; CHECK-GI-NEXT: mov v6.s[2], w13
+; CHECK-GI-NEXT: smov w13, v19.h[0]
+; CHECK-GI-NEXT: mov v18.h[7], w15
+; CHECK-GI-NEXT: smov w15, v19.h[4]
+; CHECK-GI-NEXT: mov v21.h[7], w8
; CHECK-GI-NEXT: fmov s16, w12
-; CHECK-GI-NEXT: smov w13, v19.h[5]
; CHECK-GI-NEXT: smov w12, v19.h[1]
; CHECK-GI-NEXT: mul v20.8h, v17.8h, v20.8h
-; CHECK-GI-NEXT: ldr w10, [sp, #544]
-; CHECK-GI-NEXT: add v3.4s, v4.4s, v5.4s
-; CHECK-GI-NEXT: mul v22.8h, v18.8h, v21.8h
-; CHECK-GI-NEXT: fmov s18, w11
-; CHECK-GI-NEXT: mov v16.s[1], w9
-; CHECK-GI-NEXT: fmov s17, w14
-; CHECK-GI-NEXT: smov w14, v7.h[6]
-; CHECK-GI-NEXT: smov w11, v19.h[2]
-; CHECK-GI-NEXT: smov w9, v7.h[3]
+; CHECK-GI-NEXT: ldr w11, [sp, #744]
+; CHECK-GI-NEXT: smov w16, v19.h[5]
+; CHECK-GI-NEXT: smov w8, v7.h[3]
; CHECK-GI-NEXT: sxtb w10, w10
-; CHECK-GI-NEXT: fmov s21, w8
-; CHECK-GI-NEXT: mov v18.s[1], w13
-; CHECK-GI-NEXT: sxtb w13, w15
+; CHECK-GI-NEXT: add v2.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT: mov v16.s[1], w14
+; CHECK-GI-NEXT: fmov s17, w13
+; CHECK-GI-NEXT: smov w13, v7.h[6]
+; CHECK-GI-NEXT: mul v22.8h, v18.8h, v21.8h
+; CHECK-GI-NEXT: fmov s18, w15
+; CHECK-GI-NEXT: smov w14, v19.h[2]
; CHECK-GI-NEXT: smov w15, v20.h[0]
+; CHECK-GI-NEXT: sxtb w11, w11
+; CHECK-GI-NEXT: fmov s21, w9
; CHECK-GI-NEXT: mov v17.s[1], w12
-; CHECK-GI-NEXT: smov w8, v7.h[7]
+; CHECK-GI-NEXT: smov w9, v7.h[7]
; CHECK-GI-NEXT: smov w12, v19.h[6]
-; CHECK-GI-NEXT: mov v16.s[2], w14
-; CHECK-GI-NEXT: smov w14, v20.h[1]
-; CHECK-GI-NEXT: mul w10, w10, w13
-; CHECK-GI-NEXT: smov w13, v20.h[4]
+; CHECK-GI-NEXT: mov v16.s[2], w13
+; CHECK-GI-NEXT: smov w13, v20.h[1]
+; CHECK-GI-NEXT: mov v18.s[1], w16
+; CHECK-GI-NEXT: mul w10, w10, w11
+; CHECK-GI-NEXT: smov w11, v20.h[4]
; CHECK-GI-NEXT: smov w16, v20.h[5]
-; CHECK-GI-NEXT: mov v21.s[1], wzr
; CHECK-GI-NEXT: fmov s7, w15
+; CHECK-GI-NEXT: mov v21.s[1], wzr
; CHECK-GI-NEXT: smov w15, v20.h[2]
-; CHECK-GI-NEXT: mov v6.s[3], w9
-; CHECK-GI-NEXT: mov v17.s[2], w11
-; CHECK-GI-NEXT: smov w11, v22.h[0]
+; CHECK-GI-NEXT: mov v17.s[2], w14
+; CHECK-GI-NEXT: smov w14, v22.h[0]
+; CHECK-GI-NEXT: mov v6.s[3], w8
; CHECK-GI-NEXT: sxth w10, w10
; CHECK-GI-NEXT: mov v18.s[2], w12
; CHECK-GI-NEXT: smov w12, v22.h[1]
-; CHECK-GI-NEXT: mov v16.s[3], w8
-; CHECK-GI-NEXT: mov v7.s[1], w14
-; CHECK-GI-NEXT: smov w14, v22.h[4]
-; CHECK-GI-NEXT: fmov s23, w13
-; CHECK-GI-NEXT: smov w13, v22.h[5]
+; CHECK-GI-NEXT: mov v7.s[1], w13
+; CHECK-GI-NEXT: smov w13, v22.h[4]
+; CHECK-GI-NEXT: fmov s23, w11
+; CHECK-GI-NEXT: smov w11, v22.h[5]
; CHECK-GI-NEXT: fmov s26, w10
; CHECK-GI-NEXT: smov w10, v19.h[7]
-; CHECK-GI-NEXT: fmov s24, w11
-; CHECK-GI-NEXT: smov w11, v20.h[6]
+; CHECK-GI-NEXT: fmov s24, w14
+; CHECK-GI-NEXT: smov w14, v20.h[6]
; CHECK-GI-NEXT: mov v21.s[2], wzr
; CHECK-GI-NEXT: mov v23.s[1], w16
-; CHECK-GI-NEXT: add v4.4s, v6.4s, v16.4s
-; CHECK-GI-NEXT: add v2.4s, v2.4s, v3.4s
-; CHECK-GI-NEXT: fmov s25, w14
-; CHECK-GI-NEXT: smov w14, v22.h[2]
+; CHECK-GI-NEXT: mov v16.s[3], w9
+; CHECK-GI-NEXT: fmov s25, w13
+; CHECK-GI-NEXT: smov w13, v22.h[2]
; CHECK-GI-NEXT: mov v26.s[1], wzr
; CHECK-GI-NEXT: mov v24.s[1], w12
; CHECK-GI-NEXT: smov w12, v19.h[3]
@@ -3779,24 +3875,25 @@ define i32 @test_sdot_v25i8_double(<25 x i8> %a, <25 x i8> %b, <25 x i8> %c, <25
; CHECK-GI-NEXT: smov w15, v20.h[3]
; CHECK-GI-NEXT: mov v18.s[3], w10
; CHECK-GI-NEXT: mov v21.s[3], wzr
-; CHECK-GI-NEXT: mov v25.s[1], w13
-; CHECK-GI-NEXT: smov w13, v22.h[6]
-; CHECK-GI-NEXT: mov v23.s[2], w11
-; CHECK-GI-NEXT: smov w11, v20.h[7]
+; CHECK-GI-NEXT: mov v25.s[1], w11
+; CHECK-GI-NEXT: smov w11, v22.h[6]
+; CHECK-GI-NEXT: mov v23.s[2], w14
+; CHECK-GI-NEXT: smov w14, v20.h[7]
; CHECK-GI-NEXT: mov v26.s[2], wzr
-; CHECK-GI-NEXT: mov v24.s[2], w14
-; CHECK-GI-NEXT: smov w14, v22.h[3]
+; CHECK-GI-NEXT: add v4.4s, v6.4s, v16.4s
+; CHECK-GI-NEXT: mov v24.s[2], w13
+; CHECK-GI-NEXT: smov w13, v22.h[3]
; CHECK-GI-NEXT: mov v17.s[3], w12
; CHECK-GI-NEXT: mov v7.s[3], w15
; CHECK-GI-NEXT: add v1.4s, v21.4s, v1.4s
-; CHECK-GI-NEXT: mov v25.s[2], w13
-; CHECK-GI-NEXT: smov w13, v22.h[7]
-; CHECK-GI-NEXT: mov v23.s[3], w11
+; CHECK-GI-NEXT: mov v25.s[2], w11
+; CHECK-GI-NEXT: smov w11, v22.h[7]
+; CHECK-GI-NEXT: mov v23.s[3], w14
; CHECK-GI-NEXT: mov v26.s[3], wzr
-; CHECK-GI-NEXT: mov v24.s[3], w14
+; CHECK-GI-NEXT: mov v24.s[3], w13
; CHECK-GI-NEXT: add v5.4s, v17.4s, v18.4s
; CHECK-GI-NEXT: add v1.4s, v4.4s, v1.4s
-; CHECK-GI-NEXT: mov v25.s[3], w13
+; CHECK-GI-NEXT: mov v25.s[3], w11
; CHECK-GI-NEXT: add v6.4s, v7.4s, v23.4s
; CHECK-GI-NEXT: add v0.4s, v26.4s, v0.4s
; CHECK-GI-NEXT: add v1.4s, v2.4s, v1.4s
@@ -5801,670 +5898,799 @@ define i32 @test_sdot_v33i8_double(<33 x i8> %a, <33 x i8> %b, <33 x i8> %c, <33
; CHECK-GI-NEXT: lsl w8, w0, #8
; CHECK-GI-NEXT: ldr w10, [sp, #80]
; CHECK-GI-NEXT: lsl w11, w1, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #88]
-; CHECK-GI-NEXT: ldr w13, [sp, #128]
+; CHECK-GI-NEXT: ldr w12, [sp, #88]
; CHECK-GI-NEXT: ldr w14, [sp, #136]
-; CHECK-GI-NEXT: sbfx w12, w8, #8, #8
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: sbfx w8, w11, #8, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: lsl w11, w2, #8
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: fmov s22, w12
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: ldr w12, [sp, #152]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: lsl w16, w7, #8
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: fmov s23, w10
-; CHECK-GI-NEXT: sbfx w10, w11, #8, #8
-; CHECK-GI-NEXT: lsl w11, w3, #8
-; CHECK-GI-NEXT: mov v22.h[1], w8
-; CHECK-GI-NEXT: ldr w8, [sp, #96]
+; CHECK-GI-NEXT: ldr w15, [sp, #160]
+; CHECK-GI-NEXT: sxth w9, w8
+; CHECK-GI-NEXT: mov w8, #8 // =0x8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: lsl w13, w10, #8
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: ldr w15, [sp, #176]
-; CHECK-GI-NEXT: lsl w8, w8, #8
-; CHECK-GI-NEXT: mov v23.h[1], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #104]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: asr w10, w11, w8
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: ldr w17, [sp, #224]
-; CHECK-GI-NEXT: mov v22.h[2], w10
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w11, #8, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: lsl w11, w4, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: mov v23.h[2], w8
-; CHECK-GI-NEXT: ldr w8, [sp, #112]
+; CHECK-GI-NEXT: sxth w11, w13
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: lsl w13, w2, #8
+; CHECK-GI-NEXT: fmov s22, w9
+; CHECK-GI-NEXT: ldr w9, [sp, #96]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w15, w15
; CHECK-GI-NEXT: movi d19, #0000000000000000
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
+; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: movi d21, #0000000000000000
-; CHECK-GI-NEXT: mov v22.h[3], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #144]
-; CHECK-GI-NEXT: lsl w8, w8, #8
+; CHECK-GI-NEXT: mov v22.h[1], w10
+; CHECK-GI-NEXT: asr w10, w11, w8
+; CHECK-GI-NEXT: sxth w11, w13
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: lsl w13, w3, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: fmov s23, w10
+; CHECK-GI-NEXT: ldr w10, [sp, #104]
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: asr w9, w9, w8
; CHECK-GI-NEXT: movi d16, #0000000000000000
; CHECK-GI-NEXT: movi d18, #0000000000000000
-; CHECK-GI-NEXT: movi d17, #0000000000000000
; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v23.h[3], w9
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #120]
+; CHECK-GI-NEXT: mov v22.h[2], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #112]
+; CHECK-GI-NEXT: mov v23.h[1], w12
+; CHECK-GI-NEXT: sxth w12, w13
+; CHECK-GI-NEXT: lsl w13, w4, #8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: movi d17, #0000000000000000
+; CHECK-GI-NEXT: asr w12, w12, w8
; CHECK-GI-NEXT: movi d20, #0000000000000000
; CHECK-GI-NEXT: movi d6, #0000000000000000
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: mov v22.h[4], w11
-; CHECK-GI-NEXT: lsl w11, w5, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: sxth w11, w11
; CHECK-GI-NEXT: movi d7, #0000000000000000
+; CHECK-GI-NEXT: mov v23.h[2], w9
+; CHECK-GI-NEXT: sxth w9, w13
+; CHECK-GI-NEXT: mov v22.h[3], w12
+; CHECK-GI-NEXT: lsl w13, w5, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: ldr w12, [sp, #120]
+; CHECK-GI-NEXT: asr w9, w9, w8
; CHECK-GI-NEXT: movi d2, #0000000000000000
-; CHECK-GI-NEXT: fmov s24, w10
-; CHECK-GI-NEXT: mov v23.h[4], w8
-; CHECK-GI-NEXT: ldr w8, [sp, #160]
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #168]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: lsl w8, w8, #8
; CHECK-GI-NEXT: movi d4, #0000000000000000
+; CHECK-GI-NEXT: lsl w12, w12, #8
; CHECK-GI-NEXT: movi d3, #0000000000000000
-; CHECK-GI-NEXT: mov v24.h[1], w12
-; CHECK-GI-NEXT: lsl w12, w6, #8
-; CHECK-GI-NEXT: mov v22.h[5], w11
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v23.h[5], w9
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #184]
-; CHECK-GI-NEXT: ldr w9, [sp, #192]
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
; CHECK-GI-NEXT: movi d5, #0000000000000000
+; CHECK-GI-NEXT: mov v23.h[3], w10
+; CHECK-GI-NEXT: sxth w10, w13
+; CHECK-GI-NEXT: mov v22.h[4], w9
+; CHECK-GI-NEXT: lsl w13, w6, #8
+; CHECK-GI-NEXT: ldr w9, [sp, #128]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: asr w10, w10, w8
; CHECK-GI-NEXT: movi d1, #0000000000000000
-; CHECK-GI-NEXT: mov v24.h[2], w8
-; CHECK-GI-NEXT: mov v22.h[6], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #208]
-; CHECK-GI-NEXT: mov v23.h[6], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #216]
+; CHECK-GI-NEXT: movi d0, #0000000000000000
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: asr w12, w12, w8
; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: mov v23.h[4], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #144]
+; CHECK-GI-NEXT: mov v22.h[5], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #152]
+; CHECK-GI-NEXT: asr w16, w13, w8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: ldr w13, [sp, #168]
+; CHECK-GI-NEXT: mov v19.s[1], wzr
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: mov v21.s[1], wzr
+; CHECK-GI-NEXT: sxth w17, w11
+; CHECK-GI-NEXT: mov v22.h[6], w16
+; CHECK-GI-NEXT: lsl w16, w7, #8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: mov v23.h[5], w12
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: asr w17, w17, w8
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: ldr w12, [sp, #176]
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: ldr w11, [sp, #184]
+; CHECK-GI-NEXT: fmov s25, w17
+; CHECK-GI-NEXT: ldr w17, [sp, #208]
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: mov v23.h[6], w9
+; CHECK-GI-NEXT: asr w13, w13, w8
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: ldr w8, [sp, #200]
-; CHECK-GI-NEXT: movi d0, #0000000000000000
+; CHECK-GI-NEXT: lsl w17, w17, #8
+; CHECK-GI-NEXT: mov v22.h[7], w16
+; CHECK-GI-NEXT: ldr w16, [sp, #280]
+; CHECK-GI-NEXT: mov v25.h[1], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #216]
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: sxth w17, w17
+; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: ldr w9, [sp, #192]
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: mov v23.h[7], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #288]
+; CHECK-GI-NEXT: asr w17, w17, w8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: sxth w18, w10
+; CHECK-GI-NEXT: mov v25.h[2], w15
+; CHECK-GI-NEXT: sxth w15, w16
+; CHECK-GI-NEXT: fmov s26, w17
+; CHECK-GI-NEXT: ldr w16, [sp, #224]
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w17, w18, w8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: sxth w18, w14
+; CHECK-GI-NEXT: ldr w14, [sp, #296]
+; CHECK-GI-NEXT: ldr w10, [sp, #200]
+; CHECK-GI-NEXT: mov v26.h[1], w17
+; CHECK-GI-NEXT: lsl w17, w16, #8
+; CHECK-GI-NEXT: fmov s24, w15
+; CHECK-GI-NEXT: ldr w15, [sp, #232]
+; CHECK-GI-NEXT: asr w16, w18, w8
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: sxth w17, w17
+; CHECK-GI-NEXT: mov v25.h[3], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #304]
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: mov v24.h[1], w16
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: asr w17, w17, w8
+; CHECK-GI-NEXT: sxth w18, w12
+; CHECK-GI-NEXT: ldr w16, [sp, #240]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w12, w14, w8
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: mov v26.h[2], w17
+; CHECK-GI-NEXT: asr w17, w18, w8
+; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: mov v24.h[2], w12
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v25.h[4], w17
+; CHECK-GI-NEXT: ldr w17, [sp, #312]
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: ldr w14, [sp, #248]
+; CHECK-GI-NEXT: ldr w12, [sp, #256]
+; CHECK-GI-NEXT: mov v26.h[3], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #344]
+; CHECK-GI-NEXT: lsl w17, w17, #8
+; CHECK-GI-NEXT: mov v24.h[3], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #352]
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w17, w17
+; CHECK-GI-NEXT: mov v25.h[5], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #320]
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v19.s[1], wzr
-; CHECK-GI-NEXT: mov v24.h[3], w10
-; CHECK-GI-NEXT: sbfx w10, w14, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #280]
-; CHECK-GI-NEXT: mov v22.h[7], w16
-; CHECK-GI-NEXT: ldr w16, [sp, #288]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mov v23.h[7], w10
-; CHECK-GI-NEXT: lsl w18, w16, #8
-; CHECK-GI-NEXT: fmov s27, w12
-; CHECK-GI-NEXT: ldr w10, [sp, #232]
-; CHECK-GI-NEXT: sbfx w16, w14, #8, #8
-; CHECK-GI-NEXT: mov v24.h[4], w15
-; CHECK-GI-NEXT: lsl w15, w11, #8
-; CHECK-GI-NEXT: sbfx w14, w18, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #296]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: fmov s25, w16
-; CHECK-GI-NEXT: ldr w16, [sp, #344]
-; CHECK-GI-NEXT: mov v27.h[1], w13
-; CHECK-GI-NEXT: lsl w13, w17, #8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: mov v26.h[4], w16
+; CHECK-GI-NEXT: asr w16, w17, w8
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: mov v24.h[4], w16
+; CHECK-GI-NEXT: ldr w16, [sp, #360]
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: fmov s28, w15
; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: ldr w12, [sp, #240]
-; CHECK-GI-NEXT: sbfx w17, w10, #8, #8
-; CHECK-GI-NEXT: mov v25.h[1], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #352]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v24.h[5], w15
-; CHECK-GI-NEXT: mov v27.h[2], w13
-; CHECK-GI-NEXT: lsl w13, w14, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #304]
-; CHECK-GI-NEXT: fmov s26, w16
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: ldr w15, [sp, #248]
-; CHECK-GI-NEXT: mov v25.h[2], w11
-; CHECK-GI-NEXT: ldr w11, [sp, #360]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: mov v24.h[6], w9
-; CHECK-GI-NEXT: lsl w16, w11, #8
-; CHECK-GI-NEXT: mov v26.h[1], w13
-; CHECK-GI-NEXT: mov v27.h[3], w17
-; CHECK-GI-NEXT: sbfx w13, w14, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #312]
; CHECK-GI-NEXT: ldr w17, [sp, #328]
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #256]
-; CHECK-GI-NEXT: ldr w11, [sp, #264]
-; CHECK-GI-NEXT: mov v25.h[3], w13
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: mov v26.h[5], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #416]
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: lsl w17, w17, #8
+; CHECK-GI-NEXT: ldr w15, [sp, #336]
+; CHECK-GI-NEXT: mov v28.h[1], w13
; CHECK-GI-NEXT: ldr w13, [sp, #368]
+; CHECK-GI-NEXT: mov v24.h[5], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #408]
+; CHECK-GI-NEXT: asr w16, w16, w8
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: mov v26.h[2], w16
-; CHECK-GI-NEXT: ldr w16, [sp, #320]
-; CHECK-GI-NEXT: mov v27.h[4], w12
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w9, w14, #8, #8
-; CHECK-GI-NEXT: lsl w14, w15, #8
-; CHECK-GI-NEXT: lsl w15, w16, #8
-; CHECK-GI-NEXT: ldr w16, [sp, #408]
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: sbfx w12, w13, #8, #8
-; CHECK-GI-NEXT: ldr w13, [sp, #376]
-; CHECK-GI-NEXT: mov v25.h[4], w9
-; CHECK-GI-NEXT: sbfx w9, w14, #8, #8
-; CHECK-GI-NEXT: sbfx w14, w15, #8, #8
-; CHECK-GI-NEXT: lsl w15, w16, #8
-; CHECK-GI-NEXT: mov v26.h[3], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #416]
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: lsl w16, w17, #8
-; CHECK-GI-NEXT: mov v27.h[5], w9
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
+; CHECK-GI-NEXT: sxth w17, w17
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: sxth w14, w14
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v25.h[5], w14
-; CHECK-GI-NEXT: fmov s29, w15
-; CHECK-GI-NEXT: ldr w14, [sp, #384]
-; CHECK-GI-NEXT: ldr w15, [sp, #472]
-; CHECK-GI-NEXT: mov v26.h[4], w13
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v28.h[2], w16
+; CHECK-GI-NEXT: ldr w16, [sp, #376]
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: asr w17, w17, w8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: mov v24.h[6], w17
+; CHECK-GI-NEXT: ldr w17, [sp, #384]
+; CHECK-GI-NEXT: mov v28.h[3], w13
; CHECK-GI-NEXT: ldr w13, [sp, #424]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: fmov s27, w11
+; CHECK-GI-NEXT: ldr w11, [sp, #472]
+; CHECK-GI-NEXT: asr w15, w15, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v29.h[1], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #480]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v25.h[6], w16
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: lsl w17, w17, #8
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: mov v24.h[7], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #392]
+; CHECK-GI-NEXT: mov v27.h[1], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #480]
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: mov v28.h[4], w16
; CHECK-GI-NEXT: ldr w16, [sp, #432]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v26.h[5], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #392]
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w17, w17
+; CHECK-GI-NEXT: asr w11, w11, w8
; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: mov v29.h[2], w13
-; CHECK-GI-NEXT: fmov s28, w15
-; CHECK-GI-NEXT: ldr w9, [sp, #336]
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: mov v27.h[2], w13
; CHECK-GI-NEXT: ldr w13, [sp, #488]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: ldr w15, [sp, #440]
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: fmov s29, w11
+; CHECK-GI-NEXT: asr w17, w17, w8
+; CHECK-GI-NEXT: ldr w11, [sp, #400]
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v28.h[1], w12
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: mov v29.h[3], w16
-; CHECK-GI-NEXT: ldr w16, [sp, #496]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: ldr w12, [sp, #400]
-; CHECK-GI-NEXT: mov v26.h[6], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #448]
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: mov v28.h[2], w13
-; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: mov v25.h[7], w9
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v29.h[4], w15
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: mov v28.h[5], w17
+; CHECK-GI-NEXT: ldr w17, [sp, #496]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: mov v29.h[1], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #440]
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: lsl w17, w17, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: ldr w13, [sp, #456]
-; CHECK-GI-NEXT: ldr w15, [sp, #504]
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: sbfx w9, w12, #8, #8
-; CHECK-GI-NEXT: sbfx w12, w14, #8, #8
+; CHECK-GI-NEXT: asr w13, w13, w8
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: lsl w14, w15, #8
-; CHECK-GI-NEXT: mov v28.h[3], w16
-; CHECK-GI-NEXT: ldr w15, [sp, #512]
+; CHECK-GI-NEXT: mov v27.h[3], w16
+; CHECK-GI-NEXT: ldr w16, [sp, #448]
+; CHECK-GI-NEXT: sxth w17, w17
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: mov v29.h[2], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #504]
+; CHECK-GI-NEXT: mov v28.h[6], w15
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: asr w17, w17, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mul v30.8h, v22.8h, v25.8h
-; CHECK-GI-NEXT: mov v26.h[7], w9
-; CHECK-GI-NEXT: mov v29.h[5], w12
-; CHECK-GI-NEXT: lsl w8, w8, #8
-; CHECK-GI-NEXT: sbfx w9, w14, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: sbfx w14, w11, #8, #8
-; CHECK-GI-NEXT: sbfx w11, w13, #8, #8
-; CHECK-GI-NEXT: lsl w13, w15, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: mov v27.h[4], w14
+; CHECK-GI-NEXT: mov v29.h[3], w17
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v28.h[7], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #512]
+; CHECK-GI-NEXT: ldr w14, [sp, #456]
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
; CHECK-GI-NEXT: ldr w17, [sp, #464]
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: mov v28.h[4], w9
-; CHECK-GI-NEXT: mov v27.h[6], w10
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v27.h[5], w16
; CHECK-GI-NEXT: ldr w16, [sp, #520]
-; CHECK-GI-NEXT: sbfx w10, w13, #8, #8
-; CHECK-GI-NEXT: smov w13, v30.h[0]
-; CHECK-GI-NEXT: mov v24.h[7], w8
-; CHECK-GI-NEXT: lsl w8, w17, #8
-; CHECK-GI-NEXT: mov v29.h[6], w11
-; CHECK-GI-NEXT: mul v26.8h, v23.8h, v26.8h
-; CHECK-GI-NEXT: lsl w15, w16, #8
-; CHECK-GI-NEXT: smov w16, v30.h[1]
-; CHECK-GI-NEXT: ldr w12, [sp, #528]
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: mov v28.h[5], w10
-; CHECK-GI-NEXT: mov v27.h[7], w14
-; CHECK-GI-NEXT: fmov s22, w13
-; CHECK-GI-NEXT: sbfx w10, w15, #8, #8
-; CHECK-GI-NEXT: smov w14, v30.h[4]
-; CHECK-GI-NEXT: mov v29.h[7], w8
-; CHECK-GI-NEXT: smov w15, v26.h[0]
-; CHECK-GI-NEXT: smov w13, v30.h[2]
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #544]
-; CHECK-GI-NEXT: ldr w11, [sp, #552]
-; CHECK-GI-NEXT: mov v22.s[1], w16
-; CHECK-GI-NEXT: smov w16, v26.h[4]
-; CHECK-GI-NEXT: mov v28.h[6], w10
-; CHECK-GI-NEXT: smov w10, v26.h[1]
+; CHECK-GI-NEXT: mov v29.h[4], w13
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: mul v31.8h, v22.8h, v24.8h
+; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: ldr w15, [sp, #264]
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: ldr w13, [sp, #528]
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: mul v28.8h, v23.8h, v28.8h
+; CHECK-GI-NEXT: mov v29.h[5], w11
+; CHECK-GI-NEXT: lsl w11, w17, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: mov v25.h[6], w9
+; CHECK-GI-NEXT: sxth w9, w11
+; CHECK-GI-NEXT: mov v27.h[6], w14
+; CHECK-GI-NEXT: mov v26.h[6], w12
+; CHECK-GI-NEXT: smov w12, v31.h[0]
+; CHECK-GI-NEXT: smov w14, v31.h[4]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: sxth w11, w13
+; CHECK-GI-NEXT: mov v29.h[6], w16
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: smov w16, v28.h[0]
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: smov w13, v31.h[1]
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: mov v25.h[7], w10
+; CHECK-GI-NEXT: smov w10, v31.h[5]
+; CHECK-GI-NEXT: mov v27.h[7], w9
+; CHECK-GI-NEXT: smov w17, v28.h[1]
+; CHECK-GI-NEXT: fmov s22, w12
; CHECK-GI-NEXT: fmov s23, w14
-; CHECK-GI-NEXT: smov w14, v26.h[5]
-; CHECK-GI-NEXT: mul v29.8h, v24.8h, v29.8h
-; CHECK-GI-NEXT: fmov s24, w15
-; CHECK-GI-NEXT: smov w15, v26.h[2]
-; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: smov w8, v30.h[5]
-; CHECK-GI-NEXT: smov w17, v30.h[7]
-; CHECK-GI-NEXT: fmov s25, w16
-; CHECK-GI-NEXT: mov v22.s[2], w13
-; CHECK-GI-NEXT: smov w13, v30.h[3]
-; CHECK-GI-NEXT: mov v24.s[1], w10
-; CHECK-GI-NEXT: smov w16, v26.h[6]
-; CHECK-GI-NEXT: sbfx w10, w12, #8, #8
+; CHECK-GI-NEXT: mov v26.h[7], w15
+; CHECK-GI-NEXT: mov v29.h[7], w11
+; CHECK-GI-NEXT: fmov s24, w16
+; CHECK-GI-NEXT: smov w9, v31.h[2]
+; CHECK-GI-NEXT: smov w11, v31.h[6]
+; CHECK-GI-NEXT: mov v22.s[1], w13
+; CHECK-GI-NEXT: smov w12, v28.h[2]
+; CHECK-GI-NEXT: smov w14, v31.h[3]
+; CHECK-GI-NEXT: mov v23.s[1], w10
+; CHECK-GI-NEXT: mul v30.8h, v25.8h, v27.8h
+; CHECK-GI-NEXT: smov w10, v28.h[4]
+; CHECK-GI-NEXT: mov v24.s[1], w17
+; CHECK-GI-NEXT: mul v29.8h, v26.8h, v29.8h
+; CHECK-GI-NEXT: smov w15, v31.h[7]
+; CHECK-GI-NEXT: smov w13, v28.h[5]
+; CHECK-GI-NEXT: smov w0, v28.h[7]
+; CHECK-GI-NEXT: mov v16.s[1], wzr
+; CHECK-GI-NEXT: mov v22.s[2], w9
+; CHECK-GI-NEXT: smov w9, v28.h[3]
+; CHECK-GI-NEXT: mov v18.s[1], wzr
+; CHECK-GI-NEXT: mov v23.s[2], w11
+; CHECK-GI-NEXT: smov w11, v30.h[0]
+; CHECK-GI-NEXT: smov w17, v30.h[4]
+; CHECK-GI-NEXT: mov v24.s[2], w12
; CHECK-GI-NEXT: smov w18, v29.h[0]
-; CHECK-GI-NEXT: smov w0, v29.h[1]
-; CHECK-GI-NEXT: ldr w12, [sp, #560]
-; CHECK-GI-NEXT: mov v25.s[1], w14
-; CHECK-GI-NEXT: smov w14, v26.h[7]
-; CHECK-GI-NEXT: mov v28.h[7], w10
-; CHECK-GI-NEXT: mov v22.s[3], w13
-; CHECK-GI-NEXT: smov w13, v26.h[3]
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v24.s[2], w15
-; CHECK-GI-NEXT: smov w15, v29.h[2]
+; CHECK-GI-NEXT: smov w16, v30.h[1]
+; CHECK-GI-NEXT: fmov s25, w10
+; CHECK-GI-NEXT: smov w10, v28.h[6]
+; CHECK-GI-NEXT: ldr w12, [sp, #544]
+; CHECK-GI-NEXT: mov v22.s[3], w14
+; CHECK-GI-NEXT: smov w14, v30.h[5]
+; CHECK-GI-NEXT: mov v17.s[1], wzr
+; CHECK-GI-NEXT: fmov s26, w11
+; CHECK-GI-NEXT: fmov s27, w17
+; CHECK-GI-NEXT: mov v23.s[3], w15
+; CHECK-GI-NEXT: mov v24.s[3], w9
+; CHECK-GI-NEXT: smov w9, v29.h[1]
+; CHECK-GI-NEXT: fmov s28, w18
+; CHECK-GI-NEXT: smov w15, v30.h[2]
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: fmov s26, w18
-; CHECK-GI-NEXT: mov v23.s[1], w8
-; CHECK-GI-NEXT: smov w8, v30.h[6]
-; CHECK-GI-NEXT: mov v25.s[2], w16
-; CHECK-GI-NEXT: lsl w16, w9, #8
-; CHECK-GI-NEXT: mul v31.8h, v27.8h, v28.8h
+; CHECK-GI-NEXT: mov v25.s[1], w13
+; CHECK-GI-NEXT: mov v26.s[1], w16
+; CHECK-GI-NEXT: mov v27.s[1], w14
+; CHECK-GI-NEXT: smov w14, v30.h[6]
+; CHECK-GI-NEXT: smov w16, v29.h[2]
+; CHECK-GI-NEXT: ldr w13, [sp, #552]
+; CHECK-GI-NEXT: ldr w17, [sp, #616]
+; CHECK-GI-NEXT: mov v28.s[1], w9
+; CHECK-GI-NEXT: ldr w11, [sp, #560]
+; CHECK-GI-NEXT: ldr w9, [sp, #576]
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: mov v25.s[2], w10
; CHECK-GI-NEXT: ldr w10, [sp, #568]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #584]
-; CHECK-GI-NEXT: mov v24.s[3], w13
-; CHECK-GI-NEXT: smov w13, v29.h[4]
-; CHECK-GI-NEXT: mov v26.s[1], w0
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v23.s[2], w8
-; CHECK-GI-NEXT: mov v25.s[3], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #608]
-; CHECK-GI-NEXT: ldr w8, [sp, #576]
-; CHECK-GI-NEXT: fmov s8, w16
-; CHECK-GI-NEXT: ldr w16, [sp, #616]
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: fmov s27, w13
-; CHECK-GI-NEXT: lsl w13, w14, #8
; CHECK-GI-NEXT: mov v26.s[2], w15
-; CHECK-GI-NEXT: smov w15, v29.h[5]
-; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: ldr w15, [sp, #608]
+; CHECK-GI-NEXT: mov v27.s[2], w14
+; CHECK-GI-NEXT: sxth w14, w12
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: mov v28.s[2], w16
+; CHECK-GI-NEXT: lsl w16, w15, #8
+; CHECK-GI-NEXT: lsl w15, w17, #8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: fmov s8, w14
; CHECK-GI-NEXT: ldr w14, [sp, #624]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mov v8.h[1], w11
-; CHECK-GI-NEXT: lsl w8, w8, #8
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: sxth w10, w10
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: mov v23.s[3], w17
-; CHECK-GI-NEXT: fmov s9, w13
-; CHECK-GI-NEXT: ldr w13, [sp, #632]
-; CHECK-GI-NEXT: smov w17, v31.h[1]
-; CHECK-GI-NEXT: mov v27.s[1], w15
-; CHECK-GI-NEXT: smov w15, v31.h[0]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v8.h[2], w12
-; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: mov v9.h[1], w16
-; CHECK-GI-NEXT: smov w16, v31.h[2]
; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #592]
-; CHECK-GI-NEXT: ldr w12, [sp, #600]
-; CHECK-GI-NEXT: fmov s28, w15
-; CHECK-GI-NEXT: smov w15, v29.h[6]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v8.h[3], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #640]
+; CHECK-GI-NEXT: ldr w12, [sp, #584]
+; CHECK-GI-NEXT: mov v8.h[1], w13
+; CHECK-GI-NEXT: fmov s9, w16
+; CHECK-GI-NEXT: smov w13, v29.h[4]
+; CHECK-GI-NEXT: ldr w16, [sp, #632]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: ldr w17, [sp, #760]
+; CHECK-GI-NEXT: mov v9.h[1], w15
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: mov v8.h[2], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #640]
+; CHECK-GI-NEXT: fmov s31, w13
+; CHECK-GI-NEXT: smov w13, v29.h[5]
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: asr w9, w9, w8
; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: ldr w15, [sp, #592]
+; CHECK-GI-NEXT: sxth w12, w12
; CHECK-GI-NEXT: mov v9.h[2], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #672]
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v28.s[1], w17
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: ldr w14, [sp, #600]
+; CHECK-GI-NEXT: mov v8.h[3], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #672]
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: mov v31.s[1], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #680]
+; CHECK-GI-NEXT: asr w12, w12, w8
; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: mov v27.s[2], w15
-; CHECK-GI-NEXT: ldr w15, [sp, #680]
-; CHECK-GI-NEXT: mov v8.h[4], w8
-; CHECK-GI-NEXT: smov w8, v31.h[4]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: mov v9.h[3], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #688]
-; CHECK-GI-NEXT: mov v28.s[2], w16
-; CHECK-GI-NEXT: ldr w16, [sp, #648]
-; CHECK-GI-NEXT: fmov s10, w14
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #656]
+; CHECK-GI-NEXT: mov v9.h[3], w16
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: fmov s30, w8
-; CHECK-GI-NEXT: sbfx w8, w10, #8, #8
-; CHECK-GI-NEXT: smov w10, v31.h[5]
-; CHECK-GI-NEXT: mov v8.h[5], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #696]
-; CHECK-GI-NEXT: mov v10.h[1], w15
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mov v9.h[4], w8
+; CHECK-GI-NEXT: ldr w16, [sp, #648]
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: mov v8.h[4], w9
+; CHECK-GI-NEXT: ldr w9, [sp, #656]
+; CHECK-GI-NEXT: sxth w13, w13
; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w10, w10, w8
; CHECK-GI-NEXT: lsl w9, w9, #8
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: ldr w8, [sp, #704]
-; CHECK-GI-NEXT: ldr w15, [sp, #664]
-; CHECK-GI-NEXT: ldr w17, [sp, #768]
-; CHECK-GI-NEXT: mov v30.s[1], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #744]
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: mov v10.h[2], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #736]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: mov v9.h[4], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #688]
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: fmov s10, w10
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: mov v8.h[5], w12
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: ldr w12, [sp, #704]
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: mov v10.h[1], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #696]
+; CHECK-GI-NEXT: sxth w11, w11
; CHECK-GI-NEXT: mov v9.h[5], w16
-; CHECK-GI-NEXT: mov v8.h[6], w11
+; CHECK-GI-NEXT: mov v8.h[6], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #736]
+; CHECK-GI-NEXT: asr w11, w11, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #712]
-; CHECK-GI-NEXT: lsl w8, w8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: ldr w16, [sp, #720]
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: lsl w12, w12, #8
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mov v10.h[3], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #752]
-; CHECK-GI-NEXT: mov v8.h[7], w12
-; CHECK-GI-NEXT: sbfx w12, w8, #8, #8
-; CHECK-GI-NEXT: lsl w18, w16, #8
-; CHECK-GI-NEXT: fmov s11, w13
-; CHECK-GI-NEXT: ldr w13, [sp, #760]
-; CHECK-GI-NEXT: ldr w8, [sp, #784]
-; CHECK-GI-NEXT: mov v21.s[1], wzr
-; CHECK-GI-NEXT: mov v16.s[1], wzr
-; CHECK-GI-NEXT: mov v18.s[1], wzr
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: mov v10.h[2], w11
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: ldr w10, [sp, #664]
+; CHECK-GI-NEXT: mov v9.h[6], w9
+; CHECK-GI-NEXT: ldr w9, [sp, #744]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: mov v8.h[7], w14
+; CHECK-GI-NEXT: lsl w14, w9, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: mov v10.h[3], w13
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: ldr w16, [sp, #712]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: ldr w13, [sp, #752]
+; CHECK-GI-NEXT: fmov s11, w15
+; CHECK-GI-NEXT: ldr w15, [sp, #816]
+; CHECK-GI-NEXT: ldr w11, [sp, #720]
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: asr w10, w10, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
; CHECK-GI-NEXT: mov v10.h[4], w12
-; CHECK-GI-NEXT: sbfx w12, w15, #8, #8
-; CHECK-GI-NEXT: mov v11.h[1], w10
-; CHECK-GI-NEXT: sbfx w10, w14, #8, #8
-; CHECK-GI-NEXT: lsl w14, w9, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: ldr w9, [sp, #776]
-; CHECK-GI-NEXT: lsl w8, w8, #8
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v9.h[6], w10
-; CHECK-GI-NEXT: lsl w10, w11, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #808]
-; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: mov v11.h[2], w14
-; CHECK-GI-NEXT: ldr w14, [sp, #816]
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: mov v17.s[1], wzr
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: mov v9.h[7], w12
+; CHECK-GI-NEXT: ldr w12, [sp, #808]
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: mov v11.h[1], w14
+; CHECK-GI-NEXT: mov v9.h[7], w10
+; CHECK-GI-NEXT: lsl w10, w16, #8
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: lsl w18, w11, #8
+; CHECK-GI-NEXT: ldr w11, [sp, #832]
+; CHECK-GI-NEXT: sxth w14, w12
; CHECK-GI-NEXT: ldr w12, [sp, #824]
-; CHECK-GI-NEXT: sbfx w16, w11, #8, #8
-; CHECK-GI-NEXT: mov v10.h[5], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #832]
-; CHECK-GI-NEXT: mov v11.h[3], w13
-; CHECK-GI-NEXT: sbfx w15, w14, #8, #8
-; CHECK-GI-NEXT: lsl w14, w17, #8
-; CHECK-GI-NEXT: fmov s12, w16
-; CHECK-GI-NEXT: ldr w16, [sp, #872]
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: asr w16, w10, w8
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #840]
-; CHECK-GI-NEXT: sbfx w13, w18, #8, #8
-; CHECK-GI-NEXT: sbfx w17, w12, #8, #8
-; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: ldr w12, [sp, #856]
+; CHECK-GI-NEXT: mov v11.h[2], w13
+; CHECK-GI-NEXT: mov v10.h[5], w16
+; CHECK-GI-NEXT: sxth w13, w18
+; CHECK-GI-NEXT: lsl w16, w17, #8
+; CHECK-GI-NEXT: fmov s12, w14
+; CHECK-GI-NEXT: ldr w14, [sp, #872]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: ldr w9, [sp, #768]
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w11, w11
; CHECK-GI-NEXT: mov v12.h[1], w15
-; CHECK-GI-NEXT: mov v11.h[4], w14
; CHECK-GI-NEXT: ldr w15, [sp, #880]
-; CHECK-GI-NEXT: lsl w11, w11, #8
; CHECK-GI-NEXT: mov v10.h[6], w13
-; CHECK-GI-NEXT: ldr w13, [sp, #848]
-; CHECK-GI-NEXT: lsl w14, w15, #8
-; CHECK-GI-NEXT: sbfx w15, w16, #8, #8
-; CHECK-GI-NEXT: ldr w16, [sp, #888]
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: ldr w13, [sp, #840]
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: lsl w9, w9, #8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: asr w14, w14, w8
; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: ldr w10, [sp, #776]
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: mov v12.h[2], w12
+; CHECK-GI-NEXT: mov v11.h[3], w16
+; CHECK-GI-NEXT: fmov s13, w14
+; CHECK-GI-NEXT: ldr w12, [sp, #888]
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: lsl w10, w10, #8
+; CHECK-GI-NEXT: ldr w16, [sp, #848]
; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: mov v20.s[1], wzr
-; CHECK-GI-NEXT: mov v12.h[2], w17
-; CHECK-GI-NEXT: lsl w17, w10, #8
-; CHECK-GI-NEXT: mov v11.h[5], w9
-; CHECK-GI-NEXT: fmov s13, w15
-; CHECK-GI-NEXT: ldr w9, [sp, #936]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: sbfx w15, w17, #8, #8
-; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: ldr w17, [sp, #904]
+; CHECK-GI-NEXT: mov v13.h[1], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #896]
+; CHECK-GI-NEXT: mov v12.h[3], w11
+; CHECK-GI-NEXT: sxth w11, w13
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v11.h[4], w9
+; CHECK-GI-NEXT: lsl w13, w15, #8
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: ldr w14, [sp, #856]
+; CHECK-GI-NEXT: asr w15, w11, w8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: ldr w9, [sp, #912]
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: mov v12.h[4], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #936]
+; CHECK-GI-NEXT: mov v13.h[2], w12
+; CHECK-GI-NEXT: mov v11.h[5], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #944]
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: lsl w12, w16, #8
+; CHECK-GI-NEXT: lsl w16, w17, #8
+; CHECK-GI-NEXT: lsl w10, w10, #8
; CHECK-GI-NEXT: lsl w9, w9, #8
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: ldr w10, [sp, #864]
-; CHECK-GI-NEXT: mov v12.h[3], w15
-; CHECK-GI-NEXT: mov v11.h[6], w8
-; CHECK-GI-NEXT: sbfx w8, w11, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #1000]
-; CHECK-GI-NEXT: mov v13.h[1], w14
-; CHECK-GI-NEXT: ldr w15, [sp, #944]
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #896]
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: lsl w11, w11, #8
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: mov v13.h[3], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #952]
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: fmov s14, w15
+; CHECK-GI-NEXT: ldr w15, [sp, #1000]
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: mov v12.h[5], w12
+; CHECK-GI-NEXT: mov v13.h[4], w16
+; CHECK-GI-NEXT: ldr w12, [sp, #960]
; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: mov v14.h[1], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #1008]
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: ldr w16, [sp, #968]
; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: mov v12.h[4], w8
-; CHECK-GI-NEXT: ldr w8, [sp, #1008]
-; CHECK-GI-NEXT: fmov s14, w9
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v13.h[2], w16
-; CHECK-GI-NEXT: ldr w16, [sp, #952]
+; CHECK-GI-NEXT: mov v12.h[6], w14
+; CHECK-GI-NEXT: ldr w14, [sp, #1016]
+; CHECK-GI-NEXT: mov v13.h[5], w9
+; CHECK-GI-NEXT: smov w9, v30.h[3]
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: mov v14.h[2], w13
+; CHECK-GI-NEXT: asr w13, w15, w8
+; CHECK-GI-NEXT: sxth w17, w10
+; CHECK-GI-NEXT: smov w10, v30.h[7]
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: lsl w17, w8, #8
-; CHECK-GI-NEXT: smov w8, v29.h[3]
-; CHECK-GI-NEXT: smov w9, v29.h[7]
-; CHECK-GI-NEXT: fmov s29, w11
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v14.h[1], w15
-; CHECK-GI-NEXT: sbfx w15, w17, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #904]
+; CHECK-GI-NEXT: ldr w11, [sp, #920]
+; CHECK-GI-NEXT: fmov s30, w13
+; CHECK-GI-NEXT: asr w15, w17, w8
+; CHECK-GI-NEXT: ldr w13, [sp, #1024]
; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: mov v12.h[5], w13
-; CHECK-GI-NEXT: mov v13.h[3], w14
-; CHECK-GI-NEXT: mov v29.h[1], w15
-; CHECK-GI-NEXT: ldr w15, [sp, #960]
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w14, w14
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #1016]
-; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: ldr w13, [sp, #1024]
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v14.h[2], w16
-; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: ldr w16, [sp, #912]
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v13.h[4], w11
-; CHECK-GI-NEXT: ldr w11, [sp, #968]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v12.h[6], w12
-; CHECK-GI-NEXT: ldr w12, [sp, #976]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mov v14.h[3], w15
-; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: mov v29.h[2], w14
-; CHECK-GI-NEXT: ldr w15, [sp, #1032]
-; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: lsl w12, w12, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: ldr w14, [sp, #920]
-; CHECK-GI-NEXT: mov v26.s[3], w8
-; CHECK-GI-NEXT: sbfx w16, w16, #8, #8
+; CHECK-GI-NEXT: mov v26.s[3], w9
+; CHECK-GI-NEXT: mov v30.h[1], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #976]
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: mov v14.h[3], w12
+; CHECK-GI-NEXT: ldr w12, [sp, #1032]
+; CHECK-GI-NEXT: sxth w11, w11
; CHECK-GI-NEXT: lsl w15, w15, #8
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: mov v14.h[4], w11
-; CHECK-GI-NEXT: mov v29.h[3], w13
-; CHECK-GI-NEXT: ldr w11, [sp, #984]
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: mov v27.s[3], w10
+; CHECK-GI-NEXT: mov v30.h[2], w14
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: mov v14.h[4], w16
+; CHECK-GI-NEXT: ldr w14, [sp, #784]
+; CHECK-GI-NEXT: mov v13.h[6], w11
+; CHECK-GI-NEXT: ldr w11, [sp, #928]
+; CHECK-GI-NEXT: asr w15, w15, w8
+; CHECK-GI-NEXT: sxth w12, w12
; CHECK-GI-NEXT: lsl w14, w14, #8
-; CHECK-GI-NEXT: sbfx w15, w15, #8, #8
-; CHECK-GI-NEXT: mov v13.h[5], w16
-; CHECK-GI-NEXT: ldr w16, [sp, #1040]
+; CHECK-GI-NEXT: ldr w16, [sp, #864]
+; CHECK-GI-NEXT: mov v30.h[3], w13
+; CHECK-GI-NEXT: ldr w13, [sp, #1040]
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: ldr w13, [sp, #928]
-; CHECK-GI-NEXT: sbfx w14, w14, #8, #8
-; CHECK-GI-NEXT: mov v12.h[7], w10
-; CHECK-GI-NEXT: mov v27.s[3], w9
-; CHECK-GI-NEXT: mov v14.h[5], w12
-; CHECK-GI-NEXT: mov v29.h[4], w15
-; CHECK-GI-NEXT: lsl w16, w16, #8
-; CHECK-GI-NEXT: sbfx w10, w11, #8, #8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: mov v14.h[5], w15
+; CHECK-GI-NEXT: ldr w15, [sp, #984]
; CHECK-GI-NEXT: lsl w13, w13, #8
-; CHECK-GI-NEXT: mov v13.h[6], w14
+; CHECK-GI-NEXT: sxth w14, w14
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: lsl w16, w16, #8
+; CHECK-GI-NEXT: mov v20.s[1], wzr
+; CHECK-GI-NEXT: mov v30.h[4], w12
; CHECK-GI-NEXT: ldr w12, [sp, #1048]
-; CHECK-GI-NEXT: sbfx w14, w16, #8, #8
-; CHECK-GI-NEXT: ldr w11, [sp, #728]
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: mul v15.8h, v8.8h, v12.8h
-; CHECK-GI-NEXT: smov w16, v31.h[6]
-; CHECK-GI-NEXT: mov v14.h[6], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #992]
-; CHECK-GI-NEXT: mov v29.h[5], w14
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: asr w11, w11, w8
+; CHECK-GI-NEXT: sxth w15, w15
+; CHECK-GI-NEXT: asr w13, w13, w8
; CHECK-GI-NEXT: lsl w12, w12, #8
+; CHECK-GI-NEXT: sxth w16, w16
+; CHECK-GI-NEXT: mov v11.h[6], w14
+; CHECK-GI-NEXT: mov v13.h[7], w11
+; CHECK-GI-NEXT: asr w11, w15, w8
+; CHECK-GI-NEXT: mov v30.h[5], w13
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: ldr w13, [sp, #728]
+; CHECK-GI-NEXT: ldr w14, [sp, #792]
+; CHECK-GI-NEXT: ldr w15, [sp, #992]
+; CHECK-GI-NEXT: asr w16, w16, w8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: lsl w13, w13, #8
+; CHECK-GI-NEXT: mov v14.h[6], w11
+; CHECK-GI-NEXT: lsl w14, w14, #8
+; CHECK-GI-NEXT: lsl w15, w15, #8
+; CHECK-GI-NEXT: mov v12.h[7], w16
+; CHECK-GI-NEXT: ldr w11, [sp, #1056]
+; CHECK-GI-NEXT: mov v30.h[6], w12
+; CHECK-GI-NEXT: sxth w12, w13
+; CHECK-GI-NEXT: sxth w13, w14
+; CHECK-GI-NEXT: sxth w14, w15
+; CHECK-GI-NEXT: smov w16, v29.h[6]
; CHECK-GI-NEXT: lsl w11, w11, #8
-; CHECK-GI-NEXT: mov v13.h[7], w13
-; CHECK-GI-NEXT: lsl w10, w10, #8
-; CHECK-GI-NEXT: ldr w13, [sp, #792]
-; CHECK-GI-NEXT: ldr w14, [sp, #1056]
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: mov v30.s[2], w16
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: smov w8, v15.h[1]
-; CHECK-GI-NEXT: smov w9, v15.h[5]
-; CHECK-GI-NEXT: mov v29.h[6], w12
-; CHECK-GI-NEXT: lsl w12, w13, #8
-; CHECK-GI-NEXT: lsl w13, w14, #8
-; CHECK-GI-NEXT: mov v10.h[7], w11
-; CHECK-GI-NEXT: mov v14.h[7], w10
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: smov w15, v29.h[3]
+; CHECK-GI-NEXT: asr w14, w14, w8
+; CHECK-GI-NEXT: mul v15.8h, v8.8h, v12.8h
+; CHECK-GI-NEXT: asr w13, w13, w8
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: mov v10.h[7], w12
; CHECK-GI-NEXT: mul v12.8h, v9.8h, v13.8h
-; CHECK-GI-NEXT: sbfx w12, w12, #8, #8
-; CHECK-GI-NEXT: sbfx w13, w13, #8, #8
-; CHECK-GI-NEXT: smov w10, v15.h[0]
-; CHECK-GI-NEXT: smov w11, v15.h[4]
-; CHECK-GI-NEXT: smov w14, v31.h[7]
-; CHECK-GI-NEXT: smov w15, v31.h[3]
-; CHECK-GI-NEXT: mov v11.h[7], w12
-; CHECK-GI-NEXT: mov v29.h[7], w13
-; CHECK-GI-NEXT: mov v6.s[1], wzr
+; CHECK-GI-NEXT: mov v14.h[7], w14
+; CHECK-GI-NEXT: mov v11.h[7], w13
+; CHECK-GI-NEXT: mov v31.s[2], w16
+; CHECK-GI-NEXT: asr w8, w11, w8
+; CHECK-GI-NEXT: smov w11, v29.h[7]
+; CHECK-GI-NEXT: mov v28.s[3], w15
+; CHECK-GI-NEXT: smov w12, v15.h[4]
+; CHECK-GI-NEXT: smov w9, v15.h[1]
+; CHECK-GI-NEXT: smov w10, v15.h[5]
+; CHECK-GI-NEXT: mov v30.h[7], w8
+; CHECK-GI-NEXT: smov w8, v15.h[0]
+; CHECK-GI-NEXT: smov w13, v12.h[0]
; CHECK-GI-NEXT: mul v13.8h, v10.8h, v14.8h
-; CHECK-GI-NEXT: smov w12, v12.h[0]
-; CHECK-GI-NEXT: smov w13, v12.h[1]
+; CHECK-GI-NEXT: smov w15, v12.h[5]
+; CHECK-GI-NEXT: mov v6.s[1], wzr
+; CHECK-GI-NEXT: mov v31.s[3], w11
+; CHECK-GI-NEXT: smov w11, v12.h[1]
; CHECK-GI-NEXT: mov v7.s[1], wzr
; CHECK-GI-NEXT: mov v2.s[1], wzr
; CHECK-GI-NEXT: mov v4.s[1], wzr
-; CHECK-GI-NEXT: fmov s31, w11
-; CHECK-GI-NEXT: mov v30.s[3], w14
-; CHECK-GI-NEXT: smov w11, v12.h[4]
-; CHECK-GI-NEXT: mul v14.8h, v11.8h, v29.8h
-; CHECK-GI-NEXT: fmov s29, w10
-; CHECK-GI-NEXT: smov w10, v15.h[2]
+; CHECK-GI-NEXT: mov v3.s[1], wzr
+; CHECK-GI-NEXT: mul v14.8h, v11.8h, v30.8h
+; CHECK-GI-NEXT: fmov s29, w8
+; CHECK-GI-NEXT: fmov s30, w12
; CHECK-GI-NEXT: smov w14, v13.h[0]
-; CHECK-GI-NEXT: fmov s8, w12
+; CHECK-GI-NEXT: fmov s8, w13
+; CHECK-GI-NEXT: smov w12, v12.h[4]
; CHECK-GI-NEXT: smov w16, v13.h[1]
-; CHECK-GI-NEXT: mov v31.s[1], w9
-; CHECK-GI-NEXT: smov w9, v12.h[2]
-; CHECK-GI-NEXT: mov v28.s[3], w15
-; CHECK-GI-NEXT: mov v29.s[1], w8
-; CHECK-GI-NEXT: smov w8, v15.h[6]
-; CHECK-GI-NEXT: smov w15, v12.h[5]
-; CHECK-GI-NEXT: mov v8.s[1], w13
-; CHECK-GI-NEXT: fmov s9, w11
-; CHECK-GI-NEXT: smov w12, v15.h[3]
+; CHECK-GI-NEXT: smov w8, v15.h[2]
+; CHECK-GI-NEXT: smov w13, v15.h[7]
+; CHECK-GI-NEXT: mov v29.s[1], w9
+; CHECK-GI-NEXT: smov w9, v15.h[6]
+; CHECK-GI-NEXT: mov v30.s[1], w10
+; CHECK-GI-NEXT: smov w10, v12.h[2]
+; CHECK-GI-NEXT: mov v8.s[1], w11
+; CHECK-GI-NEXT: smov w11, v15.h[3]
; CHECK-GI-NEXT: fmov s10, w14
+; CHECK-GI-NEXT: fmov s9, w12
; CHECK-GI-NEXT: smov w14, v13.h[2]
-; CHECK-GI-NEXT: smov w11, v12.h[6]
-; CHECK-GI-NEXT: smov w13, v15.h[7]
-; CHECK-GI-NEXT: mov v3.s[1], wzr
+; CHECK-GI-NEXT: smov w12, v12.h[6]
; CHECK-GI-NEXT: mov v5.s[1], wzr
-; CHECK-GI-NEXT: mov v31.s[2], w8
-; CHECK-GI-NEXT: smov w8, v13.h[4]
-; CHECK-GI-NEXT: mov v29.s[2], w10
+; CHECK-GI-NEXT: mov v25.s[3], w0
+; CHECK-GI-NEXT: mov v30.s[2], w9
+; CHECK-GI-NEXT: smov w9, v13.h[4]
+; CHECK-GI-NEXT: mov v29.s[2], w8
; CHECK-GI-NEXT: mov v10.s[1], w16
; CHECK-GI-NEXT: smov w16, v14.h[0]
-; CHECK-GI-NEXT: mov v8.s[2], w9
-; CHECK-GI-NEXT: smov w9, v13.h[5]
-; CHECK-GI-NEXT: smov w10, v12.h[3]
+; CHECK-GI-NEXT: mov v8.s[2], w10
+; CHECK-GI-NEXT: smov w10, v13.h[5]
+; CHECK-GI-NEXT: smov w8, v12.h[3]
; CHECK-GI-NEXT: mov v9.s[1], w15
; CHECK-GI-NEXT: smov w15, v13.h[6]
; CHECK-GI-NEXT: mov v1.s[1], wzr
; CHECK-GI-NEXT: mov v0.s[1], wzr
-; CHECK-GI-NEXT: fmov s11, w8
-; CHECK-GI-NEXT: smov w8, v14.h[1]
-; CHECK-GI-NEXT: mov v29.s[3], w12
+; CHECK-GI-NEXT: fmov s11, w9
+; CHECK-GI-NEXT: smov w9, v14.h[1]
+; CHECK-GI-NEXT: mov v29.s[3], w11
; CHECK-GI-NEXT: mov v10.s[2], w14
; CHECK-GI-NEXT: smov w14, v12.h[7]
; CHECK-GI-NEXT: fmov s12, w16
-; CHECK-GI-NEXT: smov w12, v14.h[4]
-; CHECK-GI-NEXT: mov v8.s[3], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #536]
-; CHECK-GI-NEXT: mov v11.s[1], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #272]
-; CHECK-GI-NEXT: mov v9.s[2], w11
-; CHECK-GI-NEXT: ldr w11, [sp, #800]
-; CHECK-GI-NEXT: mov v12.s[1], w8
-; CHECK-GI-NEXT: ldr w8, [sp, #1064]
-; CHECK-GI-NEXT: mov v31.s[3], w13
+; CHECK-GI-NEXT: smov w11, v14.h[4]
+; CHECK-GI-NEXT: mov v8.s[3], w8
+; CHECK-GI-NEXT: ldr w8, [sp, #536]
+; CHECK-GI-NEXT: mov v11.s[1], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #272]
+; CHECK-GI-NEXT: mov v9.s[2], w12
+; CHECK-GI-NEXT: ldr w12, [sp, #800]
+; CHECK-GI-NEXT: mov v12.s[1], w9
+; CHECK-GI-NEXT: ldr w9, [sp, #1064]
+; CHECK-GI-NEXT: mov v30.s[3], w13
; CHECK-GI-NEXT: smov w13, v14.h[5]
-; CHECK-GI-NEXT: sxtb w9, w9
; CHECK-GI-NEXT: sxtb w10, w10
-; CHECK-GI-NEXT: sxtb w11, w11
; CHECK-GI-NEXT: sxtb w8, w8
+; CHECK-GI-NEXT: sxtb w12, w12
+; CHECK-GI-NEXT: sxtb w9, w9
; CHECK-GI-NEXT: mov v11.s[2], w15
; CHECK-GI-NEXT: smov w15, v13.h[3]
; CHECK-GI-NEXT: smov w16, v13.h[7]
-; CHECK-GI-NEXT: fmov s13, w12
-; CHECK-GI-NEXT: mul w9, w9, w10
-; CHECK-GI-NEXT: smov w12, v14.h[2]
-; CHECK-GI-NEXT: mul w8, w11, w8
+; CHECK-GI-NEXT: fmov s13, w11
+; CHECK-GI-NEXT: mul w8, w10, w8
+; CHECK-GI-NEXT: smov w11, v14.h[2]
+; CHECK-GI-NEXT: mul w9, w12, w9
; CHECK-GI-NEXT: mov v19.s[2], wzr
; CHECK-GI-NEXT: mov v21.s[2], wzr
; CHECK-GI-NEXT: mov v16.s[2], wzr
@@ -6472,8 +6698,8 @@ define i32 @test_sdot_v33i8_double(<33 x i8> %a, <33 x i8> %b, <33 x i8> %c, <33
; CHECK-GI-NEXT: mov v17.s[2], wzr
; CHECK-GI-NEXT: mov v13.s[1], w13
; CHECK-GI-NEXT: smov w13, v14.h[6]
+; CHECK-GI-NEXT: sxth w8, w8
; CHECK-GI-NEXT: sxth w9, w9
-; CHECK-GI-NEXT: sxth w10, w8
; CHECK-GI-NEXT: mov v20.s[2], wzr
; CHECK-GI-NEXT: mov v6.s[2], wzr
; CHECK-GI-NEXT: mov v7.s[2], wzr
@@ -6483,9 +6709,9 @@ define i32 @test_sdot_v33i8_double(<33 x i8> %a, <33 x i8> %b, <33 x i8> %c, <33
; CHECK-GI-NEXT: mov v5.s[2], wzr
; CHECK-GI-NEXT: add v22.4s, v22.4s, v23.4s
; CHECK-GI-NEXT: add v25.4s, v24.4s, v25.4s
-; CHECK-GI-NEXT: fmov s23, w9
-; CHECK-GI-NEXT: fmov s24, w10
-; CHECK-GI-NEXT: mov v12.s[2], w12
+; CHECK-GI-NEXT: fmov s23, w8
+; CHECK-GI-NEXT: fmov s24, w9
+; CHECK-GI-NEXT: mov v12.s[2], w11
; CHECK-GI-NEXT: mov v13.s[2], w13
; CHECK-GI-NEXT: smov w8, v14.h[3]
; CHECK-GI-NEXT: smov w9, v14.h[7]
@@ -6521,10 +6747,10 @@ define i32 @test_sdot_v33i8_double(<33 x i8> %a, <33 x i8> %b, <33 x i8> %c, <33
; CHECK-GI-NEXT: mov v23.s[2], wzr
; CHECK-GI-NEXT: mov v24.s[2], wzr
; CHECK-GI-NEXT: add v26.4s, v26.4s, v27.4s
-; CHECK-GI-NEXT: add v27.4s, v28.4s, v30.4s
+; CHECK-GI-NEXT: add v27.4s, v28.4s, v31.4s
; CHECK-GI-NEXT: add v1.4s, v1.4s, v19.4s
; CHECK-GI-NEXT: add v4.4s, v16.4s, v17.4s
-; CHECK-GI-NEXT: add v5.4s, v29.4s, v31.4s
+; CHECK-GI-NEXT: add v5.4s, v29.4s, v30.4s
; CHECK-GI-NEXT: add v7.4s, v8.4s, v9.4s
; CHECK-GI-NEXT: add v16.4s, v10.4s, v11.4s
; CHECK-GI-NEXT: add v17.4s, v12.4s, v13.4s
diff --git a/llvm/test/CodeGen/AArch64/overflow-vec.ll b/llvm/test/CodeGen/AArch64/overflow-vec.ll
index 00a01b65b39a3..fa8c678cd1417 100644
--- a/llvm/test/CodeGen/AArch64/overflow-vec.ll
+++ b/llvm/test/CodeGen/AArch64/overflow-vec.ll
@@ -617,46 +617,53 @@ define <3 x i8> @smul_v3i8(<3 x i8> %a, <3 x i8> %b) {
;
; CHECK-GI-LABEL: smul_v3i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: lsl w8, w0, #8
-; CHECK-GI-NEXT: lsl w10, w3, #8
-; CHECK-GI-NEXT: lsl w9, w1, #8
-; CHECK-GI-NEXT: lsl w11, w4, #8
+; CHECK-GI-NEXT: lsl w9, w0, #8
+; CHECK-GI-NEXT: lsl w11, w3, #8
+; CHECK-GI-NEXT: mov w8, #8 // =0x8
+; CHECK-GI-NEXT: lsl w10, w1, #8
+; CHECK-GI-NEXT: lsl w12, w4, #8
; CHECK-GI-NEXT: fmov s0, w0
-; CHECK-GI-NEXT: fmov s1, w3
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: sbfx w10, w10, #8, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
-; CHECK-GI-NEXT: sbfx w11, w11, #8, #8
-; CHECK-GI-NEXT: lsl w12, w2, #8
-; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: fmov s3, w10
-; CHECK-GI-NEXT: lsl w8, w5, #8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: sxth w11, w11
+; CHECK-GI-NEXT: fmov s3, w3
+; CHECK-GI-NEXT: sxth w10, w10
+; CHECK-GI-NEXT: sxth w12, w12
+; CHECK-GI-NEXT: lsl w13, w2, #8
+; CHECK-GI-NEXT: asr w9, w9, w8
+; CHECK-GI-NEXT: asr w11, w11, w8
; CHECK-GI-NEXT: mov v0.h[1], w1
-; CHECK-GI-NEXT: mov v1.h[1], w4
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: mov v2.h[1], w9
-; CHECK-GI-NEXT: mov v3.h[1], w11
-; CHECK-GI-NEXT: sbfx w9, w12, #8, #8
+; CHECK-GI-NEXT: asr w10, w10, w8
+; CHECK-GI-NEXT: asr w12, w12, w8
+; CHECK-GI-NEXT: sxth w13, w13
+; CHECK-GI-NEXT: fmov s1, w9
+; CHECK-GI-NEXT: fmov s2, w11
+; CHECK-GI-NEXT: lsl w9, w5, #8
+; CHECK-GI-NEXT: mov v3.h[1], w4
+; CHECK-GI-NEXT: sxth w9, w9
; CHECK-GI-NEXT: mov v0.h[2], w2
-; CHECK-GI-NEXT: mov v1.h[2], w5
-; CHECK-GI-NEXT: mov v2.h[2], w9
-; CHECK-GI-NEXT: mov v3.h[2], w8
-; CHECK-GI-NEXT: mul v1.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: mul v2.4h, v2.4h, v3.4h
+; CHECK-GI-NEXT: mov v1.h[1], w10
+; CHECK-GI-NEXT: mov v2.h[1], w12
+; CHECK-GI-NEXT: asr w10, w13, w8
+; CHECK-GI-NEXT: asr w8, w9, w8
+; CHECK-GI-NEXT: mov v3.h[2], w5
+; CHECK-GI-NEXT: mov v1.h[2], w10
+; CHECK-GI-NEXT: mov v2.h[2], w8
+; CHECK-GI-NEXT: mul v1.4h, v1.4h, v2.4h
+; CHECK-GI-NEXT: mul v2.4h, v0.4h, v3.4h
; CHECK-GI-NEXT: movi v3.8b, #23
-; CHECK-GI-NEXT: uzp1 v4.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: sshr v2.4h, v2.4h, #8
+; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #8
+; CHECK-GI-NEXT: uzp1 v4.8b, v2.8b, v0.8b
; CHECK-GI-NEXT: neg v3.8b, v3.8b
-; CHECK-GI-NEXT: uzp1 v2.8b, v2.8b, v0.8b
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: sshl v3.8b, v4.8b, v3.8b
-; CHECK-GI-NEXT: cmeq v2.8b, v2.8b, v3.8b
+; CHECK-GI-NEXT: cmeq v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: movi d3, #0xffffffffffffffff
-; CHECK-GI-NEXT: mvn v2.8b, v2.8b
-; CHECK-GI-NEXT: zip1 v2.8b, v2.8b, v2.8b
-; CHECK-GI-NEXT: shl v2.4h, v2.4h, #15
-; CHECK-GI-NEXT: cmlt v2.4h, v2.4h, #0
-; CHECK-GI-NEXT: eor v3.8b, v2.8b, v3.8b
-; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: mvn v1.8b, v1.8b
+; CHECK-GI-NEXT: zip1 v1.8b, v1.8b, v1.8b
+; CHECK-GI-NEXT: shl v1.4h, v1.4h, #15
+; CHECK-GI-NEXT: cmlt v1.4h, v1.4h, #0
+; CHECK-GI-NEXT: eor v3.8b, v1.8b, v3.8b
+; CHECK-GI-NEXT: and v1.8b, v2.8b, v1.8b
; CHECK-GI-NEXT: and v0.8b, v0.8b, v3.8b
; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: umov w0, v0.h[0]
diff --git a/llvm/test/CodeGen/AArch64/rem-by-const.ll b/llvm/test/CodeGen/AArch64/rem-by-const.ll
index 187ab1d481a27..1947ae32833e4 100644
--- a/llvm/test/CodeGen/AArch64/rem-by-const.ll
+++ b/llvm/test/CodeGen/AArch64/rem-by-const.ll
@@ -21,9 +21,11 @@ define i8 @si8_7(i8 %a, i8 %b) {
; CHECK-GI-NEXT: sxtb w8, w0
; CHECK-GI-NEXT: mov w9, #-109 // =0xffffff93
; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #2 // =0x2
; CHECK-GI-NEXT: sxth w8, w8
; CHECK-GI-NEXT: add w8, w0, w8, asr #8
-; CHECK-GI-NEXT: sbfx w8, w8, #2, #6
+; CHECK-GI-NEXT: sxtb w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: ubfx w9, w8, #7, #1
; CHECK-GI-NEXT: add w8, w8, w9
; CHECK-GI-NEXT: sub w8, w8, w8, lsl #3
@@ -51,7 +53,9 @@ define i8 @si8_100(i8 %a, i8 %b) {
; CHECK-GI-NEXT: sxtb w8, w0
; CHECK-GI-NEXT: mov w9, #41 // =0x29
; CHECK-GI-NEXT: mul w8, w8, w9
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: mov w9, #8 // =0x8
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: asr w8, w8, #4
; CHECK-GI-NEXT: ubfx w9, w8, #7, #1
; CHECK-GI-NEXT: add w8, w8, w9
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat.ll b/llvm/test/CodeGen/AArch64/sadd_sat.ll
index 290031ac50ea7..a18552da5ae1c 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat.ll
@@ -61,13 +61,14 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
;
; CHECK-GI-LABEL: func16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sxth w8, w1
-; CHECK-GI-NEXT: add w8, w8, w0, sxth
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sxth w9, w1
+; CHECK-GI-NEXT: mov w8, #15 // =0xf
+; CHECK-GI-NEXT: add w9, w9, w0, sxth
+; CHECK-GI-NEXT: sxth w10, w9
+; CHECK-GI-NEXT: asr w8, w10, w8
+; CHECK-GI-NEXT: cmp w9, w10
+; CHECK-GI-NEXT: sub w8, w8, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -88,13 +89,14 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
;
; CHECK-GI-LABEL: func8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sxtb w8, w1
-; CHECK-GI-NEXT: add w8, w8, w0, sxtb
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sxtb w9, w1
+; CHECK-GI-NEXT: mov w8, #7 // =0x7
+; CHECK-GI-NEXT: add w9, w9, w0, sxtb
+; CHECK-GI-NEXT: sxtb w10, w9
+; CHECK-GI-NEXT: asr w8, w10, w8
+; CHECK-GI-NEXT: cmp w9, w10
+; CHECK-GI-NEXT: sub w8, w8, #128
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -116,14 +118,15 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
;
; CHECK-GI-LABEL: func3:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
-; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
-; CHECK-GI-NEXT: add w8, w8, w9
-; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
-; CHECK-GI-NEXT: asr w10, w9, #3
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: add w10, w10, #8
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
+; CHECK-GI-NEXT: sbfx w10, w1, #0, #4
+; CHECK-GI-NEXT: mov w8, #3 // =0x3
+; CHECK-GI-NEXT: add w9, w9, w10
+; CHECK-GI-NEXT: sbfx w10, w9, #0, #4
+; CHECK-GI-NEXT: asr w8, w10, w8
+; CHECK-GI-NEXT: cmp w9, w10
+; CHECK-GI-NEXT: add w8, w8, #8
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll b/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
index 4a0e49518517b..f1e8a66905883 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
@@ -73,12 +73,13 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; CHECK-GI-LABEL: func16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mul w8, w1, w2
+; CHECK-GI-NEXT: mov w10, #15 // =0xf
; CHECK-GI-NEXT: sxth w8, w8
; CHECK-GI-NEXT: add w8, w8, w0, sxth
; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i16 %y, %z
@@ -103,12 +104,13 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; CHECK-GI-LABEL: func8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mul w8, w1, w2
+; CHECK-GI-NEXT: mov w10, #7 // =0x7
; CHECK-GI-NEXT: sxtb w8, w8
; CHECK-GI-NEXT: add w8, w8, w0, sxtb
; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #128
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i8 %y, %z
@@ -135,10 +137,11 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
+; CHECK-GI-NEXT: mov w10, #3 // =0x3
; CHECK-GI-NEXT: sbfx w8, w8, #0, #4
; CHECK-GI-NEXT: add w8, w9, w8
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
-; CHECK-GI-NEXT: asr w10, w9, #3
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: add w10, w10, #8
; CHECK-GI-NEXT: csel w0, w10, w8, ne
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index 8d3a9ee8beba4..a08b62c13f153 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -279,11 +279,12 @@ define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldrsb w8, [x0]
; CHECK-GI-NEXT: ldrsb w9, [x1]
+; CHECK-GI-NEXT: mov w10, #7 // =0x7
; CHECK-GI-NEXT: add w8, w8, w9
; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #128
; CHECK-GI-NEXT: csel w8, w10, w8, ne
; CHECK-GI-NEXT: strb w8, [x2]
; CHECK-GI-NEXT: ret
@@ -307,11 +308,12 @@ define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldrsh w8, [x0]
; CHECK-GI-NEXT: ldrsh w9, [x1]
+; CHECK-GI-NEXT: mov w10, #15 // =0xf
; CHECK-GI-NEXT: add w8, w8, w9
; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
; CHECK-GI-NEXT: csel w8, w10, w8, ne
; CHECK-GI-NEXT: strh w8, [x2]
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/select_const.ll b/llvm/test/CodeGen/AArch64/select_const.ll
index daa9971dbcd58..c67d527dbfed1 100644
--- a/llvm/test/CodeGen/AArch64/select_const.ll
+++ b/llvm/test/CodeGen/AArch64/select_const.ll
@@ -672,7 +672,6 @@ define i8 @shl_constant_sel_constants(i1 %cond) {
; CHECK-GI-NEXT: sbfx w9, w0, #0, #1
; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: add w9, w9, #3
-; CHECK-GI-NEXT: and w9, w9, #0xff
; CHECK-GI-NEXT: lsl w0, w8, w9
; CHECK-GI-NEXT: ret
%sel = select i1 %cond, i8 2, i8 3
@@ -714,7 +713,6 @@ define i8 @lshr_constant_sel_constants(i1 %cond) {
; CHECK-GI-NEXT: sbfx w9, w0, #0, #1
; CHECK-GI-NEXT: mov w8, #64 // =0x40
; CHECK-GI-NEXT: add w9, w9, #3
-; CHECK-GI-NEXT: and w9, w9, #0xff
; CHECK-GI-NEXT: lsr w0, w8, w9
; CHECK-GI-NEXT: ret
%sel = select i1 %cond, i8 2, i8 3
@@ -747,7 +745,6 @@ define i8 @ashr_constant_sel_constants(i1 %cond) {
; CHECK-GI-NEXT: sbfx w9, w0, #0, #1
; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff80
; CHECK-GI-NEXT: add w9, w9, #3
-; CHECK-GI-NEXT: and w9, w9, #0xff
; CHECK-GI-NEXT: asr w0, w8, w9
; CHECK-GI-NEXT: ret
%sel = select i1 %cond, i8 2, i8 3
diff --git a/llvm/test/CodeGen/AArch64/sext.ll b/llvm/test/CodeGen/AArch64/sext.ll
index 278731ad0663a..6118e8912bb3c 100644
--- a/llvm/test/CodeGen/AArch64/sext.ll
+++ b/llvm/test/CodeGen/AArch64/sext.ll
@@ -221,11 +221,15 @@ define <3 x i16> @sext_v3i8_v3i16(<3 x i8> %a) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: lsl w8, w0, #8
; CHECK-GI-NEXT: lsl w9, w1, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
-; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
+; CHECK-GI-NEXT: mov w10, #8 // =0x8
+; CHECK-GI-NEXT: lsl w11, w2, #8
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: asr w8, w8, w10
+; CHECK-GI-NEXT: asr w9, w9, w10
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: lsl w8, w2, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: sxth w8, w11
+; CHECK-GI-NEXT: asr w8, w8, w10
; CHECK-GI-NEXT: mov v0.h[1], w9
; CHECK-GI-NEXT: mov v0.h[2], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
@@ -380,11 +384,15 @@ define <3 x i16> @sext_v3i10_v3i16(<3 x i10> %a) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: lsl w8, w0, #6
; CHECK-GI-NEXT: lsl w9, w1, #6
-; CHECK-GI-NEXT: sbfx w8, w8, #6, #10
-; CHECK-GI-NEXT: sbfx w9, w9, #6, #10
+; CHECK-GI-NEXT: mov w10, #6 // =0x6
+; CHECK-GI-NEXT: lsl w11, w2, #6
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: sxth w9, w9
+; CHECK-GI-NEXT: asr w8, w8, w10
+; CHECK-GI-NEXT: asr w9, w9, w10
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: lsl w8, w2, #6
-; CHECK-GI-NEXT: sbfx w8, w8, #6, #10
+; CHECK-GI-NEXT: sxth w8, w11
+; CHECK-GI-NEXT: asr w8, w8, w10
; CHECK-GI-NEXT: mov v0.h[1], w9
; CHECK-GI-NEXT: mov v0.h[2], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
diff --git a/llvm/test/CodeGen/AArch64/signed-truncation-check.ll b/llvm/test/CodeGen/AArch64/signed-truncation-check.ll
index fc01c6b2c5471..7d84d9123bdaa 100644
--- a/llvm/test/CodeGen/AArch64/signed-truncation-check.ll
+++ b/llvm/test/CodeGen/AArch64/signed-truncation-check.ll
@@ -31,7 +31,9 @@ define i1 @shifts_eqcmp_i16_i8(i16 %x) nounwind {
; CHECK-GI-LABEL: shifts_eqcmp_i16_i8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: lsl w8, w0, #8
-; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
+; CHECK-GI-NEXT: mov w9, #8 // =0x8
+; CHECK-GI-NEXT: sxth w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: and w8, w8, #0xffff
; CHECK-GI-NEXT: cmp w8, w0, uxth
; CHECK-GI-NEXT: cset w0, eq
diff --git a/llvm/test/CodeGen/AArch64/smul_fix.ll b/llvm/test/CodeGen/AArch64/smul_fix.ll
index b2f8472234d40..9a96b71a927d7 100644
--- a/llvm/test/CodeGen/AArch64/smul_fix.ll
+++ b/llvm/test/CodeGen/AArch64/smul_fix.ll
@@ -57,7 +57,9 @@ define i4 @func3(i4 %x, i4 %y) {
; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
; CHECK-GI-NEXT: mul w8, w8, w9
-; CHECK-GI-NEXT: sbfx w0, w8, #2, #6
+; CHECK-GI-NEXT: mov w9, #2 // =0x2
+; CHECK-GI-NEXT: sxtb w8, w8
+; CHECK-GI-NEXT: asr w0, w8, w9
; CHECK-GI-NEXT: ret
%tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 2)
ret i4 %tmp
diff --git a/llvm/test/CodeGen/AArch64/smul_fix_sat.ll b/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
index 744d1be126ff1..249aa09192c78 100644
--- a/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
+++ b/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
@@ -98,13 +98,15 @@ define i4 @func3(i4 %x, i4 %y) {
;
; CHECK-GI-LABEL: func3:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
-; CHECK-GI-NEXT: sbfx w10, w1, #0, #4
-; CHECK-GI-NEXT: mov w8, #7 // =0x7
-; CHECK-GI-NEXT: mul w9, w9, w10
-; CHECK-GI-NEXT: sbfx w9, w9, #2, #6
-; CHECK-GI-NEXT: cmp w9, #7
-; CHECK-GI-NEXT: csel w8, w9, w8, lt
+; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
+; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
+; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #2 // =0x2
+; CHECK-GI-NEXT: sxtb w8, w8
+; CHECK-GI-NEXT: asr w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #7 // =0x7
+; CHECK-GI-NEXT: cmp w8, #7
+; CHECK-GI-NEXT: csel w8, w8, w9, lt
; CHECK-GI-NEXT: mov w9, #-8 // =0xfffffff8
; CHECK-GI-NEXT: cmn w8, #8
; CHECK-GI-NEXT: csel w0, w8, w9, gt
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat.ll b/llvm/test/CodeGen/AArch64/ssub_sat.ll
index 4740803fc7622..4e009059371fe 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat.ll
@@ -61,13 +61,14 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
;
; CHECK-GI-LABEL: func16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sxth w8, w0
-; CHECK-GI-NEXT: sub w8, w8, w1, sxth
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sxth w9, w0
+; CHECK-GI-NEXT: mov w8, #15 // =0xf
+; CHECK-GI-NEXT: sub w9, w9, w1, sxth
+; CHECK-GI-NEXT: sxth w10, w9
+; CHECK-GI-NEXT: asr w8, w10, w8
+; CHECK-GI-NEXT: cmp w9, w10
+; CHECK-GI-NEXT: sub w8, w8, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -88,13 +89,14 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
;
; CHECK-GI-LABEL: func8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sxtb w8, w0
-; CHECK-GI-NEXT: sub w8, w8, w1, sxtb
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sxtb w9, w0
+; CHECK-GI-NEXT: mov w8, #7 // =0x7
+; CHECK-GI-NEXT: sub w9, w9, w1, sxtb
+; CHECK-GI-NEXT: sxtb w10, w9
+; CHECK-GI-NEXT: asr w8, w10, w8
+; CHECK-GI-NEXT: cmp w9, w10
+; CHECK-GI-NEXT: sub w8, w8, #128
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -116,14 +118,15 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
;
; CHECK-GI-LABEL: func3:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
-; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
-; CHECK-GI-NEXT: sub w8, w8, w9
-; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
-; CHECK-GI-NEXT: asr w10, w9, #3
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: add w10, w10, #8
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
+; CHECK-GI-NEXT: sbfx w10, w1, #0, #4
+; CHECK-GI-NEXT: mov w8, #3 // =0x3
+; CHECK-GI-NEXT: sub w9, w9, w10
+; CHECK-GI-NEXT: sbfx w10, w9, #0, #4
+; CHECK-GI-NEXT: asr w8, w10, w8
+; CHECK-GI-NEXT: cmp w9, w10
+; CHECK-GI-NEXT: add w8, w8, #8
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll b/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
index f08629c15f26c..32502ee3c352b 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
@@ -74,11 +74,12 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sxth w9, w0
+; CHECK-GI-NEXT: mov w10, #15 // =0xf
; CHECK-GI-NEXT: sub w8, w9, w8, sxth
; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i16 %y, %z
@@ -104,11 +105,12 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sxtb w9, w0
+; CHECK-GI-NEXT: mov w10, #7 // =0x7
; CHECK-GI-NEXT: sub w8, w9, w8, sxtb
; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #128
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i8 %y, %z
@@ -135,10 +137,11 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
+; CHECK-GI-NEXT: mov w10, #3 // =0x3
; CHECK-GI-NEXT: sbfx w8, w8, #0, #4
; CHECK-GI-NEXT: sub w8, w9, w8
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
-; CHECK-GI-NEXT: asr w10, w9, #3
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: add w10, w10, #8
; CHECK-GI-NEXT: csel w0, w10, w8, ne
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index f4359edcc1bbd..47b7562d2d845 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -279,11 +279,12 @@ define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldrsb w8, [x0]
; CHECK-GI-NEXT: ldrsb w9, [x1]
+; CHECK-GI-NEXT: mov w10, #7 // =0x7
; CHECK-GI-NEXT: sub w8, w8, w9
; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #128
; CHECK-GI-NEXT: csel w8, w10, w8, ne
; CHECK-GI-NEXT: strb w8, [x2]
; CHECK-GI-NEXT: ret
@@ -307,11 +308,12 @@ define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldrsh w8, [x0]
; CHECK-GI-NEXT: ldrsh w9, [x1]
+; CHECK-GI-NEXT: mov w10, #15 // =0xf
; CHECK-GI-NEXT: sub w8, w8, w9
; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: asr w10, w9, w10
; CHECK-GI-NEXT: cmp w8, w9
+; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
; CHECK-GI-NEXT: csel w8, w10, w8, ne
; CHECK-GI-NEXT: strh w8, [x2]
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 8a4d6c1d67b4d..5e0286359f528 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -10,7 +10,6 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX6-LABEL: v_ashr_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -18,19 +17,18 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX8-LABEL: v_ashr_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ashr_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ashr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-NEXT: v_ashrrev_i16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -38,7 +36,6 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX11-TRUE16-LABEL: v_ashr_i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -46,7 +43,6 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX11-FAKE16-LABEL: v_ashr_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -101,29 +97,14 @@ define i8 @v_ashr_i8_7(i8 %value) {
}
define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {
-; GFX6-LABEL: s_ashr_i8:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_sext_i32_i8 s0, s0
-; GFX6-NEXT: s_ashr_i32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_ashr_i8:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_sext_i32_i8 s0, s0
-; GFX8-NEXT: s_ashr_i32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_ashr_i8:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_sext_i32_i8 s0, s0
-; GFX9-NEXT: s_ashr_i32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_ashr_i8:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_sext_i32_i8 s0, s0
+; GCN-NEXT: s_ashr_i32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_ashr_i8:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xff
; GFX10PLUS-NEXT: s_sext_i32_i8 s0, s0
; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1
; GFX10PLUS-NEXT: ; return to shader part epilog
@@ -152,7 +133,6 @@ define i24 @v_ashr_i24(i24 %value, i24 %amount) {
; GCN-LABEL: v_ashr_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -160,7 +140,6 @@ define i24 @v_ashr_i24(i24 %value, i24 %amount) {
; GFX10PLUS-LABEL: v_ashr_i24:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 24
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
@@ -617,7 +596,6 @@ define i16 @v_ashr_i16(i16 %value, i16 %amount) {
; GFX6-LABEL: v_ashr_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -731,7 +709,6 @@ define amdgpu_ps i16 @s_ashr_i16_15(i16 inreg %value) {
define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: ashr_i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -768,7 +745,6 @@ define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: ashr_i16_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -809,7 +785,6 @@ define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_bfe_i32 v3, v0, 0, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v2, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v1, v3
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -939,7 +914,6 @@ define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount)
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: s_sext_i32_i16 s1, s0
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100010
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_ashr_i32_e32 v1, s0, v1
; GFX6-NEXT: v_ashr_i32_e32 v0, s1, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -977,7 +951,6 @@ define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount)
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, s1, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1024,25 +997,23 @@ define <2 x float> @v_ashr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
; GFX6-LABEL: v_ashr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v2
-; GFX6-NEXT: v_bfe_i32 v5, v0, 0, 16
-; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX6-NEXT: v_bfe_i32 v6, v0, 0, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v4, v4, v5
-; GFX6-NEXT: v_ashrrev_i32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX6-NEXT: v_bfe_i32 v5, v1, 0, 16
-; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0
+; GFX6-NEXT: v_bfe_i32 v4, v1, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v1, v3, v1
-; GFX6-NEXT: v_ashrrev_i32_e32 v2, v2, v5
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, v2, v6
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, v5, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v4
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, v3, v4
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -1078,23 +1049,23 @@ define <2 x float> @v_ashr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
define amdgpu_ps <2 x i32> @s_ashr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {
; GFX6-LABEL: s_ashr_v4i16:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_sext_i32_i16 s4, s0
-; GFX6-NEXT: s_ashr_i32 s4, s4, s2
-; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100010
+; GFX6-NEXT: s_lshr_b32 s4, s2, 16
+; GFX6-NEXT: s_sext_i32_i16 s6, s0
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100010
-; GFX6-NEXT: s_ashr_i32 s0, s0, s2
-; GFX6-NEXT: s_sext_i32_i16 s2, s1
-; GFX6-NEXT: s_ashr_i32 s2, s2, s3
-; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100010
+; GFX6-NEXT: s_lshr_b32 s5, s3, 16
+; GFX6-NEXT: s_ashr_i32 s0, s0, s4
+; GFX6-NEXT: s_sext_i32_i16 s4, s1
; GFX6-NEXT: s_bfe_i32 s1, s1, 0x100010
-; GFX6-NEXT: s_ashr_i32 s1, s1, s3
+; GFX6-NEXT: s_ashr_i32 s2, s6, s2
+; GFX6-NEXT: s_ashr_i32 s1, s1, s5
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX6-NEXT: s_and_b32 s3, s4, 0xffff
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: s_ashr_i32 s3, s4, s3
; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX6-NEXT: s_or_b32 s0, s2, s0
+; GFX6-NEXT: s_and_b32 s2, s3, 0xffff
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_or_b32 s0, s3, s0
; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: ; return to shader part epilog
;
@@ -1189,45 +1160,41 @@ define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6-LABEL: v_ashr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v4
-; GFX6-NEXT: v_bfe_i32 v9, v0, 0, 16
-; GFX6-NEXT: v_bfe_u32 v4, v4, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX6-NEXT: v_bfe_i32 v12, v0, 0, 16
; GFX6-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v8, v8, v9
-; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX6-NEXT: v_bfe_i32 v9, v1, 0, 16
-; GFX6-NEXT: v_bfe_u32 v5, v5, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v9, 16, v5
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, v8, v0
+; GFX6-NEXT: v_bfe_i32 v8, v1, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v4, v4, v9
-; GFX6-NEXT: v_ashrrev_i32_e32 v1, v5, v1
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v6
-; GFX6-NEXT: v_bfe_i32 v9, v2, 0, 16
-; GFX6-NEXT: v_bfe_u32 v6, v6, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX6-NEXT: v_ashrrev_i32_e32 v4, v4, v12
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, v5, v8
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, v9, v1
+; GFX6-NEXT: v_bfe_i32 v8, v2, 0, 16
; GFX6-NEXT: v_bfe_i32 v2, v2, 16, 16
-; GFX6-NEXT: v_ashrrev_i32_e32 v5, v5, v9
-; GFX6-NEXT: v_ashrrev_i32_e32 v2, v6, v2
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v7
-; GFX6-NEXT: v_bfe_i32 v9, v3, 0, 16
-; GFX6-NEXT: v_bfe_u32 v7, v7, 16, 16
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v11, 16, v7
+; GFX6-NEXT: v_ashrrev_i32_e32 v6, v6, v8
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, v10, v2
+; GFX6-NEXT: v_bfe_i32 v8, v3, 0, 16
; GFX6-NEXT: v_bfe_i32 v3, v3, 16, 16
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, v7, v3
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, v11, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX6-NEXT: v_ashrrev_i32_e32 v6, v6, v9
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v7, v7, v8
; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff, v8
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_or_b32_e32 v0, v7, v0
; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -1273,41 +1240,41 @@ define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
define amdgpu_ps <4 x i32> @s_ashr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {
; GFX6-LABEL: s_ashr_v8i16:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_sext_i32_i16 s8, s0
-; GFX6-NEXT: s_ashr_i32 s8, s8, s4
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100010
+; GFX6-NEXT: s_lshr_b32 s8, s4, 16
+; GFX6-NEXT: s_sext_i32_i16 s12, s0
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100010
-; GFX6-NEXT: s_ashr_i32 s0, s0, s4
-; GFX6-NEXT: s_sext_i32_i16 s4, s1
-; GFX6-NEXT: s_ashr_i32 s4, s4, s5
-; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100010
+; GFX6-NEXT: s_lshr_b32 s9, s5, 16
+; GFX6-NEXT: s_ashr_i32 s0, s0, s8
+; GFX6-NEXT: s_sext_i32_i16 s8, s1
; GFX6-NEXT: s_bfe_i32 s1, s1, 0x100010
-; GFX6-NEXT: s_ashr_i32 s1, s1, s5
-; GFX6-NEXT: s_sext_i32_i16 s5, s2
-; GFX6-NEXT: s_ashr_i32 s5, s5, s6
-; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100010
+; GFX6-NEXT: s_lshr_b32 s10, s6, 16
+; GFX6-NEXT: s_ashr_i32 s4, s12, s4
+; GFX6-NEXT: s_ashr_i32 s5, s8, s5
+; GFX6-NEXT: s_ashr_i32 s1, s1, s9
+; GFX6-NEXT: s_sext_i32_i16 s8, s2
; GFX6-NEXT: s_bfe_i32 s2, s2, 0x100010
-; GFX6-NEXT: s_ashr_i32 s2, s2, s6
-; GFX6-NEXT: s_sext_i32_i16 s6, s3
-; GFX6-NEXT: s_ashr_i32 s6, s6, s7
-; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100010
+; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
+; GFX6-NEXT: s_lshr_b32 s11, s7, 16
+; GFX6-NEXT: s_ashr_i32 s6, s8, s6
+; GFX6-NEXT: s_ashr_i32 s2, s2, s10
+; GFX6-NEXT: s_sext_i32_i16 s8, s3
; GFX6-NEXT: s_bfe_i32 s3, s3, 0x100010
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX6-NEXT: s_ashr_i32 s3, s3, s7
; GFX6-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX6-NEXT: s_lshl_b32 s0, s0, 16
+; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX6-NEXT: s_ashr_i32 s3, s3, s11
+; GFX6-NEXT: s_or_b32 s0, s4, s0
+; GFX6-NEXT: s_and_b32 s4, s5, 0xffff
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
+; GFX6-NEXT: s_ashr_i32 s7, s8, s7
; GFX6-NEXT: s_or_b32 s1, s4, s1
-; GFX6-NEXT: s_and_b32 s4, s5, 0xffff
+; GFX6-NEXT: s_and_b32 s4, s6, 0xffff
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX6-NEXT: s_and_b32 s7, s8, 0xffff
-; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_or_b32 s2, s4, s2
-; GFX6-NEXT: s_and_b32 s4, s6, 0xffff
+; GFX6-NEXT: s_and_b32 s4, s7, 0xffff
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s0, s7, s0
; GFX6-NEXT: s_or_b32 s3, s4, s3
; GFX6-NEXT: ; return to shader part epilog
;
@@ -1987,64 +1954,48 @@ define <4 x i2> @v_ashr_v4i2(<4 x i2> %value, <4 x i2> %amount) {
; GFX6-LABEL: v_ashr_v4i2:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v4, 3, v4
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 2
-; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 3, v5
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 2
-; GFX6-NEXT: v_ashrrev_i32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, 3, v6
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 2
-; GFX6-NEXT: v_ashrrev_i32_e32 v2, v4, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 3, v7
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 2
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, v4, v3
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, v5, v1
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, v6, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, v7, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ashr_v4i2:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v4, 3, v4
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 2
-; GFX8-NEXT: v_ashrrev_i16_e32 v0, v4, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 3, v5
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 2
-; GFX8-NEXT: v_ashrrev_i16_e32 v1, v4, v1
-; GFX8-NEXT: v_and_b32_e32 v4, 3, v6
; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 2
-; GFX8-NEXT: v_ashrrev_i16_e32 v2, v4, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 3, v7
; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 2
-; GFX8-NEXT: v_ashrrev_i16_e32 v3, v4, v3
+; GFX8-NEXT: v_ashrrev_i16_e32 v0, v4, v0
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, v5, v1
+; GFX8-NEXT: v_ashrrev_i16_e32 v2, v6, v2
+; GFX8-NEXT: v_ashrrev_i16_e32 v3, v7, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ashr_v4i2:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v4, 3, v4
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 2
-; GFX9-NEXT: v_ashrrev_i16_e32 v0, v4, v0
-; GFX9-NEXT: v_and_b32_e32 v4, 3, v5
; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 2
-; GFX9-NEXT: v_ashrrev_i16_e32 v1, v4, v1
-; GFX9-NEXT: v_and_b32_e32 v4, 3, v6
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 2
-; GFX9-NEXT: v_ashrrev_i16_e32 v2, v4, v2
-; GFX9-NEXT: v_and_b32_e32 v4, 3, v7
; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 2
-; GFX9-NEXT: v_ashrrev_i16_e32 v3, v4, v3
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, v4, v0
+; GFX9-NEXT: v_ashrrev_i16_e32 v1, v5, v1
+; GFX9-NEXT: v_ashrrev_i16_e32 v2, v6, v2
+; GFX9-NEXT: v_ashrrev_i16_e32 v3, v7, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ashr_v4i2:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v4, 3, v4
; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 2
-; GFX10-NEXT: v_and_b32_e32 v5, 3, v5
; GFX10-NEXT: v_bfe_i32 v1, v1, 0, 2
-; GFX10-NEXT: v_and_b32_e32 v6, 3, v6
; GFX10-NEXT: v_bfe_i32 v2, v2, 0, 2
-; GFX10-NEXT: v_and_b32_e32 v7, 3, v7
; GFX10-NEXT: v_bfe_i32 v3, v3, 0, 2
; GFX10-NEXT: v_ashrrev_i16 v0, v4, v0
; GFX10-NEXT: v_ashrrev_i16 v1, v5, v1
@@ -2058,27 +2009,19 @@ define <4 x i2> @v_ashr_v4i2(<4 x i2> %value, <4 x i2> %amount) {
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 2
; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 2
; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 2
-; GFX11-TRUE16-NEXT: v_and_b16 v4.l, v4.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v5.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v6.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v2.h, v7.l, 3
; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 2
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v4.l, v0.l
-; GFX11-TRUE16-NEXT: v_ashrrev_i16 v1.l, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_ashrrev_i16 v2.l, v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_ashrrev_i16 v3.l, v2.h, v3.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v2.l, v6.l, v2.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v3.l, v7.l, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ashr_v4i2:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 3, v5
; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v6
; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 3, v7
; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 2
; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, v4, v0
; GFX11-FAKE16-NEXT: v_ashrrev_i16 v1, v5, v1
@@ -2119,34 +2062,26 @@ define <4 x i1> @v_ashr_v4i1(<4 x i1> %value, <4 x i1> %amount) {
define amdgpu_ps <4 x i2> @s_ashr_v4i2(<4 x i2> inreg %value, <4 x i2> inreg %amount) {
; GCN-LABEL: s_ashr_v4i2:
; GCN: ; %bb.0:
-; GCN-NEXT: s_and_b32 s4, s4, 3
; GCN-NEXT: s_bfe_i32 s0, s0, 0x20000
-; GCN-NEXT: s_ashr_i32 s0, s0, s4
-; GCN-NEXT: s_and_b32 s4, s5, 3
; GCN-NEXT: s_bfe_i32 s1, s1, 0x20000
-; GCN-NEXT: s_ashr_i32 s1, s1, s4
-; GCN-NEXT: s_and_b32 s4, s6, 3
; GCN-NEXT: s_bfe_i32 s2, s2, 0x20000
-; GCN-NEXT: s_ashr_i32 s2, s2, s4
-; GCN-NEXT: s_and_b32 s4, s7, 3
; GCN-NEXT: s_bfe_i32 s3, s3, 0x20000
-; GCN-NEXT: s_ashr_i32 s3, s3, s4
+; GCN-NEXT: s_ashr_i32 s0, s0, s4
+; GCN-NEXT: s_ashr_i32 s1, s1, s5
+; GCN-NEXT: s_ashr_i32 s2, s2, s6
+; GCN-NEXT: s_ashr_i32 s3, s3, s7
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_ashr_v4i2:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_and_b32 s4, s4, 3
; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x20000
-; GFX10PLUS-NEXT: s_and_b32 s5, s5, 3
; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0x20000
-; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s4
-; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s5
-; GFX10PLUS-NEXT: s_and_b32 s4, s6, 3
; GFX10PLUS-NEXT: s_bfe_i32 s2, s2, 0x20000
-; GFX10PLUS-NEXT: s_and_b32 s5, s7, 3
; GFX10PLUS-NEXT: s_bfe_i32 s3, s3, 0x20000
-; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s4
-; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s5
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s4
+; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s5
+; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s6
+; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s7
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = ashr <4 x i2> %value, %amount
ret <4 x i2> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index bf5d5cb5462fe..14f6ce042ad11 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -70,11 +70,9 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8-NEXT: s_cselect_b32 s2, s4, s2
; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
; GFX8-NEXT: s_sub_i32 s3, 6, s2
-; GFX8-NEXT: s_and_b32 s2, s2, 0x7f
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
; GFX8-NEXT: s_lshl_b32 s0, s0, s2
-; GFX8-NEXT: s_and_b32 s2, s3, 0x7f
-; GFX8-NEXT: s_lshr_b32 s1, s1, s2
+; GFX8-NEXT: s_lshr_b32 s1, s1, s3
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
@@ -102,13 +100,11 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9-NEXT: s_add_i32 s4, s2, -7
; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: s_sub_i32 s3, 6, s2
-; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: s_sub_i32 s3, 6, s2
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
-; GFX9-NEXT: s_and_b32 s2, s3, 0x7f
-; GFX9-NEXT: s_lshr_b32 s1, s1, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: s_lshr_b32 s1, s1, s3
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
;
@@ -138,9 +134,7 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-NEXT: s_cselect_b32 s2, s4, s2
; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
; GFX10-NEXT: s_sub_i32 s3, 6, s2
-; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
; GFX10-NEXT: s_lshr_b32 s1, s1, 1
-; GFX10-NEXT: s_and_b32 s3, s3, 0x7f
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshr_b32 s1, s1, s3
; GFX10-NEXT: s_or_b32 s0, s0, s1
@@ -178,9 +172,7 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX11-NEXT: s_cselect_b32 s2, s4, s2
; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
; GFX11-NEXT: s_sub_i32 s3, 6, s2
-; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
; GFX11-NEXT: s_lshl_b32 s0, s0, s2
; GFX11-NEXT: s_lshr_b32 s1, s1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -215,10 +207,8 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 6, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -247,10 +237,8 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v3
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v3, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -277,10 +265,8 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v0, v2, v0
-; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v3
-; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX9-NEXT: v_lshrrev_b16_e32 v1, v3, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -307,8 +293,6 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: v_sub_nc_u16 v3, 6, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX10-NEXT: v_lshlrev_b16 v0, v2, v0
; GFX10-NEXT: v_lshrrev_b16 v1, v3, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
@@ -345,10 +329,7 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v1.l, 6, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0x7f, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7f, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
@@ -385,9 +366,6 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_sub_nc_u16 v3, 6, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7f, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v2, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b16 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1862,17 +1840,15 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX6-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX6-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -1894,17 +1870,15 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX8-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v4
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v2, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -1931,8 +1905,6 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v2, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1959,8 +1931,6 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -1994,11 +1964,8 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v2, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.fshl.i24(i24 %lhs, i24 %rhs, i24 %amt)
@@ -2752,13 +2719,11 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v6
-; GFX6-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX6-NEXT: v_mul_lo_u32 v4, v8, v7
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v6
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v4
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v2, v7
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2766,11 +2731,9 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 23
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -2801,13 +2764,11 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v6
-; GFX8-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_mul_lo_u32 v4, v8, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v6
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v2, v7
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2815,11 +2776,9 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v2, v1
; GFX8-NEXT: v_bfe_u32 v2, v3, 1, 23
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, v3, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -2847,12 +2806,10 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v8, v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_sub_u32_e32 v7, 23, v6
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v7
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, v7, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
@@ -2861,8 +2818,6 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v2, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2899,12 +2854,8 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v5
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v4
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffffff, v7
+; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v4
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v5, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v4, v3
@@ -2949,14 +2900,10 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v4, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v3, v7, v3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 42c153ff5023a..092b4c61df972 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -69,11 +69,9 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8-NEXT: s_add_i32 s4, s2, -7
; GFX8-NEXT: s_cmp_lg_u32 s3, 0
; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_sub_i32 s3, 6, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX8-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX8-NEXT: s_and_b32 s3, s3, 0x7f
+; GFX8-NEXT: s_sub_i32 s3, 6, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s3
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -105,8 +103,6 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9-NEXT: s_cselect_b32 s2, s4, s2
; GFX9-NEXT: s_sub_i32 s3, 6, s2
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: s_and_b32 s3, s3, 0x7f
-; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
; GFX9-NEXT: s_lshl_b32 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
@@ -140,8 +136,6 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_sub_i32 s3, 6, s2
; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX10-NEXT: s_and_b32 s3, s3, 0x7f
-; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
@@ -180,8 +174,6 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-NEXT: s_sub_i32 s3, 6, s2
; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX11-NEXT: s_and_b32 s3, s3, 0x7f
-; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
; GFX11-NEXT: s_lshl_b32 s0, s0, s3
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -217,8 +209,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 6, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX6-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
@@ -249,8 +239,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
@@ -279,8 +267,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u16_e32 v3, 6, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX9-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
@@ -309,8 +295,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: v_sub_nc_u16 v3, 6, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX10-NEXT: v_lshrrev_b16 v1, v2, v1
; GFX10-NEXT: v_lshlrev_b16 v0, v3, v0
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
@@ -346,12 +330,9 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.h, 6, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0x7f, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x7f, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -385,9 +366,6 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_sub_nc_u16 v3, 6, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x7f, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b16 v1, v2, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v3, v0
@@ -1879,15 +1857,13 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX6-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX6-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe8, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
@@ -1912,15 +1888,13 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4
; GFX8-NEXT: v_mul_lo_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v4
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffffffe8, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
@@ -1950,8 +1924,6 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v3, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1979,8 +1951,6 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v3, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -2015,9 +1985,6 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v3, v1
@@ -2776,10 +2743,8 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0
; GFX6-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v6
@@ -2790,8 +2755,6 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
@@ -2827,10 +2790,8 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v6, v0
; GFX8-NEXT: v_mul_lo_u32 v6, v8, v7
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v6
@@ -2841,8 +2802,6 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
@@ -2872,13 +2831,11 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v8, v[4:5]
; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v8, v[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_sub_u32_e32 v7, 23, v6
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v4
@@ -2888,8 +2845,6 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX9-NEXT: v_lshl_or_b32 v1, v1, v4, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2928,12 +2883,8 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v5
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v4
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v5, v2
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v7
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, 23, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v6, v2
; GFX10-NEXT: v_lshl_or_b32 v1, v1, v5, v3
@@ -2978,15 +2929,10 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-NEXT: v_lshrrev_b32_e32 v2, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v7
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 23, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v3, v5, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v6, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
index 1a7af6f5fd067..af0af87d3e861 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
@@ -121,9 +121,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
;
; VI-LABEL: name: test_ashr_s64_s16
@@ -131,9 +129,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
+ ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
;
; GFX9PLUS-LABEL: name: test_ashr_s64_s16
@@ -141,9 +137,7 @@ body: |
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
+ ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; GFX9PLUS-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -207,10 +201,8 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; VI-LABEL: name: test_ashr_s16_s16
@@ -254,10 +246,8 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; VI-LABEL: name: test_ashr_s16_i8
@@ -267,9 +257,7 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
+ ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -280,9 +268,7 @@ body: |
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
+ ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
; GFX9PLUS-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9PLUS-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -305,10 +291,8 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; VI-LABEL: name: test_ashr_i8_i8
@@ -317,11 +301,9 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
+ ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[TRUNC]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -331,11 +313,9 @@ body: |
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9PLUS-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
+ ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[TRUNC]](s16)
; GFX9PLUS-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9PLUS-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -358,10 +338,8 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; VI-LABEL: name: test_ashr_s7_s7
@@ -370,11 +348,9 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
+ ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[TRUNC]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -384,11 +360,9 @@ body: |
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
- ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9PLUS-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
+ ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[TRUNC]](s16)
; GFX9PLUS-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9PLUS-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -411,10 +385,8 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; VI-LABEL: name: test_ashr_s24_s24
@@ -422,10 +394,8 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
- ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; VI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; GFX9PLUS-LABEL: name: test_ashr_s24_s24
@@ -433,10 +403,8 @@ body: |
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9PLUS-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
- ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; GFX9PLUS-NEXT: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -458,9 +426,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; VI-LABEL: name: test_ashr_s32_s24
@@ -468,9 +434,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
+ ; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
;
; GFX9PLUS-LABEL: name: test_ashr_s32_s24
@@ -478,9 +442,7 @@ body: |
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
+ ; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; GFX9PLUS-NEXT: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -705,17 +667,15 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[BITCAST1]](i32)
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[LSHR1]](i32)
- ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ASHR]], [[C2]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ASHR1]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[SHL]]
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ASHR]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ASHR1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
;
@@ -846,28 +806,25 @@ body: |
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[BITCAST2]](i32)
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[LSHR1]](i32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
- ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND1]](s32)
- ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ASHR]], [[C2]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ASHR1]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL]]
+ ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[BITCAST3]](i32)
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ASHR]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ASHR1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ASHR2]], [[C2]]
- ; SI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[C]](i32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ASHR2]], [[C1]]
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C2]], [[C]](i32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[C]](i32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C3]], [[SHL2]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[C2]], [[C]](i32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL2]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
@@ -970,27 +927,24 @@ body: |
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
- ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[BITCAST2]](i32)
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[LSHR2]](i32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
- ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND1]](s32)
+ ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[BITCAST3]](i32)
; SI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; SI-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[LSHR3]](i32)
- ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ASHR]], [[C2]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ASHR1]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL]]
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ASHR]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ASHR1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ASHR2]], [[C2]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ASHR3]], [[C2]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C]](i32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ASHR2]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ASHR3]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
index 1a0a95e8e76a5..05ed7a3552b62 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
@@ -153,20 +153,20 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
; SI-NEXT: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
- ; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC1]], [[TRUNC2]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT2]](s32)
;
; VI-LABEL: name: test_fshl_s16_s16
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
@@ -248,33 +248,33 @@ body: |
; SI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
; SI-NEXT: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C4]]
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC2]], [[TRUNC3]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ANYEXT2]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR5]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR5]], [[ANYEXT3]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC4]], [[TRUNC5]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[ZEXT5]], [[C]](i32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT4]], [[SHL2]]
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL2]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
;
@@ -459,18 +459,16 @@ body: |
; VI-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND2]](s16)
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[C3]](s16)
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND2]], [[C2]](s16)
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
- ; VI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C2]]
- ; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[AND4]](s16)
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[TRUNC3]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -488,18 +486,16 @@ body: |
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND2]](s16)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[C3]](s16)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND2]], [[C2]](s16)
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
- ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C2]]
- ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[AND4]](s16)
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C3]]
+ ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[TRUNC3]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -552,13 +548,11 @@ body: |
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; SI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SELECT1]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[SUB4]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
@@ -593,13 +587,11 @@ body: |
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; VI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SELECT1]](s32)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C5]](s32)
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[SUB4]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
@@ -634,13 +626,11 @@ body: |
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SELECT1]](s32)
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C5]](s32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[SUB4]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
@@ -687,51 +677,51 @@ body: |
; SI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
; SI-NEXT: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC3]], [[TRUNC4]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ANYEXT2]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY6]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR5]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR5]], [[ANYEXT3]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC5]], [[TRUNC6]]
; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
; SI-NEXT: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
+ ; SI-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[AND5]](s16)
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ANYEXT4]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY7]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR7]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[AND6]](s16)
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR7]], [[ANYEXT5]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR8]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC7]], [[TRUNC8]]
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[ZEXT7]], [[C]](i32)
- ; SI-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[ZEXT6]], [[SHL3]]
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
+ ; SI-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL3]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](i32)
- ; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(i32) = G_ZEXT [[OR2]](s16)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[OR2]](s16)
; SI-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[C5]], [[C]](i32)
- ; SI-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT8]], [[SHL4]]
+ ; SI-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL4]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](i32)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[C5]], [[C]](i32)
; SI-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[C5]], [[SHL5]]
@@ -908,63 +898,63 @@ body: |
; SI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
; SI-NEXT: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC4]], [[TRUNC5]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ANYEXT2]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR2]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[LSHR8]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
+ ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[LSHR8]], [[ANYEXT3]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC6]], [[TRUNC7]]
; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
; SI-NEXT: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
+ ; SI-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[AND5]](s16)
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ANYEXT4]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY4]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR10]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[AND6]](s16)
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR10]], [[ANYEXT5]](s32)
; SI-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC8]], [[TRUNC9]]
; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C1]]
; SI-NEXT: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC3]], [[C2]]
; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C1]]
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[ZEXT6]](s32)
+ ; SI-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[AND8]](s16)
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[ANYEXT6]](s32)
; SI-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY5]](s32)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[ZEXT7]](s32)
+ ; SI-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[AND9]](s16)
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[ANYEXT7]](s32)
; SI-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR13]](s32)
; SI-NEXT: [[OR3:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC10]], [[TRUNC11]]
- ; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
- ; SI-NEXT: [[ZEXT9:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[ZEXT9]], [[C]](i32)
- ; SI-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT8]], [[SHL4]]
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
+ ; SI-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL4]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](i32)
- ; SI-NEXT: [[ZEXT10:%[0-9]+]]:_(i32) = G_ZEXT [[OR2]](s16)
- ; SI-NEXT: [[ZEXT11:%[0-9]+]]:_(i32) = G_ZEXT [[OR3]](s16)
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[ZEXT11]], [[C]](i32)
- ; SI-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[ZEXT10]], [[SHL5]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[OR2]](s16)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[OR3]](s16)
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
+ ; SI-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL5]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
index 60eb28a2f58ea..c72fc69a21285 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
@@ -118,17 +118,17 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC1]], [[TRUNC2]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT2]](s32)
;
; VI-LABEL: name: test_fshr_s16_s16
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
@@ -212,13 +212,13 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C3]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C4]]
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC2]], [[TRUNC3]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
@@ -226,17 +226,17 @@ body: |
; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[ZEXT2]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[ANYEXT2]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[ANYEXT3]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC4]], [[TRUNC5]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[ZEXT5]], [[C]](i32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT4]], [[SHL4]]
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL4]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
;
@@ -423,14 +423,12 @@ body: |
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND2]](s16)
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[TRUNC1]](s16)
; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[AND3]](s16)
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND2]], [[TRUNC2]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL1]](s16)
; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -451,14 +449,12 @@ body: |
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
- ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND2]](s16)
+ ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[TRUNC1]](s16)
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[AND3]](s16)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND2]], [[TRUNC2]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL1]](s16)
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -512,11 +508,9 @@ body: |
; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; SI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C5]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[SUB4]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[SELECT1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
@@ -552,11 +546,9 @@ body: |
; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; VI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C5]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[SUB4]](s32)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[SELECT1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
@@ -592,11 +584,9 @@ body: |
; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C5]](s32)
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[SUB4]](s32)
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[SELECT1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
@@ -645,13 +635,13 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C3]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC3]], [[TRUNC4]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
@@ -659,11 +649,11 @@ body: |
; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY6]](s32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[ZEXT2]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[ANYEXT2]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[ANYEXT3]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC5]], [[TRUNC6]]
; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
@@ -671,23 +661,23 @@ body: |
; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[COPY7]](s32)
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[ZEXT4]](s32)
+ ; SI-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[AND6]](s16)
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[ANYEXT4]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[AND5]](s16)
; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ANYEXT5]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC7]], [[TRUNC8]]
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
- ; SI-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[ZEXT7]], [[C]](i32)
- ; SI-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[ZEXT6]], [[SHL6]]
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
+ ; SI-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
+ ; SI-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL6]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](i32)
- ; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(i32) = G_ZEXT [[OR2]](s16)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[OR2]](s16)
; SI-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; SI-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[C5]], [[C]](i32)
- ; SI-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT8]], [[SHL7]]
+ ; SI-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL7]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](i32)
; SI-NEXT: [[SHL8:%[0-9]+]]:_(i32) = G_SHL [[C5]], [[C]](i32)
; SI-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[C5]], [[SHL8]]
@@ -858,13 +848,13 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C3]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ZEXT]](s32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ANYEXT]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C4]]
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ANYEXT1]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC2]], [[TRUNC3]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
@@ -872,17 +862,17 @@ body: |
; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[ZEXT2]](s32)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[ANYEXT2]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[ANYEXT3]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC4]], [[TRUNC5]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[ZEXT5]], [[C]](i32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT4]], [[SHL4]]
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[OR]](s16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[OR1]](s16)
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL4]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
@@ -897,12 +887,12 @@ body: |
; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[BITCAST4]], [[COPY4]](s32)
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[SHL5]], [[ZEXT6]](s32)
+ ; SI-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[AND6]](s16)
+ ; SI-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[SHL5]], [[ANYEXT4]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[AND5]](s16)
; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C4]]
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT7]](s32)
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ANYEXT5]](s32)
; SI-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR8]](s32)
; SI-NEXT: [[OR3:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC8]], [[TRUNC9]]
; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[C1]]
@@ -910,17 +900,17 @@ body: |
; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C1]]
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[COPY5]](s32)
- ; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[SHL7]], [[ZEXT8]](s32)
+ ; SI-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[AND9]](s16)
+ ; SI-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[SHL7]], [[ANYEXT6]](s32)
; SI-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
- ; SI-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
- ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[ZEXT9]](s32)
+ ; SI-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[AND8]](s16)
+ ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[ANYEXT7]](s32)
; SI-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC10]], [[TRUNC11]]
- ; SI-NEXT: [[ZEXT10:%[0-9]+]]:_(i32) = G_ZEXT [[OR3]](s16)
- ; SI-NEXT: [[ZEXT11:%[0-9]+]]:_(i32) = G_ZEXT [[OR4]](s16)
- ; SI-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[ZEXT11]], [[C]](i32)
- ; SI-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[ZEXT10]], [[SHL9]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[OR3]](s16)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[OR4]](s16)
+ ; SI-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
+ ; SI-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL9]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
index 904a595596e01..b68b90dde4203 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
@@ -121,9 +121,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
;
; VI-LABEL: name: test_lshr_s64_s16
@@ -131,9 +129,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
;
; GFX9-LABEL: name: test_lshr_s64_s16
@@ -141,9 +137,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -209,9 +203,8 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
;
; VI-LABEL: name: test_lshr_s16_s16
@@ -255,11 +248,9 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
;
; VI-LABEL: name: test_lshr_s16_i8
@@ -269,9 +260,7 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -282,9 +271,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -308,9 +295,8 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
;
; VI-LABEL: name: test_lshr_i8_i8
@@ -319,11 +305,10 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND]], [[TRUNC]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -333,11 +318,10 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND]], [[TRUNC]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -566,15 +550,14 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[BITCAST1]](i32)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR1]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[LSHR2]], [[C2]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR3]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR2]], [[C2]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[LSHR3]], [[C2]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
;
@@ -707,23 +690,21 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[BITCAST2]](i32)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR1]](i32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[BITCAST3]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR2]], [[C2]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[LSHR3]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[LSHR2]], [[C2]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR3]], [[C2]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C2]]
; SI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[C]](i32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND6]], [[SHL1]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -819,23 +800,21 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[BITCAST2]](i32)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR1]](i32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[BITCAST3]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR2]], [[C2]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[LSHR3]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[LSHR2]], [[C2]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR3]], [[C2]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C2]]
; SI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[C]](i32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND6]], [[SHL1]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
; SI-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[C]](i32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C3]], [[SHL2]]
@@ -941,24 +920,22 @@ body: |
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[BITCAST2]](i32)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR2]](i32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[BITCAST3]](i32)
; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[LSHR3]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C2]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[LSHR5]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C2]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR5]], [[C2]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[LSHR6]], [[C2]]
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[LSHR7]], [[C2]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C]](i32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND6]], [[SHL1]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR6]], [[C2]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[LSHR7]], [[C2]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C]](i32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
index 4ba14644b12fe..96e9c58974c13 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
@@ -40,14 +40,12 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](i32), [[C1]]
; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(i32) = G_SUB [[SELECT]], [[C1]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SELECT1]](s32)
; GFX6-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND3]](s32)
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
+ ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C5]](s32)
+ ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[SUB4]](s32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; GFX6-NEXT: $sgpr0 = COPY [[OR]](s32)
;
@@ -79,18 +77,15 @@ body: |
; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(i32) = G_SUB [[SELECT]], [[C]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT1]](s32)
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND1]](s16)
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
- ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[C5]], [[COPY2]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND2]], [[C6]](s16)
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[SUB4]], [[C4]]
- ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[LSHR]], [[AND3]](s16)
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
+ ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[C4]], [[TRUNC]]
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C6]]
+ ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[C5]](s16)
+ ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[LSHR]], [[SUB4]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -125,18 +120,18 @@ body: |
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[COPY1]]
; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SUB]](s32)
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ZEXT]](s32)
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ANYEXT]](s32)
; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
+ ; GFX6-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
+ ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ANYEXT1]](s32)
; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC2]], [[TRUNC3]]
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; GFX6-NEXT: $sgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX6-NEXT: $sgpr0 = COPY [[ANYEXT2]](s32)
;
; GFX8-LABEL: name: rotl_i16
; GFX8: liveins: $sgpr0, $sgpr1
@@ -227,14 +222,12 @@ body: |
; GFX-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](i32), [[C1]]
; GFX-NEXT: [[SUB3:%[0-9]+]]:_(i32) = G_SUB [[SELECT]], [[C1]]
; GFX-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
- ; GFX-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; GFX-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SELECT1]](s32)
; GFX-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; GFX-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; GFX-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
- ; GFX-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; GFX-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND3]](s32)
+ ; GFX-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
+ ; GFX-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C5]](s32)
+ ; GFX-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[SUB4]](s32)
; GFX-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; GFX-NEXT: $sgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $sgpr0
@@ -337,18 +330,18 @@ body: |
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[COPY1]]
; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SUB]](s32)
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[ZEXT]](s32)
+ ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[ANYEXT]](s32)
; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND2]](s16)
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ZEXT1]](s32)
+ ; GFX6-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND2]](s16)
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ANYEXT1]](s32)
; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[TRUNC2]], [[TRUNC3]]
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; GFX6-NEXT: $sgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX6-NEXT: $sgpr0 = COPY [[ANYEXT2]](s32)
;
; GFX8-LABEL: name: rotr_i16
; GFX8: liveins: $sgpr0, $sgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
index f01791b61d935..81fea4c99ab03 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
@@ -121,9 +121,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
;
; VI-LABEL: name: test_shl_s64_s16
@@ -131,9 +129,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
;
; GFX9-LABEL: name: test_shl_s64_s16
@@ -141,9 +137,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -206,9 +200,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
;
; VI-LABEL: name: test_shl_s16_s16
@@ -252,9 +244,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
;
; VI-LABEL: name: test_shl_s16_i8
@@ -264,9 +254,7 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -277,9 +265,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -302,9 +288,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
;
; VI-LABEL: name: test_shl_i8_i8
@@ -313,10 +297,8 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -326,10 +308,8 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -558,15 +538,13 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[BITCAST1]](i32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[LSHR1]](i32)
- ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C2]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL1]], [[C2]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[SHL2]]
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[SHL1]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL2]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
;
@@ -695,25 +673,22 @@ body: |
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[BITCAST2]](i32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[LSHR1]](i32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND1]](s32)
- ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C2]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[SHL1]], [[C2]]
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL3]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[BITCAST3]](i32)
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[SHL1]], [[C1]]
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL3]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[SHL2]], [[C2]]
- ; SI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[C]](i32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL4]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL2]], [[C1]]
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[C2]], [[C]](i32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL4]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[C]](i32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C3]], [[SHL5]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[C2]], [[C]](i32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL5]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
@@ -816,23 +791,20 @@ body: |
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[BITCAST2]](i32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[LSHR2]](i32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND1]](s32)
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[BITCAST3]](i32)
; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[LSHR3]](i32)
- ; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C2]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[SHL1]], [[C2]]
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL4]]
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[SHL1]], [[C1]]
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL4]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[SHL2]], [[C2]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[SHL3]], [[C2]]
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C]](i32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SHL5]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL2]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[SHL3]], [[C1]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C]](i32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL5]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -906,9 +878,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
;
; VI-LABEL: name: test_shl_s7_s7
@@ -917,10 +887,8 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
- ; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
@@ -930,10 +898,8 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
index 0adda870b0819..744b5ab8cce96 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
@@ -133,13 +133,9 @@ body: |
; GFX7-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
; GFX7-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
; GFX7-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
- ; GFX7-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
- ; GFX7-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY3]], [[C]]
- ; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[AND]](i32)
- ; GFX7-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY4]], [[C]]
- ; GFX7-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY1]], [[AND1]](i32)
- ; GFX7-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY5]], [[C]]
- ; GFX7-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[COPY2]], [[AND2]](i32)
+ ; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[COPY]], [[COPY3]](i32)
+ ; GFX7-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY1]], [[COPY4]](i32)
+ ; GFX7-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[COPY2]], [[COPY5]](i32)
; GFX7-NEXT: $vgpr0 = COPY [[SHL]](i32)
; GFX7-NEXT: $vgpr1 = COPY [[SHL1]](i32)
; GFX7-NEXT: $vgpr2 = COPY [[SHL2]](i32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index 1f10aaf81646a..bfcc8c5a65217 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -10,7 +10,6 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX6-LABEL: v_lshr_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -18,19 +17,18 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX8-LABEL: v_lshr_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -38,15 +36,13 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX11-TRUE16-LABEL: v_lshr_i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_lshr_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -100,29 +96,14 @@ define i8 @v_lshr_i8_7(i8 %value) {
}
define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) {
-; GFX6-LABEL: s_lshr_i8:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s0, s0, 0xff
-; GFX6-NEXT: s_lshr_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_lshr_i8:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s0, s0, 0xff
-; GFX8-NEXT: s_lshr_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_lshr_i8:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_and_b32 s0, s0, 0xff
-; GFX9-NEXT: s_lshr_b32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_lshr_i8:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_and_b32 s0, s0, 0xff
+; GCN-NEXT: s_lshr_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_lshr_i8:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xff
; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xff
; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1
; GFX10PLUS-NEXT: ; return to shader part epilog
@@ -162,7 +143,6 @@ define i24 @v_lshr_i24(i24 %value, i24 %amount) {
; GCN-LABEL: v_lshr_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -170,7 +150,6 @@ define i24 @v_lshr_i24(i24 %value, i24 %amount) {
; GFX10PLUS-LABEL: v_lshr_i24:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
@@ -623,7 +602,6 @@ define i16 @v_lshr_i16(i16 %value, i16 %amount) {
; GFX6-LABEL: v_lshr_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -759,7 +737,6 @@ define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) {
define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: lshr_i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -796,7 +773,6 @@ define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {
define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: lshr_i16_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -836,7 +812,6 @@ define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v2
@@ -953,7 +928,6 @@ define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshr_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
@@ -989,7 +963,6 @@ define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
@@ -1035,22 +1008,20 @@ define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
; GFX6-LABEL: v_lshr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v2
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v0
-; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v0
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, v4, v5
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v1
-; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v1
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, v5, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v6
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, v3, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v3, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v4i16:
@@ -1085,20 +1056,20 @@ define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {
; GFX6-LABEL: s_lshr_v4i16:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s4, s0, 0xffff
-; GFX6-NEXT: s_lshr_b32 s4, s4, s2
-; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100010
+; GFX6-NEXT: s_lshr_b32 s4, s2, 16
+; GFX6-NEXT: s_and_b32 s6, s0, 0xffff
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100010
-; GFX6-NEXT: s_lshr_b32 s0, s0, s2
-; GFX6-NEXT: s_and_b32 s2, s1, 0xffff
-; GFX6-NEXT: s_lshr_b32 s2, s2, s3
-; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100010
+; GFX6-NEXT: s_lshr_b32 s5, s3, 16
+; GFX6-NEXT: s_lshr_b32 s0, s0, s4
+; GFX6-NEXT: s_and_b32 s4, s1, 0xffff
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100010
-; GFX6-NEXT: s_lshr_b32 s1, s1, s3
+; GFX6-NEXT: s_lshr_b32 s1, s1, s5
+; GFX6-NEXT: s_lshr_b32 s2, s6, s2
+; GFX6-NEXT: s_lshr_b32 s3, s4, s3
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
-; GFX6-NEXT: s_or_b32 s0, s4, s0
-; GFX6-NEXT: s_or_b32 s1, s2, s1
+; GFX6-NEXT: s_or_b32 s0, s2, s0
+; GFX6-NEXT: s_or_b32 s1, s3, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_lshr_v4i16:
@@ -1182,38 +1153,34 @@ define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6-LABEL: v_lshr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v4
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v0
-; GFX6-NEXT: v_bfe_u32 v4, v4, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX6-NEXT: v_and_b32_e32 v12, 0xffff, v0
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v8, v8, v9
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v1
-; GFX6-NEXT: v_bfe_u32 v5, v5, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v9, 16, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, v5, v8
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX6-NEXT: v_lshrrev_b32_e32 v11, 16, v7
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, v4, v9
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, v5, v1
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v6
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v2
-; GFX6-NEXT: v_bfe_u32 v6, v6, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v6, v6, v8
; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, v5, v9
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v7
-; GFX6-NEXT: v_and_b32_e32 v9, 0xffff, v3
-; GFX6-NEXT: v_bfe_u32 v7, v7, 16, 16
+; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v3
; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, v7, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v6, v6, v9
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, v9, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v10, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, v11, v3
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, v4, v12
+; GFX6-NEXT: v_lshrrev_b32_e32 v7, v7, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_or_b32_e32 v0, v8, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX6-NEXT: v_or_b32_e32 v2, v6, v2
+; GFX6-NEXT: v_or_b32_e32 v3, v7, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v8i16:
@@ -1258,34 +1225,34 @@ define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {
; GFX6-LABEL: s_lshr_v8i16:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s8, s0, 0xffff
-; GFX6-NEXT: s_lshr_b32 s8, s8, s4
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100010
+; GFX6-NEXT: s_lshr_b32 s8, s4, 16
+; GFX6-NEXT: s_and_b32 s12, s0, 0xffff
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100010
-; GFX6-NEXT: s_lshr_b32 s0, s0, s4
-; GFX6-NEXT: s_and_b32 s4, s1, 0xffff
-; GFX6-NEXT: s_lshr_b32 s4, s4, s5
-; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100010
+; GFX6-NEXT: s_lshr_b32 s0, s0, s8
+; GFX6-NEXT: s_and_b32 s8, s1, 0xffff
+; GFX6-NEXT: s_lshr_b32 s9, s5, 16
+; GFX6-NEXT: s_lshr_b32 s5, s8, s5
+; GFX6-NEXT: s_and_b32 s8, s2, 0xffff
+; GFX6-NEXT: s_lshr_b32 s10, s6, 16
+; GFX6-NEXT: s_lshr_b32 s11, s7, 16
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100010
-; GFX6-NEXT: s_lshr_b32 s1, s1, s5
-; GFX6-NEXT: s_and_b32 s5, s2, 0xffff
-; GFX6-NEXT: s_lshr_b32 s5, s5, s6
-; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100010
+; GFX6-NEXT: s_lshr_b32 s6, s8, s6
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100010
-; GFX6-NEXT: s_lshr_b32 s2, s2, s6
-; GFX6-NEXT: s_and_b32 s6, s3, 0xffff
-; GFX6-NEXT: s_lshr_b32 s6, s6, s7
-; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100010
+; GFX6-NEXT: s_and_b32 s8, s3, 0xffff
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100010
-; GFX6-NEXT: s_lshr_b32 s3, s3, s7
+; GFX6-NEXT: s_lshr_b32 s1, s1, s9
+; GFX6-NEXT: s_lshr_b32 s2, s2, s10
+; GFX6-NEXT: s_lshr_b32 s3, s3, s11
+; GFX6-NEXT: s_lshr_b32 s4, s12, s4
+; GFX6-NEXT: s_lshr_b32 s7, s8, s7
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s0, s8, s0
-; GFX6-NEXT: s_or_b32 s1, s4, s1
-; GFX6-NEXT: s_or_b32 s2, s5, s2
-; GFX6-NEXT: s_or_b32 s3, s6, s3
+; GFX6-NEXT: s_or_b32 s0, s4, s0
+; GFX6-NEXT: s_or_b32 s1, s5, s1
+; GFX6-NEXT: s_or_b32 s2, s6, s2
+; GFX6-NEXT: s_or_b32 s3, s7, s3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_lshr_v8i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
index efb8fc0ed4c4c..6eb6715ab9736 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
@@ -10,40 +10,36 @@ define i8 @v_shl_i8(i8 %value, i8 %amount) {
; GFX6-LABEL: v_shl_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_shl_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_shl_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_shl_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_lshlrev_b16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_shl_i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_shl_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = shl i8 %value, %amount
@@ -91,26 +87,13 @@ define i8 @v_shl_i8_7(i8 %value) {
}
define amdgpu_ps i8 @s_shl_i8(i8 inreg %value, i8 inreg %amount) {
-; GFX6-LABEL: s_shl_i8:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_shl_i8:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_lshl_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_shl_i8:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_lshl_b32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_shl_i8:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_shl_i8:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xff
; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s1
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = shl i8 %value, %amount
@@ -136,14 +119,12 @@ define i24 @v_shl_i24(i24 %value, i24 %amount) {
; GCN-LABEL: v_shl_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10PLUS-LABEL: v_shl_i24:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = shl i24 %value, %amount
@@ -593,7 +574,6 @@ define i16 @v_shl_i16(i16 %value, i16 %amount) {
; GFX6-LABEL: v_shl_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
@@ -701,7 +681,6 @@ define amdgpu_ps i16 @s_shl_i16_15(i16 inreg %value) {
define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: shl_i16_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
@@ -737,7 +716,6 @@ define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) {
define amdgpu_ps half @shl_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: shl_i16_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
@@ -776,7 +754,6 @@ define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v3, v2
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -895,7 +872,6 @@ define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -932,7 +908,6 @@ define amdgpu_ps float @shl_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount)
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -980,18 +955,16 @@ define <2 x float> @v_shl_v4i16(<4 x i16> %value, <4 x i16> %amount) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v2
-; GFX6-NEXT: v_bfe_u32 v2, v2, 16, 16
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, v2, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, v6, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v3
-; GFX6-NEXT: v_bfe_u32 v3, v3, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, v3, v5
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, v3, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, v7, v5
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -1032,14 +1005,14 @@ define amdgpu_ps <2 x i32> @s_shl_v4i16(<4 x i16> inreg %value, <4 x i16> inreg
; GFX6-LABEL: s_shl_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s4, s0, 16
+; GFX6-NEXT: s_lshr_b32 s6, s2, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, s2
-; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100010
-; GFX6-NEXT: s_lshl_b32 s2, s4, s2
+; GFX6-NEXT: s_lshl_b32 s2, s4, s6
; GFX6-NEXT: s_lshr_b32 s5, s1, 16
-; GFX6-NEXT: s_lshl_b32 s1, s1, s3
-; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100010
+; GFX6-NEXT: s_lshr_b32 s7, s3, 16
; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX6-NEXT: s_lshl_b32 s3, s5, s3
+; GFX6-NEXT: s_lshl_b32 s1, s1, s3
+; GFX6-NEXT: s_lshl_b32 s3, s5, s7
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s0, s0, s2
@@ -1129,36 +1102,32 @@ define <4 x float> @v_shl_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX6-NEXT: v_and_b32_e32 v12, 0xffff, v4
-; GFX6-NEXT: v_bfe_u32 v4, v4, 16, 16
-; GFX6-NEXT: v_lshlrev_b32_e32 v4, v4, v8
+; GFX6-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, v12, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v12, v0
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v5
-; GFX6-NEXT: v_bfe_u32 v5, v5, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX6-NEXT: v_lshlrev_b32_e32 v5, v5, v9
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, v5, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v5, v13, v9
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, v8, v1
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v6
-; GFX6-NEXT: v_bfe_u32 v6, v6, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v14, 16, v6
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX6-NEXT: v_lshlrev_b32_e32 v6, v6, v10
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, v6, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v6, v14, v10
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2
-; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v7
-; GFX6-NEXT: v_bfe_u32 v7, v7, 16, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6
-; GFX6-NEXT: v_lshlrev_b32_e32 v7, v7, v11
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, v7, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v7, v15, v11
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, v8, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
@@ -1209,30 +1178,30 @@ define amdgpu_ps <4 x i32> @s_shl_v8i16(<8 x i16> inreg %value, <8 x i16> inreg
; GFX6-LABEL: s_shl_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s8, s0, 16
+; GFX6-NEXT: s_lshr_b32 s12, s4, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, s4
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100010
-; GFX6-NEXT: s_lshl_b32 s4, s8, s4
+; GFX6-NEXT: s_lshl_b32 s4, s8, s12
; GFX6-NEXT: s_lshr_b32 s9, s1, 16
-; GFX6-NEXT: s_lshl_b32 s1, s1, s5
-; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100010
+; GFX6-NEXT: s_lshr_b32 s13, s5, 16
; GFX6-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX6-NEXT: s_lshl_b32 s5, s9, s5
+; GFX6-NEXT: s_lshl_b32 s1, s1, s5
+; GFX6-NEXT: s_lshl_b32 s5, s9, s13
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshr_b32 s10, s2, 16
-; GFX6-NEXT: s_lshl_b32 s2, s2, s6
-; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100010
+; GFX6-NEXT: s_lshr_b32 s14, s6, 16
; GFX6-NEXT: s_or_b32 s0, s0, s4
; GFX6-NEXT: s_and_b32 s4, s5, 0xffff
-; GFX6-NEXT: s_lshl_b32 s6, s10, s6
+; GFX6-NEXT: s_lshl_b32 s2, s2, s6
+; GFX6-NEXT: s_lshl_b32 s6, s10, s14
; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshr_b32 s11, s3, 16
-; GFX6-NEXT: s_lshl_b32 s3, s3, s7
-; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100010
+; GFX6-NEXT: s_lshr_b32 s15, s7, 16
; GFX6-NEXT: s_or_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s4, s6, 0xffff
-; GFX6-NEXT: s_lshl_b32 s7, s11, s7
+; GFX6-NEXT: s_lshl_b32 s3, s3, s7
+; GFX6-NEXT: s_lshl_b32 s7, s11, s15
; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s2, s2, s4
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
index 0363189392332..8bd6f65734ea7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
@@ -27,22 +27,24 @@ define i2 @bitreverse_i2(i2 %x) {
define i3 @bitreverse_i3(i3 %x) {
; RV32-LABEL: bitreverse_i3:
; RV32: # %bb.0:
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: li a1, 2
+; RV32-NEXT: slli a2, a0, 2
; RV32-NEXT: andi a0, a0, 7
-; RV32-NEXT: andi a1, a1, 4
-; RV32-NEXT: andi a2, a0, 2
-; RV32-NEXT: or a1, a1, a2
+; RV32-NEXT: andi a2, a2, 4
+; RV32-NEXT: and a1, a0, a1
+; RV32-NEXT: or a1, a2, a1
; RV32-NEXT: srli a0, a0, 2
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: bitreverse_i3:
; RV64: # %bb.0:
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: li a1, 2
+; RV64-NEXT: slli a2, a0, 2
; RV64-NEXT: andi a0, a0, 7
-; RV64-NEXT: andi a1, a1, 4
-; RV64-NEXT: andi a2, a0, 2
-; RV64-NEXT: or a1, a1, a2
+; RV64-NEXT: andi a2, a2, 4
+; RV64-NEXT: and a1, a0, a1
+; RV64-NEXT: or a1, a2, a1
; RV64-NEXT: srli a0, a0, 2
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
@@ -87,46 +89,48 @@ define i4 @bitreverse_i4(i4 %x) {
define i7 @bitreverse_i7(i7 %x) {
; RV32-LABEL: bitreverse_i7:
; RV32: # %bb.0:
-; RV32-NEXT: slli a1, a0, 6
-; RV32-NEXT: slli a2, a0, 4
-; RV32-NEXT: slli a3, a0, 2
-; RV32-NEXT: andi a1, a1, 64
-; RV32-NEXT: andi a2, a2, 32
+; RV32-NEXT: li a1, 4
+; RV32-NEXT: slli a2, a0, 6
+; RV32-NEXT: slli a3, a0, 4
+; RV32-NEXT: andi a2, a2, 64
+; RV32-NEXT: andi a3, a3, 32
+; RV32-NEXT: slli a4, a0, 2
; RV32-NEXT: andi a0, a0, 127
-; RV32-NEXT: andi a3, a3, 16
-; RV32-NEXT: andi a4, a0, 8
-; RV32-NEXT: or a1, a1, a2
-; RV32-NEXT: or a3, a3, a4
-; RV32-NEXT: srli a2, a0, 2
-; RV32-NEXT: srli a4, a0, 4
-; RV32-NEXT: andi a2, a2, 4
-; RV32-NEXT: andi a4, a4, 2
-; RV32-NEXT: or a1, a1, a3
+; RV32-NEXT: andi a4, a4, 16
+; RV32-NEXT: andi a5, a0, 8
+; RV32-NEXT: or a2, a2, a3
+; RV32-NEXT: or a4, a4, a5
+; RV32-NEXT: srli a3, a0, 2
+; RV32-NEXT: srli a5, a0, 4
+; RV32-NEXT: and a1, a3, a1
+; RV32-NEXT: andi a5, a5, 2
; RV32-NEXT: or a2, a2, a4
-; RV32-NEXT: or a1, a1, a2
+; RV32-NEXT: or a1, a1, a5
+; RV32-NEXT: or a1, a2, a1
; RV32-NEXT: srli a0, a0, 6
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: bitreverse_i7:
; RV64: # %bb.0:
-; RV64-NEXT: slli a1, a0, 6
-; RV64-NEXT: slli a2, a0, 4
-; RV64-NEXT: slli a3, a0, 2
-; RV64-NEXT: andi a1, a1, 64
-; RV64-NEXT: andi a2, a2, 32
+; RV64-NEXT: li a1, 4
+; RV64-NEXT: slli a2, a0, 6
+; RV64-NEXT: slli a3, a0, 4
+; RV64-NEXT: andi a2, a2, 64
+; RV64-NEXT: andi a3, a3, 32
+; RV64-NEXT: slli a4, a0, 2
; RV64-NEXT: andi a0, a0, 127
-; RV64-NEXT: andi a3, a3, 16
-; RV64-NEXT: andi a4, a0, 8
-; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: or a3, a3, a4
-; RV64-NEXT: srli a2, a0, 2
-; RV64-NEXT: srli a4, a0, 4
-; RV64-NEXT: andi a2, a2, 4
-; RV64-NEXT: andi a4, a4, 2
-; RV64-NEXT: or a1, a1, a3
+; RV64-NEXT: andi a4, a4, 16
+; RV64-NEXT: andi a5, a0, 8
+; RV64-NEXT: or a2, a2, a3
+; RV64-NEXT: or a4, a4, a5
+; RV64-NEXT: srli a3, a0, 2
+; RV64-NEXT: srli a5, a0, 4
+; RV64-NEXT: and a1, a3, a1
+; RV64-NEXT: andi a5, a5, 2
; RV64-NEXT: or a2, a2, a4
-; RV64-NEXT: or a1, a1, a2
+; RV64-NEXT: or a1, a1, a5
+; RV64-NEXT: or a1, a2, a1
; RV64-NEXT: srli a0, a0, 6
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir
index e5ac59c6c4481..b22230b325ecb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir
@@ -8,12 +8,10 @@ body: |
; CHECK-LABEL: name: ashr_i7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
@@ -33,12 +31,10 @@ body: |
; CHECK-LABEL: name: ashr_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
@@ -58,12 +54,10 @@ body: |
; CHECK-LABEL: name: ashr_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir
index 0d097a5128c18..4fde1a2f78cd1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir
@@ -8,12 +8,10 @@ body: |
; CHECK-LABEL: name: ashr_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
- ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -33,12 +31,10 @@ body: |
; CHECK-LABEL: name: ashr_i15
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
- ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -58,12 +54,10 @@ body: |
; CHECK-LABEL: name: ashr_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
- ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -304,9 +298,7 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
+ ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir
index 2f1ca52c6cf0d..8b1da03abf4a7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir
@@ -280,7 +280,8 @@ body: |
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[COPY1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -366,7 +367,8 @@ body: |
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C8]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND4]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[COPY1]]
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[AND5]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C2]](s32)
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
index 14cd32020d301..892a642a26ef0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
@@ -276,7 +276,8 @@ body: |
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C3]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[COPY1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C]](s64)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
@@ -362,7 +363,8 @@ body: |
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C8]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND4]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[COPY1]]
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[AND5]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C2]](s64)
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR2]], [[C4]]
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir
index 71d7e839691dd..f70924f0c4d3f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir
@@ -9,9 +9,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
@@ -32,9 +31,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
@@ -55,9 +53,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
index ae58e2c1ff1c1..ca2bdb0c26874 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
@@ -9,9 +9,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -32,9 +31,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -55,9 +53,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -290,8 +287,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[AND1]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir
index 00ea5ff1eaed2..5056e7646d8d0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir
@@ -21,12 +21,11 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -55,12 +54,11 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -187,11 +185,10 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND2]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -221,11 +218,10 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND2]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
index 9a4bb50f383ca..4796760d5b95e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
@@ -21,12 +21,11 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -55,12 +54,11 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -168,11 +166,10 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -202,11 +199,10 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir
index 8b0728b335093..71575c9097056 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir
@@ -8,9 +8,7 @@ body: |
; CHECK-LABEL: name: shl_i7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
@@ -30,9 +28,7 @@ body: |
; CHECK-LABEL: name: shl_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
@@ -52,9 +48,7 @@ body: |
; CHECK-LABEL: name: shl_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir
index 2ee4520b14bdb..95299a0e0cc3a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir
@@ -8,9 +8,7 @@ body: |
; CHECK-LABEL: name: shl_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -30,9 +28,7 @@ body: |
; CHECK-LABEL: name: shl_i15
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -52,9 +48,7 @@ body: |
; CHECK-LABEL: name: shl_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
@@ -263,9 +257,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll
index 5dc2d30966e03..588512ffea96c 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll
@@ -42,28 +42,24 @@ define i8 @ashrv_i8(i8 %x, i8 %y) {
; NO-SIGNEXT: .functype ashrv_i8 (i32, i32) -> (i32)
; NO-SIGNEXT-NEXT: .local i32
; NO-SIGNEXT-NEXT: # %bb.0:
-; NO-SIGNEXT-NEXT: i32.const $push5=, 24
-; NO-SIGNEXT-NEXT: local.set 2, $pop5
-; NO-SIGNEXT-NEXT: local.get $push7=, 0
+; NO-SIGNEXT-NEXT: i32.const $push3=, 24
+; NO-SIGNEXT-NEXT: local.set 2, $pop3
+; NO-SIGNEXT-NEXT: local.get $push5=, 0
+; NO-SIGNEXT-NEXT: local.get $push4=, 2
+; NO-SIGNEXT-NEXT: i32.shl $push2=, $pop5, $pop4
; NO-SIGNEXT-NEXT: local.get $push6=, 2
-; NO-SIGNEXT-NEXT: i32.shl $push4=, $pop7, $pop6
-; NO-SIGNEXT-NEXT: local.get $push8=, 2
-; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop4, $pop8
-; NO-SIGNEXT-NEXT: local.get $push9=, 1
-; NO-SIGNEXT-NEXT: i32.const $push3=, 255
-; NO-SIGNEXT-NEXT: i32.and $push2=, $pop9, $pop3
-; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop2, $pop6
+; NO-SIGNEXT-NEXT: local.get $push7=, 1
+; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop7
; NO-SIGNEXT-NEXT: return $pop1
;
; SIGNEXT-LABEL: ashrv_i8:
; SIGNEXT: .functype ashrv_i8 (i32, i32) -> (i32)
; SIGNEXT-NEXT: # %bb.0:
-; SIGNEXT-NEXT: local.get $push4=, 0
-; SIGNEXT-NEXT: i32.extend8_s $push0=, $pop4
-; SIGNEXT-NEXT: local.get $push5=, 1
-; SIGNEXT-NEXT: i32.const $push3=, 255
-; SIGNEXT-NEXT: i32.and $push2=, $pop5, $pop3
-; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; SIGNEXT-NEXT: local.get $push2=, 0
+; SIGNEXT-NEXT: i32.extend8_s $push0=, $pop2
+; SIGNEXT-NEXT: local.get $push3=, 1
+; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop3
; SIGNEXT-NEXT: return $pop1
%a = ashr i8 %x, %y
ret i8 %a
@@ -107,28 +103,24 @@ define i16 @ashrv_i16(i16 %x, i16 %y) {
; NO-SIGNEXT: .functype ashrv_i16 (i32, i32) -> (i32)
; NO-SIGNEXT-NEXT: .local i32
; NO-SIGNEXT-NEXT: # %bb.0:
-; NO-SIGNEXT-NEXT: i32.const $push5=, 16
-; NO-SIGNEXT-NEXT: local.set 2, $pop5
-; NO-SIGNEXT-NEXT: local.get $push7=, 0
+; NO-SIGNEXT-NEXT: i32.const $push3=, 16
+; NO-SIGNEXT-NEXT: local.set 2, $pop3
+; NO-SIGNEXT-NEXT: local.get $push5=, 0
+; NO-SIGNEXT-NEXT: local.get $push4=, 2
+; NO-SIGNEXT-NEXT: i32.shl $push2=, $pop5, $pop4
; NO-SIGNEXT-NEXT: local.get $push6=, 2
-; NO-SIGNEXT-NEXT: i32.shl $push4=, $pop7, $pop6
-; NO-SIGNEXT-NEXT: local.get $push8=, 2
-; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop4, $pop8
-; NO-SIGNEXT-NEXT: local.get $push9=, 1
-; NO-SIGNEXT-NEXT: i32.const $push3=, 65535
-; NO-SIGNEXT-NEXT: i32.and $push2=, $pop9, $pop3
-; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop2, $pop6
+; NO-SIGNEXT-NEXT: local.get $push7=, 1
+; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop7
; NO-SIGNEXT-NEXT: return $pop1
;
; SIGNEXT-LABEL: ashrv_i16:
; SIGNEXT: .functype ashrv_i16 (i32, i32) -> (i32)
; SIGNEXT-NEXT: # %bb.0:
-; SIGNEXT-NEXT: local.get $push4=, 0
-; SIGNEXT-NEXT: i32.extend16_s $push0=, $pop4
-; SIGNEXT-NEXT: local.get $push5=, 1
-; SIGNEXT-NEXT: i32.const $push3=, 65535
-; SIGNEXT-NEXT: i32.and $push2=, $pop5, $pop3
-; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; SIGNEXT-NEXT: local.get $push2=, 0
+; SIGNEXT-NEXT: i32.extend16_s $push0=, $pop2
+; SIGNEXT-NEXT: local.get $push3=, 1
+; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop3
; SIGNEXT-NEXT: return $pop1
%a = ashr i16 %x, %y
ret i16 %a
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
index 5ee6c10a1f1ba..968a2e0fee1b7 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
@@ -32,9 +32,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
%0:i32(i32) = ARGUMENT_i32 0, implicit $arguments
%2:i32(i32) = ARGUMENT_i32 1, implicit $arguments
@@ -55,9 +53,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
%1:_(i8) = G_CONSTANT i8 37
@@ -77,9 +73,7 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
%2:i32(i32) = ARGUMENT_i32 1, implicit $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
index 265694ce8e681..32ede5a74c6b2 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
@@ -68,13 +68,9 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_1]], implicit-def dead $arguments
; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
@@ -102,17 +98,11 @@ body: |
; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_1]], [[CONST_I64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_]], implicit-def dead $arguments
; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_1:%[0-9]+]]:i64 = SHR_U_I64 [[SHR_U_I64_]], [[AND_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_1:%[0-9]+]]:i64 = SHR_U_I64 [[SHR_U_I64_]], [[I64_EXTEND_U_I32_1]], implicit-def dead $arguments
; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_1]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
index d544220f8bee5..921729edbf6f4 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
@@ -68,13 +68,9 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_1]], implicit-def dead $arguments
; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
@@ -102,17 +98,11 @@ body: |
; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_1:%[0-9]+]]:i64 = SHL_I64 [[SHL_I64_]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_1:%[0-9]+]]:i64 = SHL_I64 [[SHL_I64_]], [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[I64_EXTEND_U_I32_1]], implicit-def dead $arguments
; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_1]], [[SHR_U_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll
index 4054c2386fd08..0963624495596 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll
@@ -24,13 +24,11 @@ define i8 @lshrv_i8(i8 %x, i8 %y) {
; CHECK-LABEL: lshrv_i8:
; CHECK: .functype lshrv_i8 (i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
-; CHECK-NEXT: i32.const $push4=, 255
-; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
-; CHECK-NEXT: local.get $push6=, 1
-; CHECK-NEXT: i32.const $push3=, 255
-; CHECK-NEXT: i32.and $push2=, $pop6, $pop3
-; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop2
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push2=, 255
+; CHECK-NEXT: i32.and $push0=, $pop3, $pop2
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop4
; CHECK-NEXT: return $pop1
%a = lshr i8 %x, %y
ret i8 %a
@@ -57,13 +55,11 @@ define i16 @lshrv_i16(i16 %x, i16 %y) {
; CHECK-LABEL: lshrv_i16:
; CHECK: .functype lshrv_i16 (i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
-; CHECK-NEXT: i32.const $push4=, 65535
-; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
-; CHECK-NEXT: local.get $push6=, 1
-; CHECK-NEXT: i32.const $push3=, 65535
-; CHECK-NEXT: i32.and $push2=, $pop6, $pop3
-; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop2
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push2=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop3, $pop2
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop4
; CHECK-NEXT: return $pop1
%a = lshr i16 %x, %y
ret i16 %a
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
index 19d8cc82c8a81..a51049870923b 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
@@ -32,9 +32,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
%0:i32(i32) = ARGUMENT_i32 0, implicit $arguments
%2:i32(i32) = ARGUMENT_i32 1, implicit $arguments
@@ -55,9 +53,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
%1:_(i8) = G_CONSTANT i8 37
@@ -77,9 +73,7 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
%2:i32(i32) = ARGUMENT_i32 1, implicit $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll
index 5ceb1016e169f..0b94b95696e05 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll
@@ -19,11 +19,9 @@ define i8 @shlv_i8(i8 %x, i8 %y) {
; CHECK-LABEL: shlv_i8:
; CHECK: .functype shlv_i8 (i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push4=, 0
-; CHECK-NEXT: local.get $push3=, 1
-; CHECK-NEXT: i32.const $push2=, 255
-; CHECK-NEXT: i32.and $push1=, $pop3, $pop2
-; CHECK-NEXT: i32.shl $push0=, $pop4, $pop1
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.shl $push0=, $pop2, $pop1
; CHECK-NEXT: return $pop0
%a = shl i8 %x, %y
ret i8 %a
@@ -45,11 +43,9 @@ define i16 @shlv_i16(i16 %x, i16 %y) {
; CHECK-LABEL: shlv_i16:
; CHECK: .functype shlv_i16 (i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push4=, 0
-; CHECK-NEXT: local.get $push3=, 1
-; CHECK-NEXT: i32.const $push2=, 65535
-; CHECK-NEXT: i32.and $push1=, $pop3, $pop2
-; CHECK-NEXT: i32.shl $push0=, $pop4, $pop1
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.shl $push0=, $pop2, $pop1
; CHECK-NEXT: return $pop0
%a = shl i16 %x, %y
ret i16 %a
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
index ddbcdac0b6af6..ece33c5673284 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
@@ -32,9 +32,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
%0:i32(i32) = ARGUMENT_i32 0, implicit $arguments
%2:i32(i32) = ARGUMENT_i32 1, implicit $arguments
@@ -55,9 +53,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
%1:_(i8) = G_CONSTANT i8 37
@@ -77,9 +73,7 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
%0:i64(i64) = ARGUMENT_i64 0, implicit $arguments
%2:i32(i32) = ARGUMENT_i32 1, implicit $arguments
diff --git a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
index 8a6215e07ebf6..20951584bb2eb 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
@@ -149,7 +149,6 @@ define i1 @test_lshr_i1(i32 %arg1, i32 %arg2) {
; X64-NEXT: movl %edi, %eax
; X64-NEXT: movl %esi, %ecx
; X64-NEXT: andb $1, %al
-; X64-NEXT: andb $1, %cl
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NEXT: shrb %cl, %al
; X64-NEXT: # kill: def $al killed $al killed $eax
diff --git a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll
index c1b44f974c3df..8b68f162c49eb 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll
@@ -13,7 +13,6 @@ define i16 @test_shl_i4(i16 %v, i16 %a, i16 %b) {
; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: # kill: def $edx killed $edx def $rdx
; X64-NEXT: leal (%rdx,%rsi), %ecx
-; X64-NEXT: andb $15, %cl
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NEXT: shlb %cl, %dil
; X64-NEXT: movzbl %dil, %eax
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