[llvm] [AMDGPU] Allow combining uniform OR/AND to V_PERM (PR #220048)

[Jeffrey Byrnes via llvm-commits]

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@@ -747,32 +745,30 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
 ; GFX9-NEXT:    s_load_dword s2, s[8:9], 0x28
 ; GFX9-NEXT:    s_load_dword s3, s[8:9], 0x4c
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0xc0c0400
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0x6050400
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_sext_i32_i16 s5, s2
 ; GFX9-NEXT:    s_sext_i32_i16 s7, s3
 ; GFX9-NEXT:    s_ashr_i32 s7, s7, 8
 ; GFX9-NEXT:    s_ashr_i32 s5, s5, 8
-; GFX9-NEXT:    s_ashr_i32 s4, s2, 24
-; GFX9-NEXT:    s_ashr_i32 s6, s3, 24
 ; GFX9-NEXT:    s_min_i32 s5, s5, s7
 ; GFX9-NEXT:    s_sext_i32_i8 s7, s3
 ; GFX9-NEXT:    s_sext_i32_i8 s8, s2
+; GFX9-NEXT:    s_ashr_i32 s4, s2, 24
+; GFX9-NEXT:    s_ashr_i32 s6, s3, 24
+; GFX9-NEXT:    s_min_i32 s7, s8, s7
 ; GFX9-NEXT:    s_bfe_i32 s3, s3, 0x80010
 ; GFX9-NEXT:    s_bfe_i32 s2, s2, 0x80010
-; GFX9-NEXT:    s_min_i32 s7, s8, s7
-; GFX9-NEXT:    s_min_i32 s4, s4, s6
+; GFX9-NEXT:    v_mov_b32_e32 v1, s7
 ; GFX9-NEXT:    s_min_i32 s2, s2, s3
-; GFX9-NEXT:    s_lshl_b32 s5, s5, 8
-; GFX9-NEXT:    s_and_b32 s7, s7, 0xff
-; GFX9-NEXT:    s_lshl_b32 s4, s4, 8
-; GFX9-NEXT:    s_and_b32 s2, s2, 0xff
-; GFX9-NEXT:    s_or_b32 s5, s7, s5
-; GFX9-NEXT:    s_or_b32 s2, s2, s4
-; GFX9-NEXT:    s_and_b32 s5, s5, 0xffff
-; GFX9-NEXT:    s_lshl_b32 s2, s2, 16
-; GFX9-NEXT:    s_or_b32 s2, s5, s2
-; GFX9-NEXT:    v_mov_b32_e32 v1, s2
+; GFX9-NEXT:    v_perm_b32 v1, s5, v1, v2
+; GFX9-NEXT:    s_min_i32 s4, s4, s6
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_perm_b32 v2, s4, v2, v3
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jrbyrnes wrote:

Looks like a regression -- previously uniform code is converted to VALU , with increased demands on VGPR file

https://github.com/llvm/llvm-project/pull/220048