[llvm] [RISCV] Consistently use RISCVSubtarget::is64Bit() instead of isRV32/isRV64. (PR #223038)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

99% of code uses RISCVSubtarget::is64Bit().

Maybe we should consider removing is64Bit(), but right now I think we should be consistent.

---
Full diff: https://github.com/llvm/llvm-project/pull/223038.diff


4 Files Affected:

- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+3-3) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+1-1) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+1-1) 
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+1-2) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index eff674ea4f959..c8e8d8f247b63 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1361,9 +1361,9 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     // Use sext.h/zext.h for i16 with Zbb.
     if (SrcSize == 16 &&
         (STI.hasStdExtZbb() || (!IsSigned && STI.hasStdExtZbkb()))) {
-      MI.setDesc(TII.get(IsSigned       ? RISCV::SEXT_H
-                         : STI.isRV64() ? RISCV::ZEXT_H_RV64
-                                        : RISCV::ZEXT_H_RV32));
+      MI.setDesc(TII.get(IsSigned        ? RISCV::SEXT_H
+                         : STI.is64Bit() ? RISCV::ZEXT_H_RV64
+                                         : RISCV::ZEXT_H_RV32));
       constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
       return true;
     }
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 19b4a01b7733b..49694053ff4fc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4808,7 +4808,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
 
   SDLoc DL(Op);
 
-  if (Subtarget.isRV32() && Subtarget.hasStdExtP()) {
+  if (!Subtarget.is64Bit() && Subtarget.hasStdExtP()) {
     if (VT == MVT::v2i16) {
       SDValue Lo = DAG.getBitcast(
           MVT::v2i16,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ee47963aa041e..bebf521957568 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -544,7 +544,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   }
 
   if (RISCV::GPRPairRegClass.contains(DstReg, SrcReg)) {
-    if (STI.isRV32()) {
+    if (!STI.is64Bit()) {
       if (STI.hasStdExtZdinx()) {
         // On RV32_Zdinx, FMV.D will move a pair of registers to another pair of
         // registers, in one instruction.
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b22da42f0aec..6877d54384a52 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -262,8 +262,7 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
     if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
       return TTI::TCC_Free;
     // zext.w
-    if (Imm == UINT64_C(0xffffffff) &&
-        ((ST->hasStdExtZba() && ST->isRV64()) || ST->isRV32()))
+    if (Imm == UINT64_C(0xffffffff) && (!ST->is64Bit() || ST->hasStdExtZba()))
       return TTI::TCC_Free;
     // bclri
     if (ST->hasStdExtZbs() && (~Imm).isPowerOf2())

``````````

</details>


https://github.com/llvm/llvm-project/pull/223038