[llvm] [AMDGPU][MC] Diagnose bf16 inline constants without op_sel in the ass… (PR #223035)
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Fri Sep 11 12:49:52 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Joe Nash (Sisyph)
<details>
<summary>Changes</summary>
…embler
GFX1250 generates a bf16 inline constant in the high half of the corresponding fp32 inline constant. The VOP1 bf16 opcodes therefore only read it correctly in the VOP3 encoding with op_sel[0] set: v_cvt_f32_bf16, v_rcp_bf16, v_sqrt_bf16, v_rsq_bf16, v_log_bf16, v_exp_bf16, v_sin_bf16, v_cos_bf16 and v_tanh_bf16.
Codegen has applied this workaround since 57a9c4f939e5, but hand-written assembly and inline asm had no protection at all and silently assembled to instructions that read the wrong half. Reject those forms in the assembler.
Only single-source bf16 opcodes are affected. Multi-source and packed bf16 instructions such as v_fma_mix*_bf16, which also have a scalar bf16 src0, are explicitly excluded.
GFX1310 has the same FeatureBF16InlineConstFromUpperFP32 behaviour, so the gfx1250 and gfx13 MC tests are updated together.
Assisted-by: Claude Code:claude-opus-5[1m]
---
Patch is 57.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223035.diff
14 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+55)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+6)
- (added) llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err-fake16.s (+72)
- (added) llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err.s (+72)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s (-54)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s (-54)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s (+18-18)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s (+18-18)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_bf16_inline_const_err-fake16.s (+72)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_bf16_inline_const_err.s (+72)
- (modified) llvm/test/MC/AMDGPU/gfx13_asm_vop1.s (-54)
- (modified) llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1-fake16.s (+18-18)
- (modified) llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1.s (+18-18)
- (modified) llvm/test/MC/AMDGPU/literals.s (+4-4)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 50733d573b623..cf52274e65189 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1826,6 +1826,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
+ bool validateBF16InlineConst(const MCInst &Inst,
+ const OperandVector &Operands);
bool validateSOPLiteral(const MCInst &Inst, const OperandVector &Operands);
bool validateConstantBusLimitations(const MCInst &Inst,
const OperandVector &Operands);
@@ -4866,6 +4868,56 @@ bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,
return false;
}
+// On subtargets with FeatureBF16InlineConstFromUpperFP32 the hardware generates
+// a bf16 inline constant in the high half of the corresponding fp32 inline
+// constant. A VOP1 bf16 opcode (v_cvt_f32_bf16 and the bf16 transcendentals)
+// reads the low half of its source, so it must use the VOP3 encoding with
+// op_sel[0] set in order to see the constant at all.
+bool AMDGPUAsmParser::validateBF16InlineConst(const MCInst &Inst,
+ const OperandVector &Operands) {
+ if (!getFeatureBits()[AMDGPU::FeatureBF16InlineConstFromUpperFP32])
+ return true;
+
+ const unsigned Opc = Inst.getOpcode();
+ const MCInstrDesc &Desc = MII.get(Opc);
+ const bool IsVOP3 =
+ SIInstrFlags::isVOP3(Desc) && !SIInstrFlags::isVOP3P(Desc);
+ if (!SIInstrFlags::isVOP1(Desc) && !IsVOP3)
+ return true;
+
+ // Only the single-source VOP1 bf16 opcodes are affected. Multi-source and
+ // packed bf16 instructions such as v_fma_mix*_bf16 are not.
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1))
+ return true;
+
+ const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
+ if (Src0Idx == -1)
+ return true;
+
+ const MCOperandInfo &Src0Info = Desc.operands()[Src0Idx];
+ if (!AMDGPU::isBF16SrcOperand(Src0Info))
+ return true;
+
+ const MCOperand &Src0 = Inst.getOperand(Src0Idx);
+ if (!Src0.isImm() ||
+ !AMDGPU::isInlinableLiteralBF16(static_cast<int16_t>(Src0.getImm()),
+ hasInv2PiInlineImm()))
+ return true;
+
+ if (IsVOP3) {
+ const int ModsIdx =
+ AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
+ if (ModsIdx != -1 &&
+ (Inst.getOperand(ModsIdx).getImm() & SISrcMods::OP_SEL_0))
+ return true;
+ }
+
+ Error(getOperandLoc(Operands, Src0Idx),
+ "bf16 inline constant is read from the high half of the fp32 inline "
+ "constant on this GPU; use the e64 encoding with op_sel:[1,0]");
+ return false;
+}
+
bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst,
const OperandVector &Operands) {
unsigned Opcode = Inst.getOpcode();
@@ -5749,6 +5801,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, SMLoc IDLoc,
if (!validateOffset(Inst, Operands)) {
return false;
}
+ if (!validateBF16InlineConst(Inst, Operands)) {
+ return false;
+ }
if (!validateMAIAccWrite(Inst, Operands)) {
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 6f875db59917e..22968c499e019 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1546,6 +1546,12 @@ inline bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
return isSISrcOperand(Desc.operands()[OpNo]);
}
+/// Is this a scalar (i.e. not packed) bf16 source operand?
+constexpr bool isBF16SrcOperand(const MCOperandInfo &OpInfo) {
+ return OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_BF16 ||
+ OpInfo.OperandType == AMDGPU::OPERAND_REG_INLINE_C_BF16;
+}
+
/// Is this a KImm operand?
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err-fake16.s b/llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err-fake16.s
new file mode 100644
index 0000000000000..7103e7af7d591
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err-fake16.s
@@ -0,0 +1,72 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+// RUN: not llvm-mc -triple=amdgpu12.50 -mattr=-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=ERR --implicit-check-not=error: --strict-whitespace %s
+
+// The hardware generates a bf16 inline constant in the high half of the
+// corresponding fp32 inline constant, so these opcodes must use the VOP3
+// encoding with op_sel[0] set. Anything else silently reads the wrong half.
+
+v_cvt_f32_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:20: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rcp_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_sqrt_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:17: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rsq_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_log_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_exp_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_sin_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_cos_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_tanh_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:17: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+// The VOP1 encoding cannot be fixed up, and the VOP3 encoding is only correct
+// with op_sel[0] set.
+
+v_rcp_bf16_e32 v1, 0.5
+// ERR: :[[@LINE-1]]:20: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rcp_bf16_e64 v1, 0.5
+// ERR: :[[@LINE-1]]:20: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+// Integer inline constants are affected just like the floating-point ones.
+
+v_rcp_bf16 v1, -1
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rcp_bf16 v1, 64
+// ERR: :[[@LINE-1]]:16: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+// These are fine: a literal is not an inline constant (lit() forces one for a
+// value that would otherwise be inlinable), a register source is unaffected,
+// and the VOP3 encoding with op_sel[0] reads the correct half.
+
+v_rcp_bf16 v1, 0x4049
+
+v_rcp_bf16 v1, lit(0.5)
+
+v_rcp_bf16 v1, v2
+
+v_rcp_bf16 v1, s2
+
+v_rcp_bf16 v1, src_scc
+
+v_rcp_bf16_e64 v1, 0.5 op_sel:[1,0]
+
+v_cvt_f32_bf16_e64 v1, 0.5 op_sel:[1,0]
+
+// f16 opcodes are not affected.
+
+v_rcp_f16 v1, 0.5
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err.s
new file mode 100644
index 0000000000000..54923138c2301
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err.s
@@ -0,0 +1,72 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+// RUN: not llvm-mc -triple=amdgpu12.50 -mattr=+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=ERR --implicit-check-not=error: --strict-whitespace %s
+
+// The hardware generates a bf16 inline constant in the high half of the
+// corresponding fp32 inline constant, so these opcodes must use the VOP3
+// encoding with op_sel[0] set. Anything else silently reads the wrong half.
+
+v_cvt_f32_bf16 v1, 0.5
+// ERR: :[[@LINE-1]]:20: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rcp_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_sqrt_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:19: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rsq_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_log_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_exp_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_sin_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_cos_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_tanh_bf16 v1.l, 0.5
+// ERR: :[[@LINE-1]]:19: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+// The VOP1 encoding cannot be fixed up, and the VOP3 encoding is only correct
+// with op_sel[0] set.
+
+v_rcp_bf16_e32 v1.l, 0.5
+// ERR: :[[@LINE-1]]:22: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rcp_bf16_e64 v1.l, 0.5
+// ERR: :[[@LINE-1]]:22: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+// Integer inline constants are affected just like the floating-point ones.
+
+v_rcp_bf16 v1.l, -1
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+v_rcp_bf16 v1.l, 64
+// ERR: :[[@LINE-1]]:18: error: bf16 inline constant is read from the high half of the fp32 inline constant on this GPU; use the e64 encoding with op_sel:[1,0]
+
+// These are fine: a literal is not an inline constant (lit() forces one for a
+// value that would otherwise be inlinable), a register source is unaffected,
+// and the VOP3 encoding with op_sel[0] reads the correct half.
+
+v_rcp_bf16 v1.l, 0x4049
+
+v_rcp_bf16 v1.l, lit(0.5)
+
+v_rcp_bf16 v1.l, v2.l
+
+v_rcp_bf16 v1.l, s2
+
+v_rcp_bf16 v1.l, src_scc
+
+v_rcp_bf16_e64 v1.l, 0.5 op_sel:[1,0]
+
+v_cvt_f32_bf16_e64 v1, 0.5 op_sel:[1,0]
+
+// f16 opcodes are not affected.
+
+v_rcp_f16 v1.l, 0.5
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
index 53f9ccff58aa6..d0476d439ba4e 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
@@ -151,12 +151,6 @@ v_tanh_bf16 v5, exec_hi
v_tanh_bf16 v5, null
// GFX1250: v_tanh_bf16_e32 v5, null ; encoding: [0x7c,0x94,0x0a,0x7e]
-v_tanh_bf16 v5, -1
-// GFX1250: v_tanh_bf16_e32 v5, -1 ; encoding: [0xc1,0x94,0x0a,0x7e]
-
-v_tanh_bf16 v5, 0.5
-// GFX1250: v_tanh_bf16_e32 v5, 0.5 ; encoding: [0xf0,0x94,0x0a,0x7e]
-
v_tanh_bf16 v5, src_scc
// GFX1250: v_tanh_bf16_e32 v5, src_scc ; encoding: [0xfd,0x94,0x0a,0x7e]
@@ -241,12 +235,6 @@ v_rcp_bf16 v5, exec_hi
v_rcp_bf16 v5, null
// GFX1250: v_rcp_bf16_e32 v5, null ; encoding: [0x7c,0xf2,0x0a,0x7e]
-v_rcp_bf16 v5, -1
-// GFX1250: v_rcp_bf16_e32 v5, -1 ; encoding: [0xc1,0xf2,0x0a,0x7e]
-
-v_rcp_bf16 v5, 0.5
-// GFX1250: v_rcp_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xf2,0x0a,0x7e]
-
v_rcp_bf16 v5, src_scc
// GFX1250: v_rcp_bf16_e32 v5, src_scc ; encoding: [0xfd,0xf2,0x0a,0x7e]
@@ -286,12 +274,6 @@ v_sqrt_bf16 v5, exec_hi
v_sqrt_bf16 v5, null
// GFX1250: v_sqrt_bf16_e32 v5, null ; encoding: [0x7c,0xf4,0x0a,0x7e]
-v_sqrt_bf16 v5, -1
-// GFX1250: v_sqrt_bf16_e32 v5, -1 ; encoding: [0xc1,0xf4,0x0a,0x7e]
-
-v_sqrt_bf16 v5, 0.5
-// GFX1250: v_sqrt_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xf4,0x0a,0x7e]
-
v_sqrt_bf16 v5, src_scc
// GFX1250: v_sqrt_bf16_e32 v5, src_scc ; encoding: [0xfd,0xf4,0x0a,0x7e]
@@ -331,12 +313,6 @@ v_rsq_bf16 v5, exec_hi
v_rsq_bf16 v5, null
// GFX1250: v_rsq_bf16_e32 v5, null ; encoding: [0x7c,0xf6,0x0a,0x7e]
-v_rsq_bf16 v5, -1
-// GFX1250: v_rsq_bf16_e32 v5, -1 ; encoding: [0xc1,0xf6,0x0a,0x7e]
-
-v_rsq_bf16 v5, 0.5
-// GFX1250: v_rsq_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xf6,0x0a,0x7e]
-
v_rsq_bf16 v5, src_scc
// GFX1250: v_rsq_bf16_e32 v5, src_scc ; encoding: [0xfd,0xf6,0x0a,0x7e]
@@ -376,12 +352,6 @@ v_log_bf16 v5, exec_hi
v_log_bf16 v5, null
// GFX1250: v_log_bf16_e32 v5, null ; encoding: [0x7c,0xf8,0x0a,0x7e]
-v_log_bf16 v5, -1
-// GFX1250: v_log_bf16_e32 v5, -1 ; encoding: [0xc1,0xf8,0x0a,0x7e]
-
-v_log_bf16 v5, 0.5
-// GFX1250: v_log_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xf8,0x0a,0x7e]
-
v_log_bf16 v5, src_scc
// GFX1250: v_log_bf16_e32 v5, src_scc ; encoding: [0xfd,0xf8,0x0a,0x7e]
@@ -421,12 +391,6 @@ v_exp_bf16 v5, exec_hi
v_exp_bf16 v5, null
// GFX1250: v_exp_bf16_e32 v5, null ; encoding: [0x7c,0xfa,0x0a,0x7e]
-v_exp_bf16 v5, -1
-// GFX1250: v_exp_bf16_e32 v5, -1 ; encoding: [0xc1,0xfa,0x0a,0x7e]
-
-v_exp_bf16 v5, 0.5
-// GFX1250: v_exp_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xfa,0x0a,0x7e]
-
v_exp_bf16 v5, src_scc
// GFX1250: v_exp_bf16_e32 v5, src_scc ; encoding: [0xfd,0xfa,0x0a,0x7e]
@@ -466,12 +430,6 @@ v_sin_bf16 v5, exec_hi
v_sin_bf16 v5, null
// GFX1250: v_sin_bf16_e32 v5, null ; encoding: [0x7c,0xfc,0x0a,0x7e]
-v_sin_bf16 v5, -1
-// GFX1250: v_sin_bf16_e32 v5, -1 ; encoding: [0xc1,0xfc,0x0a,0x7e]
-
-v_sin_bf16 v5, 0.5
-// GFX1250: v_sin_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xfc,0x0a,0x7e]
-
v_sin_bf16 v5, src_scc
// GFX1250: v_sin_bf16_e32 v5, src_scc ; encoding: [0xfd,0xfc,0x0a,0x7e]
@@ -511,12 +469,6 @@ v_cos_bf16 v5, exec_hi
v_cos_bf16 v5, null
// GFX1250: v_cos_bf16_e32 v5, null ; encoding: [0x7c,0xfe,0x0a,0x7e]
-v_cos_bf16 v5, -1
-// GFX1250: v_cos_bf16_e32 v5, -1 ; encoding: [0xc1,0xfe,0x0a,0x7e]
-
-v_cos_bf16 v5, 0.5
-// GFX1250: v_cos_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xfe,0x0a,0x7e]
-
v_cos_bf16 v5, src_scc
// GFX1250: v_cos_bf16_e32 v5, src_scc ; encoding: [0xfd,0xfe,0x0a,0x7e]
@@ -556,12 +508,6 @@ v_cvt_f32_bf16 v5, exec_hi
v_cvt_f32_bf16 v5, null
// GFX1250: v_cvt_f32_bf16_e32 v5, null ; encoding: [0x7c,0xe4,0x0a,0x7e]
-v_cvt_f32_bf16 v5, -1
-// GFX1250: v_cvt_f32_bf16_e32 v5, -1 ; encoding: [0xc1,0xe4,0x0a,0x7e]
-
-v_cvt_f32_bf16 v5, 0.5
-// GFX1250: v_cvt_f32_bf16_e32 v5, 0.5 ; encoding: [0xf0,0xe4,0x0a,0x7e]
-
v_cvt_f32_bf16 v5, src_scc
// GFX1250: v_cvt_f32_bf16_e32 v5, src_scc ; encoding: [0xfd,0xe4,0x0a,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
index 09e4719c0c8cd..131432652055b 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
@@ -157,12 +157,6 @@ v_tanh_bf16 v5.l, exec_hi
v_tanh_bf16 v5.l, null
// GFX1250: v_tanh_bf16_e32 v5.l, null ; encoding: [0x7c,0x94,0x0a,0x7e]
-v_tanh_bf16 v5.l, -1
-// GFX1250: v_tanh_bf16_e32 v5.l, -1 ; encoding: [0xc1,0x94,0x0a,0x7e]
-
-v_tanh_bf16 v5.l, 0.5
-// GFX1250: v_tanh_bf16_e32 v5.l, 0.5 ; encoding: [0xf0,0x94,0x0a,0x7e]
-
v_tanh_bf16 v5.l, src_scc
// GFX1250: v_tanh_bf16_e32 v5.l, src_scc ; encoding: [0xfd,0x94,0x0a,0x7e]
@@ -250,12 +244,6 @@ v_rcp_bf16 v5.l, exec_hi
v_rcp_bf16 v5.l, null
// GFX1250: v_rcp_bf16_e32 v5.l, null ; encoding: [0x7c,0xf2,0x0a,0x7e]
-v_rcp_bf16 v5.l, -1
-// GFX1250: v_rcp_bf16_e32 v5.l, -1 ; encoding: [0xc1,0xf2,0x0a,0x7e]
-
-v_rcp_bf16 v5.l, 0.5
-// GFX1250: v_rcp_bf16_e32 v5.l, 0.5 ; encoding: [0xf0,0xf2,0x0a,0x7e]
-
v_rcp_bf16 v5.l, src_scc
// GFX1250: v_rcp_bf16_e32 v5.l, src_scc ; encoding: [0xfd,0xf2,0x0a,0x7e]
@@ -298,12 +286,6 @@ v_sqrt_bf16 v5.l, exec_hi
v_sqrt_bf16 v5.l, null
// GFX1250: v_sqrt_bf16_e32 v5.l, null ; encoding: [0x7c,0xf4,0x0a,0x7e]
-v_sqrt_bf16 v5.l, -1
-// GFX1250: v_sqrt_bf16_e32 v5.l, -1 ; encoding: [0xc1,0xf4,0x0a,0x7e]
-
-v_sqrt_bf16 v5.l, 0.5
-// GFX1250: v_sqrt_bf16_e32 v5.l, 0.5 ; encoding: [0xf0,0xf4,0x0a,0x7e]
-
v_sqrt_bf16 v5.l, src_scc
// GFX1250: v_sqrt_bf16_e32 v5.l, src_scc ; encoding: [0xfd,0xf4,0x0a,0x7e]
@@ -346,12 +328,6 @@ v_rsq_bf16 v5.l, exec_hi
v_rsq_bf16 v5.l, null
// GFX1250: v_rsq_bf16_e32 v5.l, null ; encoding: [0x7c,0xf6,0x0a,0x7e]
-v_rsq_bf16 v5.l, -1
-// GFX1250: v_rsq_bf16_e32 v5.l, -1 ; encoding: [0xc1,0xf6,0x0a,0x7e]
-
-v_rsq_bf16 v5.l, 0.5
-// GFX1250: v_rsq_bf16_e32 v5.l, 0.5 ; encoding: [0xf0,0xf6,0x0a,0x7e]
-
v_rsq_bf16 v5.l, src_scc
// GFX1250: v_rsq_bf16_e32 v5.l, src_scc ; encoding: [0xfd,0xf6,0x0a,0x7e]
@@ -394,12 +370,6 @@ v_log_bf16 v5.l, exec_hi
v_log_bf16 v5.l, null
// GFX1250: v_log_bf16_e32 v5.l, null ; encoding: [0x7c,0xf8,0x0a,0x7e]
-v_log_bf16 v5.l, -1
-// GFX1250: v_log_bf16_e32 v5.l, -1 ; encoding: [0xc1,0xf8,0x0a,0x7e]
-
-v_log_bf16 v5.l, 0.5
-// GFX1250: v_log_bf16_e32 v5.l, 0.5 ; encoding: [0xf0,0xf8,0x0a,0x7e]
-
v_log_bf16 v5.l, src_scc
// GFX1250: v_log_bf16_e32 v5.l, src_scc ; encoding: [0xfd,0xf8,0x0a,0x7e]
@@ -442,12 +412,6 @@ v_exp_bf16 v5.l, exec_hi
v_exp_bf16 v5.l, null
// GFX1250: v_exp_bf16_e32 v5.l, null ; encoding: [0x7c,0xfa,0x0a,0x7e]
-v_exp_bf16 v5.l, -1
-// GFX1250: v_exp_bf16_e32 v5.l, -1 ; encoding: [0xc1,0xfa,0x0a,0x7e]
-
-v_exp_bf16 v5.l, 0.5
-// GFX1250: v_exp_bf16_e32 v5.l, 0.5 ; encoding: [0xf0,0xfa,0x0a,0x7e]
-
v_exp_bf16 v5.l, src_scc
// GFX1250: v_exp_bf16_e32 v5.l, src_scc ; encoding: [0xfd,0xfa,0x0a,0x7e]
@@ -490,12 +454,6 @@ v_sin_bf16 v5.l, exec_hi
v_sin_bf16 v5.l, null
// GFX1250: v_sin_bf16_e32 v5.l, null ; encoding: [0x7c,0xfc,0x0a,0x7e]
-v_sin_bf16 v5.l, -1
-// GFX1250: v_sin_bf16_e32 v5.l, -1 ; encoding: [0xc1,0xfc,0x0a,0x7e]
-
-v_sin_bf16 v5.l, 0.5
-// GFX1250: v_sin_bf16_e32 v5.l, 0.5 ; encoding: [0xf0,0xfc,0x0a,0x7e]
-
v_sin_bf16 v5.l, src_scc
// GFX1250: v_sin_bf16_e32 v5.l, src_scc ; encoding: [0xfd,0xfc,0x0a,0x7e]
@@ -538,12 +496,6 @@ v_cos_bf16 v5.l, exec_hi
v_cos_bf16 v5.l, null
// GFX1250: v_cos_bf16_e32 v5.l, null ; encoding: [0x7c,0xfe,0x0a,0x7e]
-v_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223035
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