[llvm] [AMDGPU] Migrate AllowLDSDMA=true sites to isValu (PR #222992)
Akash Dutta via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 11 11:12:00 PDT 2026
https://github.com/akadutta updated https://github.com/llvm/llvm-project/pull/222992
>From ca22f1ad66c4526d186d8d3d02570452f3147b06 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 11:52:03 -0500
Subject: [PATCH 1/7] AMDGPU: Add isComputeVALU and isCoexecutableVALU helpers
to drop AllowLDSDMA
---
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 31 ++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index ea91f128f9392..1210c4f7c3f87 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -493,17 +493,40 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return SIInstrFlags::isSALU(get(Opcode));
}
- static bool isVALU(const MachineInstr &MI, bool AllowLDSDMA) {
- if (!AllowLDSDMA && isLDSDMA(MI))
- return false;
-
+ /// Return true if MI uses the VALU encoding/pipeline, including LDSDMA.
+ static bool isVALU(const MachineInstr &MI) {
return SIInstrFlags::isVALU(MI);
}
+ /// Return true if Opcode uses the VALU encoding/pipeline, including LDSDMA.
+ bool isVALU(uint32_t Opcode) const {
+ return SIInstrFlags::isVALU(get(Opcode));
+ }
+
+ /// Return true if MI is an ordinary compute VALU instruction. Excludes
+ /// LDSDMA, which is VALU-encoded but not compute/lane/exec semantics.
+ static bool isComputeVALU(const MachineInstr &MI) {
+ return isVALU(MI) && !isLDSDMA(MI);
+ }
+
+ bool isComputeVALU(uint32_t Opcode) const {
+ return isVALU(Opcode) && !isLDSDMA(Opcode);
+ }
+
+ /// Return true if MI may be a WMMA co-execution hazard victim.
+ static bool isCoexecutableVALU(const MachineInstr &MI) {
+ return isComputeVALU(MI) && !isWMMA(MI) && !isSWMMAC(MI);
+ }
+
+ bool isCoexecutableVALU(uint32_t Opcode) const {
+ return isComputeVALU(Opcode) && !isWMMA(Opcode) && !isSWMMAC(Opcode);
+ }
+
/// LDSDMA instructions act as both VALU and memory instructions, thus
/// we also tag them as VALU. However, in many places, we do not actually want
/// to include LDSDMA instructions in this query. By setting \p AllowLDSDMA to
/// false, this will return false for LDSDMA instructions.
+ /// This will be removed once call sites are migrated to the new API.
bool isVALU(uint32_t Opcode, bool AllowLDSDMA) const {
if (!AllowLDSDMA && isLDSDMA(Opcode))
return false;
>From 71688c9134a929b5009273eecb0ac5b2beec02b7 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 13:39:41 -0500
Subject: [PATCH 2/7] fix broken func def
---
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1210c4f7c3f87..ed6a4403fab78 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -527,11 +527,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// to include LDSDMA instructions in this query. By setting \p AllowLDSDMA to
/// false, this will return false for LDSDMA instructions.
/// This will be removed once call sites are migrated to the new API.
- bool isVALU(uint32_t Opcode, bool AllowLDSDMA) const {
- if (!AllowLDSDMA && isLDSDMA(Opcode))
- return false;
+ static bool isVALU(const MachineInstr &MI, bool AllowLDSDMA) {
+ return AllowLDSDMA ? isVALU(MI) : isComputeVALU(MI);
+ }
- return SIInstrFlags::isVALU(get(Opcode));
+ bool isVALU(uint32_t Opcode, bool AllowLDSDMA) const {
+ return AllowLDSDMA ? isVALU(Opcode) : isComputeVALU(Opcode);
}
static bool isImage(const MachineInstr &MI) {
>From 99ecca4932f31a94de45546feb595e79c8ec759a Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 15:55:45 -0500
Subject: [PATCH 3/7] Migrate isVALU(..., false) calls to isCompareVALU
---
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp | 4 ++--
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 11 +++--------
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 4 ++--
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 10 +++++-----
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 2 +-
11 files changed, 22 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
index 1f3905a0465e4..87e8d7bbd777c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
@@ -398,7 +398,7 @@ InstructionFlavor llvm::AMDGPU::classifyFlavor(const MachineInstr &MI,
if (SII.isTRANS(MI))
return InstructionFlavor::TRANS;
- if (SII.isVALU(MI, /*AllowLDSDMA=*/false))
+ if (SII.isComputeVALU(MI))
return InstructionFlavor::SingleCycleVALU;
if (SII.isSMRD(MI))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
index 7d39057300388..7b115389a207b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
@@ -22,7 +22,7 @@ LLVM_DUMP_METHOD void HWEvents::dump() const { dbgs() << *this << "\n"; }
static HWEvents getExpertSchedulingEventType(const MachineInstr &Inst,
const SIInstrInfo &TII) {
- if (TII.isVALU(Inst, /*AllowLDSDMA=*/false)) {
+ if (TII.isComputeVALU(Inst)) {
// Core/Side-, DP-, XDL- and TRANS-MACC VALU instructions complete
// out-of-order with respect to each other, so each of these classes
// has its own event.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
index 38ee16fd37e28..e0a6170c0a223 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
@@ -47,7 +47,7 @@ void HazardLatency::apply(ScheduleDAGInstrs *DAG) {
for (SUnit &SU : DAG->SUnits) {
const MachineInstr *MI = SU.getInstr();
- if (!SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/false))
+ if (!SIInstrInfo::isComputeVALU(*MI))
continue;
if (MI->getOpcode() == AMDGPU::V_READLANE_B32 ||
MI->getOpcode() == AMDGPU::V_READFIRSTLANE_B32)
@@ -58,7 +58,7 @@ void HazardLatency::apply(ScheduleDAGInstrs *DAG) {
// Boost latency on VALU writes to SGPRs used by VALUs.
// Reduce risk of premature VALU pipeline stall on associated reads.
MachineInstr *DestMI = SuccDep.getSUnit()->getInstr();
- if (!SIInstrInfo::isVALU(*DestMI, /*AllowLDSDMA=*/false))
+ if (!SIInstrInfo::isComputeVALU(*DestMI))
continue;
Register Reg = SuccDep.getReg();
if (!TRI.isSGPRReg(MRI, Reg))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 9ce0e4d8c7664..7fa0925c214e9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -2589,7 +2589,7 @@ bool SchedGroup::canAddMI(const MachineInstr &MI) const {
Result = !MI.mayLoadOrStore();
else if (((SGMask & SchedGroupMask::VALU) != SchedGroupMask::NONE) &&
- TII->isVALU(MI, /*AllowLDSDMA=*/false) && !TII->isMFMAorWMMA(MI) &&
+ TII->isComputeVALU(MI) && !TII->isMFMAorWMMA(MI) &&
!TII->isTRANS(MI)) {
// Some memory instructions may be marked as VALU (e.g. BUFFER_LOAD_*_LDS).
// For our purposes, these shall not be classified as VALU as this results
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
index 779d9b019971f..c9dc4d2e7dfc3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
@@ -155,7 +155,7 @@ bool AMDGPUSetWavePriority::run(MachineFunction &MF) {
MaxNumVALUInstsInMiddle =
std::max(MaxNumVALUInstsInMiddle, NumVALUInstsAtEnd);
NumVALUInstsAtEnd = 0;
- } else if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false)) {
+ } else if (SIInstrInfo::isComputeVALU(MI)) {
if (AtStart)
++MBBInfos[MBB].NumVALUInstsAtStart;
++NumVALUInstsAtEnd;
@@ -188,7 +188,7 @@ bool AMDGPUSetWavePriority::run(MachineFunction &MF) {
// Raise the priority at the beginning of the shader.
MachineBasicBlock::iterator I = Entry.begin(), E = Entry.end();
- while (I != E && !SIInstrInfo::isVALU(*I, /*AllowLDSDMA=*/false) &&
+ while (I != E && !SIInstrInfo::isComputeVALU(*I) &&
!I->isTerminator())
++I;
BuildSetprioMI(Entry, I, HighPriority);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
index d4bdaa245ff16..7aaae3a29e3aa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
@@ -273,7 +273,7 @@ class AMDGPUWaitSGPRHazards {
}
// Process only VALUs and SALUs
- bool IsVALU = SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/false);
+ bool IsVALU = SIInstrInfo::isComputeVALU(*MI);
bool IsSALU = SIInstrInfo::isSALU(*MI);
if (!IsVALU && !IsSALU)
continue;
@@ -510,7 +510,7 @@ class AMDGPUWaitSGPRHazards {
if (MI.isMetaInstruction())
continue;
- const bool IsVALU = SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false);
+ const bool IsVALU = SIInstrInfo::isComputeVALU(MI);
const bool IsSALU = SIInstrInfo::isSALU(MI);
if (!IsVALU && !IsSALU)
continue;
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 11e7e2f1edc97..17808f2bc243c 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1460,7 +1460,7 @@ int GCNHazardRecognizer::checkVALUHazardsHelper(
/// none exists.
static const MachineOperand *
getDstSelForwardingOperand(const MachineInstr &MI, const GCNSubtarget &ST) {
- if (!SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false))
+ if (!SIInstrInfo::isComputeVALU(MI))
return nullptr;
const SIInstrInfo *TII = ST.getInstrInfo();
@@ -2532,11 +2532,6 @@ bool GCNHazardRecognizer::fixWMMAHazards(MachineInstr *MI) {
return true;
}
-static bool isCoexecutableVALUInst(const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/false) &&
- !SIInstrInfo::isWMMA(MI) && !SIInstrInfo::isSWMMAC(MI);
-}
-
// Classify XDL WMMA instructions into co-execution hazard categories
// (Refer to SPG 4.6.12.1), mainly based on instruction latency.
//
@@ -2614,7 +2609,7 @@ int GCNHazardRecognizer::checkWMMACoexecutionHazards(MachineInstr *MI) const {
return 0;
const SIInstrInfo *TII = ST.getInstrInfo();
- if (!TII->isXDLWMMA(*MI) && !isCoexecutableVALUInst(*MI))
+ if (!TII->isXDLWMMA(*MI) && !SIInstrInfo::isCoexecutableVALU(*MI))
return 0;
// WaitStates here is the number of V_NOPs or unrelated VALU instructions must
@@ -2724,7 +2719,7 @@ bool GCNHazardRecognizer::isCoexecutionHazardFor(const MachineInstr &I,
// Dispatch based on MI type
if (TII.isXDLWMMA(MI))
return hasWMMAToWMMARegOverlap(I, MI);
- if (isCoexecutableVALUInst(MI))
+ if (SIInstrInfo::isCoexecutableVALU(MI))
return hasWMMAToVALURegOverlap(I, MI);
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 33fb3c7ca37a0..d2873aadb2902 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1466,7 +1466,7 @@ MCPhysReg WaitcntBrackets::determineVGPR16Dependency(const MachineInstr &MI,
if (!Wait.hasWait())
return Reg;
- if (Context->TII.isVALU(MI, /*AllowLDSDMA=*/false))
+ if (Context->TII.isComputeVALU(MI))
return Reg32;
// If hi/lo16 mixed events
@@ -2592,7 +2592,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
// waits on VA_VDST if the instruction it would precede is not a VALU
// instruction, since hardware handles VALU->VGPR->VALU hazards in
// expert scheduling mode.
- if (TII.isVALU(MI, /*AllowLDSDMA=*/false)) {
+ if (TII.isComputeVALU(MI)) {
Wait.set(AMDGPU::VA_VDST_RD, ~0u);
Wait.set(AMDGPU::VA_VDST_WR, ~0u);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d69be52d9241b..d496d3e88345b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2953,7 +2953,7 @@ bool SIInstrInfo::isLegalToSwap(const MachineInstr &MI, unsigned OpIdx0,
// It may move literal to position other than src0, this is not allowed
// pre-gfx10 However, most test cases need literals in Src0 for VOP
// FIXME: After gfx9, literal can be in place other than Src0
- if (isVALU(MI, /*AllowLDSDMA=*/false)) {
+ if (isComputeVALU(MI)) {
if ((int)OpIdx0 == Src0Idx && !MO0.isReg() &&
!isInlineConstant(MO0, OpInfo1))
return false;
@@ -5729,7 +5729,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
// Verify VOP*. Ignore multiple sgpr operands on writelane.
- if (isVALU(MI, /*AllowLDSDMA=*/false) &&
+ if (isComputeVALU(MI) &&
Desc.getOpcode() != AMDGPU::V_WRITELANE_B32) {
unsigned ConstantBusCount = 0;
bool UsesLiteral = false;
@@ -6738,7 +6738,7 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
const bool IsInlineConst = !MO->isReg() && isInlineConstant(*MO, OpInfo);
- if (isVALU(MI, /*AllowLDSDMA=*/false) && !IsInlineConst &&
+ if (isComputeVALU(MI) && !IsInlineConst &&
usesConstantBus(MRI, *MO, OpInfo)) {
const MachineOperand *UsedLiteral = nullptr;
@@ -6854,7 +6854,7 @@ bool SIInstrInfo::isNeverCoissue(MachineInstr &MI) const {
if (!IsGFX950Only && !IsGFX940Only)
return false;
- if (!isVALU(MI, /*AllowLDSDMA=*/false))
+ if (!isComputeVALU(MI))
return false;
// V_COS, V_EXP, V_RCP, etc.
@@ -10274,7 +10274,7 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
// Instructions may have a 32-bit literal encoded after them. Check
// operands that could ever be literals.
- if (isVALU(MI, /*AllowLDSDMA=*/false) || isSALU(MI)) {
+ if (isComputeVALU(MI) || isSALU(MI)) {
if (isDPP(MI))
return DescSize;
bool HasLiteral = false;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index ed6a4403fab78..a6e836d3e58e6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -909,13 +909,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isVGPRSpill(const MachineInstr &MI) {
return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
- (isSpill(MI) && isVALU(MI, /*AllowLDSDMA=*/false));
+ (isSpill(MI) && isComputeVALU(MI));
}
bool isVGPRSpill(uint32_t Opcode) const {
return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
- (isSpill(Opcode) && isVALU(Opcode, /*AllowLDSDMA=*/false));
+ (isSpill(Opcode) && isComputeVALU(Opcode));
}
static bool isSGPRSpill(const MachineInstr &MI) {
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index aab3e63f3e9d0..31a531aab203b 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -379,7 +379,7 @@ void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {
if (MI.getOperand(1).isReg()) {
if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {
SkipAnding = Def->getParent() == MI.getParent() &&
- SIInstrInfo::isVALU(*Def, /*AllowLDSDMA=*/false);
+ SIInstrInfo::isComputeVALU(*Def);
}
}
>From 5b982e1cff33bb3b23cf7b90d57d891351275936 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Thu, 10 Sep 2026 16:07:34 -0500
Subject: [PATCH 4/7] code format
---
llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp | 3 +--
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
index c9dc4d2e7dfc3..f39dacfa01483 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
@@ -188,8 +188,7 @@ bool AMDGPUSetWavePriority::run(MachineFunction &MF) {
// Raise the priority at the beginning of the shader.
MachineBasicBlock::iterator I = Entry.begin(), E = Entry.end();
- while (I != E && !SIInstrInfo::isComputeVALU(*I) &&
- !I->isTerminator())
+ while (I != E && !SIInstrInfo::isComputeVALU(*I) && !I->isTerminator())
++I;
BuildSetprioMI(Entry, I, HighPriority);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d496d3e88345b..2ffa73b622ca8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5729,8 +5729,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
// Verify VOP*. Ignore multiple sgpr operands on writelane.
- if (isComputeVALU(MI) &&
- Desc.getOpcode() != AMDGPU::V_WRITELANE_B32) {
+ if (isComputeVALU(MI) && Desc.getOpcode() != AMDGPU::V_WRITELANE_B32) {
unsigned ConstantBusCount = 0;
bool UsesLiteral = false;
const MachineOperand *LiteralVal = nullptr;
>From 345781c75e2af7d2c29bf7ee8480c2a586e93796 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Fri, 11 Sep 2026 12:11:07 -0500
Subject: [PATCH 5/7] migrate AllowLDSDMA=true sites
---
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 2 +-
.../lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 86 +++++++++----------
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +-
5 files changed, 51 insertions(+), 51 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 7fa0925c214e9..7b629cc57317f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -2584,7 +2584,7 @@ bool SchedGroup::canAddMI(const MachineInstr &MI) const {
}
else if (((SGMask & SchedGroupMask::ALU) != SchedGroupMask::NONE) &&
- (TII->isVALU(MI, /*AllowLDSDMA=*/true) || TII->isMFMAorWMMA(MI) ||
+ (TII->isVALU(MI) || TII->isMFMAorWMMA(MI) ||
TII->isSALU(MI) || TII->isTRANS(MI)))
Result = !MI.mayLoadOrStore();
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 17808f2bc243c..a687de678f3a5 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -280,7 +280,7 @@ void GCNHazardRecognizer::updateMultiCycleVALUState(const MachineInstr &MI) {
if (!hasCoExecWindowModel())
return;
// Multi-cycle VALU (CVT, etc.) blocks subsequent VALU for repeat rate cycles.
- if (!SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true))
+ if (!SIInstrInfo::isVALU(MI))
return;
// Skip WMMA, MFMA, and TRANS - they have their own tracking.
@@ -313,7 +313,7 @@ unsigned GCNHazardRecognizer::checkTRANSHazard(const MachineInstr &MI) const {
if (SIInstrInfo::isTRANS(MI))
return CyclesUntilTRANS;
- if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) &&
+ if (SIInstrInfo::isVALU(MI) &&
!SIInstrInfo::isWMMA(MI) && !SIInstrInfo::isSWMMAC(MI) &&
TII.getRepeatRate(MI) > 1)
return CyclesUntilTRANS;
@@ -329,7 +329,7 @@ GCNHazardRecognizer::checkMultiCycleVALUHazard(const MachineInstr &MI) const {
// Multi-cycle VALU blocks anything on the VALU pipe - VALU, WMMA, SWMMAC,
// and TRANS - for RepeatRate-1 cycles. Only off-pipe instructions (MEM,
// SALU, control) can fill the shadow.
- if (!SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) &&
+ if (!SIInstrInfo::isVALU(MI) &&
!SIInstrInfo::isWMMA(MI) && !SIInstrInfo::isSWMMAC(MI) &&
!SIInstrInfo::isTRANS(MI))
return 0;
@@ -389,7 +389,7 @@ GCNHazardRecognizer::checkMultiShadowHazard(const MachineInstr &MI) const {
if (!CyclesUntilTRANS)
return 0;
- if (!SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) ||
+ if (!SIInstrInfo::isVALU(MI) ||
SIInstrInfo::isLDSDMA(MI))
return 0;
@@ -599,7 +599,7 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0)
return HazardType;
- if (SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true) &&
+ if (SIInstrInfo::isVALU(*MI) &&
checkVALUHazards(MI) > 0)
return HazardType;
@@ -612,7 +612,7 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
if (isRWLane(MI->getOpcode()) && checkRWLaneHazards(MI) > 0)
return HazardType;
- if ((SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true) ||
+ if ((SIInstrInfo::isVALU(*MI) ||
SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI) ||
SIInstrInfo::isEXP(*MI)) &&
checkMAIVALUHazards(MI) > 0)
@@ -755,7 +755,7 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) const {
if (SIInstrInfo::isVMEM(*MI))
WaitStates = std::max(WaitStates, checkVMEMHazards(MI));
- if (SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true))
+ if (SIInstrInfo::isVALU(*MI))
WaitStates = std::max(WaitStates, checkVALUHazards(MI));
if (SIInstrInfo::isDPP(*MI))
@@ -767,7 +767,7 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) const {
if (isRWLane(MI->getOpcode()))
WaitStates = std::max(WaitStates, checkRWLaneHazards(MI));
- if ((SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true) ||
+ if ((SIInstrInfo::isVALU(*MI) ||
SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI) ||
SIInstrInfo::isEXP(*MI)) &&
checkMAIVALUHazards(MI) > 0)
@@ -842,7 +842,7 @@ void GCNHazardRecognizer::AdvanceCycle() {
EmittedInstrs.push_front(CurrCycleInstr);
bool IsVALUOrWMMA =
- SIInstrInfo::isVALU(*CurrCycleInstr, /*AllowLDSDMA=*/true) ||
+ SIInstrInfo::isVALU(*CurrCycleInstr) ||
SIInstrInfo::isWMMA(*CurrCycleInstr) ||
SIInstrInfo::isSWMMAC(*CurrCycleInstr);
if (IsVALUOrWMMA) {
@@ -1060,7 +1060,7 @@ int GCNHazardRecognizer::getWaitStatesSinceVALU(IsHazardFn IsHazard,
int Limit) const {
if (isHazardRecognizerMode()) {
auto GetVALUWaitStates = [](const MachineInstr &MI) -> unsigned {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) ? 1 : 0;
+ return SIInstrInfo::isVALU(MI) ? 1 : 0;
};
return getWaitStatesSince(IsHazard, Limit, GetVALUWaitStates);
}
@@ -1198,7 +1198,7 @@ int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) const {
// SGPR was written by a VALU instruction.
int SmrdSgprWaitStates = 4;
auto IsHazardDefFn = [this](const MachineInstr &MI) {
- return TII.isVALU(MI, /*AllowLDSDMA=*/true);
+ return TII.isVALU(MI);
};
auto IsBufferHazardDefFn = [this](const MachineInstr &MI) {
return TII.isSALU(MI);
@@ -1243,7 +1243,7 @@ int GCNHazardRecognizer::checkVMEMHazards(MachineInstr *VMEM) const {
// SGPR was written by a VALU Instruction.
const int VmemSgprWaitStates = 5;
auto IsHazardDefFn = [this](const MachineInstr &MI) {
- return TII.isVALU(MI, /*AllowLDSDMA=*/true);
+ return TII.isVALU(MI);
};
for (const MachineOperand &Use : VMEM->uses()) {
if (!Use.isReg() || TRI.isVectorRegister(MF.getRegInfo(), Use.getReg()))
@@ -1266,7 +1266,7 @@ int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) const {
int DppExecWaitStates = 5;
int WaitStatesNeeded = 0;
auto IsHazardDefFn = [TII](const MachineInstr &MI) {
- return TII->isVALU(MI, /*AllowLDSDMA=*/true);
+ return TII->isVALU(MI);
};
for (const MachineOperand &Use : DPP->uses()) {
@@ -1295,7 +1295,7 @@ int GCNHazardRecognizer::checkDivFMasHazards(MachineInstr *DivFMas) const {
// instruction.
const int DivFMasWaitStates = 4;
auto IsHazardDefFn = [TII](const MachineInstr &MI) {
- return TII->isVALU(MI, /*AllowLDSDMA=*/true);
+ return TII->isVALU(MI);
};
int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn,
DivFMasWaitStates);
@@ -1590,7 +1590,7 @@ int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
Register UseReg;
auto IsVALUDefSGPRFn = [&UseReg, TRI](const MachineInstr &MI) {
- if (!SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true))
+ if (!SIInstrInfo::isVALU(MI))
return false;
return MI.modifiesRegister(UseReg, TRI);
};
@@ -1729,7 +1729,7 @@ int GCNHazardRecognizer::checkRWLaneHazards(MachineInstr *RWLane) const {
Register LaneSelectReg = LaneSelectOp->getReg();
auto IsHazardFn = [TII](const MachineInstr &MI) {
- return TII->isVALU(MI, /*AllowLDSDMA=*/true);
+ return TII->isVALU(MI);
};
const int RWLaneWaitStates = 4;
@@ -1818,7 +1818,7 @@ bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) {
auto IsExpiredFn = [](const MachineInstr &MI, int) {
unsigned Opc = MI.getOpcode();
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) &&
+ return SIInstrInfo::isVALU(MI) &&
Opc != AMDGPU::V_NOP_e32 && Opc != AMDGPU::V_NOP_e64 &&
Opc != AMDGPU::V_NOP_sdwa;
};
@@ -1869,7 +1869,7 @@ bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) {
};
auto IsExpiredFn = [](const MachineInstr &MI, int) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) ||
+ return SIInstrInfo::isVALU(MI) ||
(MI.getOpcode() == AMDGPU::S_WAITCNT &&
!MI.getOperand(0).getImm()) ||
(MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR &&
@@ -1892,7 +1892,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
return false;
assert(!ST.hasExtendedWaitCounts());
- if (!SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true))
+ if (!SIInstrInfo::isVALU(*MI))
return false;
AMDGPU::OpName SDSTName;
@@ -1982,7 +1982,7 @@ bool GCNHazardRecognizer::fixVcmpxExecWARHazard(MachineInstr *MI) {
return false;
assert(!ST.hasExtendedWaitCounts());
- if (!SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true))
+ if (!SIInstrInfo::isVALU(*MI))
return false;
const SIRegisterInfo *TRI = ST.getRegisterInfo();
@@ -1990,14 +1990,14 @@ bool GCNHazardRecognizer::fixVcmpxExecWARHazard(MachineInstr *MI) {
return false;
auto IsHazardFn = [TRI](const MachineInstr &I) {
- if (SIInstrInfo::isVALU(I, /*AllowLDSDMA=*/true))
+ if (SIInstrInfo::isVALU(I))
return false;
return I.readsRegister(AMDGPU::EXEC, TRI);
};
const SIInstrInfo *TII = ST.getInstrInfo();
auto IsExpiredFn = [TII, TRI](const MachineInstr &MI, int) {
- if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true)) {
+ if (SIInstrInfo::isVALU(MI)) {
if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst))
return true;
for (auto MO : MI.implicit_operands())
@@ -2113,7 +2113,7 @@ bool GCNHazardRecognizer::fixLdsDirectVALUHazard(MachineInstr *MI) {
bool VisitedTrans = false;
auto IsHazardFn = [this, VDSTReg, &VisitedTrans](const MachineInstr &I) {
- if (!SIInstrInfo::isVALU(I, /*AllowLDSDMA=*/true))
+ if (!SIInstrInfo::isVALU(I))
return false;
VisitedTrans = VisitedTrans || SIInstrInfo::isTRANS(I);
// Cover both WAR and WAW
@@ -2127,7 +2127,7 @@ bool GCNHazardRecognizer::fixLdsDirectVALUHazard(MachineInstr *MI) {
SIInstrInfo::isEXP(I);
};
auto GetWaitStatesFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) ? 1 : 0;
+ return SIInstrInfo::isVALU(MI) ? 1 : 0;
};
DenseSet<const MachineBasicBlock *> Visited;
@@ -2163,7 +2163,7 @@ bool GCNHazardRecognizer::fixLdsDirectVMEMHazard(MachineInstr *MI) {
// TODO: On GFX12 the hazard should expire on S_WAIT_LOADCNT/SAMPLECNT/BVHCNT
// according to the type of VMEM instruction.
auto IsExpiredFn = [this, LdsdirCanWait](const MachineInstr &I, int) {
- return SIInstrInfo::isVALU(I, /*AllowLDSDMA=*/true) ||
+ return SIInstrInfo::isVALU(I) ||
SIInstrInfo::isEXP(I) ||
(I.getOpcode() == AMDGPU::S_WAITCNT && !I.getOperand(0).getImm()) ||
(I.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR &&
@@ -2192,7 +2192,7 @@ bool GCNHazardRecognizer::fixVALUPartialForwardingHazard(MachineInstr *MI) {
return false;
assert(!ST.hasExtendedWaitCounts());
- if (!ST.isWave64() || !SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true))
+ if (!ST.isWave64() || !SIInstrInfo::isVALU(*MI))
return false;
SmallSetVector<Register, 4> SrcVGPRs;
@@ -2260,7 +2260,7 @@ bool GCNHazardRecognizer::fixVALUPartialForwardingHazard(MachineInstr *MI) {
// Track registers writes
bool Changed = false;
- if (SIInstrInfo::isVALU(I, /*AllowLDSDMA=*/true)) {
+ if (SIInstrInfo::isVALU(I)) {
for (Register Src : SrcVGPRs) {
if (!State.DefPos.count(Src) && I.modifiesRegister(Src, &TRI)) {
State.DefPos[Src] = State.VALUs;
@@ -2331,7 +2331,7 @@ bool GCNHazardRecognizer::fixVALUPartialForwardingHazard(MachineInstr *MI) {
return HazardFound;
};
auto UpdateStateFn = [](StateType &State, const MachineInstr &MI) {
- if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true))
+ if (SIInstrInfo::isVALU(MI))
State.VALUs += 1;
};
@@ -2351,7 +2351,7 @@ bool GCNHazardRecognizer::fixVALUTransUseHazard(MachineInstr *MI) {
return false;
assert(!ST.hasExtendedWaitCounts());
- if (!SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true))
+ if (!SIInstrInfo::isVALU(*MI))
return false;
SmallSet<Register, 4> SrcVGPRs;
@@ -2413,7 +2413,7 @@ bool GCNHazardRecognizer::fixVALUTransUseHazard(MachineInstr *MI) {
return NoHazardFound;
};
auto UpdateStateFn = [](StateType &State, const MachineInstr &MI) {
- if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true))
+ if (SIInstrInfo::isVALU(MI))
State.VALUs += 1;
if (SIInstrInfo::isTRANS(MI))
State.TRANS += 1;
@@ -2434,7 +2434,7 @@ bool GCNHazardRecognizer::fixVALUTransUseHazard(MachineInstr *MI) {
bool GCNHazardRecognizer::fixVALUTransCoexecutionHazards(MachineInstr *MI) {
if (!ST.hasTransCoexecutionHazard() || // Coexecution disabled.
- !SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true) ||
+ !SIInstrInfo::isVALU(*MI) ||
SIInstrInfo::isTRANS(*MI))
return false;
@@ -2467,7 +2467,7 @@ bool GCNHazardRecognizer::fixVALUTransCoexecutionHazards(MachineInstr *MI) {
};
auto IsExpiredFn = [](const MachineInstr &I, int) {
- return SIInstrInfo::isVALU(I, /*AllowLDSDMA=*/true);
+ return SIInstrInfo::isVALU(I);
};
const int HasVALU = std::numeric_limits<int>::max();
@@ -2520,7 +2520,7 @@ bool GCNHazardRecognizer::fixWMMAHazards(MachineInstr *MI) {
};
auto IsExpiredFn = [](const MachineInstr &I, int) {
- return SIInstrInfo::isVALU(I, /*AllowLDSDMA=*/true);
+ return SIInstrInfo::isVALU(I);
};
if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) ==
@@ -2956,7 +2956,7 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(
};
auto IsExpiredFn = [](const MachineInstr &MI, int WaitStates) {
- if (WaitStates >= 3 || SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true))
+ if (WaitStates >= 3 || SIInstrInfo::isVALU(MI))
return true;
return SIInstrInfo::isWaitcnt(MI.getOpcode());
@@ -3007,7 +3007,7 @@ int GCNHazardRecognizer::checkMAIHazards908(MachineInstr *MI) const {
unsigned Opc = MI->getOpcode();
auto IsVALUFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) || MI.isInlineAsm();
+ return SIInstrInfo::isVALU(MI) || MI.isInlineAsm();
};
if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write
@@ -3221,12 +3221,12 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) const {
unsigned Opc = MI->getOpcode();
auto IsLegacyVALUFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) &&
+ return SIInstrInfo::isVALU(MI) &&
!SIInstrInfo::isMFMA(MI);
};
auto IsLegacyVALUNotDotFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) &&
+ return SIInstrInfo::isVALU(MI) &&
!SIInstrInfo::isMFMA(MI) && !SIInstrInfo::isDOT(MI);
};
@@ -3455,7 +3455,7 @@ int GCNHazardRecognizer::checkMAILdStHazards(MachineInstr *MI) const {
MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64)
return false;
auto IsVALUFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true) &&
+ return SIInstrInfo::isVALU(MI) &&
!SIInstrInfo::isMAI(MI);
};
return getWaitStatesSinceDef(Reg, IsVALUFn, 2 /*MaxWaitStates*/) <
@@ -3481,7 +3481,7 @@ int GCNHazardRecognizer::checkPermlaneHazards(MachineInstr *MI) const {
};
auto IsVALUFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true);
+ return SIInstrInfo::isVALU(MI);
};
const int VCmpXWritesExecWaitStates = 4;
@@ -3564,7 +3564,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) const {
bool IsMem = SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI);
bool IsMemOrExport = IsMem || SIInstrInfo::isEXP(*MI);
- bool IsVALU = SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true);
+ bool IsVALU = SIInstrInfo::isVALU(*MI);
const MachineInstr *MFMA = nullptr;
unsigned Reg;
@@ -3593,7 +3593,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) const {
// Only hazard if register is defined by a VALU and a DGEMM is found after
// after the def.
- if (!TII.isVALU(MI, /*AllowLDSDMA=*/true) || !DGEMMAfterVALUWrite)
+ if (!TII.isVALU(MI) || !DGEMMAfterVALUWrite)
return false;
return true;
@@ -3907,7 +3907,7 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
return false;
const bool IsSALU = SIInstrInfo::isSALU(*MI);
- const bool IsVALU = SIInstrInfo::isVALU(*MI, /*AllowLDSDMA=*/true);
+ const bool IsVALU = SIInstrInfo::isVALU(*MI);
if (!IsSALU && !IsVALU)
return false;
@@ -4264,7 +4264,7 @@ bool GCNHazardRecognizer::fixScratchBaseForwardingHazard(MachineInstr *MI) {
// This literally abuses the idea of waitstates. Instead of waitstates it
// returns 1 for SGPR written and 0 otherwise.
auto IsSGPRDef = [TII, TRI, &MRI](const MachineInstr &MI) -> unsigned {
- if (!TII->isSALU(MI) && !TII->isVALU(MI, /*AllowLDSDMA=*/true))
+ if (!TII->isSALU(MI) && !TII->isVALU(MI))
return 0;
for (const MachineOperand &MO : MI.all_defs()) {
if (TRI->isSGPRReg(MRI, MO.getReg()))
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index b0c896b1a122a..bbf0b91ba108c 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -1016,7 +1016,7 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
} else if (Inst->getNumExplicitDefs() != 0) {
Register Reg = Inst->getOperand(0).getReg();
if (Reg.isVirtual() && TRI->isSGPRReg(*MRI, Reg) &&
- !TII->isVALU(*Inst, /*AllowLDSDMA=*/true)) {
+ !TII->isVALU(*Inst)) {
for (auto &U : MRI->use_instructions(Reg))
Users.push_back(&U);
}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a55208053099c..5c1b4ed169248 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5881,7 +5881,7 @@ getDPPOpcForWaveReduction(unsigned Opc, const GCNSubtarget &ST) {
llvm_unreachable("unhandled lane op");
}
unsigned ClampOpc = Opc;
- if (!ST.getInstrInfo()->isVALU(Opc, /*AllowLDSDMA=*/true)) {
+ if (!ST.getInstrInfo()->isVALU(Opc)) {
if (Opc == AMDGPU::S_SUB_I32)
ClampOpc = AMDGPU::S_ADD_I32;
if (Opc == AMDGPU::S_ADD_U64_PSEUDO || Opc == AMDGPU::S_SUB_U64_PSEUDO)
@@ -6269,7 +6269,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
LaneValueReg)
.addReg(SrcReg)
.addReg(FF1Reg);
- if (ST.getInstrInfo()->isVALU(Opc, /*AllowLDSDMA=*/true)) {
+ if (ST.getInstrInfo()->isVALU(Opc)) {
// Get the Lane Value in VGPR to avoid the Constant Bus Restriction
Register LaneValVgpr = MRI.createVirtualRegister(SrcRegClass);
Register VgprResultReg = MRI.createVirtualRegister(SrcRegClass);
@@ -6291,7 +6291,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
OpInstr.addImm(0); // opsel
if (hasOMod)
OpInstr.addImm(0); // omod
- if (ST.getInstrInfo()->isVALU(Opc, /*AllowLDSDMA=*/true)) {
+ if (ST.getInstrInfo()->isVALU(Opc)) {
BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
DstReg)
.addReg(OpDstReg);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 2ffa73b622ca8..677633a599edd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -297,7 +297,7 @@ bool SIInstrInfo::isSrc1DPPRevOpcode(const GCNSubtarget &ST, uint32_t Opcode) {
// Returns true if the result of a VALU instruction depends on exec.
bool SIInstrInfo::resultDependsOnExec(const MachineInstr &MI) const {
- assert(isVALU(MI, /*AllowLDSDMA=*/true));
+ assert(isVALU(MI));
// If it is convergent it depends on EXEC.
if (MI.isConvergent())
@@ -321,7 +321,7 @@ bool SIInstrInfo::isIgnorableUse(const MachineInstr &MI, unsigned OpIdx) const {
const MachineOperand &MO = MI.getOperand(OpIdx);
// Any implicit use of exec by VALU is not a real register read.
return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
- isVALU(MI, /*AllowLDSDMA=*/true) && !resultDependsOnExec(MI);
+ isVALU(MI) && !resultDependsOnExec(MI);
}
bool SIInstrInfo::isSafeToSink(MachineInstr &MI,
@@ -5314,7 +5314,7 @@ static Register findImplicitSGPRRead(const MachineInstr &MI) {
}
static bool shouldReadExec(const MachineInstr &MI) {
- if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true)) {
+ if (SIInstrInfo::isVALU(MI)) {
switch (MI.getOpcode()) {
case AMDGPU::V_READLANE_B32:
case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
>From 52ece8297ae2f2c237c0cec7abc23de53ece57d9 Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Fri, 11 Sep 2026 12:33:31 -0500
Subject: [PATCH 6/7] fix code format
---
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 4 +-
.../lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 104 +++++++++---------
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 3 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +-
4 files changed, 54 insertions(+), 61 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 7b629cc57317f..2ee22b686e3ec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -2584,8 +2584,8 @@ bool SchedGroup::canAddMI(const MachineInstr &MI) const {
}
else if (((SGMask & SchedGroupMask::ALU) != SchedGroupMask::NONE) &&
- (TII->isVALU(MI) || TII->isMFMAorWMMA(MI) ||
- TII->isSALU(MI) || TII->isTRANS(MI)))
+ (TII->isVALU(MI) || TII->isMFMAorWMMA(MI) || TII->isSALU(MI) ||
+ TII->isTRANS(MI)))
Result = !MI.mayLoadOrStore();
else if (((SGMask & SchedGroupMask::VALU) != SchedGroupMask::NONE) &&
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index a687de678f3a5..19e80d1c16586 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -313,9 +313,8 @@ unsigned GCNHazardRecognizer::checkTRANSHazard(const MachineInstr &MI) const {
if (SIInstrInfo::isTRANS(MI))
return CyclesUntilTRANS;
- if (SIInstrInfo::isVALU(MI) &&
- !SIInstrInfo::isWMMA(MI) && !SIInstrInfo::isSWMMAC(MI) &&
- TII.getRepeatRate(MI) > 1)
+ if (SIInstrInfo::isVALU(MI) && !SIInstrInfo::isWMMA(MI) &&
+ !SIInstrInfo::isSWMMAC(MI) && TII.getRepeatRate(MI) > 1)
return CyclesUntilTRANS;
return 0;
@@ -329,9 +328,8 @@ GCNHazardRecognizer::checkMultiCycleVALUHazard(const MachineInstr &MI) const {
// Multi-cycle VALU blocks anything on the VALU pipe - VALU, WMMA, SWMMAC,
// and TRANS - for RepeatRate-1 cycles. Only off-pipe instructions (MEM,
// SALU, control) can fill the shadow.
- if (!SIInstrInfo::isVALU(MI) &&
- !SIInstrInfo::isWMMA(MI) && !SIInstrInfo::isSWMMAC(MI) &&
- !SIInstrInfo::isTRANS(MI))
+ if (!SIInstrInfo::isVALU(MI) && !SIInstrInfo::isWMMA(MI) &&
+ !SIInstrInfo::isSWMMAC(MI) && !SIInstrInfo::isTRANS(MI))
return 0;
return CyclesUntilVALU;
@@ -389,8 +387,7 @@ GCNHazardRecognizer::checkMultiShadowHazard(const MachineInstr &MI) const {
if (!CyclesUntilTRANS)
return 0;
- if (!SIInstrInfo::isVALU(MI) ||
- SIInstrInfo::isLDSDMA(MI))
+ if (!SIInstrInfo::isVALU(MI) || SIInstrInfo::isLDSDMA(MI))
return 0;
// We have a VALU instruction that is under both a TRANS and WMMA shadow.
@@ -599,8 +596,7 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0)
return HazardType;
- if (SIInstrInfo::isVALU(*MI) &&
- checkVALUHazards(MI) > 0)
+ if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0)
return HazardType;
if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0)
@@ -612,9 +608,8 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
if (isRWLane(MI->getOpcode()) && checkRWLaneHazards(MI) > 0)
return HazardType;
- if ((SIInstrInfo::isVALU(*MI) ||
- SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI) ||
- SIInstrInfo::isEXP(*MI)) &&
+ if ((SIInstrInfo::isVALU(*MI) || SIInstrInfo::isVMEM(*MI) ||
+ SIInstrInfo::isDS(*MI) || SIInstrInfo::isEXP(*MI)) &&
checkMAIVALUHazards(MI) > 0)
return HazardType;
@@ -767,9 +762,8 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) const {
if (isRWLane(MI->getOpcode()))
WaitStates = std::max(WaitStates, checkRWLaneHazards(MI));
- if ((SIInstrInfo::isVALU(*MI) ||
- SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI) ||
- SIInstrInfo::isEXP(*MI)) &&
+ if ((SIInstrInfo::isVALU(*MI) || SIInstrInfo::isVMEM(*MI) ||
+ SIInstrInfo::isDS(*MI) || SIInstrInfo::isEXP(*MI)) &&
checkMAIVALUHazards(MI) > 0)
WaitStates = std::max(WaitStates, checkMAIVALUHazards(MI));
@@ -1210,8 +1204,8 @@ int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) const {
if (!Use.isReg())
continue;
int WaitStatesNeededForUse =
- SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn,
- SmrdSgprWaitStates);
+ SmrdSgprWaitStates -
+ getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn, SmrdSgprWaitStates);
WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
// This fixes what appears to be undocumented hardware behavior in SI where
@@ -1223,9 +1217,9 @@ int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) const {
// probably never encountered in the closed-source land.
if (IsBufferSMRD) {
int WaitStatesNeededForUse =
- SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(),
- IsBufferHazardDefFn,
- SmrdSgprWaitStates);
+ SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(),
+ IsBufferHazardDefFn,
+ SmrdSgprWaitStates);
WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
}
}
@@ -1250,8 +1244,8 @@ int GCNHazardRecognizer::checkVMEMHazards(MachineInstr *VMEM) const {
continue;
int WaitStatesNeededForUse =
- VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn,
- VmemSgprWaitStates);
+ VmemSgprWaitStates -
+ getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn, VmemSgprWaitStates);
WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
}
return WaitStatesNeeded;
@@ -1297,8 +1291,8 @@ int GCNHazardRecognizer::checkDivFMasHazards(MachineInstr *DivFMas) const {
auto IsHazardDefFn = [TII](const MachineInstr &MI) {
return TII->isVALU(MI);
};
- int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn,
- DivFMasWaitStates);
+ int WaitStatesNeeded =
+ getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn, DivFMasWaitStates);
return DivFMasWaitStates - WaitStatesNeeded;
}
@@ -1649,7 +1643,8 @@ int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (const MachineOperand &Def : VALU->defs()) {
- WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI));
+ WaitStatesNeeded =
+ std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI));
}
return WaitStatesNeeded;
@@ -1728,13 +1723,11 @@ int GCNHazardRecognizer::checkRWLaneHazards(MachineInstr *RWLane) const {
return 0;
Register LaneSelectReg = LaneSelectOp->getReg();
- auto IsHazardFn = [TII](const MachineInstr &MI) {
- return TII->isVALU(MI);
- };
+ auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVALU(MI); };
const int RWLaneWaitStates = 4;
- int WaitStatesSince = getWaitStatesSinceDef(LaneSelectReg, IsHazardFn,
- RWLaneWaitStates);
+ int WaitStatesSince =
+ getWaitStatesSinceDef(LaneSelectReg, IsHazardFn, RWLaneWaitStates);
return RWLaneWaitStates - WaitStatesSince;
}
@@ -1818,9 +1811,8 @@ bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) {
auto IsExpiredFn = [](const MachineInstr &MI, int) {
unsigned Opc = MI.getOpcode();
- return SIInstrInfo::isVALU(MI) &&
- Opc != AMDGPU::V_NOP_e32 && Opc != AMDGPU::V_NOP_e64 &&
- Opc != AMDGPU::V_NOP_sdwa;
+ return SIInstrInfo::isVALU(MI) && Opc != AMDGPU::V_NOP_e32 &&
+ Opc != AMDGPU::V_NOP_e64 && Opc != AMDGPU::V_NOP_sdwa;
};
if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) ==
@@ -1912,7 +1904,8 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName);
if (!SDST) {
for (const auto &MO : MI->implicit_operands()) {
- if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) {
+ if (MO.isDef() &&
+ TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) {
SDST = &MO;
break;
}
@@ -1971,8 +1964,8 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
std::numeric_limits<int>::max())
return false;
- BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
- TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL)
+ BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
+ AMDGPU::SGPR_NULL)
.addImm(0);
return true;
}
@@ -2001,7 +1994,8 @@ bool GCNHazardRecognizer::fixVcmpxExecWARHazard(MachineInstr *MI) {
if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst))
return true;
for (auto MO : MI.implicit_operands())
- if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg())))
+ if (MO.isDef() &&
+ TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg())))
return true;
}
if (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR &&
@@ -2163,8 +2157,7 @@ bool GCNHazardRecognizer::fixLdsDirectVMEMHazard(MachineInstr *MI) {
// TODO: On GFX12 the hazard should expire on S_WAIT_LOADCNT/SAMPLECNT/BVHCNT
// according to the type of VMEM instruction.
auto IsExpiredFn = [this, LdsdirCanWait](const MachineInstr &I, int) {
- return SIInstrInfo::isVALU(I) ||
- SIInstrInfo::isEXP(I) ||
+ return SIInstrInfo::isVALU(I) || SIInstrInfo::isEXP(I) ||
(I.getOpcode() == AMDGPU::S_WAITCNT && !I.getOperand(0).getImm()) ||
(I.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR &&
AMDGPU::DepCtr::decodeFieldVmVsrc(I.getOperand(0).getImm()) == 0) ||
@@ -2434,8 +2427,7 @@ bool GCNHazardRecognizer::fixVALUTransUseHazard(MachineInstr *MI) {
bool GCNHazardRecognizer::fixVALUTransCoexecutionHazards(MachineInstr *MI) {
if (!ST.hasTransCoexecutionHazard() || // Coexecution disabled.
- !SIInstrInfo::isVALU(*MI) ||
- SIInstrInfo::isTRANS(*MI))
+ !SIInstrInfo::isVALU(*MI) || SIInstrInfo::isTRANS(*MI))
return false;
const SIInstrInfo *TII = ST.getInstrInfo();
@@ -3015,8 +3007,9 @@ int GCNHazardRecognizer::checkMAIHazards908(MachineInstr *MI) const {
const int VALUWritesExecWaitStates = 4;
const int MaxWaitStates = 4;
- int WaitStatesNeededForUse = VALUWritesExecWaitStates -
- getWaitStatesSinceDef(AMDGPU::EXEC, IsVALUFn, MaxWaitStates);
+ int WaitStatesNeededForUse =
+ VALUWritesExecWaitStates -
+ getWaitStatesSinceDef(AMDGPU::EXEC, IsVALUFn, MaxWaitStates);
WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
if (WaitStatesNeeded < MaxWaitStates) {
@@ -3221,22 +3214,22 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) const {
unsigned Opc = MI->getOpcode();
auto IsLegacyVALUFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI) &&
- !SIInstrInfo::isMFMA(MI);
+ return SIInstrInfo::isVALU(MI) && !SIInstrInfo::isMFMA(MI);
};
auto IsLegacyVALUNotDotFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI) &&
- !SIInstrInfo::isMFMA(MI) && !SIInstrInfo::isDOT(MI);
+ return SIInstrInfo::isVALU(MI) && !SIInstrInfo::isMFMA(MI) &&
+ !SIInstrInfo::isDOT(MI);
};
if (!SIInstrInfo::isMFMA(*MI))
return WaitStatesNeeded;
const int VALUWritesExecWaitStates = 4;
- int WaitStatesNeededForUse = VALUWritesExecWaitStates -
- getWaitStatesSinceDef(AMDGPU::EXEC, IsLegacyVALUFn,
- VALUWritesExecWaitStates);
+ int WaitStatesNeededForUse =
+ VALUWritesExecWaitStates -
+ getWaitStatesSinceDef(AMDGPU::EXEC, IsLegacyVALUFn,
+ VALUWritesExecWaitStates);
WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
@@ -3462,8 +3455,9 @@ int GCNHazardRecognizer::checkMAILdStHazards(MachineInstr *MI) const {
std::numeric_limits<int>::max();
};
- WaitStatesNeededForUse = VALUWriteAccVgprRdWrLdStDepVALUWaitStates -
- getWaitStatesSince(IsVALUAccVgprRdWrCheckFn, MaxWaitStates);
+ WaitStatesNeededForUse =
+ VALUWriteAccVgprRdWrLdStDepVALUWaitStates -
+ getWaitStatesSince(IsVALUAccVgprRdWrCheckFn, MaxWaitStates);
WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
}
@@ -3599,8 +3593,8 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) const {
return true;
};
- int SrcCIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
- AMDGPU::OpName::src2);
+ int SrcCIdx =
+ AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src2);
if (IsMemOrExport || IsVALU) {
const int SMFMA4x4WriteVgprVALUMemExpReadWaitStates = 5;
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index bbf0b91ba108c..e1190c4320af2 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -1015,8 +1015,7 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
}
} else if (Inst->getNumExplicitDefs() != 0) {
Register Reg = Inst->getOperand(0).getReg();
- if (Reg.isVirtual() && TRI->isSGPRReg(*MRI, Reg) &&
- !TII->isVALU(*Inst)) {
+ if (Reg.isVirtual() && TRI->isSGPRReg(*MRI, Reg) && !TII->isVALU(*Inst)) {
for (auto &U : MRI->use_instructions(Reg))
Users.push_back(&U);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 677633a599edd..965db22e2d413 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -320,8 +320,8 @@ bool SIInstrInfo::resultDependsOnExec(const MachineInstr &MI) const {
bool SIInstrInfo::isIgnorableUse(const MachineInstr &MI, unsigned OpIdx) const {
const MachineOperand &MO = MI.getOperand(OpIdx);
// Any implicit use of exec by VALU is not a real register read.
- return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
- isVALU(MI) && !resultDependsOnExec(MI);
+ return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() && isVALU(MI) &&
+ !resultDependsOnExec(MI);
}
bool SIInstrInfo::isSafeToSink(MachineInstr &MI,
>From 47c584a7d3d23445ed937651645ec2ac3cb1489e Mon Sep 17 00:00:00 2001
From: akadutta_amdeng <Akash.Dutta at amd.com>
Date: Fri, 11 Sep 2026 13:11:42 -0500
Subject: [PATCH 7/7] format code
---
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 19e80d1c16586..ab115b73beb38 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -835,10 +835,9 @@ void GCNHazardRecognizer::AdvanceCycle() {
// Keep track of emitted instructions
EmittedInstrs.push_front(CurrCycleInstr);
- bool IsVALUOrWMMA =
- SIInstrInfo::isVALU(*CurrCycleInstr) ||
- SIInstrInfo::isWMMA(*CurrCycleInstr) ||
- SIInstrInfo::isSWMMAC(*CurrCycleInstr);
+ bool IsVALUOrWMMA = SIInstrInfo::isVALU(*CurrCycleInstr) ||
+ SIInstrInfo::isWMMA(*CurrCycleInstr) ||
+ SIInstrInfo::isSWMMAC(*CurrCycleInstr);
if (IsVALUOrWMMA) {
EmittedVALUInstrs.push_front(CurrCycleInstr);
} else {
@@ -3448,8 +3447,7 @@ int GCNHazardRecognizer::checkMAILdStHazards(MachineInstr *MI) const {
MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64)
return false;
auto IsVALUFn = [](const MachineInstr &MI) {
- return SIInstrInfo::isVALU(MI) &&
- !SIInstrInfo::isMAI(MI);
+ return SIInstrInfo::isVALU(MI) && !SIInstrInfo::isMAI(MI);
};
return getWaitStatesSinceDef(Reg, IsVALUFn, 2 /*MaxWaitStates*/) <
std::numeric_limits<int>::max();
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