[llvm] [AMDGPU] Add block carried latency to CoExecSched (PR #192324)

[Austin Kerbow via llvm-commits]

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kerbowa wrote:

This code should not be part of this review because it was inadvertently carried over from the already merged DS FIFO PR. If I understand the question correctly, `TotalCycles` is decremented by `BlockingCycles` whenever the number of scheduled SUs reaches a multiple of `BufferSize`. `TotalCycles` is used when sorting critical resources. Buffer-full stalls are handled separately using the availability cycle returned by `getBufferAvailableCycle()`.

https://github.com/llvm/llvm-project/pull/192324