[llvm] [RISCV] Lower VECTOR_INTERLEAVE 4 and 8 with Zvzip (PR #222432)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 11 11:09:01 PDT 2026
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/222432
>From 71adc015040707cbbc142cd5f88b605727b09942 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Tue, 8 Sep 2026 15:45:26 -0700
Subject: [PATCH 1/4] [RISCV] Lower VECTOR_INTERLEAVE 4 and 8 with Zvzip
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 45 +
.../RISCV/rvv/vector-interleave-fixed.ll | 217 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 3203 ++++++++++-------
3 files changed, 2068 insertions(+), 1397 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5f8ad5da42da1..e7bba4b7cf02f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14641,6 +14641,51 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
SDValue Interleaved;
+ if (Subtarget.hasStdExtZvzip() && (Factor == 4 || Factor == 8)) {
+ // Interleave by a tree of vzip.vv instructions.
+ SmallVector<SDValue, 8> Operands(Op->op_values());
+ // First, reorder the operands.
+ // For Factor=4, given the original operand order `ABCD`, we need
+ // to reorder it into `ACBD`.
+ // For Factor=8, given the original operand order `ABCDEFGH`, the new
+ // order should be `AECGBFDH`.
+ // So the rule here is that for every operands with an odd index `I`, swap
+ // it with the operand of index `I + (Factor / 2 - 1)`.
+ for (unsigned I = 1U, HalfFactor = Factor / 2; I < HalfFactor; I += 2)
+ std::swap(Operands[I], Operands[I + (HalfFactor - 1)]);
+
+ for (unsigned CurrFactor = Factor; CurrFactor > 1; CurrFactor /= 2) {
+ // Generate a vzip.vv for every two operands.
+ for (unsigned I = 0U; I < CurrFactor; I += 2) {
+ assert(Operands[I].getValueType().isSimple() &&
+ isLegalVTForZvzipOperand(Operands[I].getSimpleValueType(),
+ Subtarget));
+ SDValue V1 = DAG.getFreeze(Operands[I]);
+ SDValue V2 = DAG.getFreeze(Operands[I + 1]);
+ // Do not generate VECTOR_INTERLEAVE2 + CONCAT_VECTORS here. Because
+ // when those two nodes are subsequently lowered, there will
+ // be a bunch of insert_subvector and extract_subvector generated.
+ // Though most of them can be combined, since we're not
+ // running DAGCombiner in between different operations' lowering,
+ // some of the insert/extract subvectors will be turned into
+ // VSLIDEUP/DOWN_VL right away and stay thru the rest of the codegen.
+ // We could write additional combining rules for those VSLIDEUP/DOWN_VL
+ // but I thought it'll be a lot easier to just not generate
+ // VECTOR_INTERLEAVE2 + CONCAT_VECTORS in the first place here.
+ Operands[I / 2] = lowerZvzipVZIP(V1, V2, DL, DAG, Subtarget);
+ }
+ }
+
+ // Operands[0] is the resulting concat vector, but we need to split into
+ // Factor parts.
+ Interleaved = Operands[0];
+ for (unsigned I = 0U; I < Factor; ++I) {
+ Operands[I] = DAG.getExtractSubvector(
+ DL, VecVT, Interleaved, I * VecVT.getVectorMinNumElements());
+ }
+ return DAG.getMergeValues(Operands, DL);
+ }
+
// Spill to the stack using a segment store for simplicity.
if (Factor != 2) {
EVT MemVT =
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 56a68500747dd..9296e15920121 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -278,25 +278,21 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
;
; ZVZIP-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -32
-; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 24
-; ZVZIP-NEXT: vle32.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle32.v v10, (a1)
-; ZVZIP-NEXT: vle32.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v11, v8, v10
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a0)
+; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 6
+; ZVZIP-NEXT: vslidedown.vi v12, v8, 4
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vslideup.vi v12, v10, 2
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: addi sp, sp, 32
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
@@ -674,41 +670,36 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
;
; ZVZIP-LABEL: vector_interleave8_v16i8_v2i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vsseg8e8.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 10
-; ZVZIP-NEXT: vle8.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle8.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 12
-; ZVZIP-NEXT: vle8.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 2
-; ZVZIP-NEXT: vle8.v v12, (a1)
-; ZVZIP-NEXT: vle8.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vle8.v v9, (a0)
+; ZVZIP-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v11, v16
+; ZVZIP-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v9, v11, v8
+; ZVZIP-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v9, 10
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 8
+; ZVZIP-NEXT: vslidedown.vi v12, v9, 12
+; ZVZIP-NEXT: vslidedown.vi v13, v9, 14
+; ZVZIP-NEXT: vslidedown.vi v14, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v15, v9, 4
+; ZVZIP-NEXT: vslidedown.vi v16, v9, 6
+; ZVZIP-NEXT: vmv1r.v v8, v9
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 2
-; ZVZIP-NEXT: addi a0, sp, 14
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vle8.v v12, (a0)
+; ZVZIP-NEXT: vslideup.vi v11, v10, 2
+; ZVZIP-NEXT: vslideup.vi v8, v14, 2
; ZVZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 4
-; ZVZIP-NEXT: vslideup.vi v8, v9, 4
-; ZVZIP-NEXT: addi a0, sp, 6
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vle8.v v9, (a0)
+; ZVZIP-NEXT: vslideup.vi v11, v12, 4
+; ZVZIP-NEXT: vslideup.vi v8, v15, 4
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 6
-; ZVZIP-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-NEXT: vslideup.vi v11, v13, 6
+; ZVZIP-NEXT: vslideup.vi v8, v16, 6
; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 8
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: vslideup.vi v8, v11, 8
; ZVZIP-NEXT: ret
%res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)
ret <16 x i8> %res
@@ -1103,25 +1094,21 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
;
; ZVZIP-LABEL: vector_interleave4_v8f32_v2f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -32
-; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 24
-; ZVZIP-NEXT: vle32.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle32.v v10, (a1)
-; ZVZIP-NEXT: vle32.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v11, v8, v10
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a0)
+; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 6
+; ZVZIP-NEXT: vslidedown.vi v12, v8, 4
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vslideup.vi v12, v10, 2
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: addi sp, sp, 32
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)
ret <8 x float> %res
@@ -1790,41 +1777,36 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
;
; ZVZIP-LABEL: vector_interleave8_v8f16_v1f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vsseg8e16.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 10
-; ZVZIP-NEXT: vle16.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle16.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 12
-; ZVZIP-NEXT: vle16.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 2
-; ZVZIP-NEXT: vle16.v v12, (a1)
-; ZVZIP-NEXT: vle16.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 4
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v11, v16
+; ZVZIP-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v9, v11, v8
+; ZVZIP-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v9, 5
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-NEXT: vslidedown.vi v12, v9, 6
+; ZVZIP-NEXT: vslidedown.vi v13, v9, 7
+; ZVZIP-NEXT: vslidedown.vi v14, v9, 1
+; ZVZIP-NEXT: vslidedown.vi v15, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v16, v9, 3
+; ZVZIP-NEXT: vmv1r.v v8, v9
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-NEXT: addi a0, sp, 14
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v12, (a0)
+; ZVZIP-NEXT: vslideup.vi v11, v10, 1
+; ZVZIP-NEXT: vslideup.vi v8, v14, 1
; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
-; ZVZIP-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-NEXT: addi a0, sp, 6
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vslideup.vi v11, v12, 2
+; ZVZIP-NEXT: vslideup.vi v8, v15, 2
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 3
-; ZVZIP-NEXT: vslideup.vi v8, v9, 3
+; ZVZIP-NEXT: vslideup.vi v11, v13, 3
+; ZVZIP-NEXT: vslideup.vi v8, v16, 3
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: vslideup.vi v8, v11, 4
; ZVZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave8.v8f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h)
ret <8 x half> %res
@@ -1911,41 +1893,36 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
;
; ZVZIP-LABEL: vector_interleave8_v8bf16_v1bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vsseg8e16.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 10
-; ZVZIP-NEXT: vle16.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle16.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 12
-; ZVZIP-NEXT: vle16.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 2
-; ZVZIP-NEXT: vle16.v v12, (a1)
-; ZVZIP-NEXT: vle16.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 4
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v11, v16
+; ZVZIP-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v9, v11, v8
+; ZVZIP-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v9, 5
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-NEXT: vslidedown.vi v12, v9, 6
+; ZVZIP-NEXT: vslidedown.vi v13, v9, 7
+; ZVZIP-NEXT: vslidedown.vi v14, v9, 1
+; ZVZIP-NEXT: vslidedown.vi v15, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v16, v9, 3
+; ZVZIP-NEXT: vmv1r.v v8, v9
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-NEXT: addi a0, sp, 14
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v12, (a0)
+; ZVZIP-NEXT: vslideup.vi v11, v10, 1
+; ZVZIP-NEXT: vslideup.vi v8, v14, 1
; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
-; ZVZIP-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-NEXT: addi a0, sp, 6
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vslideup.vi v11, v12, 2
+; ZVZIP-NEXT: vslideup.vi v8, v15, 2
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 3
-; ZVZIP-NEXT: vslideup.vi v8, v9, 3
+; ZVZIP-NEXT: vslideup.vi v11, v13, 3
+; ZVZIP-NEXT: vslideup.vi v8, v16, 3
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: vslideup.vi v8, v11, 4
; ZVZIP-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave8.v8bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g, <1 x bfloat> %h)
ret <8 x bfloat> %res
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index b4053654e42f2..3369df3c6ba4a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -772,50 +772,50 @@ define <vscale x 6 x i64> @vector_interleave_nxv6i64_nxv2i64(<vscale x 2 x i64>
}
define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d) nounwind {
-; CHECK-LABEL: vector_interleave_nxv64i1_nxv16i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg4e8.v v14, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vl2r.v v8, (a2)
-; CHECK-NEXT: vmsne.vi v10, v8, 0
-; CHECK-NEXT: vl2r.v v8, (a4)
-; CHECK-NEXT: vmsne.vi v11, v8, 0
-; CHECK-NEXT: vl2r.v v8, (a3)
-; CHECK-NEXT: vmsne.vi v12, v8, 0
-; CHECK-NEXT: vl2r.v v8, (a0)
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: srli a0, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v10, a0
-; CHECK-NEXT: vslideup.vx v0, v12, a0
-; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v11, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv64i1_nxv16i1:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; V-NEXT: vmv1r.v v11, v0
+; V-NEXT: vmv.v.i v12, 0
+; V-NEXT: vmv1r.v v0, v8
+; V-NEXT: vmerge.vim v16, v12, 1, v0
+; V-NEXT: vmv1r.v v0, v11
+; V-NEXT: vmerge.vim v14, v12, 1, v0
+; V-NEXT: vmv1r.v v0, v9
+; V-NEXT: vmerge.vim v18, v12, 1, v0
+; V-NEXT: vmv1r.v v0, v10
+; V-NEXT: vmerge.vim v20, v12, 1, v0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg4e8.v v14, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: add a3, a0, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a2, a4, a2
+; V-NEXT: vl2r.v v8, (a2)
+; V-NEXT: vmsne.vi v10, v8, 0
+; V-NEXT: vl2r.v v8, (a4)
+; V-NEXT: vmsne.vi v11, v8, 0
+; V-NEXT: vl2r.v v8, (a3)
+; V-NEXT: vmsne.vi v12, v8, 0
+; V-NEXT: vl2r.v v8, (a0)
+; V-NEXT: vmsne.vi v0, v8, 0
+; V-NEXT: srli a0, a1, 2
+; V-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; V-NEXT: vslideup.vx v11, v10, a0
+; V-NEXT: vslideup.vx v0, v12, a0
+; V-NEXT: srli a1, a1, 1
+; V-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; V-NEXT: vslideup.vx v0, v11, a1
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv64i1_nxv16i1:
; ZVBB: # %bb.0:
@@ -861,35 +861,67 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64i1_nxv16i1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v11, v0
+; ZVZIP-NEXT: vmv.v.i v12, 0
+; ZVZIP-NEXT: vmv1r.v v0, v10
+; ZVZIP-NEXT: vmerge.vim v14, v12, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v8
+; ZVZIP-NEXT: vmerge.vim v20, v12, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v9
+; ZVZIP-NEXT: vzip.vv v16, v20, v14
+; ZVZIP-NEXT: vmerge.vim v8, v12, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v11
+; ZVZIP-NEXT: vmerge.vim v10, v12, 1, v0
+; ZVZIP-NEXT: vzip.vv v20, v10, v8
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmsne.vi v16, v14, 0
+; ZVZIP-NEXT: vmsne.vi v14, v12, 0
+; ZVZIP-NEXT: vmsne.vi v12, v10, 0
+; ZVZIP-NEXT: vmsne.vi v0, v8, 0
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a1, a0, 2
+; ZVZIP-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vx v14, v16, a1
+; ZVZIP-NEXT: vslideup.vx v0, v12, a1
+; ZVZIP-NEXT: srli a0, a0, 1
+; ZVZIP-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vx v0, v14, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.vector.interleave4.nxv64i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d)
ret <vscale x 64 x i1> %res
}
define <vscale x 64 x i8> @vector_interleave_nxv64i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d) nounwind {
;
-; CHECK-LABEL: vector_interleave_nxv64i8_nxv16i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vsseg4e8.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl2r.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2r.v v14, (a1)
-; CHECK-NEXT: vl2r.v v8, (a0)
-; CHECK-NEXT: vl2r.v v10, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv64i8_nxv16i8:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; V-NEXT: vsseg4e8.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl2r.v v12, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl2r.v v14, (a1)
+; V-NEXT: vl2r.v v8, (a0)
+; V-NEXT: vl2r.v v10, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv64i8_nxv16i8:
; ZVBB: # %bb.0:
@@ -914,33 +946,42 @@ define <vscale x 64 x i8> @vector_interleave_nxv64i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64i8_nxv16i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.vector.interleave4.nxv64i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d)
ret <vscale x 64 x i8> %res
}
define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d) nounwind {
-; CHECK-LABEL: vector_interleave_nxv32i8_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg4e8.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl1r.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1r.v v11, (a1)
-; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv32i8_nxv8i8:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; V-NEXT: vsseg4e8.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl1r.v v10, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl1r.v v11, (a1)
+; V-NEXT: vl1r.v v8, (a0)
+; V-NEXT: vl1r.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv32i8_nxv8i8:
; ZVBB: # %bb.0:
@@ -964,35 +1005,44 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv8i8(<vscale x 8 x i8> %a
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32i8_nxv8i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v14, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.vector.interleave4.nxv32i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d)
ret <vscale x 32 x i8> %res
}
define <vscale x 16 x i32> @vector_interleave_nxv16i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d) nounwind {
;
-; CHECK-LABEL: vector_interleave_nxv16i32_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl2re32.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re32.v v14, (a1)
-; CHECK-NEXT: vl2re32.v v8, (a0)
-; CHECK-NEXT: vl2re32.v v10, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16i32_nxv4i32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; V-NEXT: vsseg4e32.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl2re32.v v12, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl2re32.v v14, (a1)
+; V-NEXT: vl2re32.v v8, (a0)
+; V-NEXT: vl2re32.v v10, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16i32_nxv4i32:
; ZVBB: # %bb.0:
@@ -1017,35 +1067,44 @@ define <vscale x 16 x i32> @vector_interleave_nxv16i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16i32_nxv4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.vector.interleave4.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d)
ret <vscale x 16 x i32> %res
}
define <vscale x 8 x i64> @vector_interleave_nxv8i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d) nounwind {
;
-; CHECK-LABEL: vector_interleave_nxv8i64_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl2re64.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re64.v v14, (a1)
-; CHECK-NEXT: vl2re64.v v8, (a0)
-; CHECK-NEXT: vl2re64.v v10, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv8i64_nxv2i64:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; V-NEXT: vsseg4e64.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl2re64.v v12, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl2re64.v v14, (a1)
+; V-NEXT: vl2re64.v v8, (a0)
+; V-NEXT: vl2re64.v v10, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8i64_nxv2i64:
; ZVBB: # %bb.0:
@@ -1070,6 +1129,15 @@ define <vscale x 8 x i64> @vector_interleave_nxv8i64_nxv2i64(<vscale x 2 x i64>
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8i64_nxv2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.vector.interleave4.nxv8i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d)
ret <vscale x 8 x i64> %res
}
@@ -5443,104 +5511,104 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
}
define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g, <vscale x 16 x i1> %h) nounwind {
-; CHECK-LABEL: vector_interleave_nxv128i1_nxv16i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v16, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v1, v17
-; CHECK-NEXT: vmerge.vim v24, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v18, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v28, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmv1r.v v2, v25
-; CHECK-NEXT: vmv1r.v v3, v19
-; CHECK-NEXT: vmerge.vim v20, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v10, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmv1r.v v4, v29
-; CHECK-NEXT: vmv1r.v v5, v21
-; CHECK-NEXT: vmerge.vim v22, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmerge.vim v12, v26, 1, v0
-; CHECK-NEXT: vmv1r.v v6, v11
-; CHECK-NEXT: vmv1r.v v7, v23
-; CHECK-NEXT: vmv1r.v v8, v13
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg8e8.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v17, v24
-; CHECK-NEXT: vmv1r.v v19, v28
-; CHECK-NEXT: vmv1r.v v21, v10
-; CHECK-NEXT: vmv1r.v v23, v12
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vsseg8e8.v v16, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: add a3, a1, a0
-; CHECK-NEXT: add a4, a3, a0
-; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v9, (a4)
-; CHECK-NEXT: vl1r.v v10, (a1)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
-; CHECK-NEXT: add a1, a4, a0
-; CHECK-NEXT: add a3, a1, a0
-; CHECK-NEXT: vl1r.v v12, (a3)
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v13, (a3)
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: add a5, a3, a0
-; CHECK-NEXT: vl1r.v v14, (a5)
-; CHECK-NEXT: vsetvli a6, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmsne.vi v16, v8, 0
-; CHECK-NEXT: add a5, a5, a0
-; CHECK-NEXT: vl1r.v v15, (a5)
-; CHECK-NEXT: vmsne.vi v8, v10, 0
-; CHECK-NEXT: vl1r.v v10, (a2)
-; CHECK-NEXT: add a5, a5, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
-; CHECK-NEXT: vmsne.vi v9, v12, 0
-; CHECK-NEXT: add a2, a5, a0
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: vl1r.v v12, (a3)
-; CHECK-NEXT: vmsne.vi v17, v14, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v13, (a3)
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vl1r.v v10, (a5)
-; CHECK-NEXT: vl1r.v v11, (a2)
-; CHECK-NEXT: vmsne.vi v14, v12, 0
-; CHECK-NEXT: vl1r.v v12, (a4)
-; CHECK-NEXT: vmsne.vi v15, v10, 0
-; CHECK-NEXT: vl1r.v v13, (a1)
-; CHECK-NEXT: vmsne.vi v10, v12, 0
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v15, v14, a1
-; CHECK-NEXT: vslideup.vx v0, v17, a1
-; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vslideup.vx v8, v16, a1
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v15, a0
-; CHECK-NEXT: vslideup.vx v8, v10, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv128i1_nxv16i1:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; V-NEXT: vmv.v.i v26, 0
+; V-NEXT: vmerge.vim v16, v26, 1, v0
+; V-NEXT: vmv1r.v v0, v8
+; V-NEXT: vmv1r.v v1, v17
+; V-NEXT: vmerge.vim v24, v26, 1, v0
+; V-NEXT: vmv1r.v v0, v9
+; V-NEXT: vmerge.vim v18, v26, 1, v0
+; V-NEXT: vmv1r.v v0, v10
+; V-NEXT: vmerge.vim v28, v26, 1, v0
+; V-NEXT: vmv1r.v v0, v11
+; V-NEXT: vmv1r.v v2, v25
+; V-NEXT: vmv1r.v v3, v19
+; V-NEXT: vmerge.vim v20, v26, 1, v0
+; V-NEXT: vmv1r.v v0, v12
+; V-NEXT: vmerge.vim v10, v26, 1, v0
+; V-NEXT: vmv1r.v v0, v13
+; V-NEXT: vmv1r.v v4, v29
+; V-NEXT: vmv1r.v v5, v21
+; V-NEXT: vmerge.vim v22, v26, 1, v0
+; V-NEXT: vmv1r.v v0, v14
+; V-NEXT: vmerge.vim v12, v26, 1, v0
+; V-NEXT: vmv1r.v v6, v11
+; V-NEXT: vmv1r.v v7, v23
+; V-NEXT: vmv1r.v v8, v13
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; V-NEXT: vsseg8e8.v v1, (a1)
+; V-NEXT: vmv1r.v v17, v24
+; V-NEXT: vmv1r.v v19, v28
+; V-NEXT: vmv1r.v v21, v10
+; V-NEXT: vmv1r.v v23, v12
+; V-NEXT: addi a2, sp, 16
+; V-NEXT: vsseg8e8.v v16, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: add a3, a1, a0
+; V-NEXT: add a4, a3, a0
+; V-NEXT: vl1r.v v8, (a4)
+; V-NEXT: add a4, a4, a0
+; V-NEXT: vl1r.v v9, (a4)
+; V-NEXT: vl1r.v v10, (a1)
+; V-NEXT: add a4, a4, a0
+; V-NEXT: vl1r.v v11, (a3)
+; V-NEXT: add a1, a4, a0
+; V-NEXT: add a3, a1, a0
+; V-NEXT: vl1r.v v12, (a3)
+; V-NEXT: add a3, a3, a0
+; V-NEXT: vl1r.v v13, (a3)
+; V-NEXT: add a3, a2, a0
+; V-NEXT: add a5, a3, a0
+; V-NEXT: vl1r.v v14, (a5)
+; V-NEXT: vsetvli a6, zero, e8, m2, ta, ma
+; V-NEXT: vmsne.vi v16, v8, 0
+; V-NEXT: add a5, a5, a0
+; V-NEXT: vl1r.v v15, (a5)
+; V-NEXT: vmsne.vi v8, v10, 0
+; V-NEXT: vl1r.v v10, (a2)
+; V-NEXT: add a5, a5, a0
+; V-NEXT: vl1r.v v11, (a3)
+; V-NEXT: vmsne.vi v9, v12, 0
+; V-NEXT: add a2, a5, a0
+; V-NEXT: add a3, a2, a0
+; V-NEXT: vl1r.v v12, (a3)
+; V-NEXT: vmsne.vi v17, v14, 0
+; V-NEXT: add a3, a3, a0
+; V-NEXT: vl1r.v v13, (a3)
+; V-NEXT: vmsne.vi v0, v10, 0
+; V-NEXT: vl1r.v v10, (a5)
+; V-NEXT: vl1r.v v11, (a2)
+; V-NEXT: vmsne.vi v14, v12, 0
+; V-NEXT: vl1r.v v12, (a4)
+; V-NEXT: vmsne.vi v15, v10, 0
+; V-NEXT: vl1r.v v13, (a1)
+; V-NEXT: vmsne.vi v10, v12, 0
+; V-NEXT: srli a1, a0, 2
+; V-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; V-NEXT: vslideup.vx v15, v14, a1
+; V-NEXT: vslideup.vx v0, v17, a1
+; V-NEXT: vslideup.vx v10, v9, a1
+; V-NEXT: vslideup.vx v8, v16, a1
+; V-NEXT: srli a0, a0, 1
+; V-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; V-NEXT: vslideup.vx v0, v15, a0
+; V-NEXT: vslideup.vx v8, v10, a0
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv128i1_nxv16i1:
; ZVBB: # %bb.0:
@@ -5640,6 +5708,75 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv128i1_nxv16i1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v15, v0
+; ZVZIP-NEXT: vmv.v.i v16, 0
+; ZVZIP-NEXT: vmv1r.v v0, v14
+; ZVZIP-NEXT: vmerge.vim v28, v16, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v10
+; ZVZIP-NEXT: vmerge.vim v30, v16, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v18, v31, v29
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmerge.vim v6, v16, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v8
+; ZVZIP-NEXT: vmerge.vim v4, v16, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v13
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v5, v7
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmerge.vim v12, v16, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v9
+; ZVZIP-NEXT: vzip.vv v24, v20, v18
+; ZVZIP-NEXT: vmerge.vim v8, v16, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v11
+; ZVZIP-NEXT: vmerge.vim v10, v16, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v15
+; ZVZIP-NEXT: vmerge.vim v14, v16, 1, v0
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v9, v13
+; ZVZIP-NEXT: vzip.vv v18, v15, v11
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v24
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v30, v28
+; ZVZIP-NEXT: vzip.vv v26, v4, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v26, v24
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v8, v12
+; ZVZIP-NEXT: vzip.vv v12, v14, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v12, v24
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v8, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmsne.vi v8, v16, 0
+; ZVZIP-NEXT: vmsne.vi v9, v18, 0
+; ZVZIP-NEXT: vmsne.vi v10, v22, 0
+; ZVZIP-NEXT: vmsne.vi v0, v24, 0
+; ZVZIP-NEXT: vmsne.vi v11, v26, 0
+; ZVZIP-NEXT: vmsne.vi v12, v30, 0
+; ZVZIP-NEXT: vmsne.vi v13, v28, 0
+; ZVZIP-NEXT: vmsne.vi v14, v20, 0
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a1, a0, 2
+; ZVZIP-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vx v13, v12, a1
+; ZVZIP-NEXT: vslideup.vx v0, v11, a1
+; ZVZIP-NEXT: vslideup.vx v14, v10, a1
+; ZVZIP-NEXT: vslideup.vx v8, v9, a1
+; ZVZIP-NEXT: srli a0, a0, 1
+; ZVZIP-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vx v0, v13, a0
+; ZVZIP-NEXT: vslideup.vx v8, v14, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 128 x i1> @llvm.vector.interleave8.nxv128i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g, <vscale x 16 x i1> %h)
ret <vscale x 128 x i1> %res
}
@@ -5647,72 +5784,72 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g, <vscale x 16 x i8> %h) nounwind {
;
-; CHECK-LABEL: vector_interleave_nxv128i8_nxv16i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e8.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e8.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1r.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1r.v v23, (t0)
-; CHECK-NEXT: vl1r.v v20, (a6)
-; CHECK-NEXT: vl1r.v v21, (a7)
-; CHECK-NEXT: vl1r.v v18, (a4)
-; CHECK-NEXT: vl1r.v v19, (a5)
-; CHECK-NEXT: vl1r.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1r.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1r.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1r.v v15, (a2)
-; CHECK-NEXT: vl1r.v v12, (a3)
-; CHECK-NEXT: vl1r.v v13, (a6)
-; CHECK-NEXT: vl1r.v v10, (a4)
-; CHECK-NEXT: vl1r.v v11, (a5)
-; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv128i8_nxv16i8:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e8.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e8.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1r.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1r.v v23, (t0)
+; V-NEXT: vl1r.v v20, (a6)
+; V-NEXT: vl1r.v v21, (a7)
+; V-NEXT: vl1r.v v18, (a4)
+; V-NEXT: vl1r.v v19, (a5)
+; V-NEXT: vl1r.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1r.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1r.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1r.v v15, (a2)
+; V-NEXT: vl1r.v v12, (a3)
+; V-NEXT: vl1r.v v13, (a6)
+; V-NEXT: vl1r.v v10, (a4)
+; V-NEXT: vl1r.v v11, (a5)
+; V-NEXT: vl1r.v v8, (a0)
+; V-NEXT: vl1r.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv128i8_nxv16i8:
; ZVBB: # %bb.0:
@@ -5780,6 +5917,38 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv128i8_nxv16i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 128 x i8> @llvm.vector.interleave8.nxv128i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g, <vscale x 16 x i8> %h)
ret <vscale x 128 x i8> %res
}
@@ -5787,72 +5956,72 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8
define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g, <vscale x 8 x i16> %h) nounwind {
;
-; CHECK-LABEL: vector_interleave_nxv64i16_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e16.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e16.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re16.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re16.v v23, (t0)
-; CHECK-NEXT: vl1re16.v v20, (a6)
-; CHECK-NEXT: vl1re16.v v21, (a7)
-; CHECK-NEXT: vl1re16.v v18, (a4)
-; CHECK-NEXT: vl1re16.v v19, (a5)
-; CHECK-NEXT: vl1re16.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re16.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re16.v v15, (a2)
-; CHECK-NEXT: vl1re16.v v12, (a3)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a4)
-; CHECK-NEXT: vl1re16.v v11, (a5)
-; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv64i16_nxv8i16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e16.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e16.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1re16.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1re16.v v23, (t0)
+; V-NEXT: vl1re16.v v20, (a6)
+; V-NEXT: vl1re16.v v21, (a7)
+; V-NEXT: vl1re16.v v18, (a4)
+; V-NEXT: vl1re16.v v19, (a5)
+; V-NEXT: vl1re16.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1re16.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1re16.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1re16.v v15, (a2)
+; V-NEXT: vl1re16.v v12, (a3)
+; V-NEXT: vl1re16.v v13, (a6)
+; V-NEXT: vl1re16.v v10, (a4)
+; V-NEXT: vl1re16.v v11, (a5)
+; V-NEXT: vl1re16.v v8, (a0)
+; V-NEXT: vl1re16.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv64i16_nxv8i16:
; ZVBB: # %bb.0:
@@ -5920,6 +6089,38 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64i16_nxv8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x i16> @llvm.vector.interleave8.nxv64i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g, <vscale x 8 x i16> %h)
ret <vscale x 64 x i16> %res
}
@@ -5927,72 +6128,72 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16
define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g, <vscale x 4 x i32> %h) nounwind {
;
-; CHECK-LABEL: vector_interleave_nxv32i32_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e32.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e32.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re32.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re32.v v23, (t0)
-; CHECK-NEXT: vl1re32.v v20, (a6)
-; CHECK-NEXT: vl1re32.v v21, (a7)
-; CHECK-NEXT: vl1re32.v v18, (a4)
-; CHECK-NEXT: vl1re32.v v19, (a5)
-; CHECK-NEXT: vl1re32.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re32.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re32.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re32.v v15, (a2)
-; CHECK-NEXT: vl1re32.v v12, (a3)
-; CHECK-NEXT: vl1re32.v v13, (a6)
-; CHECK-NEXT: vl1re32.v v10, (a4)
-; CHECK-NEXT: vl1re32.v v11, (a5)
-; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv32i32_nxv4i32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e32.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e32.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1re32.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1re32.v v23, (t0)
+; V-NEXT: vl1re32.v v20, (a6)
+; V-NEXT: vl1re32.v v21, (a7)
+; V-NEXT: vl1re32.v v18, (a4)
+; V-NEXT: vl1re32.v v19, (a5)
+; V-NEXT: vl1re32.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1re32.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1re32.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1re32.v v15, (a2)
+; V-NEXT: vl1re32.v v12, (a3)
+; V-NEXT: vl1re32.v v13, (a6)
+; V-NEXT: vl1re32.v v10, (a4)
+; V-NEXT: vl1re32.v v11, (a5)
+; V-NEXT: vl1re32.v v8, (a0)
+; V-NEXT: vl1re32.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv32i32_nxv4i32:
; ZVBB: # %bb.0:
@@ -6060,78 +6261,110 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32i32_nxv4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x i32> @llvm.vector.interleave8.nxv32i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g, <vscale x 4 x i32> %h)
ret <vscale x 32 x i32> %res
}
define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g, <vscale x 2 x i64> %h) nounwind {
;
-; CHECK-LABEL: vector_interleave_nxv16i64_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e64.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e64.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re64.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re64.v v23, (t0)
-; CHECK-NEXT: vl1re64.v v20, (a6)
-; CHECK-NEXT: vl1re64.v v21, (a7)
-; CHECK-NEXT: vl1re64.v v18, (a4)
-; CHECK-NEXT: vl1re64.v v19, (a5)
-; CHECK-NEXT: vl1re64.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re64.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re64.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re64.v v15, (a2)
-; CHECK-NEXT: vl1re64.v v12, (a3)
-; CHECK-NEXT: vl1re64.v v13, (a6)
-; CHECK-NEXT: vl1re64.v v10, (a4)
-; CHECK-NEXT: vl1re64.v v11, (a5)
-; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16i64_nxv2i64:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e64.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e64.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1re64.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1re64.v v23, (t0)
+; V-NEXT: vl1re64.v v20, (a6)
+; V-NEXT: vl1re64.v v21, (a7)
+; V-NEXT: vl1re64.v v18, (a4)
+; V-NEXT: vl1re64.v v19, (a5)
+; V-NEXT: vl1re64.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1re64.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1re64.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1re64.v v15, (a2)
+; V-NEXT: vl1re64.v v12, (a3)
+; V-NEXT: vl1re64.v v13, (a6)
+; V-NEXT: vl1re64.v v10, (a4)
+; V-NEXT: vl1re64.v v11, (a5)
+; V-NEXT: vl1re64.v v8, (a0)
+; V-NEXT: vl1re64.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16i64_nxv2i64:
; ZVBB: # %bb.0:
@@ -6199,6 +6432,38 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv2i64(<vscale x 2 x i64
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16i64_nxv2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x i64> @llvm.vector.interleave8.nxv16i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g, <vscale x 2 x i64> %h)
ret <vscale x 16 x i64> %res
}
@@ -7264,35 +7529,35 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv2f64(<vscale x 2 x do
}
define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv8f16_nxv2f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsseg4e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv8f16_nxv2f16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 1
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; V-NEXT: vsseg4e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: srli a2, a1, 1
+; V-NEXT: add a3, a0, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a2, a4, a2
+; V-NEXT: vle16.v v8, (a2)
+; V-NEXT: vle16.v v9, (a4)
+; V-NEXT: vle16.v v10, (a3)
+; V-NEXT: srli a1, a1, 2
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v9, v8, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v8, (a0)
+; V-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v8, v10, a1
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 1
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8f16_nxv2f16:
; ZVBB: # %bb.0:
@@ -7323,33 +7588,48 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8f16_nxv2f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v11, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vslidedown.vx v10, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v10, a0
+; ZVZIP-NEXT: vslidedown.vx v10, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v10, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x half> @llvm.vector.interleave4.nxv8f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3)
ret <vscale x 8 x half> %res
}
define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv16f16_nxv4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vsseg4e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a1)
-; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16f16_nxv4f16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; V-NEXT: vsseg4e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl1re16.v v10, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl1re16.v v11, (a1)
+; V-NEXT: vl1re16.v v8, (a0)
+; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16f16_nxv4f16:
; ZVBB: # %bb.0:
@@ -7373,34 +7653,43 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16f16_nxv4f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v14, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x half> @llvm.vector.interleave4.nxv16f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3)
ret <vscale x 16 x half> %res
}
define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv32f16_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT: vsseg4e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl2re16.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re16.v v14, (a1)
-; CHECK-NEXT: vl2re16.v v8, (a0)
-; CHECK-NEXT: vl2re16.v v10, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv32f16_nxv8f16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; V-NEXT: vsseg4e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl2re16.v v12, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl2re16.v v14, (a1)
+; V-NEXT: vl2re16.v v8, (a0)
+; V-NEXT: vl2re16.v v10, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv32f16_nxv8f16:
; ZVBB: # %bb.0:
@@ -7425,40 +7714,49 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32f16_nxv8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x half> @llvm.vector.interleave4.nxv32f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3)
ret <vscale x 32 x half> %res
}
define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv8bf16_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsseg4e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv8bf16_nxv2bf16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 1
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; V-NEXT: vsseg4e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: srli a2, a1, 1
+; V-NEXT: add a3, a0, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a2, a4, a2
+; V-NEXT: vle16.v v8, (a2)
+; V-NEXT: vle16.v v9, (a4)
+; V-NEXT: vle16.v v10, (a3)
+; V-NEXT: srli a1, a1, 2
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v9, v8, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v8, (a0)
+; V-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v8, v10, a1
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 1
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8bf16_nxv2bf16:
; ZVBB: # %bb.0:
@@ -7489,33 +7787,48 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8bf16_nxv2bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v11, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vslidedown.vx v10, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v10, a0
+; ZVZIP-NEXT: vslidedown.vx v10, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v10, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.vector.interleave4.nxv8bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3)
ret <vscale x 8 x bfloat> %res
}
define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv16bf16_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vsseg4e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a1)
-; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16bf16_nxv4bf16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; V-NEXT: vsseg4e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl1re16.v v10, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl1re16.v v11, (a1)
+; V-NEXT: vl1re16.v v8, (a0)
+; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16bf16_nxv4bf16:
; ZVBB: # %bb.0:
@@ -7539,34 +7852,43 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16bf16_nxv4bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v14, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x bfloat> @llvm.vector.interleave4.nxv16bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3)
ret <vscale x 16 x bfloat> %res
}
define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv32bf16_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT: vsseg4e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl2re16.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re16.v v14, (a1)
-; CHECK-NEXT: vl2re16.v v8, (a0)
-; CHECK-NEXT: vl2re16.v v10, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv32bf16_nxv8bf16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; V-NEXT: vsseg4e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl2re16.v v12, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl2re16.v v14, (a1)
+; V-NEXT: vl2re16.v v8, (a0)
+; V-NEXT: vl2re16.v v10, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv32bf16_nxv8bf16:
; ZVBB: # %bb.0:
@@ -7591,40 +7913,49 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32bf16_nxv8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x bfloat> @llvm.vector.interleave4.nxv32bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3)
ret <vscale x 32 x bfloat> %res
}
define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv4f32_nxv1f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vle32.v v8, (a2)
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv4f32_nxv1f32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 1
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; V-NEXT: vsseg4e32.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: srli a2, a1, 1
+; V-NEXT: add a3, a0, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a2, a4, a2
+; V-NEXT: vle32.v v8, (a2)
+; V-NEXT: vle32.v v9, (a4)
+; V-NEXT: vle32.v v10, (a3)
+; V-NEXT: srli a1, a1, 3
+; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; V-NEXT: vslideup.vx v9, v8, a1
+; V-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; V-NEXT: vle32.v v8, (a0)
+; V-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; V-NEXT: vslideup.vx v8, v10, a1
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 1
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv4f32_nxv1f32:
; ZVBB: # %bb.0:
@@ -7655,33 +7986,48 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv4f32_nxv1f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v11, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 3
+; ZVZIP-NEXT: vslidedown.vx v10, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v10, a0
+; ZVZIP-NEXT: vslidedown.vx v10, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v10, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 4 x float> @llvm.vector.interleave4.nxv4f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3)
ret <vscale x 4 x float> %res
}
define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv8f32_nxv2f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a1)
-; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv8f32_nxv2f32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; V-NEXT: vsseg4e32.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl1re32.v v10, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl1re32.v v11, (a1)
+; V-NEXT: vl1re32.v v8, (a0)
+; V-NEXT: vl1re32.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8f32_nxv2f32:
; ZVBB: # %bb.0:
@@ -7705,34 +8051,43 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv2f32(<vscale x 2 x flo
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8f32_nxv2f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v14, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x float> @llvm.vector.interleave4.nxv8f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3)
ret <vscale x 8 x float> %res
}
define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv16f32_nxv4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl2re32.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re32.v v14, (a1)
-; CHECK-NEXT: vl2re32.v v8, (a0)
-; CHECK-NEXT: vl2re32.v v10, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16f32_nxv4f32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; V-NEXT: vsseg4e32.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl2re32.v v12, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl2re32.v v14, (a1)
+; V-NEXT: vl2re32.v v8, (a0)
+; V-NEXT: vl2re32.v v10, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16f32_nxv4f32:
; ZVBB: # %bb.0:
@@ -7757,33 +8112,42 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16f32_nxv4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x float> @llvm.vector.interleave4.nxv16f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3)
ret <vscale x 16 x float> %res
}
define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv4f64_nxv1f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vsseg4e64.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a1)
-; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv4f64_nxv1f64:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; V-NEXT: vsseg4e64.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl1re64.v v10, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl1re64.v v11, (a1)
+; V-NEXT: vl1re64.v v8, (a0)
+; V-NEXT: vl1re64.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv4f64_nxv1f64:
; ZVBB: # %bb.0:
@@ -7807,34 +8171,43 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv4f64_nxv1f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v14, v8, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 4 x double> @llvm.vector.interleave4.nxv4f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3)
ret <vscale x 4 x double> %res
}
define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3) nounwind {
-; CHECK-LABEL: vector_interleave_nxv8f64_nxv2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vl2re64.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re64.v v14, (a1)
-; CHECK-NEXT: vl2re64.v v8, (a0)
-; CHECK-NEXT: vl2re64.v v10, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv8f64_nxv2f64:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; V-NEXT: vsseg4e64.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: vl2re64.v v12, (a3)
+; V-NEXT: add a1, a3, a1
+; V-NEXT: vl2re64.v v14, (a1)
+; V-NEXT: vl2re64.v v8, (a0)
+; V-NEXT: vl2re64.v v10, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8f64_nxv2f64:
; ZVBB: # %bb.0:
@@ -7859,6 +8232,15 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv2f64(<vscale x 2 x do
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8f64_nxv2f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x double> @llvm.vector.interleave4.nxv6f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3)
ret <vscale x 8 x double> %res
}
@@ -13730,49 +14112,49 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
}
define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5, <vscale x 2 x half> %v6, <vscale x 2 x half> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv16f16_nxv2f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: add a2, t0, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v11, (t0)
-; CHECK-NEXT: vle16.v v9, (a7)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16f16_nxv2f16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; V-NEXT: vsseg8e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: srli a2, a1, 1
+; V-NEXT: add a3, a0, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: add a2, t0, a2
+; V-NEXT: vle16.v v8, (a2)
+; V-NEXT: vle16.v v11, (t0)
+; V-NEXT: vle16.v v9, (a7)
+; V-NEXT: srli a1, a1, 2
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v11, v8, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v10, (a6)
+; V-NEXT: vle16.v v8, (a5)
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v10, v9, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v9, (a4)
+; V-NEXT: vle16.v v12, (a3)
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v9, v8, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v8, (a0)
+; V-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v8, v12, a1
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16f16_nxv2f16:
; ZVBB: # %bb.0:
@@ -13817,41 +14199,66 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16f16_nxv2f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v11, v16
+; ZVZIP-NEXT: vzip.vv v14, v10, v9
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v11, a0
+; ZVZIP-NEXT: vslideup.vx v11, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v12, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x half> @llvm.vector.interleave8.nxv16f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5, <vscale x 2 x half> %v6, <vscale x 2 x half> %v7)
ret <vscale x 16 x half> %res
}
define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv32f16_nxv4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re16.v v15, (a1)
-; CHECK-NEXT: vl1re16.v v12, (a5)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: vl1re16.v v11, (a4)
-; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv32f16_nxv4f16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; V-NEXT: vsseg8e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: add a4, a3, a1
+; V-NEXT: add a5, a4, a1
+; V-NEXT: add a6, a5, a1
+; V-NEXT: add a7, a6, a1
+; V-NEXT: vl1re16.v v14, (a7)
+; V-NEXT: add a1, a7, a1
+; V-NEXT: vl1re16.v v15, (a1)
+; V-NEXT: vl1re16.v v12, (a5)
+; V-NEXT: vl1re16.v v13, (a6)
+; V-NEXT: vl1re16.v v10, (a3)
+; V-NEXT: vl1re16.v v11, (a4)
+; V-NEXT: vl1re16.v v8, (a0)
+; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv32f16_nxv4f16:
; ZVBB: # %bb.0:
@@ -13883,77 +14290,93 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32f16_nxv4f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v11, v15
+; ZVZIP-NEXT: vzip.vv v22, v9, v13
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v22, v20
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v10, v24
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x half> @llvm.vector.interleave8.nxv32f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7)
ret <vscale x 32 x half> %res
}
define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6, <vscale x 8 x half> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv64f16_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e16.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e16.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re16.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re16.v v23, (t0)
-; CHECK-NEXT: vl1re16.v v20, (a6)
-; CHECK-NEXT: vl1re16.v v21, (a7)
-; CHECK-NEXT: vl1re16.v v18, (a4)
-; CHECK-NEXT: vl1re16.v v19, (a5)
-; CHECK-NEXT: vl1re16.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re16.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re16.v v15, (a2)
-; CHECK-NEXT: vl1re16.v v12, (a3)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a4)
-; CHECK-NEXT: vl1re16.v v11, (a5)
-; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv64f16_nxv8f16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e16.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e16.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1re16.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1re16.v v23, (t0)
+; V-NEXT: vl1re16.v v20, (a6)
+; V-NEXT: vl1re16.v v21, (a7)
+; V-NEXT: vl1re16.v v18, (a4)
+; V-NEXT: vl1re16.v v19, (a5)
+; V-NEXT: vl1re16.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1re16.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1re16.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1re16.v v15, (a2)
+; V-NEXT: vl1re16.v v12, (a3)
+; V-NEXT: vl1re16.v v13, (a6)
+; V-NEXT: vl1re16.v v10, (a4)
+; V-NEXT: vl1re16.v v11, (a5)
+; V-NEXT: vl1re16.v v8, (a0)
+; V-NEXT: vl1re16.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv64f16_nxv8f16:
; ZVBB: # %bb.0:
@@ -14021,54 +14444,86 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64f16_nxv8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x half> @llvm.vector.interleave8.nxv64f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6, <vscale x 8 x half> %v7)
ret <vscale x 64 x half> %res
}
define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5, <vscale x 2 x bfloat> %v6, <vscale x 2 x bfloat> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv16bf16_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: add a2, t0, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v11, (t0)
-; CHECK-NEXT: vle16.v v9, (a7)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16bf16_nxv2bf16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; V-NEXT: vsseg8e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: srli a2, a1, 1
+; V-NEXT: add a3, a0, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: add a2, t0, a2
+; V-NEXT: vle16.v v8, (a2)
+; V-NEXT: vle16.v v11, (t0)
+; V-NEXT: vle16.v v9, (a7)
+; V-NEXT: srli a1, a1, 2
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v11, v8, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v10, (a6)
+; V-NEXT: vle16.v v8, (a5)
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v10, v9, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v9, (a4)
+; V-NEXT: vle16.v v12, (a3)
+; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v9, v8, a1
+; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v8, (a0)
+; V-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; V-NEXT: vslideup.vx v8, v12, a1
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16bf16_nxv2bf16:
; ZVBB: # %bb.0:
@@ -14113,41 +14568,66 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16bf16_nxv2bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v11, v16
+; ZVZIP-NEXT: vzip.vv v14, v10, v9
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v11, a0
+; ZVZIP-NEXT: vslideup.vx v11, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v12, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x bfloat> @llvm.vector.interleave8.nxv16bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5, <vscale x 2 x bfloat> %v6, <vscale x 2 x bfloat> %v7)
ret <vscale x 16 x bfloat> %res
}
define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv32bf16_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re16.v v15, (a1)
-; CHECK-NEXT: vl1re16.v v12, (a5)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: vl1re16.v v11, (a4)
-; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv32bf16_nxv4bf16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; V-NEXT: vsseg8e16.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: add a4, a3, a1
+; V-NEXT: add a5, a4, a1
+; V-NEXT: add a6, a5, a1
+; V-NEXT: add a7, a6, a1
+; V-NEXT: vl1re16.v v14, (a7)
+; V-NEXT: add a1, a7, a1
+; V-NEXT: vl1re16.v v15, (a1)
+; V-NEXT: vl1re16.v v12, (a5)
+; V-NEXT: vl1re16.v v13, (a6)
+; V-NEXT: vl1re16.v v10, (a3)
+; V-NEXT: vl1re16.v v11, (a4)
+; V-NEXT: vl1re16.v v8, (a0)
+; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv32bf16_nxv4bf16:
; ZVBB: # %bb.0:
@@ -14179,77 +14659,93 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32bf16_nxv4bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v11, v15
+; ZVZIP-NEXT: vzip.vv v22, v9, v13
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v22, v20
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v10, v24
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x bfloat> @llvm.vector.interleave8.nxv32bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7)
ret <vscale x 32 x bfloat> %res
}
define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6, <vscale x 8 x bfloat> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv64bf16_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e16.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e16.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re16.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re16.v v23, (t0)
-; CHECK-NEXT: vl1re16.v v20, (a6)
-; CHECK-NEXT: vl1re16.v v21, (a7)
-; CHECK-NEXT: vl1re16.v v18, (a4)
-; CHECK-NEXT: vl1re16.v v19, (a5)
-; CHECK-NEXT: vl1re16.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re16.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re16.v v15, (a2)
-; CHECK-NEXT: vl1re16.v v12, (a3)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a4)
-; CHECK-NEXT: vl1re16.v v11, (a5)
-; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv64bf16_nxv8bf16:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e16.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e16.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1re16.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1re16.v v23, (t0)
+; V-NEXT: vl1re16.v v20, (a6)
+; V-NEXT: vl1re16.v v21, (a7)
+; V-NEXT: vl1re16.v v18, (a4)
+; V-NEXT: vl1re16.v v19, (a5)
+; V-NEXT: vl1re16.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1re16.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1re16.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1re16.v v15, (a2)
+; V-NEXT: vl1re16.v v12, (a3)
+; V-NEXT: vl1re16.v v13, (a6)
+; V-NEXT: vl1re16.v v10, (a4)
+; V-NEXT: vl1re16.v v11, (a5)
+; V-NEXT: vl1re16.v v8, (a0)
+; V-NEXT: vl1re16.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv64bf16_nxv8bf16:
; ZVBB: # %bb.0:
@@ -14317,54 +14813,86 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64bf16_nxv8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x bfloat> @llvm.vector.interleave8.nxv64bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6, <vscale x 8 x bfloat> %v7)
ret <vscale x 64 x bfloat> %res
}
define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v5, <vscale x 1 x float> %v6, <vscale x 1 x float> %v8) nounwind {
-; CHECK-LABEL: vector_interleave_nxv8f32_nxv1f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vsseg8e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: add a2, t0, a2
-; CHECK-NEXT: vle32.v v8, (a2)
-; CHECK-NEXT: vle32.v v11, (t0)
-; CHECK-NEXT: vle32.v v9, (a7)
-; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: vle32.v v8, (a5)
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv8f32_nxv1f32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; V-NEXT: vsseg8e32.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: srli a2, a1, 1
+; V-NEXT: add a3, a0, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: add a2, t0, a2
+; V-NEXT: vle32.v v8, (a2)
+; V-NEXT: vle32.v v11, (t0)
+; V-NEXT: vle32.v v9, (a7)
+; V-NEXT: srli a1, a1, 3
+; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; V-NEXT: vslideup.vx v11, v8, a1
+; V-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; V-NEXT: vle32.v v10, (a6)
+; V-NEXT: vle32.v v8, (a5)
+; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; V-NEXT: vslideup.vx v10, v9, a1
+; V-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; V-NEXT: vle32.v v9, (a4)
+; V-NEXT: vle32.v v12, (a3)
+; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; V-NEXT: vslideup.vx v9, v8, a1
+; V-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; V-NEXT: vle32.v v8, (a0)
+; V-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; V-NEXT: vslideup.vx v8, v12, a1
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 2
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8f32_nxv1f32:
; ZVBB: # %bb.0:
@@ -14409,41 +14937,66 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8f32_nxv1f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v11, v16
+; ZVZIP-NEXT: vzip.vv v14, v10, v9
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 3
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v11, a0
+; ZVZIP-NEXT: vslideup.vx v11, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v12, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x float> @llvm.vector.interleave8.nxv8f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v5, <vscale x 1 x float> %v6, <vscale x 1 x float> %v8)
ret <vscale x 8 x float> %res
}
define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5, <vscale x 2 x float> %v6, <vscale x 2 x float> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv16f32_nxv2f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsseg8e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re32.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re32.v v15, (a1)
-; CHECK-NEXT: vl1re32.v v12, (a5)
-; CHECK-NEXT: vl1re32.v v13, (a6)
-; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: vl1re32.v v11, (a4)
-; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16f32_nxv2f32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; V-NEXT: vsseg8e32.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: add a4, a3, a1
+; V-NEXT: add a5, a4, a1
+; V-NEXT: add a6, a5, a1
+; V-NEXT: add a7, a6, a1
+; V-NEXT: vl1re32.v v14, (a7)
+; V-NEXT: add a1, a7, a1
+; V-NEXT: vl1re32.v v15, (a1)
+; V-NEXT: vl1re32.v v12, (a5)
+; V-NEXT: vl1re32.v v13, (a6)
+; V-NEXT: vl1re32.v v10, (a3)
+; V-NEXT: vl1re32.v v11, (a4)
+; V-NEXT: vl1re32.v v8, (a0)
+; V-NEXT: vl1re32.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16f32_nxv2f32:
; ZVBB: # %bb.0:
@@ -14475,77 +15028,93 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16f32_nxv2f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v11, v15
+; ZVZIP-NEXT: vzip.vv v22, v9, v13
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v22, v20
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v10, v24
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x float> @llvm.vector.interleave8.nxv16f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5, <vscale x 2 x float> %v6, <vscale x 2 x float> %v7)
ret <vscale x 16 x float> %res
}
define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6, <vscale x 4 x float> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv32f32_nxv4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e32.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e32.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re32.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re32.v v23, (t0)
-; CHECK-NEXT: vl1re32.v v20, (a6)
-; CHECK-NEXT: vl1re32.v v21, (a7)
-; CHECK-NEXT: vl1re32.v v18, (a4)
-; CHECK-NEXT: vl1re32.v v19, (a5)
-; CHECK-NEXT: vl1re32.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re32.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re32.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re32.v v15, (a2)
-; CHECK-NEXT: vl1re32.v v12, (a3)
-; CHECK-NEXT: vl1re32.v v13, (a6)
-; CHECK-NEXT: vl1re32.v v10, (a4)
-; CHECK-NEXT: vl1re32.v v11, (a5)
-; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv32f32_nxv4f32:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e32.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e32.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1re32.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1re32.v v23, (t0)
+; V-NEXT: vl1re32.v v20, (a6)
+; V-NEXT: vl1re32.v v21, (a7)
+; V-NEXT: vl1re32.v v18, (a4)
+; V-NEXT: vl1re32.v v19, (a5)
+; V-NEXT: vl1re32.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1re32.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1re32.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1re32.v v15, (a2)
+; V-NEXT: vl1re32.v v12, (a3)
+; V-NEXT: vl1re32.v v13, (a6)
+; V-NEXT: vl1re32.v v10, (a4)
+; V-NEXT: vl1re32.v v11, (a5)
+; V-NEXT: vl1re32.v v8, (a0)
+; V-NEXT: vl1re32.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv32f32_nxv4f32:
; ZVBB: # %bb.0:
@@ -14613,41 +15182,73 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32f32_nxv4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x float> @llvm.vector.interleave8.nxv32f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6, <vscale x 4 x float> %v7)
ret <vscale x 32 x float> %res
}
define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5, <vscale x 1 x double> %v6, <vscale x 1 x double> %v8) nounwind {
-; CHECK-LABEL: vector_interleave_nxv8f64_nxv1f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vsseg8e64.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re64.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re64.v v15, (a1)
-; CHECK-NEXT: vl1re64.v v12, (a5)
-; CHECK-NEXT: vl1re64.v v13, (a6)
-; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: vl1re64.v v11, (a4)
-; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv8f64_nxv1f64:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; V-NEXT: vsseg8e64.v v8, (a0)
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: add a2, a0, a1
+; V-NEXT: add a3, a2, a1
+; V-NEXT: add a4, a3, a1
+; V-NEXT: add a5, a4, a1
+; V-NEXT: add a6, a5, a1
+; V-NEXT: add a7, a6, a1
+; V-NEXT: vl1re64.v v14, (a7)
+; V-NEXT: add a1, a7, a1
+; V-NEXT: vl1re64.v v15, (a1)
+; V-NEXT: vl1re64.v v12, (a5)
+; V-NEXT: vl1re64.v v13, (a6)
+; V-NEXT: vl1re64.v v10, (a3)
+; V-NEXT: vl1re64.v v11, (a4)
+; V-NEXT: vl1re64.v v8, (a0)
+; V-NEXT: vl1re64.v v9, (a2)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8f64_nxv1f64:
; ZVBB: # %bb.0:
@@ -14679,77 +15280,93 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8f64_nxv1f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v11, v15
+; ZVZIP-NEXT: vzip.vv v22, v9, v13
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v22, v20
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v10, v24
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x double> @llvm.vector.interleave8.nxv8f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5, <vscale x 1 x double> %v6, <vscale x 1 x double> %v8)
ret <vscale x 8 x double> %res
}
define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6, <vscale x 2 x double> %v7) nounwind {
-; CHECK-LABEL: vector_interleave_nxv16f64_nxv2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-NEXT: vmv2r.v v30, v20
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv2r.v v26, v12
-; CHECK-NEXT: vmv2r.v v24, v8
-; CHECK-NEXT: vmv1r.v v1, v25
-; CHECK-NEXT: vmv1r.v v2, v11
-; CHECK-NEXT: vmv1r.v v3, v27
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v29
-; CHECK-NEXT: vmv1r.v v6, v19
-; CHECK-NEXT: vmv1r.v v7, v31
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg8e64.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v25, v10
-; CHECK-NEXT: vmv1r.v v27, v14
-; CHECK-NEXT: vmv1r.v v29, v18
-; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsseg8e64.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re64.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re64.v v23, (t0)
-; CHECK-NEXT: vl1re64.v v20, (a6)
-; CHECK-NEXT: vl1re64.v v21, (a7)
-; CHECK-NEXT: vl1re64.v v18, (a4)
-; CHECK-NEXT: vl1re64.v v19, (a5)
-; CHECK-NEXT: vl1re64.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re64.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re64.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re64.v v15, (a2)
-; CHECK-NEXT: vl1re64.v v12, (a3)
-; CHECK-NEXT: vl1re64.v v13, (a6)
-; CHECK-NEXT: vl1re64.v v10, (a4)
-; CHECK-NEXT: vl1re64.v v11, (a5)
-; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; V-LABEL: vector_interleave_nxv16f64_nxv2f64:
+; V: # %bb.0:
+; V-NEXT: addi sp, sp, -16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: sub sp, sp, a0
+; V-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; V-NEXT: vmv2r.v v30, v20
+; V-NEXT: vmv2r.v v28, v16
+; V-NEXT: vmv2r.v v26, v12
+; V-NEXT: vmv2r.v v24, v8
+; V-NEXT: vmv1r.v v1, v25
+; V-NEXT: vmv1r.v v2, v11
+; V-NEXT: vmv1r.v v3, v27
+; V-NEXT: vmv1r.v v4, v15
+; V-NEXT: vmv1r.v v5, v29
+; V-NEXT: vmv1r.v v6, v19
+; V-NEXT: vmv1r.v v7, v31
+; V-NEXT: vmv1r.v v8, v23
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a1, a1, 3
+; V-NEXT: add a1, sp, a1
+; V-NEXT: addi a1, a1, 16
+; V-NEXT: vsseg8e64.v v1, (a1)
+; V-NEXT: vmv1r.v v25, v10
+; V-NEXT: vmv1r.v v27, v14
+; V-NEXT: vmv1r.v v29, v18
+; V-NEXT: vmv1r.v v31, v22
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsseg8e64.v v24, (a0)
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: add a3, a1, a2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: add a6, a5, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: add t0, a7, a2
+; V-NEXT: vl1re64.v v22, (t0)
+; V-NEXT: add t0, t0, a2
+; V-NEXT: vl1re64.v v23, (t0)
+; V-NEXT: vl1re64.v v20, (a6)
+; V-NEXT: vl1re64.v v21, (a7)
+; V-NEXT: vl1re64.v v18, (a4)
+; V-NEXT: vl1re64.v v19, (a5)
+; V-NEXT: vl1re64.v v16, (a1)
+; V-NEXT: add a1, a0, a2
+; V-NEXT: add a4, a1, a2
+; V-NEXT: add a5, a4, a2
+; V-NEXT: vl1re64.v v17, (a3)
+; V-NEXT: add a3, a5, a2
+; V-NEXT: add a6, a3, a2
+; V-NEXT: add a7, a6, a2
+; V-NEXT: vl1re64.v v14, (a7)
+; V-NEXT: add a2, a7, a2
+; V-NEXT: vl1re64.v v15, (a2)
+; V-NEXT: vl1re64.v v12, (a3)
+; V-NEXT: vl1re64.v v13, (a6)
+; V-NEXT: vl1re64.v v10, (a4)
+; V-NEXT: vl1re64.v v11, (a5)
+; V-NEXT: vl1re64.v v8, (a0)
+; V-NEXT: vl1re64.v v9, (a1)
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 4
+; V-NEXT: add sp, sp, a0
+; V-NEXT: addi sp, sp, 16
+; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv16f64_nxv2f64:
; ZVBB: # %bb.0:
@@ -14817,6 +15434,38 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv2f64(<vscale x 2 x
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16f64_nxv2f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v28, v22
+; ZVZIP-NEXT: vmv2r.v v24, v20
+; ZVZIP-NEXT: vmv2r.v v30, v18
+; ZVZIP-NEXT: vmv2r.v v26, v16
+; ZVZIP-NEXT: vzip.vv v16, v15, v29
+; ZVZIP-NEXT: vzip.vv v18, v11, v31
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v4, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v13, v25
+; ZVZIP-NEXT: vzip.vv v18, v9, v27
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v0, v18, v16
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v0, v4
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v6, v14, v28
+; ZVZIP-NEXT: vzip.vv v14, v10, v30
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v28, v14, v6
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v10, v12, v24
+; ZVZIP-NEXT: vzip.vv v12, v8, v26
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v10
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v28
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x double> @llvm.vector.interleave8.nxv16f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6, <vscale x 2 x double> %v7)
ret <vscale x 16 x double> %res
}
>From a724a1d2bd7dbe006bbe9c355cb4cdeaa1498dd1 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Wed, 9 Sep 2026 14:24:36 -0700
Subject: [PATCH 2/4] fixup! Revise comment
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e7bba4b7cf02f..2c5950442ecc5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14670,7 +14670,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
// some of the insert/extract subvectors will be turned into
// VSLIDEUP/DOWN_VL right away and stay thru the rest of the codegen.
// We could write additional combining rules for those VSLIDEUP/DOWN_VL
- // but I thought it'll be a lot easier to just not generate
+ // but it'll probably be a lot easier to just not generate
// VECTOR_INTERLEAVE2 + CONCAT_VECTORS in the first place here.
Operands[I / 2] = lowerZvzipVZIP(V1, V2, DL, DAG, Subtarget);
}
>From 2d16e60d3e73a247758a96a3f705a245eca19b72 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Thu, 10 Sep 2026 09:56:01 -0700
Subject: [PATCH 3/4] fixup! Do not freeze the operands
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2c5950442ecc5..f71ef490d7edb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14660,8 +14660,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
assert(Operands[I].getValueType().isSimple() &&
isLegalVTForZvzipOperand(Operands[I].getSimpleValueType(),
Subtarget));
- SDValue V1 = DAG.getFreeze(Operands[I]);
- SDValue V2 = DAG.getFreeze(Operands[I + 1]);
// Do not generate VECTOR_INTERLEAVE2 + CONCAT_VECTORS here. Because
// when those two nodes are subsequently lowered, there will
// be a bunch of insert_subvector and extract_subvector generated.
@@ -14672,7 +14670,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
// We could write additional combining rules for those VSLIDEUP/DOWN_VL
// but it'll probably be a lot easier to just not generate
// VECTOR_INTERLEAVE2 + CONCAT_VECTORS in the first place here.
- Operands[I / 2] = lowerZvzipVZIP(V1, V2, DL, DAG, Subtarget);
+ Operands[I / 2] =
+ lowerZvzipVZIP(Operands[I], Operands[I + 1], DL, DAG, Subtarget);
}
}
>From 017933c476d26856435640e6dd1fe9efdec2b152 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 11 Sep 2026 11:08:35 -0700
Subject: [PATCH 4/4] fixup! Account for cases where the size exceeds MVT
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 12001 +++++++++++++++-
2 files changed, 12000 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f71ef490d7edb..3c6fa82d0d476 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14641,7 +14641,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
SDValue Interleaved;
- if (Subtarget.hasStdExtZvzip() && (Factor == 4 || Factor == 8)) {
+ if (Subtarget.hasStdExtZvzip() && (Factor == 4 || Factor == 8) &&
+ VecVT.changeVectorElementCount(VecVT.getVectorElementCount() * Factor)
+ .isValid()) {
// Interleave by a tree of vzip.vv instructions.
SmallVector<SDValue, 8> Operands(Op->op_values());
// First, reorder the operands.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 9296e15920121..354175a2adfc3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -1,10 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck -check-prefixes=CHECK %s
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck -check-prefixes=CHECK %s
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck -check-prefixes=CHECK,CHECK-RV32 %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck -check-prefixes=CHECK,CHECK-RV64 %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV32
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV64
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip,+zvl2048b | FileCheck -check-prefixes=ZVZIP-WIDE,ZVZIP-WIDE-RV32 %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip,+zvl2048b | FileCheck -check-prefixes=ZVZIP-WIDE,ZVZIP-WIDE-RV64 %s
; Integers
@@ -59,6 +61,21 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v32i1_v16i1:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v0, v8, 2
+; ZVZIP-WIDE-NEXT: li a0, 32
+; ZVZIP-WIDE-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vmv.v.i v8, 0
+; ZVZIP-WIDE-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVZIP-WIDE-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v9, v8, 16
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vmsne.vi v0, v10, 0
+; ZVZIP-WIDE-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
}
@@ -90,6 +107,13 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v16i16_v8i16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
ret <16 x i16> %res
}
@@ -122,6 +146,13 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v8i32_v4i32:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
ret <8 x i32> %res
}
@@ -164,6 +195,14 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v4i64_v2i64:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-WIDE-NEXT: vmv1r.v v10, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v11, v8
+; ZVZIP-WIDE-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
ret <4 x i64> %res
}
@@ -225,6 +264,25 @@ define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave3_v6i32_v2i32:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg3e32.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 16
+; ZVZIP-WIDE-NEXT: vle32.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle32.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vle32.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <6 x i32> @llvm.vector.interleave3.v6i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)
ret <6 x i32> %res
}
@@ -294,10 +352,11409 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave4_v8i32_v2i32:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-WIDE-NEXT: vzip.vv v9, v8, v10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v9, v12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v9, v10, 2
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v10, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v9, v10, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
}
+; <2048 x i8> exceeds the largest MVT
+define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8> %v1, <512 x i8> %v2, <512 x i8> %v3) nounwind {
+;
+;
+; CHECK-RV32-LABEL: vector_interleave4_v512i8_v2048i8:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: addi sp, sp, -2032
+; CHECK-RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: sw s1, 2020(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: sw s2, 2016(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: sw s3, 2012(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: sw s4, 2008(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: sw s5, 2004(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: sw s6, 2000(sp) # 4-byte Folded Spill
+; CHECK-RV32-NEXT: addi s0, sp, 2032
+; CHECK-RV32-NEXT: addi sp, sp, -80
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 3
+; CHECK-RV32-NEXT: mv a4, a2
+; CHECK-RV32-NEXT: slli a2, a2, 1
+; CHECK-RV32-NEXT: add a4, a4, a2
+; CHECK-RV32-NEXT: slli a2, a2, 1
+; CHECK-RV32-NEXT: add a4, a4, a2
+; CHECK-RV32-NEXT: slli a2, a2, 3
+; CHECK-RV32-NEXT: add a2, a2, a4
+; CHECK-RV32-NEXT: sub sp, sp, a2
+; CHECK-RV32-NEXT: andi sp, sp, -32
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 3
+; CHECK-RV32-NEXT: mv a4, a2
+; CHECK-RV32-NEXT: slli a2, a2, 2
+; CHECK-RV32-NEXT: add a4, a4, a2
+; CHECK-RV32-NEXT: slli a2, a2, 3
+; CHECK-RV32-NEXT: add a2, a2, a4
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 2047
+; CHECK-RV32-NEXT: addi a2, a2, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 8
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 2047
+; CHECK-RV32-NEXT: addi a2, a2, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: li a2, 128
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v16, (a7)
+; CHECK-RV32-NEXT: csrr a4, vlenb
+; CHECK-RV32-NEXT: slli a4, a4, 4
+; CHECK-RV32-NEXT: mv a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 3
+; CHECK-RV32-NEXT: add a4, a4, a5
+; CHECK-RV32-NEXT: add a4, sp, a4
+; CHECK-RV32-NEXT: addi a4, a4, 2047
+; CHECK-RV32-NEXT: addi a4, a4, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a4, vlenb
+; CHECK-RV32-NEXT: slli a4, a4, 3
+; CHECK-RV32-NEXT: mv a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a4, a4, a5
+; CHECK-RV32-NEXT: add a4, sp, a4
+; CHECK-RV32-NEXT: addi a4, a4, 2047
+; CHECK-RV32-NEXT: addi a4, a4, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a4, a7, 256
+; CHECK-RV32-NEXT: vle8.v v16, (a4)
+; CHECK-RV32-NEXT: csrr a4, vlenb
+; CHECK-RV32-NEXT: slli a4, a4, 5
+; CHECK-RV32-NEXT: mv a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 3
+; CHECK-RV32-NEXT: add a4, a4, a5
+; CHECK-RV32-NEXT: add a4, sp, a4
+; CHECK-RV32-NEXT: addi a4, a4, 2047
+; CHECK-RV32-NEXT: addi a4, a4, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a4, a1, 128
+; CHECK-RV32-NEXT: vle8.v v24, (a4)
+; CHECK-RV32-NEXT: csrr a4, vlenb
+; CHECK-RV32-NEXT: slli a4, a4, 4
+; CHECK-RV32-NEXT: mv a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a4, a4, a5
+; CHECK-RV32-NEXT: add a4, sp, a4
+; CHECK-RV32-NEXT: addi a4, a4, 2047
+; CHECK-RV32-NEXT: addi a4, a4, 33
+; CHECK-RV32-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a4, a3, 384
+; CHECK-RV32-NEXT: vle8.v v16, (a4)
+; CHECK-RV32-NEXT: csrr a4, vlenb
+; CHECK-RV32-NEXT: slli a4, a4, 3
+; CHECK-RV32-NEXT: mv a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 2
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a5, a5, a4
+; CHECK-RV32-NEXT: slli a4, a4, 1
+; CHECK-RV32-NEXT: add a4, a4, a5
+; CHECK-RV32-NEXT: add a4, sp, a4
+; CHECK-RV32-NEXT: addi a4, a4, 2047
+; CHECK-RV32-NEXT: addi a4, a4, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: li a4, 64
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v24, a4
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a5, a7, 384
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (a5)
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 5
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v0, v16, a4
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a5, s0, 768
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v24, (a5)
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 4
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a5, a3, 256
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v16, (a5)
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 4
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v24, a4
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 4
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v16, (a1)
+; CHECK-RV32-NEXT: csrr a1, vlenb
+; CHECK-RV32-NEXT: slli a1, a1, 4
+; CHECK-RV32-NEXT: mv a5, a1
+; CHECK-RV32-NEXT: slli a1, a1, 4
+; CHECK-RV32-NEXT: add a1, a1, a5
+; CHECK-RV32-NEXT: add a1, sp, a1
+; CHECK-RV32-NEXT: addi a1, a1, 2047
+; CHECK-RV32-NEXT: addi a1, a1, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: li a1, 32
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v20, v0, a1
+; CHECK-RV32-NEXT: addi a5, a7, 128
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v0, (a5)
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 4
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v16, v8, a1
+; CHECK-RV32-NEXT: addi a3, a3, 128
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vmv2r.v v18, v20
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV32-NEXT: vmv2r.v v22, v24
+; CHECK-RV32-NEXT: addi a3, sp, 672
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v16, (a3)
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a4
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 5
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v16, v16, a4
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 4
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a5, s0, 512
+; CHECK-RV32-NEXT: vslidedown.vx v0, v0, a4
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 3
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 2
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (a5)
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 7
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v20, v16, a1
+; CHECK-RV32-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v16, v8, a1
+; CHECK-RV32-NEXT: vmv2r.v v18, v20
+; CHECK-RV32-NEXT: vslidedown.vx v20, v0, a1
+; CHECK-RV32-NEXT: vmv2r.v v22, v24
+; CHECK-RV32-NEXT: addi a5, sp, 1696
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v16, (a5)
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 4
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 4
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v0, v16, a4
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 4
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 2
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 3
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 4
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v24, v16, a4
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 3
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 2
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a6, s0, 640
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 5
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a4
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 5
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 2
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (a6)
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 6
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 5
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v20, v24, a1
+; CHECK-RV32-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV32-NEXT: vslidedown.vx v16, v0, a1
+; CHECK-RV32-NEXT: vmv2r.v v18, v20
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 5
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 2
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV32-NEXT: vmv2r.v v22, v24
+; CHECK-RV32-NEXT: addi s5, sp, 1184
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v16, (s5)
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 3
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 2
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v20, v16, a1
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 3
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 2
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 4
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v16, v0, a1
+; CHECK-RV32-NEXT: vmv2r.v v18, v20
+; CHECK-RV32-NEXT: csrr a6, vlenb
+; CHECK-RV32-NEXT: slli a6, a6, 5
+; CHECK-RV32-NEXT: mv a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a7, a7, a6
+; CHECK-RV32-NEXT: slli a6, a6, 1
+; CHECK-RV32-NEXT: add a6, a6, a7
+; CHECK-RV32-NEXT: add a6, sp, a6
+; CHECK-RV32-NEXT: addi a6, a6, 2047
+; CHECK-RV32-NEXT: addi a6, a6, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV32-NEXT: vmv2r.v v22, v24
+; CHECK-RV32-NEXT: addi a6, sp, 928
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v16, (a6)
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 8
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v16, v8, a4
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 6
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a7, s0, 384
+; CHECK-RV32-NEXT: csrr t0, vlenb
+; CHECK-RV32-NEXT: slli t0, t0, 4
+; CHECK-RV32-NEXT: mv t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 1
+; CHECK-RV32-NEXT: add t1, t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 3
+; CHECK-RV32-NEXT: add t0, t0, t1
+; CHECK-RV32-NEXT: add t0, sp, t0
+; CHECK-RV32-NEXT: addi t0, t0, 2047
+; CHECK-RV32-NEXT: addi t0, t0, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV32-NEXT: csrr t0, vlenb
+; CHECK-RV32-NEXT: slli t0, t0, 4
+; CHECK-RV32-NEXT: mv t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 3
+; CHECK-RV32-NEXT: add t0, t0, t1
+; CHECK-RV32-NEXT: add t0, sp, t0
+; CHECK-RV32-NEXT: addi t0, t0, 2047
+; CHECK-RV32-NEXT: addi t0, t0, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vle8.v v24, (a7)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v24, a4
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v12, v16, a1
+; CHECK-RV32-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v8, v0, a1
+; CHECK-RV32-NEXT: vmv2r.v v10, v12
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 4
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v12, v0, a1
+; CHECK-RV32-NEXT: vmv2r.v v14, v20
+; CHECK-RV32-NEXT: addi s4, sp, 160
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (s4)
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 5
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v12, v16, a1
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 2
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 3
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v4, v16, a1
+; CHECK-RV32-NEXT: vmv2r.v v6, v8
+; CHECK-RV32-NEXT: csrr a7, vlenb
+; CHECK-RV32-NEXT: slli a7, a7, 4
+; CHECK-RV32-NEXT: mv t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 2
+; CHECK-RV32-NEXT: add t0, t0, a7
+; CHECK-RV32-NEXT: slli a7, a7, 1
+; CHECK-RV32-NEXT: add a7, a7, t0
+; CHECK-RV32-NEXT: add a7, sp, a7
+; CHECK-RV32-NEXT: addi a7, a7, 2047
+; CHECK-RV32-NEXT: addi a7, a7, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a1
+; CHECK-RV32-NEXT: vmv2r.v v10, v12
+; CHECK-RV32-NEXT: addi a7, sp, 1952
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v4, (a7)
+; CHECK-RV32-NEXT: csrr t0, vlenb
+; CHECK-RV32-NEXT: slli t0, t0, 3
+; CHECK-RV32-NEXT: mv t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 1
+; CHECK-RV32-NEXT: add t1, t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 4
+; CHECK-RV32-NEXT: add t0, t0, t1
+; CHECK-RV32-NEXT: add t0, sp, t0
+; CHECK-RV32-NEXT: addi t0, t0, 2047
+; CHECK-RV32-NEXT: addi t0, t0, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-RV32-NEXT: csrr t0, vlenb
+; CHECK-RV32-NEXT: slli t0, t0, 6
+; CHECK-RV32-NEXT: mv t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 1
+; CHECK-RV32-NEXT: add t0, t0, t1
+; CHECK-RV32-NEXT: add t0, sp, t0
+; CHECK-RV32-NEXT: addi t0, t0, 2047
+; CHECK-RV32-NEXT: addi t0, t0, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v12, v16, a1
+; CHECK-RV32-NEXT: csrr t0, vlenb
+; CHECK-RV32-NEXT: slli t0, t0, 4
+; CHECK-RV32-NEXT: mv t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 4
+; CHECK-RV32-NEXT: add t0, t0, t1
+; CHECK-RV32-NEXT: add t0, sp, t0
+; CHECK-RV32-NEXT: addi t0, t0, 2047
+; CHECK-RV32-NEXT: addi t0, t0, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v4, v16, a1
+; CHECK-RV32-NEXT: vmv2r.v v6, v8
+; CHECK-RV32-NEXT: csrr t0, vlenb
+; CHECK-RV32-NEXT: slli t0, t0, 5
+; CHECK-RV32-NEXT: mv t1, t0
+; CHECK-RV32-NEXT: slli t0, t0, 3
+; CHECK-RV32-NEXT: add t0, t0, t1
+; CHECK-RV32-NEXT: add t0, sp, t0
+; CHECK-RV32-NEXT: addi t0, t0, 2047
+; CHECK-RV32-NEXT: addi t0, t0, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a1
+; CHECK-RV32-NEXT: vmv2r.v v10, v12
+; CHECK-RV32-NEXT: addi t0, sp, 1440
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v4, (t0)
+; CHECK-RV32-NEXT: csrr t1, vlenb
+; CHECK-RV32-NEXT: slli t1, t1, 3
+; CHECK-RV32-NEXT: mv t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 2
+; CHECK-RV32-NEXT: add t1, t1, t2
+; CHECK-RV32-NEXT: add t1, sp, t1
+; CHECK-RV32-NEXT: addi t1, t1, 2047
+; CHECK-RV32-NEXT: addi t1, t1, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t1, vlenb
+; CHECK-RV32-NEXT: slli t1, t1, 3
+; CHECK-RV32-NEXT: mv t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t1, t1, t2
+; CHECK-RV32-NEXT: add t1, sp, t1
+; CHECK-RV32-NEXT: addi t1, t1, 2047
+; CHECK-RV32-NEXT: addi t1, t1, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t1, vlenb
+; CHECK-RV32-NEXT: slli t1, t1, 4
+; CHECK-RV32-NEXT: mv t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 2
+; CHECK-RV32-NEXT: add t1, t1, t2
+; CHECK-RV32-NEXT: add t1, sp, t1
+; CHECK-RV32-NEXT: addi t1, t1, 2047
+; CHECK-RV32-NEXT: addi t1, t1, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: csrr t1, vlenb
+; CHECK-RV32-NEXT: slli t1, t1, 3
+; CHECK-RV32-NEXT: mv t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 4
+; CHECK-RV32-NEXT: add t1, t1, t2
+; CHECK-RV32-NEXT: add t1, sp, t1
+; CHECK-RV32-NEXT: addi t1, t1, 2047
+; CHECK-RV32-NEXT: addi t1, t1, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v14, v16
+; CHECK-RV32-NEXT: addi s3, sp, 544
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (s3)
+; CHECK-RV32-NEXT: csrr t1, vlenb
+; CHECK-RV32-NEXT: slli t1, t1, 3
+; CHECK-RV32-NEXT: mv t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t1, t1, t2
+; CHECK-RV32-NEXT: add t1, sp, t1
+; CHECK-RV32-NEXT: addi t1, t1, 2047
+; CHECK-RV32-NEXT: addi t1, t1, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-RV32-NEXT: vslidedown.vx v12, v24, a1
+; CHECK-RV32-NEXT: csrr t1, vlenb
+; CHECK-RV32-NEXT: slli t1, t1, 8
+; CHECK-RV32-NEXT: add t1, sp, t1
+; CHECK-RV32-NEXT: addi t1, t1, 2047
+; CHECK-RV32-NEXT: addi t1, t1, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v4, v16, a1
+; CHECK-RV32-NEXT: vmv2r.v v6, v8
+; CHECK-RV32-NEXT: csrr t1, vlenb
+; CHECK-RV32-NEXT: slli t1, t1, 4
+; CHECK-RV32-NEXT: mv t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 1
+; CHECK-RV32-NEXT: add t2, t2, t1
+; CHECK-RV32-NEXT: slli t1, t1, 3
+; CHECK-RV32-NEXT: add t1, t1, t2
+; CHECK-RV32-NEXT: add t1, sp, t1
+; CHECK-RV32-NEXT: addi t1, t1, 2047
+; CHECK-RV32-NEXT: addi t1, t1, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a1
+; CHECK-RV32-NEXT: vmv2r.v v10, v12
+; CHECK-RV32-NEXT: addi t1, sp, 416
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vsseg4e8.v v4, (t1)
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 3
+; CHECK-RV32-NEXT: mv t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 2
+; CHECK-RV32-NEXT: add t3, t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 2
+; CHECK-RV32-NEXT: add t2, t2, t3
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 4
+; CHECK-RV32-NEXT: mv t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 1
+; CHECK-RV32-NEXT: add t3, t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 1
+; CHECK-RV32-NEXT: add t2, t2, t3
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 3
+; CHECK-RV32-NEXT: mv t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 2
+; CHECK-RV32-NEXT: add t3, t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 1
+; CHECK-RV32-NEXT: add t2, t2, t3
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 7
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v14, v16
+; CHECK-RV32-NEXT: addi s2, sp, 1568
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (s2)
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 4
+; CHECK-RV32-NEXT: mv t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 2
+; CHECK-RV32-NEXT: add t2, t2, t3
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 3
+; CHECK-RV32-NEXT: mv t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 1
+; CHECK-RV32-NEXT: add t3, t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 2
+; CHECK-RV32-NEXT: add t2, t2, t3
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 5
+; CHECK-RV32-NEXT: mv t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 2
+; CHECK-RV32-NEXT: add t2, t2, t3
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: csrr t2, vlenb
+; CHECK-RV32-NEXT: slli t2, t2, 5
+; CHECK-RV32-NEXT: mv t3, t2
+; CHECK-RV32-NEXT: slli t2, t2, 1
+; CHECK-RV32-NEXT: add t2, t2, t3
+; CHECK-RV32-NEXT: add t2, sp, t2
+; CHECK-RV32-NEXT: addi t2, t2, 2047
+; CHECK-RV32-NEXT: addi t2, t2, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v14, v16
+; CHECK-RV32-NEXT: addi t2, sp, 1056
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (t2)
+; CHECK-RV32-NEXT: csrr t3, vlenb
+; CHECK-RV32-NEXT: slli t3, t3, 4
+; CHECK-RV32-NEXT: mv t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t4, t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t4, t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t3, t3, t4
+; CHECK-RV32-NEXT: add t3, sp, t3
+; CHECK-RV32-NEXT: addi t3, t3, 2047
+; CHECK-RV32-NEXT: addi t3, t3, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t3, vlenb
+; CHECK-RV32-NEXT: slli t3, t3, 3
+; CHECK-RV32-NEXT: mv t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 2
+; CHECK-RV32-NEXT: add t4, t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t4, t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t3, t3, t4
+; CHECK-RV32-NEXT: add t3, sp, t3
+; CHECK-RV32-NEXT: addi t3, t3, 2047
+; CHECK-RV32-NEXT: addi t3, t3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t3, vlenb
+; CHECK-RV32-NEXT: slli t3, t3, 5
+; CHECK-RV32-NEXT: mv t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t4, t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t3, t3, t4
+; CHECK-RV32-NEXT: add t3, sp, t3
+; CHECK-RV32-NEXT: addi t3, t3, 2047
+; CHECK-RV32-NEXT: addi t3, t3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: csrr t3, vlenb
+; CHECK-RV32-NEXT: slli t3, t3, 3
+; CHECK-RV32-NEXT: mv t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t4, t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 2
+; CHECK-RV32-NEXT: add t4, t4, t3
+; CHECK-RV32-NEXT: slli t3, t3, 1
+; CHECK-RV32-NEXT: add t3, t3, t4
+; CHECK-RV32-NEXT: add t3, sp, t3
+; CHECK-RV32-NEXT: addi t3, t3, 2047
+; CHECK-RV32-NEXT: addi t3, t3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v14, v16
+; CHECK-RV32-NEXT: addi t3, sp, 800
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (t3)
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: mv t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 1
+; CHECK-RV32-NEXT: add t5, t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: add t4, t4, t5
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 6
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 4
+; CHECK-RV32-NEXT: mv t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: add t4, t4, t5
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: mv t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: add t4, t4, t5
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v14, v16
+; CHECK-RV32-NEXT: addi s1, sp, 32
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (s1)
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: mv t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 2
+; CHECK-RV32-NEXT: add t5, t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: add t4, t4, t5
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: mv t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 5
+; CHECK-RV32-NEXT: add t4, t4, t5
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 4
+; CHECK-RV32-NEXT: mv t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 2
+; CHECK-RV32-NEXT: add t5, t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 1
+; CHECK-RV32-NEXT: add t4, t4, t5
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: csrr t4, vlenb
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: mv t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 3
+; CHECK-RV32-NEXT: add t5, t5, t4
+; CHECK-RV32-NEXT: slli t4, t4, 1
+; CHECK-RV32-NEXT: add t4, t4, t5
+; CHECK-RV32-NEXT: add t4, sp, t4
+; CHECK-RV32-NEXT: addi t4, t4, 2047
+; CHECK-RV32-NEXT: addi t4, t4, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v14, v16
+; CHECK-RV32-NEXT: addi t4, sp, 1824
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (t4)
+; CHECK-RV32-NEXT: csrr t5, vlenb
+; CHECK-RV32-NEXT: slli t5, t5, 4
+; CHECK-RV32-NEXT: mv t6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 4
+; CHECK-RV32-NEXT: add t5, t5, t6
+; CHECK-RV32-NEXT: add t5, sp, t5
+; CHECK-RV32-NEXT: addi t5, t5, 2047
+; CHECK-RV32-NEXT: addi t5, t5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t5, vlenb
+; CHECK-RV32-NEXT: slli t5, t5, 3
+; CHECK-RV32-NEXT: mv t6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 1
+; CHECK-RV32-NEXT: add t6, t6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 4
+; CHECK-RV32-NEXT: add t5, t5, t6
+; CHECK-RV32-NEXT: add t5, sp, t5
+; CHECK-RV32-NEXT: addi t5, t5, 2047
+; CHECK-RV32-NEXT: addi t5, t5, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t5, vlenb
+; CHECK-RV32-NEXT: slli t5, t5, 5
+; CHECK-RV32-NEXT: mv t6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 3
+; CHECK-RV32-NEXT: add t5, t5, t6
+; CHECK-RV32-NEXT: add t5, sp, t5
+; CHECK-RV32-NEXT: addi t5, t5, 2047
+; CHECK-RV32-NEXT: addi t5, t5, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: csrr t5, vlenb
+; CHECK-RV32-NEXT: slli t5, t5, 6
+; CHECK-RV32-NEXT: mv t6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 1
+; CHECK-RV32-NEXT: add t5, t5, t6
+; CHECK-RV32-NEXT: add t5, sp, t5
+; CHECK-RV32-NEXT: addi t5, t5, 2047
+; CHECK-RV32-NEXT: addi t5, t5, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v14, v16
+; CHECK-RV32-NEXT: addi t6, sp, 1312
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (t6)
+; CHECK-RV32-NEXT: csrr t5, vlenb
+; CHECK-RV32-NEXT: slli t5, t5, 8
+; CHECK-RV32-NEXT: add t5, sp, t5
+; CHECK-RV32-NEXT: addi t5, t5, 2047
+; CHECK-RV32-NEXT: addi t5, t5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: csrr t5, vlenb
+; CHECK-RV32-NEXT: slli t5, t5, 3
+; CHECK-RV32-NEXT: mv s6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 1
+; CHECK-RV32-NEXT: add s6, s6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 1
+; CHECK-RV32-NEXT: add s6, s6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 1
+; CHECK-RV32-NEXT: add s6, s6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 1
+; CHECK-RV32-NEXT: add t5, t5, s6
+; CHECK-RV32-NEXT: add t5, sp, t5
+; CHECK-RV32-NEXT: addi t5, t5, 2047
+; CHECK-RV32-NEXT: addi t5, t5, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v10, v16
+; CHECK-RV32-NEXT: csrr t5, vlenb
+; CHECK-RV32-NEXT: slli t5, t5, 4
+; CHECK-RV32-NEXT: mv s6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 1
+; CHECK-RV32-NEXT: add s6, s6, t5
+; CHECK-RV32-NEXT: slli t5, t5, 3
+; CHECK-RV32-NEXT: add t5, t5, s6
+; CHECK-RV32-NEXT: add t5, sp, t5
+; CHECK-RV32-NEXT: addi t5, t5, 2047
+; CHECK-RV32-NEXT: addi t5, t5, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv2r.v v12, v16
+; CHECK-RV32-NEXT: vmv2r.v v14, v24
+; CHECK-RV32-NEXT: addi t5, sp, 288
+; CHECK-RV32-NEXT: vsseg4e8.v v8, (t5)
+; CHECK-RV32-NEXT: addi s6, sp, 768
+; CHECK-RV32-NEXT: vle8.v v8, (s6)
+; CHECK-RV32-NEXT: csrr s6, vlenb
+; CHECK-RV32-NEXT: slli s6, s6, 4
+; CHECK-RV32-NEXT: mv ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 1
+; CHECK-RV32-NEXT: add ra, ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 3
+; CHECK-RV32-NEXT: add s6, s6, ra
+; CHECK-RV32-NEXT: add s6, sp, s6
+; CHECK-RV32-NEXT: addi s6, s6, 2047
+; CHECK-RV32-NEXT: addi s6, s6, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s6, sp, 704
+; CHECK-RV32-NEXT: vle8.v v8, (s6)
+; CHECK-RV32-NEXT: csrr s6, vlenb
+; CHECK-RV32-NEXT: slli s6, s6, 3
+; CHECK-RV32-NEXT: mv ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 2
+; CHECK-RV32-NEXT: add ra, ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 3
+; CHECK-RV32-NEXT: add s6, s6, ra
+; CHECK-RV32-NEXT: add s6, sp, s6
+; CHECK-RV32-NEXT: addi s6, s6, 2047
+; CHECK-RV32-NEXT: addi s6, s6, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s6, sp, 1792
+; CHECK-RV32-NEXT: vle8.v v8, (s6)
+; CHECK-RV32-NEXT: csrr s6, vlenb
+; CHECK-RV32-NEXT: slli s6, s6, 5
+; CHECK-RV32-NEXT: mv ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 3
+; CHECK-RV32-NEXT: add s6, s6, ra
+; CHECK-RV32-NEXT: add s6, sp, s6
+; CHECK-RV32-NEXT: addi s6, s6, 2047
+; CHECK-RV32-NEXT: addi s6, s6, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s6, sp, 1728
+; CHECK-RV32-NEXT: vle8.v v8, (s6)
+; CHECK-RV32-NEXT: csrr s6, vlenb
+; CHECK-RV32-NEXT: slli s6, s6, 3
+; CHECK-RV32-NEXT: mv ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 1
+; CHECK-RV32-NEXT: add ra, ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 4
+; CHECK-RV32-NEXT: add s6, s6, ra
+; CHECK-RV32-NEXT: add s6, sp, s6
+; CHECK-RV32-NEXT: addi s6, s6, 2047
+; CHECK-RV32-NEXT: addi s6, s6, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s6, sp, 1280
+; CHECK-RV32-NEXT: vle8.v v16, (s6)
+; CHECK-RV32-NEXT: addi s6, sp, 1248
+; CHECK-RV32-NEXT: vle8.v v8, (s6)
+; CHECK-RV32-NEXT: addi s6, sp, 1216
+; CHECK-RV32-NEXT: vle8.v v12, (s6)
+; CHECK-RV32-NEXT: addi s6, sp, 1024
+; CHECK-RV32-NEXT: vle8.v v20, (s6)
+; CHECK-RV32-NEXT: csrr s6, vlenb
+; CHECK-RV32-NEXT: slli s6, s6, 4
+; CHECK-RV32-NEXT: mv ra, s6
+; CHECK-RV32-NEXT: slli s6, s6, 4
+; CHECK-RV32-NEXT: add s6, s6, ra
+; CHECK-RV32-NEXT: add s6, sp, s6
+; CHECK-RV32-NEXT: addi s6, s6, 2047
+; CHECK-RV32-NEXT: addi s6, s6, 33
+; CHECK-RV32-NEXT: vs4r.v v20, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v16, (s5)
+; CHECK-RV32-NEXT: addi s5, sp, 960
+; CHECK-RV32-NEXT: vle8.v v20, (s5)
+; CHECK-RV32-NEXT: csrr s5, vlenb
+; CHECK-RV32-NEXT: slli s5, s5, 3
+; CHECK-RV32-NEXT: mv s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 5
+; CHECK-RV32-NEXT: add s5, s5, s6
+; CHECK-RV32-NEXT: add s5, sp, s5
+; CHECK-RV32-NEXT: addi s5, s5, 2047
+; CHECK-RV32-NEXT: addi s5, s5, 33
+; CHECK-RV32-NEXT: vs4r.v v20, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v12, a1
+; CHECK-RV32-NEXT: vmv.v.v v24, v16
+; CHECK-RV32-NEXT: addi s5, sp, 256
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v20, (s5)
+; CHECK-RV32-NEXT: addi s5, sp, 192
+; CHECK-RV32-NEXT: vle8.v v16, (s5)
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a4
+; CHECK-RV32-NEXT: csrr s5, vlenb
+; CHECK-RV32-NEXT: slli s5, s5, 8
+; CHECK-RV32-NEXT: add s5, sp, s5
+; CHECK-RV32-NEXT: addi s5, s5, 2047
+; CHECK-RV32-NEXT: addi s5, s5, 33
+; CHECK-RV32-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi s5, sp, 2047
+; CHECK-RV32-NEXT: addi s5, s5, 1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (s5)
+; CHECK-RV32-NEXT: csrr s5, vlenb
+; CHECK-RV32-NEXT: slli s5, s5, 3
+; CHECK-RV32-NEXT: mv s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s6, s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s6, s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s6, s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s5, s5, s6
+; CHECK-RV32-NEXT: add s5, sp, s5
+; CHECK-RV32-NEXT: addi s5, s5, 2047
+; CHECK-RV32-NEXT: addi s5, s5, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s5, sp, 1984
+; CHECK-RV32-NEXT: vle8.v v8, (s5)
+; CHECK-RV32-NEXT: csrr s5, vlenb
+; CHECK-RV32-NEXT: slli s5, s5, 4
+; CHECK-RV32-NEXT: mv s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s6, s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s6, s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s5, s5, s6
+; CHECK-RV32-NEXT: add s5, sp, s5
+; CHECK-RV32-NEXT: addi s5, s5, 2047
+; CHECK-RV32-NEXT: addi s5, s5, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s5, sp, 224
+; CHECK-RV32-NEXT: vle8.v v8, (s5)
+; CHECK-RV32-NEXT: addi s5, sp, 1536
+; CHECK-RV32-NEXT: vle8.v v12, (s5)
+; CHECK-RV32-NEXT: csrr s5, vlenb
+; CHECK-RV32-NEXT: slli s5, s5, 3
+; CHECK-RV32-NEXT: mv s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 2
+; CHECK-RV32-NEXT: add s6, s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s6, s6, s5
+; CHECK-RV32-NEXT: slli s5, s5, 1
+; CHECK-RV32-NEXT: add s5, s5, s6
+; CHECK-RV32-NEXT: add s5, sp, s5
+; CHECK-RV32-NEXT: addi s5, s5, 2047
+; CHECK-RV32-NEXT: addi s5, s5, 33
+; CHECK-RV32-NEXT: vs4r.v v12, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v24, (s4)
+; CHECK-RV32-NEXT: addi s4, sp, 1472
+; CHECK-RV32-NEXT: vle8.v v12, (s4)
+; CHECK-RV32-NEXT: csrr s4, vlenb
+; CHECK-RV32-NEXT: slli s4, s4, 5
+; CHECK-RV32-NEXT: mv s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 1
+; CHECK-RV32-NEXT: add s5, s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 1
+; CHECK-RV32-NEXT: add s4, s4, s5
+; CHECK-RV32-NEXT: add s4, sp, s4
+; CHECK-RV32-NEXT: addi s4, s4, 2047
+; CHECK-RV32-NEXT: addi s4, s4, 33
+; CHECK-RV32-NEXT: vs4r.v v12, (s4) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v16, a1
+; CHECK-RV32-NEXT: vmv.v.v v0, v24
+; CHECK-RV32-NEXT: addi s4, sp, 640
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v20, (s4)
+; CHECK-RV32-NEXT: addi s4, sp, 576
+; CHECK-RV32-NEXT: vle8.v v24, (s4)
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v0, v8, a4
+; CHECK-RV32-NEXT: csrr s4, vlenb
+; CHECK-RV32-NEXT: slli s4, s4, 3
+; CHECK-RV32-NEXT: mv s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 1
+; CHECK-RV32-NEXT: add s5, s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 2
+; CHECK-RV32-NEXT: add s5, s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 1
+; CHECK-RV32-NEXT: add s4, s4, s5
+; CHECK-RV32-NEXT: add s4, sp, s4
+; CHECK-RV32-NEXT: addi s4, s4, 2047
+; CHECK-RV32-NEXT: addi s4, s4, 33
+; CHECK-RV32-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi s4, sp, 512
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (s4)
+; CHECK-RV32-NEXT: csrr s4, vlenb
+; CHECK-RV32-NEXT: slli s4, s4, 4
+; CHECK-RV32-NEXT: mv s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 2
+; CHECK-RV32-NEXT: add s5, s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 1
+; CHECK-RV32-NEXT: add s4, s4, s5
+; CHECK-RV32-NEXT: add s4, sp, s4
+; CHECK-RV32-NEXT: addi s4, s4, 2047
+; CHECK-RV32-NEXT: addi s4, s4, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s4, sp, 448
+; CHECK-RV32-NEXT: vle8.v v8, (s4)
+; CHECK-RV32-NEXT: csrr s4, vlenb
+; CHECK-RV32-NEXT: slli s4, s4, 3
+; CHECK-RV32-NEXT: mv s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 3
+; CHECK-RV32-NEXT: add s5, s5, s4
+; CHECK-RV32-NEXT: slli s4, s4, 1
+; CHECK-RV32-NEXT: add s4, s4, s5
+; CHECK-RV32-NEXT: add s4, sp, s4
+; CHECK-RV32-NEXT: addi s4, s4, 2047
+; CHECK-RV32-NEXT: addi s4, s4, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s4, sp, 608
+; CHECK-RV32-NEXT: vle8.v v8, (s4)
+; CHECK-RV32-NEXT: addi s4, sp, 1664
+; CHECK-RV32-NEXT: vle8.v v16, (s4)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v0, (s3)
+; CHECK-RV32-NEXT: addi s3, sp, 1600
+; CHECK-RV32-NEXT: vle8.v v20, (s3)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v0, v24, a1
+; CHECK-RV32-NEXT: addi s3, sp, 1152
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v12, (s3)
+; CHECK-RV32-NEXT: csrr s3, vlenb
+; CHECK-RV32-NEXT: slli s3, s3, 3
+; CHECK-RV32-NEXT: mv s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 1
+; CHECK-RV32-NEXT: add s4, s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 1
+; CHECK-RV32-NEXT: add s4, s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 2
+; CHECK-RV32-NEXT: add s3, s3, s4
+; CHECK-RV32-NEXT: add s3, sp, s3
+; CHECK-RV32-NEXT: addi s3, s3, 2047
+; CHECK-RV32-NEXT: addi s3, s3, 33
+; CHECK-RV32-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s3, sp, 1088
+; CHECK-RV32-NEXT: vle8.v v24, (s3)
+; CHECK-RV32-NEXT: csrr s3, vlenb
+; CHECK-RV32-NEXT: slli s3, s3, 4
+; CHECK-RV32-NEXT: mv s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 1
+; CHECK-RV32-NEXT: add s4, s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 2
+; CHECK-RV32-NEXT: add s3, s3, s4
+; CHECK-RV32-NEXT: add s3, sp, s3
+; CHECK-RV32-NEXT: addi s3, s3, 2047
+; CHECK-RV32-NEXT: addi s3, s3, 33
+; CHECK-RV32-NEXT: vs4r.v v24, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v0, v8, a4
+; CHECK-RV32-NEXT: csrr s3, vlenb
+; CHECK-RV32-NEXT: slli s3, s3, 6
+; CHECK-RV32-NEXT: mv s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 1
+; CHECK-RV32-NEXT: add s3, s3, s4
+; CHECK-RV32-NEXT: add s3, sp, s3
+; CHECK-RV32-NEXT: addi s3, s3, 2047
+; CHECK-RV32-NEXT: addi s3, s3, 33
+; CHECK-RV32-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi s3, sp, 896
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (s3)
+; CHECK-RV32-NEXT: csrr s3, vlenb
+; CHECK-RV32-NEXT: slli s3, s3, 3
+; CHECK-RV32-NEXT: mv s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 2
+; CHECK-RV32-NEXT: add s4, s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 2
+; CHECK-RV32-NEXT: add s3, s3, s4
+; CHECK-RV32-NEXT: add s3, sp, s3
+; CHECK-RV32-NEXT: addi s3, s3, 2047
+; CHECK-RV32-NEXT: addi s3, s3, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s3, sp, 832
+; CHECK-RV32-NEXT: vle8.v v8, (s3)
+; CHECK-RV32-NEXT: csrr s3, vlenb
+; CHECK-RV32-NEXT: slli s3, s3, 3
+; CHECK-RV32-NEXT: mv s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 1
+; CHECK-RV32-NEXT: add s4, s4, s3
+; CHECK-RV32-NEXT: slli s3, s3, 3
+; CHECK-RV32-NEXT: add s3, s3, s4
+; CHECK-RV32-NEXT: add s3, sp, s3
+; CHECK-RV32-NEXT: addi s3, s3, 2047
+; CHECK-RV32-NEXT: addi s3, s3, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s3, sp, 1632
+; CHECK-RV32-NEXT: vle8.v v8, (s3)
+; CHECK-RV32-NEXT: addi s3, sp, 128
+; CHECK-RV32-NEXT: vle8.v v24, (s3)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v16, (s2)
+; CHECK-RV32-NEXT: addi s2, sp, 64
+; CHECK-RV32-NEXT: vle8.v v28, (s2)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV32-NEXT: addi s2, sp, 1920
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v12, (s2)
+; CHECK-RV32-NEXT: csrr s2, vlenb
+; CHECK-RV32-NEXT: slli s2, s2, 4
+; CHECK-RV32-NEXT: mv s3, s2
+; CHECK-RV32-NEXT: slli s2, s2, 3
+; CHECK-RV32-NEXT: add s2, s2, s3
+; CHECK-RV32-NEXT: add s2, sp, s2
+; CHECK-RV32-NEXT: addi s2, s2, 2047
+; CHECK-RV32-NEXT: addi s2, s2, 33
+; CHECK-RV32-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s2, sp, 1856
+; CHECK-RV32-NEXT: vle8.v v20, (s2)
+; CHECK-RV32-NEXT: csrr s2, vlenb
+; CHECK-RV32-NEXT: slli s2, s2, 3
+; CHECK-RV32-NEXT: mv s3, s2
+; CHECK-RV32-NEXT: slli s2, s2, 1
+; CHECK-RV32-NEXT: add s3, s3, s2
+; CHECK-RV32-NEXT: slli s2, s2, 1
+; CHECK-RV32-NEXT: add s3, s3, s2
+; CHECK-RV32-NEXT: slli s2, s2, 1
+; CHECK-RV32-NEXT: add s2, s2, s3
+; CHECK-RV32-NEXT: add s2, sp, s2
+; CHECK-RV32-NEXT: addi s2, s2, 2047
+; CHECK-RV32-NEXT: addi s2, s2, 33
+; CHECK-RV32-NEXT: vs4r.v v20, (s2) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV32-NEXT: csrr s2, vlenb
+; CHECK-RV32-NEXT: slli s2, s2, 5
+; CHECK-RV32-NEXT: mv s3, s2
+; CHECK-RV32-NEXT: slli s2, s2, 2
+; CHECK-RV32-NEXT: add s2, s2, s3
+; CHECK-RV32-NEXT: add s2, sp, s2
+; CHECK-RV32-NEXT: addi s2, s2, 2047
+; CHECK-RV32-NEXT: addi s2, s2, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi s2, sp, 1408
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v4, (s2)
+; CHECK-RV32-NEXT: addi s2, sp, 1344
+; CHECK-RV32-NEXT: vle8.v v8, (s2)
+; CHECK-RV32-NEXT: csrr s2, vlenb
+; CHECK-RV32-NEXT: slli s2, s2, 5
+; CHECK-RV32-NEXT: mv s3, s2
+; CHECK-RV32-NEXT: slli s2, s2, 1
+; CHECK-RV32-NEXT: add s2, s2, s3
+; CHECK-RV32-NEXT: add s2, sp, s2
+; CHECK-RV32-NEXT: addi s2, s2, 2047
+; CHECK-RV32-NEXT: addi s2, s2, 33
+; CHECK-RV32-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
+; CHECK-RV32-NEXT: addi s2, sp, 96
+; CHECK-RV32-NEXT: vle8.v v8, (s2)
+; CHECK-RV32-NEXT: addi s2, sp, 384
+; CHECK-RV32-NEXT: vle8.v v0, (s2)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v16, (s1)
+; CHECK-RV32-NEXT: addi s1, sp, 320
+; CHECK-RV32-NEXT: vmv2r.v v12, v28
+; CHECK-RV32-NEXT: vle8.v v28, (s1)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v12, a1
+; CHECK-RV32-NEXT: addi s1, sp, 736
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v24, (s1)
+; CHECK-RV32-NEXT: csrr s1, vlenb
+; CHECK-RV32-NEXT: slli s1, s1, 7
+; CHECK-RV32-NEXT: add s1, sp, s1
+; CHECK-RV32-NEXT: addi s1, s1, 2047
+; CHECK-RV32-NEXT: addi s1, s1, 33
+; CHECK-RV32-NEXT: vs8r.v v24, (s1) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vle8.v v24, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv s1, a3
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: add a3, a3, s1
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv s1, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, s1
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a3, sp, 1760
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv s1, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add s1, s1, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, s1
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vle8.v v8, (a5)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a3, sp, 1376
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: addi a3, sp, 992
+; CHECK-RV32-NEXT: vle8.v v24, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v4, a1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v24, (t6)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: vle8.v v16, (a6)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v12, a1
+; CHECK-RV32-NEXT: addi a3, sp, 2016
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v16, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 6
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vle8.v v16, (a7)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vmv4r.v v16, v24
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a3, sp, 1504
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vle8.v v8, (t0)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a3, sp, 352
+; CHECK-RV32-NEXT: vle8.v v16, (a3)
+; CHECK-RV32-NEXT: addi a3, sp, 480
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v0, a1
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v0, (t5)
+; CHECK-RV32-NEXT: vle8.v v8, (t1)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v0, v28, a1
+; CHECK-RV32-NEXT: addi a3, sp, 1120
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vle8.v v8, (t2)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v0, v16, a4
+; CHECK-RV32-NEXT: addi a3, sp, 864
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vle8.v v24, (a3)
+; CHECK-RV32-NEXT: vle8.v v8, (t3)
+; CHECK-RV32-NEXT: addi a3, sp, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: addi a3, sp, 1888
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: vle8.v v16, (t4)
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v12, a1
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v0, (a0)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v12, a1
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV32-NEXT: addi a3, a0, 1024
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vse8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: addi a3, sp, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslideup.vx v0, v8, a1
+; CHECK-RV32-NEXT: addi a3, a0, 512
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v16, (a3)
+; CHECK-RV32-NEXT: vslideup.vx v0, v24, a4
+; CHECK-RV32-NEXT: addi a3, a0, 256
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 4
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vse8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV32-NEXT: addi a3, a0, 1536
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v0, (a3)
+; CHECK-RV32-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: addi a3, a0, 1280
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v16, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV32-NEXT: addi a3, a0, 768
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 5
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vse8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: addi a3, a0, 128
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v16, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV32-NEXT: vmv.v.v v0, v16
+; CHECK-RV32-NEXT: addi a3, a0, 1792
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 6
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vse8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 6
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV32-NEXT: addi a3, a0, 1152
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v0, (a3)
+; CHECK-RV32-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: addi a3, a0, 640
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v16, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV32-NEXT: addi a3, a0, 384
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 3
+; CHECK-RV32-NEXT: mv a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 2
+; CHECK-RV32-NEXT: add a6, a6, a5
+; CHECK-RV32-NEXT: slli a5, a5, 1
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vse8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: addi a3, a0, 1664
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v16, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV32-NEXT: vmv.v.v v0, v16
+; CHECK-RV32-NEXT: addi a3, a0, 1408
+; CHECK-RV32-NEXT: csrr a5, vlenb
+; CHECK-RV32-NEXT: slli a5, a5, 8
+; CHECK-RV32-NEXT: add a5, sp, a5
+; CHECK-RV32-NEXT: addi a5, a5, 2047
+; CHECK-RV32-NEXT: addi a5, a5, 33
+; CHECK-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vse8.v v8, (a3)
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 1
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 7
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV32-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 2
+; CHECK-RV32-NEXT: add a5, a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 3
+; CHECK-RV32-NEXT: mv a5, a3
+; CHECK-RV32-NEXT: slli a3, a3, 4
+; CHECK-RV32-NEXT: add a3, a3, a5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 2047
+; CHECK-RV32-NEXT: addi a3, a3, 33
+; CHECK-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV32-NEXT: addi a1, a0, 896
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV32-NEXT: vse8.v v0, (a1)
+; CHECK-RV32-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV32-NEXT: addi a0, a0, 1920
+; CHECK-RV32-NEXT: vse8.v v16, (a0)
+; CHECK-RV32-NEXT: addi sp, s0, -2032
+; CHECK-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: lw s3, 2012(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: lw s4, 2008(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: lw s5, 2004(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: lw s6, 2000(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT: addi sp, sp, 2032
+; CHECK-RV32-NEXT: ret
+;
+; CHECK-RV64-LABEL: vector_interleave4_v512i8_v2048i8:
+; CHECK-RV64: # %bb.0:
+; CHECK-RV64-NEXT: addi sp, sp, -2032
+; CHECK-RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: sd s4, 1984(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: sd s5, 1976(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: sd s6, 1968(sp) # 8-byte Folded Spill
+; CHECK-RV64-NEXT: addi s0, sp, 2032
+; CHECK-RV64-NEXT: addi sp, sp, -112
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 3
+; CHECK-RV64-NEXT: mv a4, a2
+; CHECK-RV64-NEXT: slli a2, a2, 1
+; CHECK-RV64-NEXT: add a4, a4, a2
+; CHECK-RV64-NEXT: slli a2, a2, 1
+; CHECK-RV64-NEXT: add a4, a4, a2
+; CHECK-RV64-NEXT: slli a2, a2, 3
+; CHECK-RV64-NEXT: add a2, a2, a4
+; CHECK-RV64-NEXT: sub sp, sp, a2
+; CHECK-RV64-NEXT: andi sp, sp, -32
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 3
+; CHECK-RV64-NEXT: mv a4, a2
+; CHECK-RV64-NEXT: slli a2, a2, 2
+; CHECK-RV64-NEXT: add a4, a4, a2
+; CHECK-RV64-NEXT: slli a2, a2, 3
+; CHECK-RV64-NEXT: add a2, a2, a4
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 2047
+; CHECK-RV64-NEXT: addi a2, a2, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 8
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 2047
+; CHECK-RV64-NEXT: addi a2, a2, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: li a2, 128
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v16, (a7)
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: slli a4, a4, 4
+; CHECK-RV64-NEXT: mv a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 3
+; CHECK-RV64-NEXT: add a4, a4, a5
+; CHECK-RV64-NEXT: add a4, sp, a4
+; CHECK-RV64-NEXT: addi a4, a4, 2047
+; CHECK-RV64-NEXT: addi a4, a4, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: slli a4, a4, 3
+; CHECK-RV64-NEXT: mv a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a4, a4, a5
+; CHECK-RV64-NEXT: add a4, sp, a4
+; CHECK-RV64-NEXT: addi a4, a4, 2047
+; CHECK-RV64-NEXT: addi a4, a4, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a4, a7, 256
+; CHECK-RV64-NEXT: vle8.v v16, (a4)
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: slli a4, a4, 5
+; CHECK-RV64-NEXT: mv a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 3
+; CHECK-RV64-NEXT: add a4, a4, a5
+; CHECK-RV64-NEXT: add a4, sp, a4
+; CHECK-RV64-NEXT: addi a4, a4, 2047
+; CHECK-RV64-NEXT: addi a4, a4, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a4, a1, 128
+; CHECK-RV64-NEXT: vle8.v v24, (a4)
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: slli a4, a4, 4
+; CHECK-RV64-NEXT: mv a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a4, a4, a5
+; CHECK-RV64-NEXT: add a4, sp, a4
+; CHECK-RV64-NEXT: addi a4, a4, 2047
+; CHECK-RV64-NEXT: addi a4, a4, 33
+; CHECK-RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a4, a3, 384
+; CHECK-RV64-NEXT: vle8.v v16, (a4)
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: slli a4, a4, 3
+; CHECK-RV64-NEXT: mv a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 2
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a5, a5, a4
+; CHECK-RV64-NEXT: slli a4, a4, 1
+; CHECK-RV64-NEXT: add a4, a4, a5
+; CHECK-RV64-NEXT: add a4, sp, a4
+; CHECK-RV64-NEXT: addi a4, a4, 2047
+; CHECK-RV64-NEXT: addi a4, a4, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: li a4, 64
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v24, a4
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a5, a7, 384
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (a5)
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 5
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v0, v16, a4
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a5, s0, 768
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v24, (a5)
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 4
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a5, a3, 256
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v16, (a5)
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 4
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v24, a4
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 4
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v16, (a1)
+; CHECK-RV64-NEXT: csrr a1, vlenb
+; CHECK-RV64-NEXT: slli a1, a1, 4
+; CHECK-RV64-NEXT: mv a5, a1
+; CHECK-RV64-NEXT: slli a1, a1, 4
+; CHECK-RV64-NEXT: add a1, a1, a5
+; CHECK-RV64-NEXT: add a1, sp, a1
+; CHECK-RV64-NEXT: addi a1, a1, 2047
+; CHECK-RV64-NEXT: addi a1, a1, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: li a1, 32
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v20, v0, a1
+; CHECK-RV64-NEXT: addi a5, a7, 128
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v0, (a5)
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 4
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v16, v8, a1
+; CHECK-RV64-NEXT: addi a3, a3, 128
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vmv2r.v v18, v20
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV64-NEXT: vmv2r.v v22, v24
+; CHECK-RV64-NEXT: addi a3, sp, 672
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v16, (a3)
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a4
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 5
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v16, v16, a4
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 4
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a5, s0, 512
+; CHECK-RV64-NEXT: vslidedown.vx v0, v0, a4
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 3
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 2
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (a5)
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 7
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v20, v16, a1
+; CHECK-RV64-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v16, v8, a1
+; CHECK-RV64-NEXT: vmv2r.v v18, v20
+; CHECK-RV64-NEXT: vslidedown.vx v20, v0, a1
+; CHECK-RV64-NEXT: vmv2r.v v22, v24
+; CHECK-RV64-NEXT: addi a5, sp, 1696
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v16, (a5)
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 4
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 4
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v0, v16, a4
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 4
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 2
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 3
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 4
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v24, v16, a4
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 3
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 2
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a6, s0, 640
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 5
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a4
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 5
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 2
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (a6)
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 6
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 5
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v20, v24, a1
+; CHECK-RV64-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV64-NEXT: vslidedown.vx v16, v0, a1
+; CHECK-RV64-NEXT: vmv2r.v v18, v20
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 5
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 2
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV64-NEXT: vmv2r.v v22, v24
+; CHECK-RV64-NEXT: addi s5, sp, 1184
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v16, (s5)
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 3
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 2
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v20, v16, a1
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 3
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 2
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 4
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v16, v0, a1
+; CHECK-RV64-NEXT: vmv2r.v v18, v20
+; CHECK-RV64-NEXT: csrr a6, vlenb
+; CHECK-RV64-NEXT: slli a6, a6, 5
+; CHECK-RV64-NEXT: mv a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a7, a7, a6
+; CHECK-RV64-NEXT: slli a6, a6, 1
+; CHECK-RV64-NEXT: add a6, a6, a7
+; CHECK-RV64-NEXT: add a6, sp, a6
+; CHECK-RV64-NEXT: addi a6, a6, 2047
+; CHECK-RV64-NEXT: addi a6, a6, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV64-NEXT: vmv2r.v v22, v24
+; CHECK-RV64-NEXT: addi a6, sp, 928
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v16, (a6)
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 8
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v16, v8, a4
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 6
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a7, s0, 384
+; CHECK-RV64-NEXT: csrr t0, vlenb
+; CHECK-RV64-NEXT: slli t0, t0, 4
+; CHECK-RV64-NEXT: mv t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 1
+; CHECK-RV64-NEXT: add t1, t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 3
+; CHECK-RV64-NEXT: add t0, t0, t1
+; CHECK-RV64-NEXT: add t0, sp, t0
+; CHECK-RV64-NEXT: addi t0, t0, 2047
+; CHECK-RV64-NEXT: addi t0, t0, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a4
+; CHECK-RV64-NEXT: csrr t0, vlenb
+; CHECK-RV64-NEXT: slli t0, t0, 4
+; CHECK-RV64-NEXT: mv t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 3
+; CHECK-RV64-NEXT: add t0, t0, t1
+; CHECK-RV64-NEXT: add t0, sp, t0
+; CHECK-RV64-NEXT: addi t0, t0, 2047
+; CHECK-RV64-NEXT: addi t0, t0, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vle8.v v24, (a7)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v24, a4
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v12, v16, a1
+; CHECK-RV64-NEXT: vslidedown.vx v20, v8, a1
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v8, v0, a1
+; CHECK-RV64-NEXT: vmv2r.v v10, v12
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 4
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v12, v0, a1
+; CHECK-RV64-NEXT: vmv2r.v v14, v20
+; CHECK-RV64-NEXT: addi s4, sp, 160
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (s4)
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 5
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v12, v16, a1
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 2
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 3
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v4, v16, a1
+; CHECK-RV64-NEXT: vmv2r.v v6, v8
+; CHECK-RV64-NEXT: csrr a7, vlenb
+; CHECK-RV64-NEXT: slli a7, a7, 4
+; CHECK-RV64-NEXT: mv t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 2
+; CHECK-RV64-NEXT: add t0, t0, a7
+; CHECK-RV64-NEXT: slli a7, a7, 1
+; CHECK-RV64-NEXT: add a7, a7, t0
+; CHECK-RV64-NEXT: add a7, sp, a7
+; CHECK-RV64-NEXT: addi a7, a7, 2047
+; CHECK-RV64-NEXT: addi a7, a7, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv2r.v v10, v12
+; CHECK-RV64-NEXT: addi a7, sp, 1952
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v4, (a7)
+; CHECK-RV64-NEXT: csrr t0, vlenb
+; CHECK-RV64-NEXT: slli t0, t0, 3
+; CHECK-RV64-NEXT: mv t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 1
+; CHECK-RV64-NEXT: add t1, t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 4
+; CHECK-RV64-NEXT: add t0, t0, t1
+; CHECK-RV64-NEXT: add t0, sp, t0
+; CHECK-RV64-NEXT: addi t0, t0, 2047
+; CHECK-RV64-NEXT: addi t0, t0, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-RV64-NEXT: csrr t0, vlenb
+; CHECK-RV64-NEXT: slli t0, t0, 6
+; CHECK-RV64-NEXT: mv t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 1
+; CHECK-RV64-NEXT: add t0, t0, t1
+; CHECK-RV64-NEXT: add t0, sp, t0
+; CHECK-RV64-NEXT: addi t0, t0, 2047
+; CHECK-RV64-NEXT: addi t0, t0, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v12, v16, a1
+; CHECK-RV64-NEXT: csrr t0, vlenb
+; CHECK-RV64-NEXT: slli t0, t0, 4
+; CHECK-RV64-NEXT: mv t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 4
+; CHECK-RV64-NEXT: add t0, t0, t1
+; CHECK-RV64-NEXT: add t0, sp, t0
+; CHECK-RV64-NEXT: addi t0, t0, 2047
+; CHECK-RV64-NEXT: addi t0, t0, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v4, v16, a1
+; CHECK-RV64-NEXT: vmv2r.v v6, v8
+; CHECK-RV64-NEXT: csrr t0, vlenb
+; CHECK-RV64-NEXT: slli t0, t0, 5
+; CHECK-RV64-NEXT: mv t1, t0
+; CHECK-RV64-NEXT: slli t0, t0, 3
+; CHECK-RV64-NEXT: add t0, t0, t1
+; CHECK-RV64-NEXT: add t0, sp, t0
+; CHECK-RV64-NEXT: addi t0, t0, 2047
+; CHECK-RV64-NEXT: addi t0, t0, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv2r.v v10, v12
+; CHECK-RV64-NEXT: addi t0, sp, 1440
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v4, (t0)
+; CHECK-RV64-NEXT: csrr t1, vlenb
+; CHECK-RV64-NEXT: slli t1, t1, 3
+; CHECK-RV64-NEXT: mv t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 2
+; CHECK-RV64-NEXT: add t1, t1, t2
+; CHECK-RV64-NEXT: add t1, sp, t1
+; CHECK-RV64-NEXT: addi t1, t1, 2047
+; CHECK-RV64-NEXT: addi t1, t1, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t1, vlenb
+; CHECK-RV64-NEXT: slli t1, t1, 3
+; CHECK-RV64-NEXT: mv t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t1, t1, t2
+; CHECK-RV64-NEXT: add t1, sp, t1
+; CHECK-RV64-NEXT: addi t1, t1, 2047
+; CHECK-RV64-NEXT: addi t1, t1, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t1, vlenb
+; CHECK-RV64-NEXT: slli t1, t1, 4
+; CHECK-RV64-NEXT: mv t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 2
+; CHECK-RV64-NEXT: add t1, t1, t2
+; CHECK-RV64-NEXT: add t1, sp, t1
+; CHECK-RV64-NEXT: addi t1, t1, 2047
+; CHECK-RV64-NEXT: addi t1, t1, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: csrr t1, vlenb
+; CHECK-RV64-NEXT: slli t1, t1, 3
+; CHECK-RV64-NEXT: mv t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 4
+; CHECK-RV64-NEXT: add t1, t1, t2
+; CHECK-RV64-NEXT: add t1, sp, t1
+; CHECK-RV64-NEXT: addi t1, t1, 2047
+; CHECK-RV64-NEXT: addi t1, t1, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v14, v16
+; CHECK-RV64-NEXT: addi s3, sp, 544
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (s3)
+; CHECK-RV64-NEXT: csrr t1, vlenb
+; CHECK-RV64-NEXT: slli t1, t1, 3
+; CHECK-RV64-NEXT: mv t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t1, t1, t2
+; CHECK-RV64-NEXT: add t1, sp, t1
+; CHECK-RV64-NEXT: addi t1, t1, 2047
+; CHECK-RV64-NEXT: addi t1, t1, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-RV64-NEXT: vslidedown.vx v12, v24, a1
+; CHECK-RV64-NEXT: csrr t1, vlenb
+; CHECK-RV64-NEXT: slli t1, t1, 8
+; CHECK-RV64-NEXT: add t1, sp, t1
+; CHECK-RV64-NEXT: addi t1, t1, 2047
+; CHECK-RV64-NEXT: addi t1, t1, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v4, v16, a1
+; CHECK-RV64-NEXT: vmv2r.v v6, v8
+; CHECK-RV64-NEXT: csrr t1, vlenb
+; CHECK-RV64-NEXT: slli t1, t1, 4
+; CHECK-RV64-NEXT: mv t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 1
+; CHECK-RV64-NEXT: add t2, t2, t1
+; CHECK-RV64-NEXT: slli t1, t1, 3
+; CHECK-RV64-NEXT: add t1, t1, t2
+; CHECK-RV64-NEXT: add t1, sp, t1
+; CHECK-RV64-NEXT: addi t1, t1, 2047
+; CHECK-RV64-NEXT: addi t1, t1, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv2r.v v10, v12
+; CHECK-RV64-NEXT: addi t1, sp, 416
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vsseg4e8.v v4, (t1)
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 3
+; CHECK-RV64-NEXT: mv t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 2
+; CHECK-RV64-NEXT: add t3, t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 2
+; CHECK-RV64-NEXT: add t2, t2, t3
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 4
+; CHECK-RV64-NEXT: mv t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 1
+; CHECK-RV64-NEXT: add t3, t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 1
+; CHECK-RV64-NEXT: add t2, t2, t3
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 3
+; CHECK-RV64-NEXT: mv t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 2
+; CHECK-RV64-NEXT: add t3, t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 1
+; CHECK-RV64-NEXT: add t2, t2, t3
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 7
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v14, v16
+; CHECK-RV64-NEXT: addi s2, sp, 1568
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (s2)
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 4
+; CHECK-RV64-NEXT: mv t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 2
+; CHECK-RV64-NEXT: add t2, t2, t3
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 3
+; CHECK-RV64-NEXT: mv t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 1
+; CHECK-RV64-NEXT: add t3, t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 2
+; CHECK-RV64-NEXT: add t2, t2, t3
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 5
+; CHECK-RV64-NEXT: mv t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 2
+; CHECK-RV64-NEXT: add t2, t2, t3
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: csrr t2, vlenb
+; CHECK-RV64-NEXT: slli t2, t2, 5
+; CHECK-RV64-NEXT: mv t3, t2
+; CHECK-RV64-NEXT: slli t2, t2, 1
+; CHECK-RV64-NEXT: add t2, t2, t3
+; CHECK-RV64-NEXT: add t2, sp, t2
+; CHECK-RV64-NEXT: addi t2, t2, 2047
+; CHECK-RV64-NEXT: addi t2, t2, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v14, v16
+; CHECK-RV64-NEXT: addi t2, sp, 1056
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (t2)
+; CHECK-RV64-NEXT: csrr t3, vlenb
+; CHECK-RV64-NEXT: slli t3, t3, 4
+; CHECK-RV64-NEXT: mv t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t4, t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t4, t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t3, t3, t4
+; CHECK-RV64-NEXT: add t3, sp, t3
+; CHECK-RV64-NEXT: addi t3, t3, 2047
+; CHECK-RV64-NEXT: addi t3, t3, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t3, vlenb
+; CHECK-RV64-NEXT: slli t3, t3, 3
+; CHECK-RV64-NEXT: mv t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 2
+; CHECK-RV64-NEXT: add t4, t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t4, t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t3, t3, t4
+; CHECK-RV64-NEXT: add t3, sp, t3
+; CHECK-RV64-NEXT: addi t3, t3, 2047
+; CHECK-RV64-NEXT: addi t3, t3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t3, vlenb
+; CHECK-RV64-NEXT: slli t3, t3, 5
+; CHECK-RV64-NEXT: mv t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t4, t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t3, t3, t4
+; CHECK-RV64-NEXT: add t3, sp, t3
+; CHECK-RV64-NEXT: addi t3, t3, 2047
+; CHECK-RV64-NEXT: addi t3, t3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: csrr t3, vlenb
+; CHECK-RV64-NEXT: slli t3, t3, 3
+; CHECK-RV64-NEXT: mv t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t4, t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 2
+; CHECK-RV64-NEXT: add t4, t4, t3
+; CHECK-RV64-NEXT: slli t3, t3, 1
+; CHECK-RV64-NEXT: add t3, t3, t4
+; CHECK-RV64-NEXT: add t3, sp, t3
+; CHECK-RV64-NEXT: addi t3, t3, 2047
+; CHECK-RV64-NEXT: addi t3, t3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v14, v16
+; CHECK-RV64-NEXT: addi t3, sp, 800
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (t3)
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: mv t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 1
+; CHECK-RV64-NEXT: add t5, t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: add t4, t4, t5
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 6
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 4
+; CHECK-RV64-NEXT: mv t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: add t4, t4, t5
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: mv t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: add t4, t4, t5
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v14, v16
+; CHECK-RV64-NEXT: addi s1, sp, 32
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (s1)
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: mv t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 2
+; CHECK-RV64-NEXT: add t5, t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: add t4, t4, t5
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: mv t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 5
+; CHECK-RV64-NEXT: add t4, t4, t5
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 4
+; CHECK-RV64-NEXT: mv t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 2
+; CHECK-RV64-NEXT: add t5, t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 1
+; CHECK-RV64-NEXT: add t4, t4, t5
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: csrr t4, vlenb
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: mv t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 3
+; CHECK-RV64-NEXT: add t5, t5, t4
+; CHECK-RV64-NEXT: slli t4, t4, 1
+; CHECK-RV64-NEXT: add t4, t4, t5
+; CHECK-RV64-NEXT: add t4, sp, t4
+; CHECK-RV64-NEXT: addi t4, t4, 2047
+; CHECK-RV64-NEXT: addi t4, t4, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v14, v16
+; CHECK-RV64-NEXT: addi t4, sp, 1824
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (t4)
+; CHECK-RV64-NEXT: csrr t5, vlenb
+; CHECK-RV64-NEXT: slli t5, t5, 4
+; CHECK-RV64-NEXT: mv t6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 4
+; CHECK-RV64-NEXT: add t5, t5, t6
+; CHECK-RV64-NEXT: add t5, sp, t5
+; CHECK-RV64-NEXT: addi t5, t5, 2047
+; CHECK-RV64-NEXT: addi t5, t5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t5, vlenb
+; CHECK-RV64-NEXT: slli t5, t5, 3
+; CHECK-RV64-NEXT: mv t6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 1
+; CHECK-RV64-NEXT: add t6, t6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 4
+; CHECK-RV64-NEXT: add t5, t5, t6
+; CHECK-RV64-NEXT: add t5, sp, t5
+; CHECK-RV64-NEXT: addi t5, t5, 2047
+; CHECK-RV64-NEXT: addi t5, t5, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t5, vlenb
+; CHECK-RV64-NEXT: slli t5, t5, 5
+; CHECK-RV64-NEXT: mv t6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 3
+; CHECK-RV64-NEXT: add t5, t5, t6
+; CHECK-RV64-NEXT: add t5, sp, t5
+; CHECK-RV64-NEXT: addi t5, t5, 2047
+; CHECK-RV64-NEXT: addi t5, t5, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: csrr t5, vlenb
+; CHECK-RV64-NEXT: slli t5, t5, 6
+; CHECK-RV64-NEXT: mv t6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 1
+; CHECK-RV64-NEXT: add t5, t5, t6
+; CHECK-RV64-NEXT: add t5, sp, t5
+; CHECK-RV64-NEXT: addi t5, t5, 2047
+; CHECK-RV64-NEXT: addi t5, t5, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v14, v16
+; CHECK-RV64-NEXT: addi t6, sp, 1312
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (t6)
+; CHECK-RV64-NEXT: csrr t5, vlenb
+; CHECK-RV64-NEXT: slli t5, t5, 8
+; CHECK-RV64-NEXT: add t5, sp, t5
+; CHECK-RV64-NEXT: addi t5, t5, 2047
+; CHECK-RV64-NEXT: addi t5, t5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr t5, vlenb
+; CHECK-RV64-NEXT: slli t5, t5, 3
+; CHECK-RV64-NEXT: mv s6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 1
+; CHECK-RV64-NEXT: add s6, s6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 1
+; CHECK-RV64-NEXT: add s6, s6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 1
+; CHECK-RV64-NEXT: add s6, s6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 1
+; CHECK-RV64-NEXT: add t5, t5, s6
+; CHECK-RV64-NEXT: add t5, sp, t5
+; CHECK-RV64-NEXT: addi t5, t5, 2047
+; CHECK-RV64-NEXT: addi t5, t5, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v10, v16
+; CHECK-RV64-NEXT: csrr t5, vlenb
+; CHECK-RV64-NEXT: slli t5, t5, 4
+; CHECK-RV64-NEXT: mv s6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 1
+; CHECK-RV64-NEXT: add s6, s6, t5
+; CHECK-RV64-NEXT: slli t5, t5, 3
+; CHECK-RV64-NEXT: add t5, t5, s6
+; CHECK-RV64-NEXT: add t5, sp, t5
+; CHECK-RV64-NEXT: addi t5, t5, 2047
+; CHECK-RV64-NEXT: addi t5, t5, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv2r.v v12, v16
+; CHECK-RV64-NEXT: vmv2r.v v14, v24
+; CHECK-RV64-NEXT: addi t5, sp, 288
+; CHECK-RV64-NEXT: vsseg4e8.v v8, (t5)
+; CHECK-RV64-NEXT: addi s6, sp, 768
+; CHECK-RV64-NEXT: vle8.v v8, (s6)
+; CHECK-RV64-NEXT: csrr s6, vlenb
+; CHECK-RV64-NEXT: slli s6, s6, 4
+; CHECK-RV64-NEXT: mv ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 1
+; CHECK-RV64-NEXT: add ra, ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 3
+; CHECK-RV64-NEXT: add s6, s6, ra
+; CHECK-RV64-NEXT: add s6, sp, s6
+; CHECK-RV64-NEXT: addi s6, s6, 2047
+; CHECK-RV64-NEXT: addi s6, s6, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s6, sp, 704
+; CHECK-RV64-NEXT: vle8.v v8, (s6)
+; CHECK-RV64-NEXT: csrr s6, vlenb
+; CHECK-RV64-NEXT: slli s6, s6, 3
+; CHECK-RV64-NEXT: mv ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 2
+; CHECK-RV64-NEXT: add ra, ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 3
+; CHECK-RV64-NEXT: add s6, s6, ra
+; CHECK-RV64-NEXT: add s6, sp, s6
+; CHECK-RV64-NEXT: addi s6, s6, 2047
+; CHECK-RV64-NEXT: addi s6, s6, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s6, sp, 1792
+; CHECK-RV64-NEXT: vle8.v v8, (s6)
+; CHECK-RV64-NEXT: csrr s6, vlenb
+; CHECK-RV64-NEXT: slli s6, s6, 5
+; CHECK-RV64-NEXT: mv ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 3
+; CHECK-RV64-NEXT: add s6, s6, ra
+; CHECK-RV64-NEXT: add s6, sp, s6
+; CHECK-RV64-NEXT: addi s6, s6, 2047
+; CHECK-RV64-NEXT: addi s6, s6, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s6, sp, 1728
+; CHECK-RV64-NEXT: vle8.v v8, (s6)
+; CHECK-RV64-NEXT: csrr s6, vlenb
+; CHECK-RV64-NEXT: slli s6, s6, 3
+; CHECK-RV64-NEXT: mv ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 1
+; CHECK-RV64-NEXT: add ra, ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 4
+; CHECK-RV64-NEXT: add s6, s6, ra
+; CHECK-RV64-NEXT: add s6, sp, s6
+; CHECK-RV64-NEXT: addi s6, s6, 2047
+; CHECK-RV64-NEXT: addi s6, s6, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s6, sp, 1280
+; CHECK-RV64-NEXT: vle8.v v16, (s6)
+; CHECK-RV64-NEXT: addi s6, sp, 1248
+; CHECK-RV64-NEXT: vle8.v v8, (s6)
+; CHECK-RV64-NEXT: addi s6, sp, 1216
+; CHECK-RV64-NEXT: vle8.v v12, (s6)
+; CHECK-RV64-NEXT: addi s6, sp, 1024
+; CHECK-RV64-NEXT: vle8.v v20, (s6)
+; CHECK-RV64-NEXT: csrr s6, vlenb
+; CHECK-RV64-NEXT: slli s6, s6, 4
+; CHECK-RV64-NEXT: mv ra, s6
+; CHECK-RV64-NEXT: slli s6, s6, 4
+; CHECK-RV64-NEXT: add s6, s6, ra
+; CHECK-RV64-NEXT: add s6, sp, s6
+; CHECK-RV64-NEXT: addi s6, s6, 2047
+; CHECK-RV64-NEXT: addi s6, s6, 33
+; CHECK-RV64-NEXT: vs4r.v v20, (s6) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v16, (s5)
+; CHECK-RV64-NEXT: addi s5, sp, 960
+; CHECK-RV64-NEXT: vle8.v v20, (s5)
+; CHECK-RV64-NEXT: csrr s5, vlenb
+; CHECK-RV64-NEXT: slli s5, s5, 3
+; CHECK-RV64-NEXT: mv s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 5
+; CHECK-RV64-NEXT: add s5, s5, s6
+; CHECK-RV64-NEXT: add s5, sp, s5
+; CHECK-RV64-NEXT: addi s5, s5, 2047
+; CHECK-RV64-NEXT: addi s5, s5, 33
+; CHECK-RV64-NEXT: vs4r.v v20, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v12, a1
+; CHECK-RV64-NEXT: vmv.v.v v24, v16
+; CHECK-RV64-NEXT: addi s5, sp, 256
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v20, (s5)
+; CHECK-RV64-NEXT: addi s5, sp, 192
+; CHECK-RV64-NEXT: vle8.v v16, (s5)
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a4
+; CHECK-RV64-NEXT: csrr s5, vlenb
+; CHECK-RV64-NEXT: slli s5, s5, 8
+; CHECK-RV64-NEXT: add s5, sp, s5
+; CHECK-RV64-NEXT: addi s5, s5, 2047
+; CHECK-RV64-NEXT: addi s5, s5, 33
+; CHECK-RV64-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi s5, sp, 2047
+; CHECK-RV64-NEXT: addi s5, s5, 1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (s5)
+; CHECK-RV64-NEXT: csrr s5, vlenb
+; CHECK-RV64-NEXT: slli s5, s5, 3
+; CHECK-RV64-NEXT: mv s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s6, s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s6, s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s6, s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s5, s5, s6
+; CHECK-RV64-NEXT: add s5, sp, s5
+; CHECK-RV64-NEXT: addi s5, s5, 2047
+; CHECK-RV64-NEXT: addi s5, s5, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s5, sp, 1984
+; CHECK-RV64-NEXT: vle8.v v8, (s5)
+; CHECK-RV64-NEXT: csrr s5, vlenb
+; CHECK-RV64-NEXT: slli s5, s5, 4
+; CHECK-RV64-NEXT: mv s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s6, s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s6, s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s5, s5, s6
+; CHECK-RV64-NEXT: add s5, sp, s5
+; CHECK-RV64-NEXT: addi s5, s5, 2047
+; CHECK-RV64-NEXT: addi s5, s5, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s5, sp, 224
+; CHECK-RV64-NEXT: vle8.v v8, (s5)
+; CHECK-RV64-NEXT: addi s5, sp, 1536
+; CHECK-RV64-NEXT: vle8.v v12, (s5)
+; CHECK-RV64-NEXT: csrr s5, vlenb
+; CHECK-RV64-NEXT: slli s5, s5, 3
+; CHECK-RV64-NEXT: mv s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 2
+; CHECK-RV64-NEXT: add s6, s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s6, s6, s5
+; CHECK-RV64-NEXT: slli s5, s5, 1
+; CHECK-RV64-NEXT: add s5, s5, s6
+; CHECK-RV64-NEXT: add s5, sp, s5
+; CHECK-RV64-NEXT: addi s5, s5, 2047
+; CHECK-RV64-NEXT: addi s5, s5, 33
+; CHECK-RV64-NEXT: vs4r.v v12, (s5) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v20, a1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v24, (s4)
+; CHECK-RV64-NEXT: addi s4, sp, 1472
+; CHECK-RV64-NEXT: vle8.v v12, (s4)
+; CHECK-RV64-NEXT: csrr s4, vlenb
+; CHECK-RV64-NEXT: slli s4, s4, 5
+; CHECK-RV64-NEXT: mv s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 1
+; CHECK-RV64-NEXT: add s5, s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 1
+; CHECK-RV64-NEXT: add s4, s4, s5
+; CHECK-RV64-NEXT: add s4, sp, s4
+; CHECK-RV64-NEXT: addi s4, s4, 2047
+; CHECK-RV64-NEXT: addi s4, s4, 33
+; CHECK-RV64-NEXT: vs4r.v v12, (s4) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v16, a1
+; CHECK-RV64-NEXT: vmv.v.v v0, v24
+; CHECK-RV64-NEXT: addi s4, sp, 640
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v20, (s4)
+; CHECK-RV64-NEXT: addi s4, sp, 576
+; CHECK-RV64-NEXT: vle8.v v24, (s4)
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v0, v8, a4
+; CHECK-RV64-NEXT: csrr s4, vlenb
+; CHECK-RV64-NEXT: slli s4, s4, 3
+; CHECK-RV64-NEXT: mv s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 1
+; CHECK-RV64-NEXT: add s5, s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 2
+; CHECK-RV64-NEXT: add s5, s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 1
+; CHECK-RV64-NEXT: add s4, s4, s5
+; CHECK-RV64-NEXT: add s4, sp, s4
+; CHECK-RV64-NEXT: addi s4, s4, 2047
+; CHECK-RV64-NEXT: addi s4, s4, 33
+; CHECK-RV64-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi s4, sp, 512
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (s4)
+; CHECK-RV64-NEXT: csrr s4, vlenb
+; CHECK-RV64-NEXT: slli s4, s4, 4
+; CHECK-RV64-NEXT: mv s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 2
+; CHECK-RV64-NEXT: add s5, s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 1
+; CHECK-RV64-NEXT: add s4, s4, s5
+; CHECK-RV64-NEXT: add s4, sp, s4
+; CHECK-RV64-NEXT: addi s4, s4, 2047
+; CHECK-RV64-NEXT: addi s4, s4, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s4, sp, 448
+; CHECK-RV64-NEXT: vle8.v v8, (s4)
+; CHECK-RV64-NEXT: csrr s4, vlenb
+; CHECK-RV64-NEXT: slli s4, s4, 3
+; CHECK-RV64-NEXT: mv s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 3
+; CHECK-RV64-NEXT: add s5, s5, s4
+; CHECK-RV64-NEXT: slli s4, s4, 1
+; CHECK-RV64-NEXT: add s4, s4, s5
+; CHECK-RV64-NEXT: add s4, sp, s4
+; CHECK-RV64-NEXT: addi s4, s4, 2047
+; CHECK-RV64-NEXT: addi s4, s4, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s4, sp, 608
+; CHECK-RV64-NEXT: vle8.v v8, (s4)
+; CHECK-RV64-NEXT: addi s4, sp, 1664
+; CHECK-RV64-NEXT: vle8.v v16, (s4)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v20, a1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v0, (s3)
+; CHECK-RV64-NEXT: addi s3, sp, 1600
+; CHECK-RV64-NEXT: vle8.v v20, (s3)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v0, v24, a1
+; CHECK-RV64-NEXT: addi s3, sp, 1152
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v12, (s3)
+; CHECK-RV64-NEXT: csrr s3, vlenb
+; CHECK-RV64-NEXT: slli s3, s3, 3
+; CHECK-RV64-NEXT: mv s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 1
+; CHECK-RV64-NEXT: add s4, s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 1
+; CHECK-RV64-NEXT: add s4, s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 2
+; CHECK-RV64-NEXT: add s3, s3, s4
+; CHECK-RV64-NEXT: add s3, sp, s3
+; CHECK-RV64-NEXT: addi s3, s3, 2047
+; CHECK-RV64-NEXT: addi s3, s3, 33
+; CHECK-RV64-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s3, sp, 1088
+; CHECK-RV64-NEXT: vle8.v v24, (s3)
+; CHECK-RV64-NEXT: csrr s3, vlenb
+; CHECK-RV64-NEXT: slli s3, s3, 4
+; CHECK-RV64-NEXT: mv s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 1
+; CHECK-RV64-NEXT: add s4, s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 2
+; CHECK-RV64-NEXT: add s3, s3, s4
+; CHECK-RV64-NEXT: add s3, sp, s3
+; CHECK-RV64-NEXT: addi s3, s3, 2047
+; CHECK-RV64-NEXT: addi s3, s3, 33
+; CHECK-RV64-NEXT: vs4r.v v24, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v0, v8, a4
+; CHECK-RV64-NEXT: csrr s3, vlenb
+; CHECK-RV64-NEXT: slli s3, s3, 6
+; CHECK-RV64-NEXT: mv s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 1
+; CHECK-RV64-NEXT: add s3, s3, s4
+; CHECK-RV64-NEXT: add s3, sp, s3
+; CHECK-RV64-NEXT: addi s3, s3, 2047
+; CHECK-RV64-NEXT: addi s3, s3, 33
+; CHECK-RV64-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi s3, sp, 896
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (s3)
+; CHECK-RV64-NEXT: csrr s3, vlenb
+; CHECK-RV64-NEXT: slli s3, s3, 3
+; CHECK-RV64-NEXT: mv s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 2
+; CHECK-RV64-NEXT: add s4, s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 2
+; CHECK-RV64-NEXT: add s3, s3, s4
+; CHECK-RV64-NEXT: add s3, sp, s3
+; CHECK-RV64-NEXT: addi s3, s3, 2047
+; CHECK-RV64-NEXT: addi s3, s3, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s3, sp, 832
+; CHECK-RV64-NEXT: vle8.v v8, (s3)
+; CHECK-RV64-NEXT: csrr s3, vlenb
+; CHECK-RV64-NEXT: slli s3, s3, 3
+; CHECK-RV64-NEXT: mv s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 1
+; CHECK-RV64-NEXT: add s4, s4, s3
+; CHECK-RV64-NEXT: slli s3, s3, 3
+; CHECK-RV64-NEXT: add s3, s3, s4
+; CHECK-RV64-NEXT: add s3, sp, s3
+; CHECK-RV64-NEXT: addi s3, s3, 2047
+; CHECK-RV64-NEXT: addi s3, s3, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s3, sp, 1632
+; CHECK-RV64-NEXT: vle8.v v8, (s3)
+; CHECK-RV64-NEXT: addi s3, sp, 128
+; CHECK-RV64-NEXT: vle8.v v24, (s3)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v16, (s2)
+; CHECK-RV64-NEXT: addi s2, sp, 64
+; CHECK-RV64-NEXT: vle8.v v28, (s2)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: addi s2, sp, 1920
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v12, (s2)
+; CHECK-RV64-NEXT: csrr s2, vlenb
+; CHECK-RV64-NEXT: slli s2, s2, 4
+; CHECK-RV64-NEXT: mv s3, s2
+; CHECK-RV64-NEXT: slli s2, s2, 3
+; CHECK-RV64-NEXT: add s2, s2, s3
+; CHECK-RV64-NEXT: add s2, sp, s2
+; CHECK-RV64-NEXT: addi s2, s2, 2047
+; CHECK-RV64-NEXT: addi s2, s2, 33
+; CHECK-RV64-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s2, sp, 1856
+; CHECK-RV64-NEXT: vle8.v v20, (s2)
+; CHECK-RV64-NEXT: csrr s2, vlenb
+; CHECK-RV64-NEXT: slli s2, s2, 3
+; CHECK-RV64-NEXT: mv s3, s2
+; CHECK-RV64-NEXT: slli s2, s2, 1
+; CHECK-RV64-NEXT: add s3, s3, s2
+; CHECK-RV64-NEXT: slli s2, s2, 1
+; CHECK-RV64-NEXT: add s3, s3, s2
+; CHECK-RV64-NEXT: slli s2, s2, 1
+; CHECK-RV64-NEXT: add s2, s2, s3
+; CHECK-RV64-NEXT: add s2, sp, s2
+; CHECK-RV64-NEXT: addi s2, s2, 2047
+; CHECK-RV64-NEXT: addi s2, s2, 33
+; CHECK-RV64-NEXT: vs4r.v v20, (s2) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV64-NEXT: csrr s2, vlenb
+; CHECK-RV64-NEXT: slli s2, s2, 5
+; CHECK-RV64-NEXT: mv s3, s2
+; CHECK-RV64-NEXT: slli s2, s2, 2
+; CHECK-RV64-NEXT: add s2, s2, s3
+; CHECK-RV64-NEXT: add s2, sp, s2
+; CHECK-RV64-NEXT: addi s2, s2, 2047
+; CHECK-RV64-NEXT: addi s2, s2, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi s2, sp, 1408
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v4, (s2)
+; CHECK-RV64-NEXT: addi s2, sp, 1344
+; CHECK-RV64-NEXT: vle8.v v8, (s2)
+; CHECK-RV64-NEXT: csrr s2, vlenb
+; CHECK-RV64-NEXT: slli s2, s2, 5
+; CHECK-RV64-NEXT: mv s3, s2
+; CHECK-RV64-NEXT: slli s2, s2, 1
+; CHECK-RV64-NEXT: add s2, s2, s3
+; CHECK-RV64-NEXT: add s2, sp, s2
+; CHECK-RV64-NEXT: addi s2, s2, 2047
+; CHECK-RV64-NEXT: addi s2, s2, 33
+; CHECK-RV64-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
+; CHECK-RV64-NEXT: addi s2, sp, 96
+; CHECK-RV64-NEXT: vle8.v v8, (s2)
+; CHECK-RV64-NEXT: addi s2, sp, 384
+; CHECK-RV64-NEXT: vle8.v v0, (s2)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v24, a1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v16, (s1)
+; CHECK-RV64-NEXT: addi s1, sp, 320
+; CHECK-RV64-NEXT: vmv2r.v v12, v28
+; CHECK-RV64-NEXT: vle8.v v28, (s1)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v12, a1
+; CHECK-RV64-NEXT: addi s1, sp, 736
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v24, (s1)
+; CHECK-RV64-NEXT: csrr s1, vlenb
+; CHECK-RV64-NEXT: slli s1, s1, 7
+; CHECK-RV64-NEXT: add s1, sp, s1
+; CHECK-RV64-NEXT: addi s1, s1, 2047
+; CHECK-RV64-NEXT: addi s1, s1, 33
+; CHECK-RV64-NEXT: vs8r.v v24, (s1) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vle8.v v24, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv s1, a3
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: add a3, a3, s1
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv s1, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, s1
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a3, sp, 1760
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv s1, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add s1, s1, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, s1
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vle8.v v8, (a5)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a3, sp, 1376
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: addi a3, sp, 992
+; CHECK-RV64-NEXT: vle8.v v24, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v4, a1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v24, (t6)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: vle8.v v16, (a6)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v12, a1
+; CHECK-RV64-NEXT: addi a3, sp, 2016
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v16, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 6
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vle8.v v16, (a7)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vmv4r.v v16, v24
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a3, sp, 1504
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vle8.v v8, (t0)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a3, sp, 352
+; CHECK-RV64-NEXT: vle8.v v16, (a3)
+; CHECK-RV64-NEXT: addi a3, sp, 480
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v0, a1
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v0, (t5)
+; CHECK-RV64-NEXT: vle8.v v8, (t1)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v0, v28, a1
+; CHECK-RV64-NEXT: addi a3, sp, 1120
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vle8.v v8, (t2)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v0, v16, a4
+; CHECK-RV64-NEXT: addi a3, sp, 864
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV64-NEXT: vle8.v v24, (a3)
+; CHECK-RV64-NEXT: vle8.v v8, (t3)
+; CHECK-RV64-NEXT: addi a3, sp, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: addi a3, sp, 1888
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: vle8.v v16, (t4)
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v12, a1
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v0, (a0)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v12, a1
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a4
+; CHECK-RV64-NEXT: addi a3, a0, 1024
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vse8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: addi a3, sp, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslideup.vx v0, v8, a1
+; CHECK-RV64-NEXT: addi a3, a0, 512
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v16, (a3)
+; CHECK-RV64-NEXT: vslideup.vx v0, v24, a4
+; CHECK-RV64-NEXT: addi a3, a0, 256
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 4
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vse8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV64-NEXT: addi a3, a0, 1536
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v0, (a3)
+; CHECK-RV64-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: addi a3, a0, 1280
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v16, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV64-NEXT: addi a3, a0, 768
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 5
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vse8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: addi a3, a0, 128
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v16, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV64-NEXT: vmv.v.v v0, v16
+; CHECK-RV64-NEXT: addi a3, a0, 1792
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 6
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vse8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 6
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV64-NEXT: addi a3, a0, 1152
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v0, (a3)
+; CHECK-RV64-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: addi a3, a0, 640
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v16, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV64-NEXT: addi a3, a0, 384
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 3
+; CHECK-RV64-NEXT: mv a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 2
+; CHECK-RV64-NEXT: add a6, a6, a5
+; CHECK-RV64-NEXT: slli a5, a5, 1
+; CHECK-RV64-NEXT: add a5, a5, a6
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vse8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: addi a3, a0, 1664
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v16, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV64-NEXT: vmv.v.v v0, v16
+; CHECK-RV64-NEXT: addi a3, a0, 1408
+; CHECK-RV64-NEXT: csrr a5, vlenb
+; CHECK-RV64-NEXT: slli a5, a5, 8
+; CHECK-RV64-NEXT: add a5, sp, a5
+; CHECK-RV64-NEXT: addi a5, a5, 2047
+; CHECK-RV64-NEXT: addi a5, a5, 33
+; CHECK-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vse8.v v8, (a3)
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 1
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 7
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vslideup.vx v24, v8, a1
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 2
+; CHECK-RV64-NEXT: add a5, a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 3
+; CHECK-RV64-NEXT: mv a5, a3
+; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: add a3, a3, a5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 2047
+; CHECK-RV64-NEXT: addi a3, a3, 33
+; CHECK-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vslideup.vx v16, v8, a1
+; CHECK-RV64-NEXT: addi a1, a0, 896
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-RV64-NEXT: vse8.v v0, (a1)
+; CHECK-RV64-NEXT: vslideup.vx v16, v24, a4
+; CHECK-RV64-NEXT: addi a0, a0, 1920
+; CHECK-RV64-NEXT: vse8.v v16, (a0)
+; CHECK-RV64-NEXT: addi sp, s0, -2032
+; CHECK-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: ld s4, 1984(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: ld s5, 1976(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: ld s6, 1968(sp) # 8-byte Folded Reload
+; CHECK-RV64-NEXT: addi sp, sp, 2032
+; CHECK-RV64-NEXT: ret
+;
+; ZVBB-RV32-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVBB-RV32: # %bb.0:
+; ZVBB-RV32-NEXT: addi sp, sp, -2032
+; ZVBB-RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: sw s1, 2020(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: sw s2, 2016(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: sw s3, 2012(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: sw s4, 2008(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: sw s5, 2004(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: sw s6, 2000(sp) # 4-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s0, sp, 2032
+; ZVBB-RV32-NEXT: addi sp, sp, -80
+; ZVBB-RV32-NEXT: csrr a2, vlenb
+; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: mv a4, a2
+; ZVBB-RV32-NEXT: slli a2, a2, 1
+; ZVBB-RV32-NEXT: add a4, a4, a2
+; ZVBB-RV32-NEXT: slli a2, a2, 1
+; ZVBB-RV32-NEXT: add a4, a4, a2
+; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a2, a2, a4
+; ZVBB-RV32-NEXT: sub sp, sp, a2
+; ZVBB-RV32-NEXT: andi sp, sp, -32
+; ZVBB-RV32-NEXT: csrr a2, vlenb
+; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: mv a4, a2
+; ZVBB-RV32-NEXT: slli a2, a2, 2
+; ZVBB-RV32-NEXT: add a4, a4, a2
+; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a2, a2, a4
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 2047
+; ZVBB-RV32-NEXT: addi a2, a2, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: csrr a2, vlenb
+; ZVBB-RV32-NEXT: slli a2, a2, 8
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 2047
+; ZVBB-RV32-NEXT: addi a2, a2, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: li a2, 128
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v16, (a7)
+; ZVBB-RV32-NEXT: csrr a4, vlenb
+; ZVBB-RV32-NEXT: slli a4, a4, 4
+; ZVBB-RV32-NEXT: mv a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 3
+; ZVBB-RV32-NEXT: add a4, a4, a5
+; ZVBB-RV32-NEXT: add a4, sp, a4
+; ZVBB-RV32-NEXT: addi a4, a4, 2047
+; ZVBB-RV32-NEXT: addi a4, a4, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a4, vlenb
+; ZVBB-RV32-NEXT: slli a4, a4, 3
+; ZVBB-RV32-NEXT: mv a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a4, a4, a5
+; ZVBB-RV32-NEXT: add a4, sp, a4
+; ZVBB-RV32-NEXT: addi a4, a4, 2047
+; ZVBB-RV32-NEXT: addi a4, a4, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a4, a7, 256
+; ZVBB-RV32-NEXT: vle8.v v16, (a4)
+; ZVBB-RV32-NEXT: csrr a4, vlenb
+; ZVBB-RV32-NEXT: slli a4, a4, 5
+; ZVBB-RV32-NEXT: mv a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 3
+; ZVBB-RV32-NEXT: add a4, a4, a5
+; ZVBB-RV32-NEXT: add a4, sp, a4
+; ZVBB-RV32-NEXT: addi a4, a4, 2047
+; ZVBB-RV32-NEXT: addi a4, a4, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a4, a1, 128
+; ZVBB-RV32-NEXT: vle8.v v24, (a4)
+; ZVBB-RV32-NEXT: csrr a4, vlenb
+; ZVBB-RV32-NEXT: slli a4, a4, 4
+; ZVBB-RV32-NEXT: mv a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a4, a4, a5
+; ZVBB-RV32-NEXT: add a4, sp, a4
+; ZVBB-RV32-NEXT: addi a4, a4, 2047
+; ZVBB-RV32-NEXT: addi a4, a4, 33
+; ZVBB-RV32-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a4, a3, 384
+; ZVBB-RV32-NEXT: vle8.v v16, (a4)
+; ZVBB-RV32-NEXT: csrr a4, vlenb
+; ZVBB-RV32-NEXT: slli a4, a4, 3
+; ZVBB-RV32-NEXT: mv a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 2
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a5, a5, a4
+; ZVBB-RV32-NEXT: slli a4, a4, 1
+; ZVBB-RV32-NEXT: add a4, a4, a5
+; ZVBB-RV32-NEXT: add a4, sp, a4
+; ZVBB-RV32-NEXT: addi a4, a4, 2047
+; ZVBB-RV32-NEXT: addi a4, a4, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: li a4, 64
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a5, a7, 384
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (a5)
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 5
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v0, v16, a4
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a5, s0, 768
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v24, (a5)
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 4
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a5, a3, 256
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v16, (a5)
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 4
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 4
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v16, (a1)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: slli a1, a1, 4
+; ZVBB-RV32-NEXT: mv a5, a1
+; ZVBB-RV32-NEXT: slli a1, a1, 4
+; ZVBB-RV32-NEXT: add a1, a1, a5
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 2047
+; ZVBB-RV32-NEXT: addi a1, a1, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: li a1, 32
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v0, a1
+; ZVBB-RV32-NEXT: addi a5, a7, 128
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v0, (a5)
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 4
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v16, v8, a1
+; ZVBB-RV32-NEXT: addi a3, a3, 128
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vmv2r.v v18, v20
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV32-NEXT: vmv2r.v v22, v24
+; ZVBB-RV32-NEXT: addi a3, sp, 672
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v16, (a3)
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a4
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 5
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v16, v16, a4
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 4
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a5, s0, 512
+; ZVBB-RV32-NEXT: vslidedown.vx v0, v0, a4
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 3
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 2
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (a5)
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 7
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v16, a1
+; ZVBB-RV32-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v16, v8, a1
+; ZVBB-RV32-NEXT: vmv2r.v v18, v20
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v0, a1
+; ZVBB-RV32-NEXT: vmv2r.v v22, v24
+; ZVBB-RV32-NEXT: addi a5, sp, 1696
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v16, (a5)
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 4
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 4
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v0, v16, a4
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 4
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 2
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 3
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 4
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v24, v16, a4
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 3
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 2
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a6, s0, 640
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 5
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a4
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 5
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 2
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (a6)
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 6
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 5
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v24, a1
+; ZVBB-RV32-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV32-NEXT: vslidedown.vx v16, v0, a1
+; ZVBB-RV32-NEXT: vmv2r.v v18, v20
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 5
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 2
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV32-NEXT: vmv2r.v v22, v24
+; ZVBB-RV32-NEXT: addi s5, sp, 1184
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v16, (s5)
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 3
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 2
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v16, a1
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 3
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 2
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 4
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v16, v0, a1
+; ZVBB-RV32-NEXT: vmv2r.v v18, v20
+; ZVBB-RV32-NEXT: csrr a6, vlenb
+; ZVBB-RV32-NEXT: slli a6, a6, 5
+; ZVBB-RV32-NEXT: mv a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a7, a7, a6
+; ZVBB-RV32-NEXT: slli a6, a6, 1
+; ZVBB-RV32-NEXT: add a6, a6, a7
+; ZVBB-RV32-NEXT: add a6, sp, a6
+; ZVBB-RV32-NEXT: addi a6, a6, 2047
+; ZVBB-RV32-NEXT: addi a6, a6, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV32-NEXT: vmv2r.v v22, v24
+; ZVBB-RV32-NEXT: addi a6, sp, 928
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v16, (a6)
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 8
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v16, v8, a4
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 6
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a7, s0, 384
+; ZVBB-RV32-NEXT: csrr t0, vlenb
+; ZVBB-RV32-NEXT: slli t0, t0, 4
+; ZVBB-RV32-NEXT: mv t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 1
+; ZVBB-RV32-NEXT: add t1, t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 3
+; ZVBB-RV32-NEXT: add t0, t0, t1
+; ZVBB-RV32-NEXT: add t0, sp, t0
+; ZVBB-RV32-NEXT: addi t0, t0, 2047
+; ZVBB-RV32-NEXT: addi t0, t0, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV32-NEXT: csrr t0, vlenb
+; ZVBB-RV32-NEXT: slli t0, t0, 4
+; ZVBB-RV32-NEXT: mv t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 3
+; ZVBB-RV32-NEXT: add t0, t0, t1
+; ZVBB-RV32-NEXT: add t0, sp, t0
+; ZVBB-RV32-NEXT: addi t0, t0, 2047
+; ZVBB-RV32-NEXT: addi t0, t0, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v24, (a7)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v12, v16, a1
+; ZVBB-RV32-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v0, a1
+; ZVBB-RV32-NEXT: vmv2r.v v10, v12
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 4
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v12, v0, a1
+; ZVBB-RV32-NEXT: vmv2r.v v14, v20
+; ZVBB-RV32-NEXT: addi s4, sp, 160
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s4)
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 5
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a1
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v12, v16, a1
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 2
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 3
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v4, v16, a1
+; ZVBB-RV32-NEXT: vmv2r.v v6, v8
+; ZVBB-RV32-NEXT: csrr a7, vlenb
+; ZVBB-RV32-NEXT: slli a7, a7, 4
+; ZVBB-RV32-NEXT: mv t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 2
+; ZVBB-RV32-NEXT: add t0, t0, a7
+; ZVBB-RV32-NEXT: slli a7, a7, 1
+; ZVBB-RV32-NEXT: add a7, a7, t0
+; ZVBB-RV32-NEXT: add a7, sp, a7
+; ZVBB-RV32-NEXT: addi a7, a7, 2047
+; ZVBB-RV32-NEXT: addi a7, a7, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a1
+; ZVBB-RV32-NEXT: vmv2r.v v10, v12
+; ZVBB-RV32-NEXT: addi a7, sp, 1952
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v4, (a7)
+; ZVBB-RV32-NEXT: csrr t0, vlenb
+; ZVBB-RV32-NEXT: slli t0, t0, 3
+; ZVBB-RV32-NEXT: mv t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 1
+; ZVBB-RV32-NEXT: add t1, t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 4
+; ZVBB-RV32-NEXT: add t0, t0, t1
+; ZVBB-RV32-NEXT: add t0, sp, t0
+; ZVBB-RV32-NEXT: addi t0, t0, 2047
+; ZVBB-RV32-NEXT: addi t0, t0, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a1
+; ZVBB-RV32-NEXT: csrr t0, vlenb
+; ZVBB-RV32-NEXT: slli t0, t0, 6
+; ZVBB-RV32-NEXT: mv t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 1
+; ZVBB-RV32-NEXT: add t0, t0, t1
+; ZVBB-RV32-NEXT: add t0, sp, t0
+; ZVBB-RV32-NEXT: addi t0, t0, 2047
+; ZVBB-RV32-NEXT: addi t0, t0, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v12, v16, a1
+; ZVBB-RV32-NEXT: csrr t0, vlenb
+; ZVBB-RV32-NEXT: slli t0, t0, 4
+; ZVBB-RV32-NEXT: mv t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 4
+; ZVBB-RV32-NEXT: add t0, t0, t1
+; ZVBB-RV32-NEXT: add t0, sp, t0
+; ZVBB-RV32-NEXT: addi t0, t0, 2047
+; ZVBB-RV32-NEXT: addi t0, t0, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v4, v16, a1
+; ZVBB-RV32-NEXT: vmv2r.v v6, v8
+; ZVBB-RV32-NEXT: csrr t0, vlenb
+; ZVBB-RV32-NEXT: slli t0, t0, 5
+; ZVBB-RV32-NEXT: mv t1, t0
+; ZVBB-RV32-NEXT: slli t0, t0, 3
+; ZVBB-RV32-NEXT: add t0, t0, t1
+; ZVBB-RV32-NEXT: add t0, sp, t0
+; ZVBB-RV32-NEXT: addi t0, t0, 2047
+; ZVBB-RV32-NEXT: addi t0, t0, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a1
+; ZVBB-RV32-NEXT: vmv2r.v v10, v12
+; ZVBB-RV32-NEXT: addi t0, sp, 1440
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v4, (t0)
+; ZVBB-RV32-NEXT: csrr t1, vlenb
+; ZVBB-RV32-NEXT: slli t1, t1, 3
+; ZVBB-RV32-NEXT: mv t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 2
+; ZVBB-RV32-NEXT: add t1, t1, t2
+; ZVBB-RV32-NEXT: add t1, sp, t1
+; ZVBB-RV32-NEXT: addi t1, t1, 2047
+; ZVBB-RV32-NEXT: addi t1, t1, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t1, vlenb
+; ZVBB-RV32-NEXT: slli t1, t1, 3
+; ZVBB-RV32-NEXT: mv t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t1, t1, t2
+; ZVBB-RV32-NEXT: add t1, sp, t1
+; ZVBB-RV32-NEXT: addi t1, t1, 2047
+; ZVBB-RV32-NEXT: addi t1, t1, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t1, vlenb
+; ZVBB-RV32-NEXT: slli t1, t1, 4
+; ZVBB-RV32-NEXT: mv t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 2
+; ZVBB-RV32-NEXT: add t1, t1, t2
+; ZVBB-RV32-NEXT: add t1, sp, t1
+; ZVBB-RV32-NEXT: addi t1, t1, 2047
+; ZVBB-RV32-NEXT: addi t1, t1, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: csrr t1, vlenb
+; ZVBB-RV32-NEXT: slli t1, t1, 3
+; ZVBB-RV32-NEXT: mv t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 4
+; ZVBB-RV32-NEXT: add t1, t1, t2
+; ZVBB-RV32-NEXT: add t1, sp, t1
+; ZVBB-RV32-NEXT: addi t1, t1, 2047
+; ZVBB-RV32-NEXT: addi t1, t1, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v14, v16
+; ZVBB-RV32-NEXT: addi s3, sp, 544
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s3)
+; ZVBB-RV32-NEXT: csrr t1, vlenb
+; ZVBB-RV32-NEXT: slli t1, t1, 3
+; ZVBB-RV32-NEXT: mv t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t1, t1, t2
+; ZVBB-RV32-NEXT: add t1, sp, t1
+; ZVBB-RV32-NEXT: addi t1, t1, 2047
+; ZVBB-RV32-NEXT: addi t1, t1, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v8, a1
+; ZVBB-RV32-NEXT: vslidedown.vx v12, v24, a1
+; ZVBB-RV32-NEXT: csrr t1, vlenb
+; ZVBB-RV32-NEXT: slli t1, t1, 8
+; ZVBB-RV32-NEXT: add t1, sp, t1
+; ZVBB-RV32-NEXT: addi t1, t1, 2047
+; ZVBB-RV32-NEXT: addi t1, t1, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v4, v16, a1
+; ZVBB-RV32-NEXT: vmv2r.v v6, v8
+; ZVBB-RV32-NEXT: csrr t1, vlenb
+; ZVBB-RV32-NEXT: slli t1, t1, 4
+; ZVBB-RV32-NEXT: mv t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 1
+; ZVBB-RV32-NEXT: add t2, t2, t1
+; ZVBB-RV32-NEXT: slli t1, t1, 3
+; ZVBB-RV32-NEXT: add t1, t1, t2
+; ZVBB-RV32-NEXT: add t1, sp, t1
+; ZVBB-RV32-NEXT: addi t1, t1, 2047
+; ZVBB-RV32-NEXT: addi t1, t1, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a1
+; ZVBB-RV32-NEXT: vmv2r.v v10, v12
+; ZVBB-RV32-NEXT: addi t1, sp, 416
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vsseg4e8.v v4, (t1)
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 3
+; ZVBB-RV32-NEXT: mv t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 2
+; ZVBB-RV32-NEXT: add t3, t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 2
+; ZVBB-RV32-NEXT: add t2, t2, t3
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 4
+; ZVBB-RV32-NEXT: mv t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 1
+; ZVBB-RV32-NEXT: add t3, t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 1
+; ZVBB-RV32-NEXT: add t2, t2, t3
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 3
+; ZVBB-RV32-NEXT: mv t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 2
+; ZVBB-RV32-NEXT: add t3, t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 1
+; ZVBB-RV32-NEXT: add t2, t2, t3
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 7
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v14, v16
+; ZVBB-RV32-NEXT: addi s2, sp, 1568
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s2)
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 4
+; ZVBB-RV32-NEXT: mv t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 2
+; ZVBB-RV32-NEXT: add t2, t2, t3
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 3
+; ZVBB-RV32-NEXT: mv t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 1
+; ZVBB-RV32-NEXT: add t3, t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 2
+; ZVBB-RV32-NEXT: add t2, t2, t3
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 5
+; ZVBB-RV32-NEXT: mv t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 2
+; ZVBB-RV32-NEXT: add t2, t2, t3
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: csrr t2, vlenb
+; ZVBB-RV32-NEXT: slli t2, t2, 5
+; ZVBB-RV32-NEXT: mv t3, t2
+; ZVBB-RV32-NEXT: slli t2, t2, 1
+; ZVBB-RV32-NEXT: add t2, t2, t3
+; ZVBB-RV32-NEXT: add t2, sp, t2
+; ZVBB-RV32-NEXT: addi t2, t2, 2047
+; ZVBB-RV32-NEXT: addi t2, t2, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v14, v16
+; ZVBB-RV32-NEXT: addi t2, sp, 1056
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t2)
+; ZVBB-RV32-NEXT: csrr t3, vlenb
+; ZVBB-RV32-NEXT: slli t3, t3, 4
+; ZVBB-RV32-NEXT: mv t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t4, t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t4, t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t3, t3, t4
+; ZVBB-RV32-NEXT: add t3, sp, t3
+; ZVBB-RV32-NEXT: addi t3, t3, 2047
+; ZVBB-RV32-NEXT: addi t3, t3, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t3, vlenb
+; ZVBB-RV32-NEXT: slli t3, t3, 3
+; ZVBB-RV32-NEXT: mv t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 2
+; ZVBB-RV32-NEXT: add t4, t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t4, t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t3, t3, t4
+; ZVBB-RV32-NEXT: add t3, sp, t3
+; ZVBB-RV32-NEXT: addi t3, t3, 2047
+; ZVBB-RV32-NEXT: addi t3, t3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t3, vlenb
+; ZVBB-RV32-NEXT: slli t3, t3, 5
+; ZVBB-RV32-NEXT: mv t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t4, t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t3, t3, t4
+; ZVBB-RV32-NEXT: add t3, sp, t3
+; ZVBB-RV32-NEXT: addi t3, t3, 2047
+; ZVBB-RV32-NEXT: addi t3, t3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: csrr t3, vlenb
+; ZVBB-RV32-NEXT: slli t3, t3, 3
+; ZVBB-RV32-NEXT: mv t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t4, t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 2
+; ZVBB-RV32-NEXT: add t4, t4, t3
+; ZVBB-RV32-NEXT: slli t3, t3, 1
+; ZVBB-RV32-NEXT: add t3, t3, t4
+; ZVBB-RV32-NEXT: add t3, sp, t3
+; ZVBB-RV32-NEXT: addi t3, t3, 2047
+; ZVBB-RV32-NEXT: addi t3, t3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v14, v16
+; ZVBB-RV32-NEXT: addi t3, sp, 800
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t3)
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: mv t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 1
+; ZVBB-RV32-NEXT: add t5, t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: add t4, t4, t5
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 6
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 4
+; ZVBB-RV32-NEXT: mv t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: add t4, t4, t5
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: mv t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: add t4, t4, t5
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v14, v16
+; ZVBB-RV32-NEXT: addi s1, sp, 32
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s1)
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: mv t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 2
+; ZVBB-RV32-NEXT: add t5, t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: add t4, t4, t5
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: mv t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 5
+; ZVBB-RV32-NEXT: add t4, t4, t5
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 4
+; ZVBB-RV32-NEXT: mv t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 2
+; ZVBB-RV32-NEXT: add t5, t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 1
+; ZVBB-RV32-NEXT: add t4, t4, t5
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: csrr t4, vlenb
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: mv t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 3
+; ZVBB-RV32-NEXT: add t5, t5, t4
+; ZVBB-RV32-NEXT: slli t4, t4, 1
+; ZVBB-RV32-NEXT: add t4, t4, t5
+; ZVBB-RV32-NEXT: add t4, sp, t4
+; ZVBB-RV32-NEXT: addi t4, t4, 2047
+; ZVBB-RV32-NEXT: addi t4, t4, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v14, v16
+; ZVBB-RV32-NEXT: addi t4, sp, 1824
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t4)
+; ZVBB-RV32-NEXT: csrr t5, vlenb
+; ZVBB-RV32-NEXT: slli t5, t5, 4
+; ZVBB-RV32-NEXT: mv t6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 4
+; ZVBB-RV32-NEXT: add t5, t5, t6
+; ZVBB-RV32-NEXT: add t5, sp, t5
+; ZVBB-RV32-NEXT: addi t5, t5, 2047
+; ZVBB-RV32-NEXT: addi t5, t5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t5, vlenb
+; ZVBB-RV32-NEXT: slli t5, t5, 3
+; ZVBB-RV32-NEXT: mv t6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 1
+; ZVBB-RV32-NEXT: add t6, t6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 4
+; ZVBB-RV32-NEXT: add t5, t5, t6
+; ZVBB-RV32-NEXT: add t5, sp, t5
+; ZVBB-RV32-NEXT: addi t5, t5, 2047
+; ZVBB-RV32-NEXT: addi t5, t5, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t5, vlenb
+; ZVBB-RV32-NEXT: slli t5, t5, 5
+; ZVBB-RV32-NEXT: mv t6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 3
+; ZVBB-RV32-NEXT: add t5, t5, t6
+; ZVBB-RV32-NEXT: add t5, sp, t5
+; ZVBB-RV32-NEXT: addi t5, t5, 2047
+; ZVBB-RV32-NEXT: addi t5, t5, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: csrr t5, vlenb
+; ZVBB-RV32-NEXT: slli t5, t5, 6
+; ZVBB-RV32-NEXT: mv t6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 1
+; ZVBB-RV32-NEXT: add t5, t5, t6
+; ZVBB-RV32-NEXT: add t5, sp, t5
+; ZVBB-RV32-NEXT: addi t5, t5, 2047
+; ZVBB-RV32-NEXT: addi t5, t5, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v14, v16
+; ZVBB-RV32-NEXT: addi t6, sp, 1312
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t6)
+; ZVBB-RV32-NEXT: csrr t5, vlenb
+; ZVBB-RV32-NEXT: slli t5, t5, 8
+; ZVBB-RV32-NEXT: add t5, sp, t5
+; ZVBB-RV32-NEXT: addi t5, t5, 2047
+; ZVBB-RV32-NEXT: addi t5, t5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr t5, vlenb
+; ZVBB-RV32-NEXT: slli t5, t5, 3
+; ZVBB-RV32-NEXT: mv s6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 1
+; ZVBB-RV32-NEXT: add s6, s6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 1
+; ZVBB-RV32-NEXT: add s6, s6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 1
+; ZVBB-RV32-NEXT: add s6, s6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 1
+; ZVBB-RV32-NEXT: add t5, t5, s6
+; ZVBB-RV32-NEXT: add t5, sp, t5
+; ZVBB-RV32-NEXT: addi t5, t5, 2047
+; ZVBB-RV32-NEXT: addi t5, t5, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v10, v16
+; ZVBB-RV32-NEXT: csrr t5, vlenb
+; ZVBB-RV32-NEXT: slli t5, t5, 4
+; ZVBB-RV32-NEXT: mv s6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 1
+; ZVBB-RV32-NEXT: add s6, s6, t5
+; ZVBB-RV32-NEXT: slli t5, t5, 3
+; ZVBB-RV32-NEXT: add t5, t5, s6
+; ZVBB-RV32-NEXT: add t5, sp, t5
+; ZVBB-RV32-NEXT: addi t5, t5, 2047
+; ZVBB-RV32-NEXT: addi t5, t5, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vmv2r.v v12, v16
+; ZVBB-RV32-NEXT: vmv2r.v v14, v24
+; ZVBB-RV32-NEXT: addi t5, sp, 288
+; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t5)
+; ZVBB-RV32-NEXT: addi s6, sp, 768
+; ZVBB-RV32-NEXT: vle8.v v8, (s6)
+; ZVBB-RV32-NEXT: csrr s6, vlenb
+; ZVBB-RV32-NEXT: slli s6, s6, 4
+; ZVBB-RV32-NEXT: mv ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 1
+; ZVBB-RV32-NEXT: add ra, ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 3
+; ZVBB-RV32-NEXT: add s6, s6, ra
+; ZVBB-RV32-NEXT: add s6, sp, s6
+; ZVBB-RV32-NEXT: addi s6, s6, 2047
+; ZVBB-RV32-NEXT: addi s6, s6, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s6, sp, 704
+; ZVBB-RV32-NEXT: vle8.v v8, (s6)
+; ZVBB-RV32-NEXT: csrr s6, vlenb
+; ZVBB-RV32-NEXT: slli s6, s6, 3
+; ZVBB-RV32-NEXT: mv ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 2
+; ZVBB-RV32-NEXT: add ra, ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 3
+; ZVBB-RV32-NEXT: add s6, s6, ra
+; ZVBB-RV32-NEXT: add s6, sp, s6
+; ZVBB-RV32-NEXT: addi s6, s6, 2047
+; ZVBB-RV32-NEXT: addi s6, s6, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s6, sp, 1792
+; ZVBB-RV32-NEXT: vle8.v v8, (s6)
+; ZVBB-RV32-NEXT: csrr s6, vlenb
+; ZVBB-RV32-NEXT: slli s6, s6, 5
+; ZVBB-RV32-NEXT: mv ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 3
+; ZVBB-RV32-NEXT: add s6, s6, ra
+; ZVBB-RV32-NEXT: add s6, sp, s6
+; ZVBB-RV32-NEXT: addi s6, s6, 2047
+; ZVBB-RV32-NEXT: addi s6, s6, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s6, sp, 1728
+; ZVBB-RV32-NEXT: vle8.v v8, (s6)
+; ZVBB-RV32-NEXT: csrr s6, vlenb
+; ZVBB-RV32-NEXT: slli s6, s6, 3
+; ZVBB-RV32-NEXT: mv ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 1
+; ZVBB-RV32-NEXT: add ra, ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 4
+; ZVBB-RV32-NEXT: add s6, s6, ra
+; ZVBB-RV32-NEXT: add s6, sp, s6
+; ZVBB-RV32-NEXT: addi s6, s6, 2047
+; ZVBB-RV32-NEXT: addi s6, s6, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s6, sp, 1280
+; ZVBB-RV32-NEXT: vle8.v v16, (s6)
+; ZVBB-RV32-NEXT: addi s6, sp, 1248
+; ZVBB-RV32-NEXT: vle8.v v8, (s6)
+; ZVBB-RV32-NEXT: addi s6, sp, 1216
+; ZVBB-RV32-NEXT: vle8.v v12, (s6)
+; ZVBB-RV32-NEXT: addi s6, sp, 1024
+; ZVBB-RV32-NEXT: vle8.v v20, (s6)
+; ZVBB-RV32-NEXT: csrr s6, vlenb
+; ZVBB-RV32-NEXT: slli s6, s6, 4
+; ZVBB-RV32-NEXT: mv ra, s6
+; ZVBB-RV32-NEXT: slli s6, s6, 4
+; ZVBB-RV32-NEXT: add s6, s6, ra
+; ZVBB-RV32-NEXT: add s6, sp, s6
+; ZVBB-RV32-NEXT: addi s6, s6, 2047
+; ZVBB-RV32-NEXT: addi s6, s6, 33
+; ZVBB-RV32-NEXT: vs4r.v v20, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v8, v16, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v16, (s5)
+; ZVBB-RV32-NEXT: addi s5, sp, 960
+; ZVBB-RV32-NEXT: vle8.v v20, (s5)
+; ZVBB-RV32-NEXT: csrr s5, vlenb
+; ZVBB-RV32-NEXT: slli s5, s5, 3
+; ZVBB-RV32-NEXT: mv s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 5
+; ZVBB-RV32-NEXT: add s5, s5, s6
+; ZVBB-RV32-NEXT: add s5, sp, s5
+; ZVBB-RV32-NEXT: addi s5, s5, 2047
+; ZVBB-RV32-NEXT: addi s5, s5, 33
+; ZVBB-RV32-NEXT: vs4r.v v20, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v12, a1
+; ZVBB-RV32-NEXT: vmv.v.v v24, v16
+; ZVBB-RV32-NEXT: addi s5, sp, 256
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v20, (s5)
+; ZVBB-RV32-NEXT: addi s5, sp, 192
+; ZVBB-RV32-NEXT: vle8.v v16, (s5)
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a4
+; ZVBB-RV32-NEXT: csrr s5, vlenb
+; ZVBB-RV32-NEXT: slli s5, s5, 8
+; ZVBB-RV32-NEXT: add s5, sp, s5
+; ZVBB-RV32-NEXT: addi s5, s5, 2047
+; ZVBB-RV32-NEXT: addi s5, s5, 33
+; ZVBB-RV32-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s5, sp, 2047
+; ZVBB-RV32-NEXT: addi s5, s5, 1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (s5)
+; ZVBB-RV32-NEXT: csrr s5, vlenb
+; ZVBB-RV32-NEXT: slli s5, s5, 3
+; ZVBB-RV32-NEXT: mv s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s6, s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s6, s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s6, s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s5, s5, s6
+; ZVBB-RV32-NEXT: add s5, sp, s5
+; ZVBB-RV32-NEXT: addi s5, s5, 2047
+; ZVBB-RV32-NEXT: addi s5, s5, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s5, sp, 1984
+; ZVBB-RV32-NEXT: vle8.v v8, (s5)
+; ZVBB-RV32-NEXT: csrr s5, vlenb
+; ZVBB-RV32-NEXT: slli s5, s5, 4
+; ZVBB-RV32-NEXT: mv s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s6, s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s6, s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s5, s5, s6
+; ZVBB-RV32-NEXT: add s5, sp, s5
+; ZVBB-RV32-NEXT: addi s5, s5, 2047
+; ZVBB-RV32-NEXT: addi s5, s5, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s5, sp, 224
+; ZVBB-RV32-NEXT: vle8.v v8, (s5)
+; ZVBB-RV32-NEXT: addi s5, sp, 1536
+; ZVBB-RV32-NEXT: vle8.v v12, (s5)
+; ZVBB-RV32-NEXT: csrr s5, vlenb
+; ZVBB-RV32-NEXT: slli s5, s5, 3
+; ZVBB-RV32-NEXT: mv s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 2
+; ZVBB-RV32-NEXT: add s6, s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s6, s6, s5
+; ZVBB-RV32-NEXT: slli s5, s5, 1
+; ZVBB-RV32-NEXT: add s5, s5, s6
+; ZVBB-RV32-NEXT: add s5, sp, s5
+; ZVBB-RV32-NEXT: addi s5, s5, 2047
+; ZVBB-RV32-NEXT: addi s5, s5, 33
+; ZVBB-RV32-NEXT: vs4r.v v12, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v8, v20, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v24, (s4)
+; ZVBB-RV32-NEXT: addi s4, sp, 1472
+; ZVBB-RV32-NEXT: vle8.v v12, (s4)
+; ZVBB-RV32-NEXT: csrr s4, vlenb
+; ZVBB-RV32-NEXT: slli s4, s4, 5
+; ZVBB-RV32-NEXT: mv s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 1
+; ZVBB-RV32-NEXT: add s5, s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 1
+; ZVBB-RV32-NEXT: add s4, s4, s5
+; ZVBB-RV32-NEXT: add s4, sp, s4
+; ZVBB-RV32-NEXT: addi s4, s4, 2047
+; ZVBB-RV32-NEXT: addi s4, s4, 33
+; ZVBB-RV32-NEXT: vs4r.v v12, (s4) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v16, a1
+; ZVBB-RV32-NEXT: vmv.v.v v0, v24
+; ZVBB-RV32-NEXT: addi s4, sp, 640
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v20, (s4)
+; ZVBB-RV32-NEXT: addi s4, sp, 576
+; ZVBB-RV32-NEXT: vle8.v v24, (s4)
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v0, v8, a4
+; ZVBB-RV32-NEXT: csrr s4, vlenb
+; ZVBB-RV32-NEXT: slli s4, s4, 3
+; ZVBB-RV32-NEXT: mv s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 1
+; ZVBB-RV32-NEXT: add s5, s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 2
+; ZVBB-RV32-NEXT: add s5, s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 1
+; ZVBB-RV32-NEXT: add s4, s4, s5
+; ZVBB-RV32-NEXT: add s4, sp, s4
+; ZVBB-RV32-NEXT: addi s4, s4, 2047
+; ZVBB-RV32-NEXT: addi s4, s4, 33
+; ZVBB-RV32-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s4, sp, 512
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (s4)
+; ZVBB-RV32-NEXT: csrr s4, vlenb
+; ZVBB-RV32-NEXT: slli s4, s4, 4
+; ZVBB-RV32-NEXT: mv s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 2
+; ZVBB-RV32-NEXT: add s5, s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 1
+; ZVBB-RV32-NEXT: add s4, s4, s5
+; ZVBB-RV32-NEXT: add s4, sp, s4
+; ZVBB-RV32-NEXT: addi s4, s4, 2047
+; ZVBB-RV32-NEXT: addi s4, s4, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s4, sp, 448
+; ZVBB-RV32-NEXT: vle8.v v8, (s4)
+; ZVBB-RV32-NEXT: csrr s4, vlenb
+; ZVBB-RV32-NEXT: slli s4, s4, 3
+; ZVBB-RV32-NEXT: mv s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 3
+; ZVBB-RV32-NEXT: add s5, s5, s4
+; ZVBB-RV32-NEXT: slli s4, s4, 1
+; ZVBB-RV32-NEXT: add s4, s4, s5
+; ZVBB-RV32-NEXT: add s4, sp, s4
+; ZVBB-RV32-NEXT: addi s4, s4, 2047
+; ZVBB-RV32-NEXT: addi s4, s4, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s4, sp, 608
+; ZVBB-RV32-NEXT: vle8.v v8, (s4)
+; ZVBB-RV32-NEXT: addi s4, sp, 1664
+; ZVBB-RV32-NEXT: vle8.v v16, (s4)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v8, v20, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v0, (s3)
+; ZVBB-RV32-NEXT: addi s3, sp, 1600
+; ZVBB-RV32-NEXT: vle8.v v20, (s3)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v0, v24, a1
+; ZVBB-RV32-NEXT: addi s3, sp, 1152
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v12, (s3)
+; ZVBB-RV32-NEXT: csrr s3, vlenb
+; ZVBB-RV32-NEXT: slli s3, s3, 3
+; ZVBB-RV32-NEXT: mv s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 1
+; ZVBB-RV32-NEXT: add s4, s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 1
+; ZVBB-RV32-NEXT: add s4, s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 2
+; ZVBB-RV32-NEXT: add s3, s3, s4
+; ZVBB-RV32-NEXT: add s3, sp, s3
+; ZVBB-RV32-NEXT: addi s3, s3, 2047
+; ZVBB-RV32-NEXT: addi s3, s3, 33
+; ZVBB-RV32-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s3, sp, 1088
+; ZVBB-RV32-NEXT: vle8.v v24, (s3)
+; ZVBB-RV32-NEXT: csrr s3, vlenb
+; ZVBB-RV32-NEXT: slli s3, s3, 4
+; ZVBB-RV32-NEXT: mv s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 1
+; ZVBB-RV32-NEXT: add s4, s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 2
+; ZVBB-RV32-NEXT: add s3, s3, s4
+; ZVBB-RV32-NEXT: add s3, sp, s3
+; ZVBB-RV32-NEXT: addi s3, s3, 2047
+; ZVBB-RV32-NEXT: addi s3, s3, 33
+; ZVBB-RV32-NEXT: vs4r.v v24, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v0, v8, a4
+; ZVBB-RV32-NEXT: csrr s3, vlenb
+; ZVBB-RV32-NEXT: slli s3, s3, 6
+; ZVBB-RV32-NEXT: mv s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 1
+; ZVBB-RV32-NEXT: add s3, s3, s4
+; ZVBB-RV32-NEXT: add s3, sp, s3
+; ZVBB-RV32-NEXT: addi s3, s3, 2047
+; ZVBB-RV32-NEXT: addi s3, s3, 33
+; ZVBB-RV32-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s3, sp, 896
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (s3)
+; ZVBB-RV32-NEXT: csrr s3, vlenb
+; ZVBB-RV32-NEXT: slli s3, s3, 3
+; ZVBB-RV32-NEXT: mv s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 2
+; ZVBB-RV32-NEXT: add s4, s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 2
+; ZVBB-RV32-NEXT: add s3, s3, s4
+; ZVBB-RV32-NEXT: add s3, sp, s3
+; ZVBB-RV32-NEXT: addi s3, s3, 2047
+; ZVBB-RV32-NEXT: addi s3, s3, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s3, sp, 832
+; ZVBB-RV32-NEXT: vle8.v v8, (s3)
+; ZVBB-RV32-NEXT: csrr s3, vlenb
+; ZVBB-RV32-NEXT: slli s3, s3, 3
+; ZVBB-RV32-NEXT: mv s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 1
+; ZVBB-RV32-NEXT: add s4, s4, s3
+; ZVBB-RV32-NEXT: slli s3, s3, 3
+; ZVBB-RV32-NEXT: add s3, s3, s4
+; ZVBB-RV32-NEXT: add s3, sp, s3
+; ZVBB-RV32-NEXT: addi s3, s3, 2047
+; ZVBB-RV32-NEXT: addi s3, s3, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s3, sp, 1632
+; ZVBB-RV32-NEXT: vle8.v v8, (s3)
+; ZVBB-RV32-NEXT: addi s3, sp, 128
+; ZVBB-RV32-NEXT: vle8.v v24, (s3)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v8, v16, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v16, (s2)
+; ZVBB-RV32-NEXT: addi s2, sp, 64
+; ZVBB-RV32-NEXT: vle8.v v28, (s2)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v20, a1
+; ZVBB-RV32-NEXT: addi s2, sp, 1920
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v12, (s2)
+; ZVBB-RV32-NEXT: csrr s2, vlenb
+; ZVBB-RV32-NEXT: slli s2, s2, 4
+; ZVBB-RV32-NEXT: mv s3, s2
+; ZVBB-RV32-NEXT: slli s2, s2, 3
+; ZVBB-RV32-NEXT: add s2, s2, s3
+; ZVBB-RV32-NEXT: add s2, sp, s2
+; ZVBB-RV32-NEXT: addi s2, s2, 2047
+; ZVBB-RV32-NEXT: addi s2, s2, 33
+; ZVBB-RV32-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s2, sp, 1856
+; ZVBB-RV32-NEXT: vle8.v v20, (s2)
+; ZVBB-RV32-NEXT: csrr s2, vlenb
+; ZVBB-RV32-NEXT: slli s2, s2, 3
+; ZVBB-RV32-NEXT: mv s3, s2
+; ZVBB-RV32-NEXT: slli s2, s2, 1
+; ZVBB-RV32-NEXT: add s3, s3, s2
+; ZVBB-RV32-NEXT: slli s2, s2, 1
+; ZVBB-RV32-NEXT: add s3, s3, s2
+; ZVBB-RV32-NEXT: slli s2, s2, 1
+; ZVBB-RV32-NEXT: add s2, s2, s3
+; ZVBB-RV32-NEXT: add s2, sp, s2
+; ZVBB-RV32-NEXT: addi s2, s2, 2047
+; ZVBB-RV32-NEXT: addi s2, s2, 33
+; ZVBB-RV32-NEXT: vs4r.v v20, (s2) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV32-NEXT: csrr s2, vlenb
+; ZVBB-RV32-NEXT: slli s2, s2, 5
+; ZVBB-RV32-NEXT: mv s3, s2
+; ZVBB-RV32-NEXT: slli s2, s2, 2
+; ZVBB-RV32-NEXT: add s2, s2, s3
+; ZVBB-RV32-NEXT: add s2, sp, s2
+; ZVBB-RV32-NEXT: addi s2, s2, 2047
+; ZVBB-RV32-NEXT: addi s2, s2, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s2, sp, 1408
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v4, (s2)
+; ZVBB-RV32-NEXT: addi s2, sp, 1344
+; ZVBB-RV32-NEXT: vle8.v v8, (s2)
+; ZVBB-RV32-NEXT: csrr s2, vlenb
+; ZVBB-RV32-NEXT: slli s2, s2, 5
+; ZVBB-RV32-NEXT: mv s3, s2
+; ZVBB-RV32-NEXT: slli s2, s2, 1
+; ZVBB-RV32-NEXT: add s2, s2, s3
+; ZVBB-RV32-NEXT: add s2, sp, s2
+; ZVBB-RV32-NEXT: addi s2, s2, 2047
+; ZVBB-RV32-NEXT: addi s2, s2, 33
+; ZVBB-RV32-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
+; ZVBB-RV32-NEXT: addi s2, sp, 96
+; ZVBB-RV32-NEXT: vle8.v v8, (s2)
+; ZVBB-RV32-NEXT: addi s2, sp, 384
+; ZVBB-RV32-NEXT: vle8.v v0, (s2)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v8, v24, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v16, (s1)
+; ZVBB-RV32-NEXT: addi s1, sp, 320
+; ZVBB-RV32-NEXT: vmv2r.v v12, v28
+; ZVBB-RV32-NEXT: vle8.v v28, (s1)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v12, a1
+; ZVBB-RV32-NEXT: addi s1, sp, 736
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v24, (s1)
+; ZVBB-RV32-NEXT: csrr s1, vlenb
+; ZVBB-RV32-NEXT: slli s1, s1, 7
+; ZVBB-RV32-NEXT: add s1, sp, s1
+; ZVBB-RV32-NEXT: addi s1, s1, 2047
+; ZVBB-RV32-NEXT: addi s1, s1, 33
+; ZVBB-RV32-NEXT: vs8r.v v24, (s1) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vle8.v v24, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv s1, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: add a3, a3, s1
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv s1, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, s1
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a3, sp, 1760
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv s1, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add s1, s1, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, s1
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vle8.v v8, (a5)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a3, sp, 1376
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: addi a3, sp, 992
+; ZVBB-RV32-NEXT: vle8.v v24, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v8, v4, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v24, (t6)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: vle8.v v16, (a6)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v12, a1
+; ZVBB-RV32-NEXT: addi a3, sp, 2016
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v16, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 6
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vle8.v v16, (a7)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vmv4r.v v16, v24
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a3, sp, 1504
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vle8.v v8, (t0)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a3, sp, 352
+; ZVBB-RV32-NEXT: vle8.v v16, (a3)
+; ZVBB-RV32-NEXT: addi a3, sp, 480
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v0, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v0, (t5)
+; ZVBB-RV32-NEXT: vle8.v v8, (t1)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v0, v28, a1
+; ZVBB-RV32-NEXT: addi a3, sp, 1120
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vle8.v v8, (t2)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v0, v16, a4
+; ZVBB-RV32-NEXT: addi a3, sp, 864
+; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV32-NEXT: vle8.v v24, (a3)
+; ZVBB-RV32-NEXT: vle8.v v8, (t3)
+; ZVBB-RV32-NEXT: addi a3, sp, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV32-NEXT: addi a3, sp, 1888
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: vle8.v v16, (t4)
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v0, (a0)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v12, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV32-NEXT: addi a3, a0, 1024
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vse8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: addi a3, sp, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslideup.vx v0, v8, a1
+; ZVBB-RV32-NEXT: addi a3, a0, 512
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v16, (a3)
+; ZVBB-RV32-NEXT: vslideup.vx v0, v24, a4
+; ZVBB-RV32-NEXT: addi a3, a0, 256
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 4
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vse8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV32-NEXT: addi a3, a0, 1536
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v0, (a3)
+; ZVBB-RV32-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: addi a3, a0, 1280
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v16, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV32-NEXT: addi a3, a0, 768
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 5
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vse8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: addi a3, a0, 128
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v16, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV32-NEXT: vmv.v.v v0, v16
+; ZVBB-RV32-NEXT: addi a3, a0, 1792
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 6
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vse8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 6
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV32-NEXT: addi a3, a0, 1152
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v0, (a3)
+; ZVBB-RV32-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: addi a3, a0, 640
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v16, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV32-NEXT: addi a3, a0, 384
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 3
+; ZVBB-RV32-NEXT: mv a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 2
+; ZVBB-RV32-NEXT: add a6, a6, a5
+; ZVBB-RV32-NEXT: slli a5, a5, 1
+; ZVBB-RV32-NEXT: add a5, a5, a6
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vse8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 5
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: addi a3, a0, 1664
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v16, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV32-NEXT: vmv.v.v v0, v16
+; ZVBB-RV32-NEXT: addi a3, a0, 1408
+; ZVBB-RV32-NEXT: csrr a5, vlenb
+; ZVBB-RV32-NEXT: slli a5, a5, 8
+; ZVBB-RV32-NEXT: add a5, sp, a5
+; ZVBB-RV32-NEXT: addi a5, a5, 2047
+; ZVBB-RV32-NEXT: addi a5, a5, 33
+; ZVBB-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vse8.v v8, (a3)
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 1
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 7
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 2
+; ZVBB-RV32-NEXT: add a5, a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV32-NEXT: csrr a3, vlenb
+; ZVBB-RV32-NEXT: slli a3, a3, 3
+; ZVBB-RV32-NEXT: mv a5, a3
+; ZVBB-RV32-NEXT: slli a3, a3, 4
+; ZVBB-RV32-NEXT: add a3, a3, a5
+; ZVBB-RV32-NEXT: add a3, sp, a3
+; ZVBB-RV32-NEXT: addi a3, a3, 2047
+; ZVBB-RV32-NEXT: addi a3, a3, 33
+; ZVBB-RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV32-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV32-NEXT: addi a1, a0, 896
+; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV32-NEXT: vse8.v v0, (a1)
+; ZVBB-RV32-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV32-NEXT: addi a0, a0, 1920
+; ZVBB-RV32-NEXT: vse8.v v16, (a0)
+; ZVBB-RV32-NEXT: addi sp, s0, -2032
+; ZVBB-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: lw s3, 2012(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: lw s4, 2008(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: lw s5, 2004(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: lw s6, 2000(sp) # 4-byte Folded Reload
+; ZVBB-RV32-NEXT: addi sp, sp, 2032
+; ZVBB-RV32-NEXT: ret
+;
+; ZVBB-RV64-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVBB-RV64: # %bb.0:
+; ZVBB-RV64-NEXT: addi sp, sp, -2032
+; ZVBB-RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: sd s1, 2008(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: sd s2, 2000(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: sd s3, 1992(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: sd s4, 1984(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: sd s5, 1976(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: sd s6, 1968(sp) # 8-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s0, sp, 2032
+; ZVBB-RV64-NEXT: addi sp, sp, -112
+; ZVBB-RV64-NEXT: csrr a2, vlenb
+; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: mv a4, a2
+; ZVBB-RV64-NEXT: slli a2, a2, 1
+; ZVBB-RV64-NEXT: add a4, a4, a2
+; ZVBB-RV64-NEXT: slli a2, a2, 1
+; ZVBB-RV64-NEXT: add a4, a4, a2
+; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a2, a2, a4
+; ZVBB-RV64-NEXT: sub sp, sp, a2
+; ZVBB-RV64-NEXT: andi sp, sp, -32
+; ZVBB-RV64-NEXT: csrr a2, vlenb
+; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: mv a4, a2
+; ZVBB-RV64-NEXT: slli a2, a2, 2
+; ZVBB-RV64-NEXT: add a4, a4, a2
+; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a2, a2, a4
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 2047
+; ZVBB-RV64-NEXT: addi a2, a2, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: csrr a2, vlenb
+; ZVBB-RV64-NEXT: slli a2, a2, 8
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 2047
+; ZVBB-RV64-NEXT: addi a2, a2, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: li a2, 128
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v16, (a7)
+; ZVBB-RV64-NEXT: csrr a4, vlenb
+; ZVBB-RV64-NEXT: slli a4, a4, 4
+; ZVBB-RV64-NEXT: mv a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 3
+; ZVBB-RV64-NEXT: add a4, a4, a5
+; ZVBB-RV64-NEXT: add a4, sp, a4
+; ZVBB-RV64-NEXT: addi a4, a4, 2047
+; ZVBB-RV64-NEXT: addi a4, a4, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a4, vlenb
+; ZVBB-RV64-NEXT: slli a4, a4, 3
+; ZVBB-RV64-NEXT: mv a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a4, a4, a5
+; ZVBB-RV64-NEXT: add a4, sp, a4
+; ZVBB-RV64-NEXT: addi a4, a4, 2047
+; ZVBB-RV64-NEXT: addi a4, a4, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a4, a7, 256
+; ZVBB-RV64-NEXT: vle8.v v16, (a4)
+; ZVBB-RV64-NEXT: csrr a4, vlenb
+; ZVBB-RV64-NEXT: slli a4, a4, 5
+; ZVBB-RV64-NEXT: mv a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 3
+; ZVBB-RV64-NEXT: add a4, a4, a5
+; ZVBB-RV64-NEXT: add a4, sp, a4
+; ZVBB-RV64-NEXT: addi a4, a4, 2047
+; ZVBB-RV64-NEXT: addi a4, a4, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a4, a1, 128
+; ZVBB-RV64-NEXT: vle8.v v24, (a4)
+; ZVBB-RV64-NEXT: csrr a4, vlenb
+; ZVBB-RV64-NEXT: slli a4, a4, 4
+; ZVBB-RV64-NEXT: mv a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a4, a4, a5
+; ZVBB-RV64-NEXT: add a4, sp, a4
+; ZVBB-RV64-NEXT: addi a4, a4, 2047
+; ZVBB-RV64-NEXT: addi a4, a4, 33
+; ZVBB-RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a4, a3, 384
+; ZVBB-RV64-NEXT: vle8.v v16, (a4)
+; ZVBB-RV64-NEXT: csrr a4, vlenb
+; ZVBB-RV64-NEXT: slli a4, a4, 3
+; ZVBB-RV64-NEXT: mv a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 2
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a5, a5, a4
+; ZVBB-RV64-NEXT: slli a4, a4, 1
+; ZVBB-RV64-NEXT: add a4, a4, a5
+; ZVBB-RV64-NEXT: add a4, sp, a4
+; ZVBB-RV64-NEXT: addi a4, a4, 2047
+; ZVBB-RV64-NEXT: addi a4, a4, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: li a4, 64
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a5, a7, 384
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (a5)
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 5
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v0, v16, a4
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a5, s0, 768
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v24, (a5)
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 4
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a5, a3, 256
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v16, (a5)
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 4
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 4
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v16, (a1)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: slli a1, a1, 4
+; ZVBB-RV64-NEXT: mv a5, a1
+; ZVBB-RV64-NEXT: slli a1, a1, 4
+; ZVBB-RV64-NEXT: add a1, a1, a5
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 2047
+; ZVBB-RV64-NEXT: addi a1, a1, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: li a1, 32
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v0, a1
+; ZVBB-RV64-NEXT: addi a5, a7, 128
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v0, (a5)
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 4
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v16, v8, a1
+; ZVBB-RV64-NEXT: addi a3, a3, 128
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vmv2r.v v18, v20
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV64-NEXT: vmv2r.v v22, v24
+; ZVBB-RV64-NEXT: addi a3, sp, 672
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v16, (a3)
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a4
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 5
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v16, v16, a4
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 4
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a5, s0, 512
+; ZVBB-RV64-NEXT: vslidedown.vx v0, v0, a4
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 3
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 2
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (a5)
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 7
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v16, a1
+; ZVBB-RV64-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v16, v8, a1
+; ZVBB-RV64-NEXT: vmv2r.v v18, v20
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v0, a1
+; ZVBB-RV64-NEXT: vmv2r.v v22, v24
+; ZVBB-RV64-NEXT: addi a5, sp, 1696
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v16, (a5)
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 4
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 4
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v0, v16, a4
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 4
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 2
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vs8r.v v0, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 3
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 4
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v24, v16, a4
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 3
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 2
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a6, s0, 640
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 5
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a4
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 5
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 2
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (a6)
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 6
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 5
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v24, a1
+; ZVBB-RV64-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV64-NEXT: vslidedown.vx v16, v0, a1
+; ZVBB-RV64-NEXT: vmv2r.v v18, v20
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 5
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 2
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV64-NEXT: vmv2r.v v22, v24
+; ZVBB-RV64-NEXT: addi s5, sp, 1184
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v16, (s5)
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 3
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 2
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v16, a1
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 3
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 2
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 4
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v16, v0, a1
+; ZVBB-RV64-NEXT: vmv2r.v v18, v20
+; ZVBB-RV64-NEXT: csrr a6, vlenb
+; ZVBB-RV64-NEXT: slli a6, a6, 5
+; ZVBB-RV64-NEXT: mv a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a7, a7, a6
+; ZVBB-RV64-NEXT: slli a6, a6, 1
+; ZVBB-RV64-NEXT: add a6, a6, a7
+; ZVBB-RV64-NEXT: add a6, sp, a6
+; ZVBB-RV64-NEXT: addi a6, a6, 2047
+; ZVBB-RV64-NEXT: addi a6, a6, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV64-NEXT: vmv2r.v v22, v24
+; ZVBB-RV64-NEXT: addi a6, sp, 928
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v16, (a6)
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 8
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v16, v8, a4
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 6
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a7, s0, 384
+; ZVBB-RV64-NEXT: csrr t0, vlenb
+; ZVBB-RV64-NEXT: slli t0, t0, 4
+; ZVBB-RV64-NEXT: mv t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 1
+; ZVBB-RV64-NEXT: add t1, t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 3
+; ZVBB-RV64-NEXT: add t0, t0, t1
+; ZVBB-RV64-NEXT: add t0, sp, t0
+; ZVBB-RV64-NEXT: addi t0, t0, 2047
+; ZVBB-RV64-NEXT: addi t0, t0, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVBB-RV64-NEXT: csrr t0, vlenb
+; ZVBB-RV64-NEXT: slli t0, t0, 4
+; ZVBB-RV64-NEXT: mv t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 3
+; ZVBB-RV64-NEXT: add t0, t0, t1
+; ZVBB-RV64-NEXT: add t0, sp, t0
+; ZVBB-RV64-NEXT: addi t0, t0, 2047
+; ZVBB-RV64-NEXT: addi t0, t0, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v24, (a7)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a7) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v12, v16, a1
+; ZVBB-RV64-NEXT: vslidedown.vx v20, v8, a1
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v0, a1
+; ZVBB-RV64-NEXT: vmv2r.v v10, v12
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 4
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v12, v0, a1
+; ZVBB-RV64-NEXT: vmv2r.v v14, v20
+; ZVBB-RV64-NEXT: addi s4, sp, 160
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s4)
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 5
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a1
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v12, v16, a1
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 2
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 3
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v4, v16, a1
+; ZVBB-RV64-NEXT: vmv2r.v v6, v8
+; ZVBB-RV64-NEXT: csrr a7, vlenb
+; ZVBB-RV64-NEXT: slli a7, a7, 4
+; ZVBB-RV64-NEXT: mv t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 2
+; ZVBB-RV64-NEXT: add t0, t0, a7
+; ZVBB-RV64-NEXT: slli a7, a7, 1
+; ZVBB-RV64-NEXT: add a7, a7, t0
+; ZVBB-RV64-NEXT: add a7, sp, a7
+; ZVBB-RV64-NEXT: addi a7, a7, 2047
+; ZVBB-RV64-NEXT: addi a7, a7, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a1
+; ZVBB-RV64-NEXT: vmv2r.v v10, v12
+; ZVBB-RV64-NEXT: addi a7, sp, 1952
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v4, (a7)
+; ZVBB-RV64-NEXT: csrr t0, vlenb
+; ZVBB-RV64-NEXT: slli t0, t0, 3
+; ZVBB-RV64-NEXT: mv t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 1
+; ZVBB-RV64-NEXT: add t1, t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 4
+; ZVBB-RV64-NEXT: add t0, t0, t1
+; ZVBB-RV64-NEXT: add t0, sp, t0
+; ZVBB-RV64-NEXT: addi t0, t0, 2047
+; ZVBB-RV64-NEXT: addi t0, t0, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a1
+; ZVBB-RV64-NEXT: csrr t0, vlenb
+; ZVBB-RV64-NEXT: slli t0, t0, 6
+; ZVBB-RV64-NEXT: mv t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 1
+; ZVBB-RV64-NEXT: add t0, t0, t1
+; ZVBB-RV64-NEXT: add t0, sp, t0
+; ZVBB-RV64-NEXT: addi t0, t0, 2047
+; ZVBB-RV64-NEXT: addi t0, t0, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v12, v16, a1
+; ZVBB-RV64-NEXT: csrr t0, vlenb
+; ZVBB-RV64-NEXT: slli t0, t0, 4
+; ZVBB-RV64-NEXT: mv t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 4
+; ZVBB-RV64-NEXT: add t0, t0, t1
+; ZVBB-RV64-NEXT: add t0, sp, t0
+; ZVBB-RV64-NEXT: addi t0, t0, 2047
+; ZVBB-RV64-NEXT: addi t0, t0, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v4, v16, a1
+; ZVBB-RV64-NEXT: vmv2r.v v6, v8
+; ZVBB-RV64-NEXT: csrr t0, vlenb
+; ZVBB-RV64-NEXT: slli t0, t0, 5
+; ZVBB-RV64-NEXT: mv t1, t0
+; ZVBB-RV64-NEXT: slli t0, t0, 3
+; ZVBB-RV64-NEXT: add t0, t0, t1
+; ZVBB-RV64-NEXT: add t0, sp, t0
+; ZVBB-RV64-NEXT: addi t0, t0, 2047
+; ZVBB-RV64-NEXT: addi t0, t0, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a1
+; ZVBB-RV64-NEXT: vmv2r.v v10, v12
+; ZVBB-RV64-NEXT: addi t0, sp, 1440
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v4, (t0)
+; ZVBB-RV64-NEXT: csrr t1, vlenb
+; ZVBB-RV64-NEXT: slli t1, t1, 3
+; ZVBB-RV64-NEXT: mv t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 2
+; ZVBB-RV64-NEXT: add t1, t1, t2
+; ZVBB-RV64-NEXT: add t1, sp, t1
+; ZVBB-RV64-NEXT: addi t1, t1, 2047
+; ZVBB-RV64-NEXT: addi t1, t1, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t1, vlenb
+; ZVBB-RV64-NEXT: slli t1, t1, 3
+; ZVBB-RV64-NEXT: mv t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t1, t1, t2
+; ZVBB-RV64-NEXT: add t1, sp, t1
+; ZVBB-RV64-NEXT: addi t1, t1, 2047
+; ZVBB-RV64-NEXT: addi t1, t1, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t1, vlenb
+; ZVBB-RV64-NEXT: slli t1, t1, 4
+; ZVBB-RV64-NEXT: mv t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 2
+; ZVBB-RV64-NEXT: add t1, t1, t2
+; ZVBB-RV64-NEXT: add t1, sp, t1
+; ZVBB-RV64-NEXT: addi t1, t1, 2047
+; ZVBB-RV64-NEXT: addi t1, t1, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: csrr t1, vlenb
+; ZVBB-RV64-NEXT: slli t1, t1, 3
+; ZVBB-RV64-NEXT: mv t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 4
+; ZVBB-RV64-NEXT: add t1, t1, t2
+; ZVBB-RV64-NEXT: add t1, sp, t1
+; ZVBB-RV64-NEXT: addi t1, t1, 2047
+; ZVBB-RV64-NEXT: addi t1, t1, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v14, v16
+; ZVBB-RV64-NEXT: addi s3, sp, 544
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s3)
+; ZVBB-RV64-NEXT: csrr t1, vlenb
+; ZVBB-RV64-NEXT: slli t1, t1, 3
+; ZVBB-RV64-NEXT: mv t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t1, t1, t2
+; ZVBB-RV64-NEXT: add t1, sp, t1
+; ZVBB-RV64-NEXT: addi t1, t1, 2047
+; ZVBB-RV64-NEXT: addi t1, t1, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v8, a1
+; ZVBB-RV64-NEXT: vslidedown.vx v12, v24, a1
+; ZVBB-RV64-NEXT: csrr t1, vlenb
+; ZVBB-RV64-NEXT: slli t1, t1, 8
+; ZVBB-RV64-NEXT: add t1, sp, t1
+; ZVBB-RV64-NEXT: addi t1, t1, 2047
+; ZVBB-RV64-NEXT: addi t1, t1, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v4, v16, a1
+; ZVBB-RV64-NEXT: vmv2r.v v6, v8
+; ZVBB-RV64-NEXT: csrr t1, vlenb
+; ZVBB-RV64-NEXT: slli t1, t1, 4
+; ZVBB-RV64-NEXT: mv t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 1
+; ZVBB-RV64-NEXT: add t2, t2, t1
+; ZVBB-RV64-NEXT: slli t1, t1, 3
+; ZVBB-RV64-NEXT: add t1, t1, t2
+; ZVBB-RV64-NEXT: add t1, sp, t1
+; ZVBB-RV64-NEXT: addi t1, t1, 2047
+; ZVBB-RV64-NEXT: addi t1, t1, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a1
+; ZVBB-RV64-NEXT: vmv2r.v v10, v12
+; ZVBB-RV64-NEXT: addi t1, sp, 416
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vsseg4e8.v v4, (t1)
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 3
+; ZVBB-RV64-NEXT: mv t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 2
+; ZVBB-RV64-NEXT: add t3, t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 2
+; ZVBB-RV64-NEXT: add t2, t2, t3
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 4
+; ZVBB-RV64-NEXT: mv t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 1
+; ZVBB-RV64-NEXT: add t3, t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 1
+; ZVBB-RV64-NEXT: add t2, t2, t3
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 3
+; ZVBB-RV64-NEXT: mv t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 2
+; ZVBB-RV64-NEXT: add t3, t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 1
+; ZVBB-RV64-NEXT: add t2, t2, t3
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 7
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v14, v16
+; ZVBB-RV64-NEXT: addi s2, sp, 1568
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s2)
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 4
+; ZVBB-RV64-NEXT: mv t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 2
+; ZVBB-RV64-NEXT: add t2, t2, t3
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 3
+; ZVBB-RV64-NEXT: mv t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 1
+; ZVBB-RV64-NEXT: add t3, t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 2
+; ZVBB-RV64-NEXT: add t2, t2, t3
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 5
+; ZVBB-RV64-NEXT: mv t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 2
+; ZVBB-RV64-NEXT: add t2, t2, t3
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: csrr t2, vlenb
+; ZVBB-RV64-NEXT: slli t2, t2, 5
+; ZVBB-RV64-NEXT: mv t3, t2
+; ZVBB-RV64-NEXT: slli t2, t2, 1
+; ZVBB-RV64-NEXT: add t2, t2, t3
+; ZVBB-RV64-NEXT: add t2, sp, t2
+; ZVBB-RV64-NEXT: addi t2, t2, 2047
+; ZVBB-RV64-NEXT: addi t2, t2, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v14, v16
+; ZVBB-RV64-NEXT: addi t2, sp, 1056
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t2)
+; ZVBB-RV64-NEXT: csrr t3, vlenb
+; ZVBB-RV64-NEXT: slli t3, t3, 4
+; ZVBB-RV64-NEXT: mv t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t4, t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t4, t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t3, t3, t4
+; ZVBB-RV64-NEXT: add t3, sp, t3
+; ZVBB-RV64-NEXT: addi t3, t3, 2047
+; ZVBB-RV64-NEXT: addi t3, t3, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t3, vlenb
+; ZVBB-RV64-NEXT: slli t3, t3, 3
+; ZVBB-RV64-NEXT: mv t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 2
+; ZVBB-RV64-NEXT: add t4, t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t4, t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t3, t3, t4
+; ZVBB-RV64-NEXT: add t3, sp, t3
+; ZVBB-RV64-NEXT: addi t3, t3, 2047
+; ZVBB-RV64-NEXT: addi t3, t3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t3, vlenb
+; ZVBB-RV64-NEXT: slli t3, t3, 5
+; ZVBB-RV64-NEXT: mv t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t4, t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t3, t3, t4
+; ZVBB-RV64-NEXT: add t3, sp, t3
+; ZVBB-RV64-NEXT: addi t3, t3, 2047
+; ZVBB-RV64-NEXT: addi t3, t3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: csrr t3, vlenb
+; ZVBB-RV64-NEXT: slli t3, t3, 3
+; ZVBB-RV64-NEXT: mv t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t4, t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 2
+; ZVBB-RV64-NEXT: add t4, t4, t3
+; ZVBB-RV64-NEXT: slli t3, t3, 1
+; ZVBB-RV64-NEXT: add t3, t3, t4
+; ZVBB-RV64-NEXT: add t3, sp, t3
+; ZVBB-RV64-NEXT: addi t3, t3, 2047
+; ZVBB-RV64-NEXT: addi t3, t3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v14, v16
+; ZVBB-RV64-NEXT: addi t3, sp, 800
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t3)
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: mv t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 1
+; ZVBB-RV64-NEXT: add t5, t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: add t4, t4, t5
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 6
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 4
+; ZVBB-RV64-NEXT: mv t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: add t4, t4, t5
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: mv t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: add t4, t4, t5
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v14, v16
+; ZVBB-RV64-NEXT: addi s1, sp, 32
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s1)
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: mv t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 2
+; ZVBB-RV64-NEXT: add t5, t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: add t4, t4, t5
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: mv t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 5
+; ZVBB-RV64-NEXT: add t4, t4, t5
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 4
+; ZVBB-RV64-NEXT: mv t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 2
+; ZVBB-RV64-NEXT: add t5, t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 1
+; ZVBB-RV64-NEXT: add t4, t4, t5
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: csrr t4, vlenb
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: mv t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 3
+; ZVBB-RV64-NEXT: add t5, t5, t4
+; ZVBB-RV64-NEXT: slli t4, t4, 1
+; ZVBB-RV64-NEXT: add t4, t4, t5
+; ZVBB-RV64-NEXT: add t4, sp, t4
+; ZVBB-RV64-NEXT: addi t4, t4, 2047
+; ZVBB-RV64-NEXT: addi t4, t4, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v14, v16
+; ZVBB-RV64-NEXT: addi t4, sp, 1824
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t4)
+; ZVBB-RV64-NEXT: csrr t5, vlenb
+; ZVBB-RV64-NEXT: slli t5, t5, 4
+; ZVBB-RV64-NEXT: mv t6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 4
+; ZVBB-RV64-NEXT: add t5, t5, t6
+; ZVBB-RV64-NEXT: add t5, sp, t5
+; ZVBB-RV64-NEXT: addi t5, t5, 2047
+; ZVBB-RV64-NEXT: addi t5, t5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t5, vlenb
+; ZVBB-RV64-NEXT: slli t5, t5, 3
+; ZVBB-RV64-NEXT: mv t6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 1
+; ZVBB-RV64-NEXT: add t6, t6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 4
+; ZVBB-RV64-NEXT: add t5, t5, t6
+; ZVBB-RV64-NEXT: add t5, sp, t5
+; ZVBB-RV64-NEXT: addi t5, t5, 2047
+; ZVBB-RV64-NEXT: addi t5, t5, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t5, vlenb
+; ZVBB-RV64-NEXT: slli t5, t5, 5
+; ZVBB-RV64-NEXT: mv t6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 3
+; ZVBB-RV64-NEXT: add t5, t5, t6
+; ZVBB-RV64-NEXT: add t5, sp, t5
+; ZVBB-RV64-NEXT: addi t5, t5, 2047
+; ZVBB-RV64-NEXT: addi t5, t5, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: csrr t5, vlenb
+; ZVBB-RV64-NEXT: slli t5, t5, 6
+; ZVBB-RV64-NEXT: mv t6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 1
+; ZVBB-RV64-NEXT: add t5, t5, t6
+; ZVBB-RV64-NEXT: add t5, sp, t5
+; ZVBB-RV64-NEXT: addi t5, t5, 2047
+; ZVBB-RV64-NEXT: addi t5, t5, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v14, v16
+; ZVBB-RV64-NEXT: addi t6, sp, 1312
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t6)
+; ZVBB-RV64-NEXT: csrr t5, vlenb
+; ZVBB-RV64-NEXT: slli t5, t5, 8
+; ZVBB-RV64-NEXT: add t5, sp, t5
+; ZVBB-RV64-NEXT: addi t5, t5, 2047
+; ZVBB-RV64-NEXT: addi t5, t5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr t5, vlenb
+; ZVBB-RV64-NEXT: slli t5, t5, 3
+; ZVBB-RV64-NEXT: mv s6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 1
+; ZVBB-RV64-NEXT: add s6, s6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 1
+; ZVBB-RV64-NEXT: add s6, s6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 1
+; ZVBB-RV64-NEXT: add s6, s6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 1
+; ZVBB-RV64-NEXT: add t5, t5, s6
+; ZVBB-RV64-NEXT: add t5, sp, t5
+; ZVBB-RV64-NEXT: addi t5, t5, 2047
+; ZVBB-RV64-NEXT: addi t5, t5, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v10, v16
+; ZVBB-RV64-NEXT: csrr t5, vlenb
+; ZVBB-RV64-NEXT: slli t5, t5, 4
+; ZVBB-RV64-NEXT: mv s6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 1
+; ZVBB-RV64-NEXT: add s6, s6, t5
+; ZVBB-RV64-NEXT: slli t5, t5, 3
+; ZVBB-RV64-NEXT: add t5, t5, s6
+; ZVBB-RV64-NEXT: add t5, sp, t5
+; ZVBB-RV64-NEXT: addi t5, t5, 2047
+; ZVBB-RV64-NEXT: addi t5, t5, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vmv2r.v v12, v16
+; ZVBB-RV64-NEXT: vmv2r.v v14, v24
+; ZVBB-RV64-NEXT: addi t5, sp, 288
+; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t5)
+; ZVBB-RV64-NEXT: addi s6, sp, 768
+; ZVBB-RV64-NEXT: vle8.v v8, (s6)
+; ZVBB-RV64-NEXT: csrr s6, vlenb
+; ZVBB-RV64-NEXT: slli s6, s6, 4
+; ZVBB-RV64-NEXT: mv ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 1
+; ZVBB-RV64-NEXT: add ra, ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 3
+; ZVBB-RV64-NEXT: add s6, s6, ra
+; ZVBB-RV64-NEXT: add s6, sp, s6
+; ZVBB-RV64-NEXT: addi s6, s6, 2047
+; ZVBB-RV64-NEXT: addi s6, s6, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s6, sp, 704
+; ZVBB-RV64-NEXT: vle8.v v8, (s6)
+; ZVBB-RV64-NEXT: csrr s6, vlenb
+; ZVBB-RV64-NEXT: slli s6, s6, 3
+; ZVBB-RV64-NEXT: mv ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 2
+; ZVBB-RV64-NEXT: add ra, ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 3
+; ZVBB-RV64-NEXT: add s6, s6, ra
+; ZVBB-RV64-NEXT: add s6, sp, s6
+; ZVBB-RV64-NEXT: addi s6, s6, 2047
+; ZVBB-RV64-NEXT: addi s6, s6, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s6, sp, 1792
+; ZVBB-RV64-NEXT: vle8.v v8, (s6)
+; ZVBB-RV64-NEXT: csrr s6, vlenb
+; ZVBB-RV64-NEXT: slli s6, s6, 5
+; ZVBB-RV64-NEXT: mv ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 3
+; ZVBB-RV64-NEXT: add s6, s6, ra
+; ZVBB-RV64-NEXT: add s6, sp, s6
+; ZVBB-RV64-NEXT: addi s6, s6, 2047
+; ZVBB-RV64-NEXT: addi s6, s6, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s6, sp, 1728
+; ZVBB-RV64-NEXT: vle8.v v8, (s6)
+; ZVBB-RV64-NEXT: csrr s6, vlenb
+; ZVBB-RV64-NEXT: slli s6, s6, 3
+; ZVBB-RV64-NEXT: mv ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 1
+; ZVBB-RV64-NEXT: add ra, ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 4
+; ZVBB-RV64-NEXT: add s6, s6, ra
+; ZVBB-RV64-NEXT: add s6, sp, s6
+; ZVBB-RV64-NEXT: addi s6, s6, 2047
+; ZVBB-RV64-NEXT: addi s6, s6, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s6, sp, 1280
+; ZVBB-RV64-NEXT: vle8.v v16, (s6)
+; ZVBB-RV64-NEXT: addi s6, sp, 1248
+; ZVBB-RV64-NEXT: vle8.v v8, (s6)
+; ZVBB-RV64-NEXT: addi s6, sp, 1216
+; ZVBB-RV64-NEXT: vle8.v v12, (s6)
+; ZVBB-RV64-NEXT: addi s6, sp, 1024
+; ZVBB-RV64-NEXT: vle8.v v20, (s6)
+; ZVBB-RV64-NEXT: csrr s6, vlenb
+; ZVBB-RV64-NEXT: slli s6, s6, 4
+; ZVBB-RV64-NEXT: mv ra, s6
+; ZVBB-RV64-NEXT: slli s6, s6, 4
+; ZVBB-RV64-NEXT: add s6, s6, ra
+; ZVBB-RV64-NEXT: add s6, sp, s6
+; ZVBB-RV64-NEXT: addi s6, s6, 2047
+; ZVBB-RV64-NEXT: addi s6, s6, 33
+; ZVBB-RV64-NEXT: vs4r.v v20, (s6) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v8, v16, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v16, (s5)
+; ZVBB-RV64-NEXT: addi s5, sp, 960
+; ZVBB-RV64-NEXT: vle8.v v20, (s5)
+; ZVBB-RV64-NEXT: csrr s5, vlenb
+; ZVBB-RV64-NEXT: slli s5, s5, 3
+; ZVBB-RV64-NEXT: mv s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 5
+; ZVBB-RV64-NEXT: add s5, s5, s6
+; ZVBB-RV64-NEXT: add s5, sp, s5
+; ZVBB-RV64-NEXT: addi s5, s5, 2047
+; ZVBB-RV64-NEXT: addi s5, s5, 33
+; ZVBB-RV64-NEXT: vs4r.v v20, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v12, a1
+; ZVBB-RV64-NEXT: vmv.v.v v24, v16
+; ZVBB-RV64-NEXT: addi s5, sp, 256
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v20, (s5)
+; ZVBB-RV64-NEXT: addi s5, sp, 192
+; ZVBB-RV64-NEXT: vle8.v v16, (s5)
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a4
+; ZVBB-RV64-NEXT: csrr s5, vlenb
+; ZVBB-RV64-NEXT: slli s5, s5, 8
+; ZVBB-RV64-NEXT: add s5, sp, s5
+; ZVBB-RV64-NEXT: addi s5, s5, 2047
+; ZVBB-RV64-NEXT: addi s5, s5, 33
+; ZVBB-RV64-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s5, sp, 2047
+; ZVBB-RV64-NEXT: addi s5, s5, 1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (s5)
+; ZVBB-RV64-NEXT: csrr s5, vlenb
+; ZVBB-RV64-NEXT: slli s5, s5, 3
+; ZVBB-RV64-NEXT: mv s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s6, s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s6, s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s6, s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s5, s5, s6
+; ZVBB-RV64-NEXT: add s5, sp, s5
+; ZVBB-RV64-NEXT: addi s5, s5, 2047
+; ZVBB-RV64-NEXT: addi s5, s5, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s5, sp, 1984
+; ZVBB-RV64-NEXT: vle8.v v8, (s5)
+; ZVBB-RV64-NEXT: csrr s5, vlenb
+; ZVBB-RV64-NEXT: slli s5, s5, 4
+; ZVBB-RV64-NEXT: mv s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s6, s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s6, s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s5, s5, s6
+; ZVBB-RV64-NEXT: add s5, sp, s5
+; ZVBB-RV64-NEXT: addi s5, s5, 2047
+; ZVBB-RV64-NEXT: addi s5, s5, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s5, sp, 224
+; ZVBB-RV64-NEXT: vle8.v v8, (s5)
+; ZVBB-RV64-NEXT: addi s5, sp, 1536
+; ZVBB-RV64-NEXT: vle8.v v12, (s5)
+; ZVBB-RV64-NEXT: csrr s5, vlenb
+; ZVBB-RV64-NEXT: slli s5, s5, 3
+; ZVBB-RV64-NEXT: mv s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 2
+; ZVBB-RV64-NEXT: add s6, s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s6, s6, s5
+; ZVBB-RV64-NEXT: slli s5, s5, 1
+; ZVBB-RV64-NEXT: add s5, s5, s6
+; ZVBB-RV64-NEXT: add s5, sp, s5
+; ZVBB-RV64-NEXT: addi s5, s5, 2047
+; ZVBB-RV64-NEXT: addi s5, s5, 33
+; ZVBB-RV64-NEXT: vs4r.v v12, (s5) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v8, v20, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v24, (s4)
+; ZVBB-RV64-NEXT: addi s4, sp, 1472
+; ZVBB-RV64-NEXT: vle8.v v12, (s4)
+; ZVBB-RV64-NEXT: csrr s4, vlenb
+; ZVBB-RV64-NEXT: slli s4, s4, 5
+; ZVBB-RV64-NEXT: mv s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 1
+; ZVBB-RV64-NEXT: add s5, s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 1
+; ZVBB-RV64-NEXT: add s4, s4, s5
+; ZVBB-RV64-NEXT: add s4, sp, s4
+; ZVBB-RV64-NEXT: addi s4, s4, 2047
+; ZVBB-RV64-NEXT: addi s4, s4, 33
+; ZVBB-RV64-NEXT: vs4r.v v12, (s4) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v16, a1
+; ZVBB-RV64-NEXT: vmv.v.v v0, v24
+; ZVBB-RV64-NEXT: addi s4, sp, 640
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v20, (s4)
+; ZVBB-RV64-NEXT: addi s4, sp, 576
+; ZVBB-RV64-NEXT: vle8.v v24, (s4)
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v0, v8, a4
+; ZVBB-RV64-NEXT: csrr s4, vlenb
+; ZVBB-RV64-NEXT: slli s4, s4, 3
+; ZVBB-RV64-NEXT: mv s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 1
+; ZVBB-RV64-NEXT: add s5, s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 2
+; ZVBB-RV64-NEXT: add s5, s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 1
+; ZVBB-RV64-NEXT: add s4, s4, s5
+; ZVBB-RV64-NEXT: add s4, sp, s4
+; ZVBB-RV64-NEXT: addi s4, s4, 2047
+; ZVBB-RV64-NEXT: addi s4, s4, 33
+; ZVBB-RV64-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s4, sp, 512
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (s4)
+; ZVBB-RV64-NEXT: csrr s4, vlenb
+; ZVBB-RV64-NEXT: slli s4, s4, 4
+; ZVBB-RV64-NEXT: mv s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 2
+; ZVBB-RV64-NEXT: add s5, s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 1
+; ZVBB-RV64-NEXT: add s4, s4, s5
+; ZVBB-RV64-NEXT: add s4, sp, s4
+; ZVBB-RV64-NEXT: addi s4, s4, 2047
+; ZVBB-RV64-NEXT: addi s4, s4, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s4, sp, 448
+; ZVBB-RV64-NEXT: vle8.v v8, (s4)
+; ZVBB-RV64-NEXT: csrr s4, vlenb
+; ZVBB-RV64-NEXT: slli s4, s4, 3
+; ZVBB-RV64-NEXT: mv s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 3
+; ZVBB-RV64-NEXT: add s5, s5, s4
+; ZVBB-RV64-NEXT: slli s4, s4, 1
+; ZVBB-RV64-NEXT: add s4, s4, s5
+; ZVBB-RV64-NEXT: add s4, sp, s4
+; ZVBB-RV64-NEXT: addi s4, s4, 2047
+; ZVBB-RV64-NEXT: addi s4, s4, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s4, sp, 608
+; ZVBB-RV64-NEXT: vle8.v v8, (s4)
+; ZVBB-RV64-NEXT: addi s4, sp, 1664
+; ZVBB-RV64-NEXT: vle8.v v16, (s4)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v8, v20, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v0, (s3)
+; ZVBB-RV64-NEXT: addi s3, sp, 1600
+; ZVBB-RV64-NEXT: vle8.v v20, (s3)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v0, v24, a1
+; ZVBB-RV64-NEXT: addi s3, sp, 1152
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v12, (s3)
+; ZVBB-RV64-NEXT: csrr s3, vlenb
+; ZVBB-RV64-NEXT: slli s3, s3, 3
+; ZVBB-RV64-NEXT: mv s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 1
+; ZVBB-RV64-NEXT: add s4, s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 1
+; ZVBB-RV64-NEXT: add s4, s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 2
+; ZVBB-RV64-NEXT: add s3, s3, s4
+; ZVBB-RV64-NEXT: add s3, sp, s3
+; ZVBB-RV64-NEXT: addi s3, s3, 2047
+; ZVBB-RV64-NEXT: addi s3, s3, 33
+; ZVBB-RV64-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s3, sp, 1088
+; ZVBB-RV64-NEXT: vle8.v v24, (s3)
+; ZVBB-RV64-NEXT: csrr s3, vlenb
+; ZVBB-RV64-NEXT: slli s3, s3, 4
+; ZVBB-RV64-NEXT: mv s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 1
+; ZVBB-RV64-NEXT: add s4, s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 2
+; ZVBB-RV64-NEXT: add s3, s3, s4
+; ZVBB-RV64-NEXT: add s3, sp, s3
+; ZVBB-RV64-NEXT: addi s3, s3, 2047
+; ZVBB-RV64-NEXT: addi s3, s3, 33
+; ZVBB-RV64-NEXT: vs4r.v v24, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v0, v8, a4
+; ZVBB-RV64-NEXT: csrr s3, vlenb
+; ZVBB-RV64-NEXT: slli s3, s3, 6
+; ZVBB-RV64-NEXT: mv s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 1
+; ZVBB-RV64-NEXT: add s3, s3, s4
+; ZVBB-RV64-NEXT: add s3, sp, s3
+; ZVBB-RV64-NEXT: addi s3, s3, 2047
+; ZVBB-RV64-NEXT: addi s3, s3, 33
+; ZVBB-RV64-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s3, sp, 896
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (s3)
+; ZVBB-RV64-NEXT: csrr s3, vlenb
+; ZVBB-RV64-NEXT: slli s3, s3, 3
+; ZVBB-RV64-NEXT: mv s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 2
+; ZVBB-RV64-NEXT: add s4, s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 2
+; ZVBB-RV64-NEXT: add s3, s3, s4
+; ZVBB-RV64-NEXT: add s3, sp, s3
+; ZVBB-RV64-NEXT: addi s3, s3, 2047
+; ZVBB-RV64-NEXT: addi s3, s3, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s3, sp, 832
+; ZVBB-RV64-NEXT: vle8.v v8, (s3)
+; ZVBB-RV64-NEXT: csrr s3, vlenb
+; ZVBB-RV64-NEXT: slli s3, s3, 3
+; ZVBB-RV64-NEXT: mv s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 1
+; ZVBB-RV64-NEXT: add s4, s4, s3
+; ZVBB-RV64-NEXT: slli s3, s3, 3
+; ZVBB-RV64-NEXT: add s3, s3, s4
+; ZVBB-RV64-NEXT: add s3, sp, s3
+; ZVBB-RV64-NEXT: addi s3, s3, 2047
+; ZVBB-RV64-NEXT: addi s3, s3, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s3, sp, 1632
+; ZVBB-RV64-NEXT: vle8.v v8, (s3)
+; ZVBB-RV64-NEXT: addi s3, sp, 128
+; ZVBB-RV64-NEXT: vle8.v v24, (s3)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v8, v16, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v16, (s2)
+; ZVBB-RV64-NEXT: addi s2, sp, 64
+; ZVBB-RV64-NEXT: vle8.v v28, (s2)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v20, a1
+; ZVBB-RV64-NEXT: addi s2, sp, 1920
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v12, (s2)
+; ZVBB-RV64-NEXT: csrr s2, vlenb
+; ZVBB-RV64-NEXT: slli s2, s2, 4
+; ZVBB-RV64-NEXT: mv s3, s2
+; ZVBB-RV64-NEXT: slli s2, s2, 3
+; ZVBB-RV64-NEXT: add s2, s2, s3
+; ZVBB-RV64-NEXT: add s2, sp, s2
+; ZVBB-RV64-NEXT: addi s2, s2, 2047
+; ZVBB-RV64-NEXT: addi s2, s2, 33
+; ZVBB-RV64-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s2, sp, 1856
+; ZVBB-RV64-NEXT: vle8.v v20, (s2)
+; ZVBB-RV64-NEXT: csrr s2, vlenb
+; ZVBB-RV64-NEXT: slli s2, s2, 3
+; ZVBB-RV64-NEXT: mv s3, s2
+; ZVBB-RV64-NEXT: slli s2, s2, 1
+; ZVBB-RV64-NEXT: add s3, s3, s2
+; ZVBB-RV64-NEXT: slli s2, s2, 1
+; ZVBB-RV64-NEXT: add s3, s3, s2
+; ZVBB-RV64-NEXT: slli s2, s2, 1
+; ZVBB-RV64-NEXT: add s2, s2, s3
+; ZVBB-RV64-NEXT: add s2, sp, s2
+; ZVBB-RV64-NEXT: addi s2, s2, 2047
+; ZVBB-RV64-NEXT: addi s2, s2, 33
+; ZVBB-RV64-NEXT: vs4r.v v20, (s2) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV64-NEXT: csrr s2, vlenb
+; ZVBB-RV64-NEXT: slli s2, s2, 5
+; ZVBB-RV64-NEXT: mv s3, s2
+; ZVBB-RV64-NEXT: slli s2, s2, 2
+; ZVBB-RV64-NEXT: add s2, s2, s3
+; ZVBB-RV64-NEXT: add s2, sp, s2
+; ZVBB-RV64-NEXT: addi s2, s2, 2047
+; ZVBB-RV64-NEXT: addi s2, s2, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s2, sp, 1408
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v4, (s2)
+; ZVBB-RV64-NEXT: addi s2, sp, 1344
+; ZVBB-RV64-NEXT: vle8.v v8, (s2)
+; ZVBB-RV64-NEXT: csrr s2, vlenb
+; ZVBB-RV64-NEXT: slli s2, s2, 5
+; ZVBB-RV64-NEXT: mv s3, s2
+; ZVBB-RV64-NEXT: slli s2, s2, 1
+; ZVBB-RV64-NEXT: add s2, s2, s3
+; ZVBB-RV64-NEXT: add s2, sp, s2
+; ZVBB-RV64-NEXT: addi s2, s2, 2047
+; ZVBB-RV64-NEXT: addi s2, s2, 33
+; ZVBB-RV64-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
+; ZVBB-RV64-NEXT: addi s2, sp, 96
+; ZVBB-RV64-NEXT: vle8.v v8, (s2)
+; ZVBB-RV64-NEXT: addi s2, sp, 384
+; ZVBB-RV64-NEXT: vle8.v v0, (s2)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v8, v24, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v16, (s1)
+; ZVBB-RV64-NEXT: addi s1, sp, 320
+; ZVBB-RV64-NEXT: vmv2r.v v12, v28
+; ZVBB-RV64-NEXT: vle8.v v28, (s1)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v12, a1
+; ZVBB-RV64-NEXT: addi s1, sp, 736
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v24, (s1)
+; ZVBB-RV64-NEXT: csrr s1, vlenb
+; ZVBB-RV64-NEXT: slli s1, s1, 7
+; ZVBB-RV64-NEXT: add s1, sp, s1
+; ZVBB-RV64-NEXT: addi s1, s1, 2047
+; ZVBB-RV64-NEXT: addi s1, s1, 33
+; ZVBB-RV64-NEXT: vs8r.v v24, (s1) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vle8.v v24, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv s1, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: add a3, a3, s1
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv s1, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, s1
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a3, sp, 1760
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv s1, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add s1, s1, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, s1
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vle8.v v8, (a5)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a3, sp, 1376
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: addi a3, sp, 992
+; ZVBB-RV64-NEXT: vle8.v v24, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v8, v4, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v24, (t6)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: vle8.v v16, (a6)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v12, a1
+; ZVBB-RV64-NEXT: addi a3, sp, 2016
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v16, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 6
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vle8.v v16, (a7)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vmv4r.v v16, v24
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a3, sp, 1504
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vle8.v v8, (t0)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a3, sp, 352
+; ZVBB-RV64-NEXT: vle8.v v16, (a3)
+; ZVBB-RV64-NEXT: addi a3, sp, 480
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v0, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v0, (t5)
+; ZVBB-RV64-NEXT: vle8.v v8, (t1)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v0, v28, a1
+; ZVBB-RV64-NEXT: addi a3, sp, 1120
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vle8.v v8, (t2)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v0, v16, a4
+; ZVBB-RV64-NEXT: addi a3, sp, 864
+; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVBB-RV64-NEXT: vle8.v v24, (a3)
+; ZVBB-RV64-NEXT: vle8.v v8, (t3)
+; ZVBB-RV64-NEXT: addi a3, sp, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVBB-RV64-NEXT: addi a3, sp, 1888
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: vle8.v v16, (t4)
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v0, (a0)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v12, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v12, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a4
+; ZVBB-RV64-NEXT: addi a3, a0, 1024
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vse8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: addi a3, sp, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslideup.vx v0, v8, a1
+; ZVBB-RV64-NEXT: addi a3, a0, 512
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v16, (a3)
+; ZVBB-RV64-NEXT: vslideup.vx v0, v24, a4
+; ZVBB-RV64-NEXT: addi a3, a0, 256
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 4
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vse8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV64-NEXT: addi a3, a0, 1536
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v0, (a3)
+; ZVBB-RV64-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: addi a3, a0, 1280
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v16, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV64-NEXT: addi a3, a0, 768
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 5
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vse8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: addi a3, a0, 128
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v16, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV64-NEXT: vmv.v.v v0, v16
+; ZVBB-RV64-NEXT: addi a3, a0, 1792
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 6
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vse8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 6
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV64-NEXT: addi a3, a0, 1152
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v0, (a3)
+; ZVBB-RV64-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: addi a3, a0, 640
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v16, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV64-NEXT: addi a3, a0, 384
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 3
+; ZVBB-RV64-NEXT: mv a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 2
+; ZVBB-RV64-NEXT: add a6, a6, a5
+; ZVBB-RV64-NEXT: slli a5, a5, 1
+; ZVBB-RV64-NEXT: add a5, a5, a6
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vse8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 5
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: addi a3, a0, 1664
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v16, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV64-NEXT: vmv.v.v v0, v16
+; ZVBB-RV64-NEXT: addi a3, a0, 1408
+; ZVBB-RV64-NEXT: csrr a5, vlenb
+; ZVBB-RV64-NEXT: slli a5, a5, 8
+; ZVBB-RV64-NEXT: add a5, sp, a5
+; ZVBB-RV64-NEXT: addi a5, a5, 2047
+; ZVBB-RV64-NEXT: addi a5, a5, 33
+; ZVBB-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vse8.v v8, (a3)
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 1
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 7
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a1
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 2
+; ZVBB-RV64-NEXT: add a5, a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl4r.v v8, (a3) # vscale x 32-byte Folded Reload
+; ZVBB-RV64-NEXT: csrr a3, vlenb
+; ZVBB-RV64-NEXT: slli a3, a3, 3
+; ZVBB-RV64-NEXT: mv a5, a3
+; ZVBB-RV64-NEXT: slli a3, a3, 4
+; ZVBB-RV64-NEXT: add a3, a3, a5
+; ZVBB-RV64-NEXT: add a3, sp, a3
+; ZVBB-RV64-NEXT: addi a3, a3, 2047
+; ZVBB-RV64-NEXT: addi a3, a3, 33
+; ZVBB-RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVBB-RV64-NEXT: vslideup.vx v16, v8, a1
+; ZVBB-RV64-NEXT: addi a1, a0, 896
+; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVBB-RV64-NEXT: vse8.v v0, (a1)
+; ZVBB-RV64-NEXT: vslideup.vx v16, v24, a4
+; ZVBB-RV64-NEXT: addi a0, a0, 1920
+; ZVBB-RV64-NEXT: vse8.v v16, (a0)
+; ZVBB-RV64-NEXT: addi sp, s0, -2032
+; ZVBB-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: ld s2, 2000(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: ld s3, 1992(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: ld s4, 1984(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: ld s5, 1976(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: ld s6, 1968(sp) # 8-byte Folded Reload
+; ZVBB-RV64-NEXT: addi sp, sp, 2032
+; ZVBB-RV64-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: mv a4, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a4, a2
+; ZVZIP-NEXT: slli a2, a2, 1
+; ZVZIP-NEXT: add a4, a4, a2
+; ZVZIP-NEXT: slli a2, a2, 1
+; ZVZIP-NEXT: add a2, a2, a4
+; ZVZIP-NEXT: sub sp, sp, a2
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: mv a4, a2
+; ZVZIP-NEXT: slli a2, a2, 1
+; ZVZIP-NEXT: add a4, a4, a2
+; ZVZIP-NEXT: slli a2, a2, 1
+; ZVZIP-NEXT: add a4, a4, a2
+; ZVZIP-NEXT: slli a2, a2, 1
+; ZVZIP-NEXT: add a4, a4, a2
+; ZVZIP-NEXT: slli a2, a2, 2
+; ZVZIP-NEXT: add a2, a2, a4
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 16
+; ZVZIP-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: li a2, 128
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vmv8r.v v0, v8
+; ZVZIP-NEXT: csrr a4, vlenb
+; ZVZIP-NEXT: slli a4, a4, 3
+; ZVZIP-NEXT: mv a5, a4
+; ZVZIP-NEXT: slli a4, a4, 2
+; ZVZIP-NEXT: add a5, a5, a4
+; ZVZIP-NEXT: slli a4, a4, 3
+; ZVZIP-NEXT: add a4, a4, a5
+; ZVZIP-NEXT: add a4, sp, a4
+; ZVZIP-NEXT: addi a4, a4, 16
+; ZVZIP-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a4, vlenb
+; ZVZIP-NEXT: slli a4, a4, 3
+; ZVZIP-NEXT: mv a5, a4
+; ZVZIP-NEXT: slli a4, a4, 3
+; ZVZIP-NEXT: add a5, a5, a4
+; ZVZIP-NEXT: slli a4, a4, 1
+; ZVZIP-NEXT: add a5, a5, a4
+; ZVZIP-NEXT: slli a4, a4, 1
+; ZVZIP-NEXT: add a4, a4, a5
+; ZVZIP-NEXT: add a4, sp, a4
+; ZVZIP-NEXT: addi a4, a4, 528
+; ZVZIP-NEXT: vle8.v v8, (a4)
+; ZVZIP-NEXT: addi a4, sp, 16
+; ZVZIP-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: li a4, 64
+; ZVZIP-NEXT: addi a5, a3, 128
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: slli a6, a6, 3
+; ZVZIP-NEXT: mv t0, a6
+; ZVZIP-NEXT: slli a6, a6, 2
+; ZVZIP-NEXT: add t0, t0, a6
+; ZVZIP-NEXT: slli a6, a6, 1
+; ZVZIP-NEXT: add a6, a6, t0
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 16
+; ZVZIP-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a5)
+; ZVZIP-NEXT: csrr a5, vlenb
+; ZVZIP-NEXT: slli a5, a5, 7
+; ZVZIP-NEXT: mv a6, a5
+; ZVZIP-NEXT: slli a5, a5, 1
+; ZVZIP-NEXT: add a5, a5, a6
+; ZVZIP-NEXT: add a5, sp, a5
+; ZVZIP-NEXT: addi a5, a5, 16
+; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-NEXT: csrr a5, vlenb
+; ZVZIP-NEXT: slli a5, a5, 3
+; ZVZIP-NEXT: mv a6, a5
+; ZVZIP-NEXT: slli a5, a5, 1
+; ZVZIP-NEXT: add a6, a6, a5
+; ZVZIP-NEXT: slli a5, a5, 3
+; ZVZIP-NEXT: add a6, a6, a5
+; ZVZIP-NEXT: slli a5, a5, 1
+; ZVZIP-NEXT: add a5, a5, a6
+; ZVZIP-NEXT: add a5, sp, a5
+; ZVZIP-NEXT: addi a5, a5, 16
+; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi a5, a7, 128
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: slli a6, a6, 4
+; ZVZIP-NEXT: mv t0, a6
+; ZVZIP-NEXT: slli a6, a6, 3
+; ZVZIP-NEXT: add t0, t0, a6
+; ZVZIP-NEXT: slli a6, a6, 1
+; ZVZIP-NEXT: add a6, a6, t0
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 16
+; ZVZIP-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a5)
+; ZVZIP-NEXT: csrr a5, vlenb
+; ZVZIP-NEXT: slli a5, a5, 4
+; ZVZIP-NEXT: mv a6, a5
+; ZVZIP-NEXT: slli a5, a5, 1
+; ZVZIP-NEXT: add a6, a6, a5
+; ZVZIP-NEXT: slli a5, a5, 1
+; ZVZIP-NEXT: add a6, a6, a5
+; ZVZIP-NEXT: slli a5, a5, 2
+; ZVZIP-NEXT: add a5, a5, a6
+; ZVZIP-NEXT: add a5, sp, a5
+; ZVZIP-NEXT: addi a5, a5, 16
+; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-NEXT: csrr a5, vlenb
+; ZVZIP-NEXT: slli a5, a5, 4
+; ZVZIP-NEXT: mv a6, a5
+; ZVZIP-NEXT: slli a5, a5, 4
+; ZVZIP-NEXT: add a5, a5, a6
+; ZVZIP-NEXT: add a5, sp, a5
+; ZVZIP-NEXT: addi a5, a5, 16
+; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: li a5, 32
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v24, a5
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: slli a6, a6, 3
+; ZVZIP-NEXT: mv t0, a6
+; ZVZIP-NEXT: slli a6, a6, 1
+; ZVZIP-NEXT: add t0, t0, a6
+; ZVZIP-NEXT: slli a6, a6, 3
+; ZVZIP-NEXT: add t0, t0, a6
+; ZVZIP-NEXT: slli a6, a6, 1
+; ZVZIP-NEXT: add a6, a6, t0
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 16
+; ZVZIP-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: slli a6, a6, 4
+; ZVZIP-NEXT: mv t0, a6
+; ZVZIP-NEXT: slli a6, a6, 3
+; ZVZIP-NEXT: add t0, t0, a6
+; ZVZIP-NEXT: slli a6, a6, 1
+; ZVZIP-NEXT: add a6, a6, t0
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 16
+; ZVZIP-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v16, v16, a5
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: slli a6, a6, 4
+; ZVZIP-NEXT: mv t0, a6
+; ZVZIP-NEXT: slli a6, a6, 4
+; ZVZIP-NEXT: add a6, a6, t0
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 16
+; ZVZIP-NEXT: vl8r.v v24, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v16, v20
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: li a6, 96
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 4
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 5
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 656
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr t1, vlenb
+; ZVZIP-NEXT: slli t1, t1, 3
+; ZVZIP-NEXT: mv t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t2, t2, t1
+; ZVZIP-NEXT: slli t1, t1, 2
+; ZVZIP-NEXT: add t2, t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t1, t1, t2
+; ZVZIP-NEXT: add t1, sp, t1
+; ZVZIP-NEXT: addi t1, t1, 16
+; ZVZIP-NEXT: vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (t0)
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 4
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi t0, a3, 256
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v16, v8, a4
+; ZVZIP-NEXT: csrr t1, vlenb
+; ZVZIP-NEXT: slli t1, t1, 5
+; ZVZIP-NEXT: mv t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t1, t1, t2
+; ZVZIP-NEXT: add t1, sp, t1
+; ZVZIP-NEXT: addi t1, t1, 16
+; ZVZIP-NEXT: vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (t0)
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a1)
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 5
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi t0, a7, 256
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-NEXT: csrr t1, vlenb
+; ZVZIP-NEXT: slli t1, t1, 3
+; ZVZIP-NEXT: mv t2, t1
+; ZVZIP-NEXT: slli t1, t1, 5
+; ZVZIP-NEXT: add t1, t1, t2
+; ZVZIP-NEXT: add t1, sp, t1
+; ZVZIP-NEXT: addi t1, t1, 16
+; ZVZIP-NEXT: vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (t0)
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 8
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a5
+; ZVZIP-NEXT: vslidedown.vx v12, v24, a5
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 5
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v16, v16, a5
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 8
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v16, v20
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 6
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 4
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 784
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr t1, vlenb
+; ZVZIP-NEXT: slli t1, t1, 3
+; ZVZIP-NEXT: mv t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t2, t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t2, t2, t1
+; ZVZIP-NEXT: slli t1, t1, 2
+; ZVZIP-NEXT: add t2, t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t1, t1, t2
+; ZVZIP-NEXT: add t1, sp, t1
+; ZVZIP-NEXT: addi t1, t1, 16
+; ZVZIP-NEXT: vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (t0)
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 4
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi t0, a3, 384
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v16, v8, a4
+; ZVZIP-NEXT: csrr t1, vlenb
+; ZVZIP-NEXT: slli t1, t1, 6
+; ZVZIP-NEXT: add t1, sp, t1
+; ZVZIP-NEXT: addi t1, t1, 16
+; ZVZIP-NEXT: vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (t0)
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 2
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi t0, a7, 384
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-NEXT: csrr t1, vlenb
+; ZVZIP-NEXT: slli t1, t1, 3
+; ZVZIP-NEXT: mv t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t2, t2, t1
+; ZVZIP-NEXT: slli t1, t1, 1
+; ZVZIP-NEXT: add t1, t1, t2
+; ZVZIP-NEXT: add t1, sp, t1
+; ZVZIP-NEXT: addi t1, t1, 16
+; ZVZIP-NEXT: vs8r.v v24, (t1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (t0)
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi a1, a1, 128
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 3
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t1, t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a5
+; ZVZIP-NEXT: vslidedown.vx v12, v24, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v16, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add t0, t0, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 400
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr t0, vlenb
+; ZVZIP-NEXT: slli t0, t0, 6
+; ZVZIP-NEXT: mv t1, t0
+; ZVZIP-NEXT: slli t0, t0, 1
+; ZVZIP-NEXT: add t0, t0, t1
+; ZVZIP-NEXT: add t0, sp, t0
+; ZVZIP-NEXT: addi t0, t0, 16
+; ZVZIP-NEXT: vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv t0, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, t0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v16, v8, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a3)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v0, v0, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a7)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a5
+; ZVZIP-NEXT: vslidedown.vx v12, v24, a5
+; ZVZIP-NEXT: vslidedown.vx v16, v0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v16, v20
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi a1, sp, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 7
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v16, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v16, v20
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v16, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v16, v20
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v16, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 7
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v8, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v16, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslidedown.vx v20, v24, a5
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v24, v12, v8
+; ZVZIP-NEXT: vzip.vv v8, v16, v20
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v16, v24
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v12, v16, v24
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v12, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 8
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v12, v16, v24
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v12, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v12, v24, v16
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v12, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 8
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v12, v24, v16
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v12, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v12, v16, v24
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v12, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v12, v24, v16
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v12, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 7
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v16, v0
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v12, v16, v24
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v12, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 7
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v20, v24, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v24, v8, v0
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v24, v20
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v16, v8, a6
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vslidedown.vx v16, v8, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vx v0, v12, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v0, v24, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v16, a5
+; ZVZIP-NEXT: vslideup.vx v0, v12, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v0, v24, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v24, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v0, a5
+; ZVZIP-NEXT: vslideup.vx v24, v12, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v8, v16
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: vslideup.vx v8, v12, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v8, v24, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v8, v16
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: vslideup.vx v8, v12, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v8, v24, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v8, v16
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: vslideup.vx v8, v12, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v8, v24, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v8, v24
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v24, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v0, a5
+; ZVZIP-NEXT: vslideup.vx v8, v12, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v8, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v4, v0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v8, a5
+; ZVZIP-NEXT: vslideup.vx v0, v4, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v0, v16, a4
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v8, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v16, a5
+; ZVZIP-NEXT: vslideup.vx v8, v12, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v8, v24, a4
+; ZVZIP-NEXT: vmv.v.v v16, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 7
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v24, v8, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v16, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v16, v8
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v8, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 7
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vx v8, v24, a5
+; ZVZIP-NEXT: addi a1, a0, 1536
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v0, (a1)
+; ZVZIP-NEXT: vslideup.vx v8, v16, a4
+; ZVZIP-NEXT: addi a1, a0, 1024
+; ZVZIP-NEXT: csrr a3, vlenb
+; ZVZIP-NEXT: slli a3, a3, 3
+; ZVZIP-NEXT: mv a6, a3
+; ZVZIP-NEXT: slli a3, a3, 4
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a3, a3, a6
+; ZVZIP-NEXT: add a3, sp, a3
+; ZVZIP-NEXT: addi a3, a3, 16
+; ZVZIP-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vse8.v v16, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v20, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 8
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: vslideup.vx v16, v20, a5
+; ZVZIP-NEXT: addi a1, a0, 512
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: vslideup.vx v16, v24, a4
+; ZVZIP-NEXT: vmv.v.v v8, v16
+; ZVZIP-NEXT: addi a1, a0, 256
+; ZVZIP-NEXT: csrr a3, vlenb
+; ZVZIP-NEXT: slli a3, a3, 4
+; ZVZIP-NEXT: mv a6, a3
+; ZVZIP-NEXT: slli a3, a3, 3
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a3, a3, a6
+; ZVZIP-NEXT: add a3, sp, a3
+; ZVZIP-NEXT: addi a3, a3, 16
+; ZVZIP-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vse8.v v16, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v20, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: addi a1, a0, 1792
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v20, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v24, a4
+; ZVZIP-NEXT: vmv.v.v v8, v16
+; ZVZIP-NEXT: addi a1, a0, 1280
+; ZVZIP-NEXT: csrr a3, vlenb
+; ZVZIP-NEXT: slli a3, a3, 3
+; ZVZIP-NEXT: mv a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 3
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a3, a3, a6
+; ZVZIP-NEXT: add a3, sp, a3
+; ZVZIP-NEXT: addi a3, a3, 16
+; ZVZIP-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vse8.v v16, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v20, v16, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 7
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: addi a1, a0, 768
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v20, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v24, a4
+; ZVZIP-NEXT: vmv.v.v v24, v16
+; ZVZIP-NEXT: addi a1, a0, 128
+; ZVZIP-NEXT: csrr a3, vlenb
+; ZVZIP-NEXT: slli a3, a3, 5
+; ZVZIP-NEXT: mv a6, a3
+; ZVZIP-NEXT: slli a3, a3, 2
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a3, a3, a6
+; ZVZIP-NEXT: add a3, sp, a3
+; ZVZIP-NEXT: addi a3, a3, 16
+; ZVZIP-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a5
+; ZVZIP-NEXT: addi a1, a0, 1664
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v24, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: vslideup.vx v16, v8, a5
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vslideup.vx v16, v24, a4
+; ZVZIP-NEXT: vmv.v.v v24, v16
+; ZVZIP-NEXT: addi a1, a0, 1152
+; ZVZIP-NEXT: csrr a3, vlenb
+; ZVZIP-NEXT: slli a3, a3, 3
+; ZVZIP-NEXT: mv a6, a3
+; ZVZIP-NEXT: slli a3, a3, 2
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 2
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a3, a3, a6
+; ZVZIP-NEXT: add a3, sp, a3
+; ZVZIP-NEXT: addi a3, a3, 16
+; ZVZIP-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a5
+; ZVZIP-NEXT: addi a1, a0, 640
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v24, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 6
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: vslideup.vx v16, v8, a5
+; ZVZIP-NEXT: addi a1, a0, 384
+; ZVZIP-NEXT: csrr a3, vlenb
+; ZVZIP-NEXT: slli a3, a3, 4
+; ZVZIP-NEXT: mv a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 2
+; ZVZIP-NEXT: add a6, a6, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a3, a3, a6
+; ZVZIP-NEXT: add a3, sp, a3
+; ZVZIP-NEXT: addi a3, a3, 16
+; ZVZIP-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: vslideup.vx v16, v24, a4
+; ZVZIP-NEXT: vmv.v.v v24, v16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 4
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a5, e8, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v16, a5
+; ZVZIP-NEXT: addi a1, a0, 1920
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v24, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 5
+; ZVZIP-NEXT: mv a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a3, a3, a1
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 16
+; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a4, e8, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vx v24, v0, a5
+; ZVZIP-NEXT: vslideup.vx v16, v8, a5
+; ZVZIP-NEXT: addi a1, a0, 1408
+; ZVZIP-NEXT: csrr a3, vlenb
+; ZVZIP-NEXT: slli a3, a3, 6
+; ZVZIP-NEXT: mv a5, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a5, a5, a3
+; ZVZIP-NEXT: slli a3, a3, 1
+; ZVZIP-NEXT: add a3, a3, a5
+; ZVZIP-NEXT: add a3, sp, a3
+; ZVZIP-NEXT: addi a3, a3, 16
+; ZVZIP-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: vslideup.vx v16, v24, a4
+; ZVZIP-NEXT: addi a0, a0, 896
+; ZVZIP-NEXT: vse8.v v16, (a0)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: mv a1, a0
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add a1, a1, a0
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add a1, a1, a0
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add a0, a0, a1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-RV32-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVZIP-WIDE-RV32: # %bb.0:
+; ZVZIP-WIDE-RV32-NEXT: addi sp, sp, -2032
+; ZVZIP-WIDE-RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
+; ZVZIP-WIDE-RV32-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
+; ZVZIP-WIDE-RV32-NEXT: addi s0, sp, 2032
+; ZVZIP-WIDE-RV32-NEXT: addi sp, sp, -1040
+; ZVZIP-WIDE-RV32-NEXT: andi sp, sp, -512
+; ZVZIP-WIDE-RV32-NEXT: li a0, 512
+; ZVZIP-WIDE-RV32-NEXT: addi a1, sp, 512
+; ZVZIP-WIDE-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-WIDE-RV32-NEXT: vsseg4e8.v v8, (a1)
+; ZVZIP-WIDE-RV32-NEXT: vle8.v v8, (a1)
+; ZVZIP-WIDE-RV32-NEXT: addi a1, sp, 1024
+; ZVZIP-WIDE-RV32-NEXT: vle8.v v12, (a1)
+; ZVZIP-WIDE-RV32-NEXT: li a1, 1024
+; ZVZIP-WIDE-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-WIDE-RV32-NEXT: vslideup.vx v8, v12, a0
+; ZVZIP-WIDE-RV32-NEXT: addi a2, sp, 1536
+; ZVZIP-WIDE-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-WIDE-RV32-NEXT: vle8.v v12, (a2)
+; ZVZIP-WIDE-RV32-NEXT: addi a2, sp, 2047
+; ZVZIP-WIDE-RV32-NEXT: addi a2, a2, 1
+; ZVZIP-WIDE-RV32-NEXT: vle8.v v16, (a2)
+; ZVZIP-WIDE-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-WIDE-RV32-NEXT: vslideup.vx v12, v16, a0
+; ZVZIP-WIDE-RV32-NEXT: addi sp, s0, -2032
+; ZVZIP-WIDE-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
+; ZVZIP-WIDE-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
+; ZVZIP-WIDE-RV32-NEXT: addi sp, sp, 2032
+; ZVZIP-WIDE-RV32-NEXT: ret
+;
+; ZVZIP-WIDE-RV64-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVZIP-WIDE-RV64: # %bb.0:
+; ZVZIP-WIDE-RV64-NEXT: addi sp, sp, -2032
+; ZVZIP-WIDE-RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; ZVZIP-WIDE-RV64-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; ZVZIP-WIDE-RV64-NEXT: addi s0, sp, 2032
+; ZVZIP-WIDE-RV64-NEXT: addi sp, sp, -1040
+; ZVZIP-WIDE-RV64-NEXT: andi sp, sp, -512
+; ZVZIP-WIDE-RV64-NEXT: li a0, 512
+; ZVZIP-WIDE-RV64-NEXT: addi a1, sp, 512
+; ZVZIP-WIDE-RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-WIDE-RV64-NEXT: vsseg4e8.v v8, (a1)
+; ZVZIP-WIDE-RV64-NEXT: vle8.v v8, (a1)
+; ZVZIP-WIDE-RV64-NEXT: addi a1, sp, 1024
+; ZVZIP-WIDE-RV64-NEXT: vle8.v v12, (a1)
+; ZVZIP-WIDE-RV64-NEXT: li a1, 1024
+; ZVZIP-WIDE-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-WIDE-RV64-NEXT: vslideup.vx v8, v12, a0
+; ZVZIP-WIDE-RV64-NEXT: addi a2, sp, 1536
+; ZVZIP-WIDE-RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-WIDE-RV64-NEXT: vle8.v v12, (a2)
+; ZVZIP-WIDE-RV64-NEXT: addi a2, sp, 2047
+; ZVZIP-WIDE-RV64-NEXT: addi a2, a2, 1
+; ZVZIP-WIDE-RV64-NEXT: vle8.v v16, (a2)
+; ZVZIP-WIDE-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-WIDE-RV64-NEXT: vslideup.vx v12, v16, a0
+; ZVZIP-WIDE-RV64-NEXT: addi sp, s0, -2032
+; ZVZIP-WIDE-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; ZVZIP-WIDE-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
+; ZVZIP-WIDE-RV64-NEXT: addi sp, sp, 2032
+; ZVZIP-WIDE-RV64-NEXT: ret
+ %v = call <2048 x i8> @llvm.vector.interleave4(<512 x i8> %v0, <512 x i8> %v1, <512 x i8> %v2, <512 x i8> %v3)
+ ret <2048 x i8> %v
+}
+
define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) nounwind {
; CHECK-LABEL: vector_interleave5_v10i16_v2i16:
; CHECK: # %bb.0:
@@ -376,6 +11833,35 @@ define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave5_v10i16_v2i16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg5e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 16
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 20
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 28
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 8
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
ret <10 x i16> %res
}
@@ -473,6 +11959,40 @@ define <12 x i16> @vector_interleave6_v12i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave6_v12i16_v2i16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 12
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 16
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 20
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 28
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 12, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 10
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <12 x i16> @llvm.vector.interleave6.v12i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f)
ret <12 x i16> %res
}
@@ -585,6 +12105,45 @@ define <14 x i8> @vector_interleave7_v14i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVZIP-NEXT: vslideup.vi v8, v12, 8
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave7_v14i8_v2i8:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -16
+; ZVZIP-WIDE-NEXT: addi a0, sp, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg7e8.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 4
+; ZVZIP-WIDE-NEXT: vle8.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle8.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vle8.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vle8.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vle8.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vle8.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 14
+; ZVZIP-WIDE-NEXT: vsetivli zero, 12, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vle8.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 14, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 12
+; ZVZIP-WIDE-NEXT: addi sp, sp, 16
+; ZVZIP-WIDE-NEXT: ret
%res = call <14 x i8> @llvm.vector.interleave7.v14i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g)
ret <14 x i8> %res
}
@@ -701,6 +12260,48 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v11, 8
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave8_v16i8_v2i8:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-WIDE-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-WIDE-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v8, v11, v16
+; ZVZIP-WIDE-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v9, v11, v8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v9, 2
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v9
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v9, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v9, 10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v9, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 12, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v9, v9, 14
+; ZVZIP-WIDE-NEXT: vsetivli zero, 14, e8, mf8, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 14
+; ZVZIP-WIDE-NEXT: ret
%res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)
ret <16 x i8> %res
}
@@ -731,6 +12332,13 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v4f16_v2f16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
ret <4 x half> %res
}
@@ -759,6 +12367,13 @@ define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloa
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v4bf16_v2bf16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <4 x bfloat> %res
}
@@ -787,6 +12402,13 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v8f16_v4f16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
ret <8 x half> %res
}
@@ -815,6 +12437,13 @@ define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloa
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v8bf16_v4bf16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <8 x bfloat> %res
}
@@ -844,6 +12473,13 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v4f32_v2f32:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
}
@@ -875,6 +12511,13 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v16f16_v8f16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
ret <16 x half> %res
}
@@ -906,6 +12549,13 @@ define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfl
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v16bf16_v8bf16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)
ret <16 x bfloat> %res
}
@@ -938,6 +12588,13 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v8f32_v4f32:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v8, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret <8 x float> %res
}
@@ -980,6 +12637,14 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double>
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave_v4f64_v2f64:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-WIDE-NEXT: vmv1r.v v10, v9
+; ZVZIP-WIDE-NEXT: vmv1r.v v11, v8
+; ZVZIP-WIDE-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-WIDE-NEXT: ret
%res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
ret <4 x double> %res
}
@@ -1041,6 +12706,25 @@ define <6 x float> @vector_interleave3_v6f32_v2f32(<2 x float> %a, <2 x float> %
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave3_v6f32_v2f32:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg3e32.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 16
+; ZVZIP-WIDE-NEXT: vle32.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle32.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vle32.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <6 x float> @llvm.vector.interleave3.v6f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
ret <6 x float> %res
}
@@ -1110,6 +12794,27 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave4_v8f32_v2f32:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-WIDE-NEXT: vzip.vv v9, v8, v10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v8, v9, v12
+; ZVZIP-WIDE-NEXT: vmv1r.v v9, v8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v8, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vslidedown.vi v9, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)
ret <8 x float> %res
}
@@ -1192,6 +12897,35 @@ define <10 x half> @vector_interleave5_v10f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave5_v10f16_v2f16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg5e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 16
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 20
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 28
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 8
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <10 x half> @llvm.vector.interleave5.v10f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e)
ret <10 x half> %res
}
@@ -1274,6 +13008,35 @@ define <10 x bfloat> @vector_interleave5_v10bf16_v2bf16(<2 x bfloat> %a, <2 x bf
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave5_v10bf16_v2bf16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg5e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 16
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 20
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 28
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 8
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <10 x bfloat> @llvm.vector.interleave5.v10bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c, <2 x bfloat> %d, <2 x bfloat> %e)
ret <10 x bfloat> %res
}
@@ -1371,6 +13134,40 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave6_v12f16_v2f16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 12
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 16
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 20
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 28
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 12, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 10
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <12 x half> @llvm.vector.interleave6.v12f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f)
ret <12 x half> %res
}
@@ -1468,6 +13265,40 @@ define <12 x bfloat> @vector_interleave6_v12bf16_v2bf16(<2 x bfloat> %a, <2 x bf
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave6_v12bf16_v2bf16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -32
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 12
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 16
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 20
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 24
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 28
+; ZVZIP-WIDE-NEXT: vsetivli zero, 10, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 12, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 10
+; ZVZIP-WIDE-NEXT: addi sp, sp, 32
+; ZVZIP-WIDE-NEXT: ret
%res = call <12 x bfloat> @llvm.vector.interleave6.v12bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c, <2 x bfloat> %d, <2 x bfloat> %e, <2 x bfloat> %f)
ret <12 x bfloat> %res
}
@@ -1580,6 +13411,45 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave7_v7f16_v1f16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -16
+; ZVZIP-WIDE-NEXT: addi a0, sp, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg7e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 4
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 3
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 14
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 5
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: addi sp, sp, 16
+; ZVZIP-WIDE-NEXT: ret
%res = call <7 x half> @llvm.vector.interleave7.v7f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g)
ret <7 x half> %res
}
@@ -1692,6 +13562,45 @@ define <7 x bfloat> @vector_interleave7_v7bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave7_v7bf16_v1bf16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: addi sp, sp, -16
+; ZVZIP-WIDE-NEXT: addi a0, sp, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vsseg7e16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a1, sp, 4
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a1)
+; ZVZIP-WIDE-NEXT: vle16.v v8, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 8
+; ZVZIP-WIDE-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 10
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 3
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: addi a0, sp, 14
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 5
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vle16.v v9, (a0)
+; ZVZIP-WIDE-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-WIDE-NEXT: addi sp, sp, 16
+; ZVZIP-WIDE-NEXT: ret
%res = call <7 x bfloat> @llvm.vector.interleave7.v7bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g)
ret <7 x bfloat> %res
}
@@ -1808,6 +13717,42 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v11, 4
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave8_v8f16_v1f16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-WIDE-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-WIDE-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v12, v11, v16
+; ZVZIP-WIDE-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-WIDE-NEXT: vmv1r.v v9, v8
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v8, 1
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v8, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v9, 3
+; ZVZIP-WIDE-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 2
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 3
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v9, 5
+; ZVZIP-WIDE-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 4
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 5
+; ZVZIP-WIDE-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 6
+; ZVZIP-WIDE-NEXT: vslidedown.vi v9, v9, 7
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 7
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave8.v8f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h)
ret <8 x half> %res
}
@@ -1924,6 +13869,42 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v11, 4
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: vector_interleave8_v8bf16_v1bf16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v16, v11, v15
+; ZVZIP-WIDE-NEXT: vzip.vv v11, v9, v13
+; ZVZIP-WIDE-NEXT: vzip.vv v9, v10, v14
+; ZVZIP-WIDE-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v12, v11, v16
+; ZVZIP-WIDE-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-WIDE-NEXT: vmv1r.v v9, v8
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v8, 1
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v8, 2
+; ZVZIP-WIDE-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v9, 3
+; ZVZIP-WIDE-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 2
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-WIDE-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 3
+; ZVZIP-WIDE-NEXT: vslidedown.vi v10, v9, 5
+; ZVZIP-WIDE-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 4
+; ZVZIP-WIDE-NEXT: vslidedown.vi v11, v9, 6
+; ZVZIP-WIDE-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v10, 5
+; ZVZIP-WIDE-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v11, 6
+; ZVZIP-WIDE-NEXT: vslidedown.vi v9, v9, 7
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vslideup.vi v8, v9, 7
+; ZVZIP-WIDE-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave8.v8bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g, <1 x bfloat> %h)
ret <8 x bfloat> %res
}
@@ -1946,6 +13927,12 @@ define <8 x i16> @interleave4_const_splat_v8i16(<2 x i16> %a) {
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vmv.v.i v8, 3
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: interleave4_const_splat_v8i16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vmv.v.i v8, 3
+; ZVZIP-WIDE-NEXT: ret
%retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3))
ret <8 x i16> %retval
}
@@ -1968,6 +13955,12 @@ define <8 x i16> @interleave4_same_nonconst_splat_v8i16(i16 %a) {
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vmv.v.x v8, a0
; ZVZIP-NEXT: ret
+;
+; ZVZIP-WIDE-LABEL: interleave4_same_nonconst_splat_v8i16:
+; ZVZIP-WIDE: # %bb.0:
+; ZVZIP-WIDE-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-WIDE-NEXT: vmv.v.x v8, a0
+; ZVZIP-WIDE-NEXT: ret
%ins = insertelement <2 x i16> poison, i16 %a, i32 0
%splat = shufflevector <2 x i16> %ins, <2 x i16> poison, <2 x i32> zeroinitializer
%retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat)
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