[llvm] [AArch64] Pair far-offset LDP/STP via base-address CSE and base-register adjustment (PR #222646)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index e8292ffd5..b72e56510 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -2152,8 +2152,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
       // FirstMI and the next instruction; a store's Rt looks dead there,
       // which the regsOverlap skip below compensates for.
       RS.backward(I);
-      AvailableScratchRegs =
-          RS.getRegsAvailable(&AArch64::GPR64commonRegClass);
+      AvailableScratchRegs = RS.getRegsAvailable(&AArch64::GPR64commonRegClass);
       ScavengerReady = true;
     }
   };
@@ -2261,8 +2260,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
           if (!inBoundsForPair(IsUnscaled, MinOffset, OffsetStride)) {
             if (EnableLdpStpBaseAdjust) {
               int MemScale = TII->getMemScale(FirstMI);
-              int64_t ByteOffset = static_cast<int64_t>(MinOffset) *
-                  (IsUnscaled ? 1 : MemScale);
+              int64_t ByteOffset =
+                  static_cast<int64_t>(MinOffset) * (IsUnscaled ? 1 : MemScale);
               if (ByteOffset >= 0 && canEncodeAddXriImm(ByteOffset)) {
                 Register Reg0 = getLdStRegOp(FirstMI).getReg();
                 Register Reg1 = getLdStRegOp(MI).getReg();
@@ -2276,8 +2275,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
                 // `ldr x0, [x0, #8]`). X16/X17 are skipped here too; see
                 // the scavenger path below.
                 if (MayLoad && AArch64::GPR64RegClass.contains(Reg0) &&
-                    !TRI->regsOverlap(Reg0, Reg1) &&
-                    Reg0 != AArch64::X16 && Reg0 != AArch64::X17)
+                    !TRI->regsOverlap(Reg0, Reg1) && Reg0 != AArch64::X16 &&
+                    Reg0 != AArch64::X17)
                   Scratch = Reg0;
                 else {
                   // Stores and sub-64-bit loads cannot reuse a dest/source
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index b4f37d4f2..54e94bf4d 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -1054,7 +1054,7 @@ bool AArch64MIPeepholeOptImpl::shareBaseAddresses(MachineBasicBlock &MBB) {
       if (Pos[PrimaryDef] >= Pos[Sec.UserMI])
         continue;
       bool IsPairOrPre = AArch64InstrInfo::isPairedLdSt(*Sec.UserMI) ||
-                        AArch64InstrInfo::isPreLdSt(*Sec.UserMI);
+                         AArch64InstrInfo::isPreLdSt(*Sec.UserMI);
       unsigned BaseIdx = IsPairOrPre ? 2 : 1;
       unsigned OffIdx = IsPairOrPre ? 3 : 2;
       MachineOperand &BaseOp = Sec.UserMI->getOperand(BaseIdx);

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https://github.com/llvm/llvm-project/pull/222646