[llvm] 0bf534a - [AMDGPU] Remove the VGPR-alignment check from the machine verifier (#219230)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 11 07:22:31 PDT 2026
Author: Valery Pykhtin
Date: 2026-09-11T16:22:27+02:00
New Revision: 0bf534a7b76c7623edb7785cd8b21d89ec63e5d9
URL: https://github.com/llvm/llvm-project/commit/0bf534a7b76c7623edb7785cd8b21d89ec63e5d9
DIFF: https://github.com/llvm/llvm-project/commit/0bf534a7b76c7623edb7785cd8b21d89ec63e5d9.diff
LOG: [AMDGPU] Remove the VGPR-alignment check from the machine verifier (#219230)
The machine verifier had a check that a 64-bit-or-wider VALU operand uses an even-aligned VGPR/AGPR tuple on subtargets that require it. Now that most operands express their alignment requirement through `_AlignTarget`, the check is redundant: the generic verifier already rejects a register that does not fit its operand's class.
This removes the "Subtarget requires even aligned vector registers" and "Operand has incorrect register class" diagnostics, leaving the generic "Illegal virtual/physical register for instruction".
The image `vaddr` parity check is left in place: single-VGPR alignment cannot be expressed as a register class, so it still needs an explicit check.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
llvm/test/CodeGen/AMDGPU/verify-image.mir
llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d69be52d9241b..8b9fca9bd0aa2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5438,7 +5438,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
const MCOperandInfo &OpInfo = Desc.operands()[i];
- int16_t RegClass = getOpRegClassID(OpInfo);
switch (OpInfo.OperandType) {
case MCOI::OPERAND_REGISTER:
@@ -5524,46 +5523,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
continue;
break;
}
-
- if (!MO.isReg())
- continue;
- Register Reg = MO.getReg();
- if (!Reg)
- continue;
-
- // FIXME: Ideally we would have separate instruction definitions with the
- // aligned register constraint.
- // FIXME: We do not verify inline asm operands, but custom inline asm
- // verification is broken anyway
- if (ST.needsAlignedVGPRs() && Opcode != AMDGPU::AV_MOV_B64_IMM_PSEUDO &&
- Opcode != AMDGPU::V_MOV_B64_PSEUDO && !isSpill(MI)) {
- const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg);
- if (RI.hasVectorRegisters(RC) && MO.getSubReg()) {
- if (const TargetRegisterClass *SubRC =
- RI.getSubRegisterClass(RC, MO.getSubReg())) {
- RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg());
- if (RC)
- RC = SubRC;
- }
- }
-
- // Check that this is the aligned version of the class.
- if (!RC || !RI.isProperlyAlignedRC(*RC)) {
- ErrInfo = "Subtarget requires even aligned vector registers";
- return false;
- }
- }
-
- if (RegClass != -1) {
- if (Reg.isVirtual())
- continue;
-
- const TargetRegisterClass *RC = RI.getRegClass(RegClass);
- if (!RC->contains(Reg)) {
- ErrInfo = "Operand has incorrect register class.";
- return false;
- }
- }
}
// Verify SDWA
@@ -6109,16 +6068,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
!(RI.getChannelFromSubReg(Op->getSubReg()) & 1);
};
- if (Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_SEMA_BR ||
- Opcode == AMDGPU::DS_GWS_BARRIER) {
-
- if (!isAlignedReg(AMDGPU::OpName::data0)) {
- ErrInfo = "Subtarget requires even aligned vector registers "
- "for DS_GWS instructions";
- return false;
- }
- }
-
if (isMIMG(MI)) {
if (!isAlignedReg(AMDGPU::OpName::vaddr)) {
ErrInfo = "Subtarget requires even aligned vector registers "
diff --git a/llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir b/llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
index 8a7fc2a3af057..d38822a4a8550 100644
--- a/llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
+++ b/llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
@@ -10,29 +10,21 @@ body: |
bb.0:
; A 32-bit sub-register does not fit the 64-bit AV_64_Align2 data0 operand.
%0:areg_128_align2 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT killed %0.sub1:areg_128_align2
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: - instruction: DS_GWS_INIT killed %0.sub1:areg_128_align2
; GFX90A-ERR: AReg_128_Align2.sub1 cannot be used for AV_64_Align2 operands.
DS_GWS_INIT killed %0.sub1, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
%0:areg_128_align2 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT killed %0.sub3:areg_128_align2
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: - instruction: DS_GWS_INIT killed %0.sub3:areg_128_align2
; GFX90A-ERR: AReg_128_Align2.sub3 cannot be used for AV_64_Align2 operands.
DS_GWS_INIT killed %0.sub3, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
%1:vreg_64_align2 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
- ; GFX90A-ERR: - instruction: DS_GWS_SEMA_BR killed %1.sub1:vreg_64_align2
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: - instruction: DS_GWS_SEMA_BR killed %1.sub1:vreg_64_align2
; GFX90A-ERR: VReg_64_Align2.sub1 cannot be used for AV_64_Align2 operands.
DS_GWS_SEMA_BR killed %1.sub1, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
%2:vreg_64 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
- ; GFX90A-ERR: - instruction: DS_GWS_BARRIER killed %2.sub0:vreg_64
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: - instruction: DS_GWS_BARRIER killed %2.sub0:vreg_64
; GFX90A-ERR: VReg_64.sub0 cannot be used for AV_64_Align2 operands.
@@ -40,8 +32,6 @@ body: |
; A whole 32-bit register is the wrong size for the 64-bit operand.
%3:vgpr_32 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS instructions ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT killed %3:vgpr_32
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: - instruction: DS_GWS_INIT killed %3:vgpr_32
; GFX90A-ERR: Expected a AV_64_Align2 register, but got a VGPR_32 register
@@ -49,51 +39,37 @@ body: |
; Physical single 32-bit registers are the wrong class for the operand.
$vgpr1 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Operand has incorrect register class. ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT $vgpr1,
; GFX90A-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX90A-ERR: $vgpr1 is not a AV_64_Align2 register.
DS_GWS_INIT $vgpr1, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
$agpr1 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Operand has incorrect register class. ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT $agpr1,
; GFX90A-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX90A-ERR: $agpr1 is not a AV_64_Align2 register.
DS_GWS_INIT $agpr1, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
; Odd-aligned physical 64-bit tuples are a genuine alignment error.
$vgpr3_vgpr4 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT $vgpr1_vgpr2
; GFX90A-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX90A-ERR: $vgpr1_vgpr2 is not a AV_64_Align2 register.
DS_GWS_INIT $vgpr1_vgpr2, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
$agpr3_agpr4 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT $agpr3_agpr4
; GFX90A-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX90A-ERR: $agpr3_agpr4 is not a AV_64_Align2 register.
DS_GWS_INIT $agpr3_agpr4, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
; Unaligned virtual 64-bit tuples are a genuine alignment error.
%4:vreg_64 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT %4:vreg_64
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: Expected a AV_64_Align2 register, but got a VReg_64 register
DS_GWS_INIT %4, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
%5:areg_64 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT %5:areg_64
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: Expected a AV_64_Align2 register, but got a AReg_64 register
DS_GWS_INIT %5, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
%6:av_64 = IMPLICIT_DEF
- ; GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; GFX90A-ERR: - instruction: DS_GWS_INIT %6:av_64
; GFX90A-ERR: *** Bad machine code: Illegal virtual register for instruction ***
; GFX90A-ERR: Expected a AV_64_Align2 register, but got a AV_64 register
DS_GWS_INIT %6, 0, implicit $m0, implicit $exec :: (store (s32) into custom "GWSResource")
diff --git a/llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir b/llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
index f8f8197cbc005..fa0433369b585 100644
--- a/llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
+++ b/llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
@@ -63,91 +63,59 @@ body: |
; Check virtual register uses: an unaligned tuple is a misalignment, and its
; class is also wrong for the aligned operand.
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX2 %0:vreg_64_align2, %1:vreg_64
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: Expected a AV_64_Align2 register, but got a VReg_64 register
GLOBAL_STORE_DWORDX2 %0, %1, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX3 %0:vreg_64_align2, %2:vreg_96
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: Expected a AV_96_Align2 register, but got a VReg_96 register
GLOBAL_STORE_DWORDX3 %0, %2, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX4 %0:vreg_64_align2, %3:vreg_128
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: Expected a AV_128_Align2 register, but got a VReg_128 register
GLOBAL_STORE_DWORDX4 %0, %3, 0, 0, implicit $exec
; Check virtual registers with subregisters.
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX2 %0:vreg_64_align2, %3.sub0_sub1:vreg_128
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: VReg_128.sub0_sub1 cannot be used for AV_64_Align2 operands.
GLOBAL_STORE_DWORDX2 %0, %3.sub0_sub1, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX2 %0:vreg_64_align2, %3.sub2_sub3:vreg_128
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: VReg_128.sub2_sub3 cannot be used for AV_64_Align2 operands.
GLOBAL_STORE_DWORDX2 %0, %3.sub2_sub3, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX2 %0:vreg_64_align2, %3.sub1_sub2:vreg_128
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: VReg_128.sub1_sub2 cannot be used for AV_64_Align2 operands.
GLOBAL_STORE_DWORDX2 %0, %3.sub1_sub2, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX2 %0:vreg_64_align2, %5.sub1_sub2:vreg_128_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: VReg_128_Align2.sub1_sub2 cannot be used for AV_64_Align2 operands.
GLOBAL_STORE_DWORDX2 %0, %5.sub1_sub2, 0, 0, implicit $exec
; Check physical register uses.
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr3_vgpr4
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
; CHECK: $vgpr3_vgpr4 is not a AV_64_Align2 register.
GLOBAL_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr3_vgpr4, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
; CHECK: $vgpr3_vgpr4_vgpr5 is not a AV_96_Align2 register.
GLOBAL_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: GLOBAL_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5_vgpr6
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
; CHECK: $vgpr3_vgpr4_vgpr5_vgpr6 is not a AV_128_Align2 register.
GLOBAL_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5_vgpr6, 0, 0, implicit $exec
; Check virtual register defs.
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: %6:vreg_64 = GLOBAL_LOAD_DWORDX2 %0:vreg_64_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: Expected a AV_64_Align2 register, but got a VReg_64 register
%6:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: %7:vreg_96 = GLOBAL_LOAD_DWORDX3 %0:vreg_64_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: Expected a AV_96_Align2 register, but got a VReg_96 register
%7:vreg_96 = GLOBAL_LOAD_DWORDX3 %0, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: %8:vreg_128 = GLOBAL_LOAD_DWORDX4 %0:vreg_64_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: Expected a AV_128_Align2 register, but got a VReg_128 register
%8:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
; Check physical register defs.
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr1_vgpr2 = GLOBAL_LOAD_DWORDX2 %0:vreg_64_align2
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
; CHECK: $vgpr1_vgpr2 is not a AV_64_Align2 register.
$vgpr1_vgpr2 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr1_vgpr2_vgpr3 = GLOBAL_LOAD_DWORDX3 %0:vreg_64_align2
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
; CHECK: $vgpr1_vgpr2_vgpr3 is not a AV_96_Align2 register.
$vgpr1_vgpr2_vgpr3 = GLOBAL_LOAD_DWORDX3 %0, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr1_vgpr2_vgpr3_vgpr4 = GLOBAL_LOAD_DWORDX4 %0:vreg_64_align2
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
; CHECK: $vgpr1_vgpr2_vgpr3_vgpr4 is not a AV_128_Align2 register.
$vgpr1_vgpr2_vgpr3_vgpr4 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec
@@ -156,13 +124,9 @@ body: |
%9:vgpr_32 = IMPLICIT_DEF
%10:areg_64 = IMPLICIT_DEF
%11:areg_128_align2 = IMPLICIT_DEF
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: DS_WRITE_B64_gfx9 %9:vgpr_32, %10:areg_64
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: Expected a AV_64_Align2 register, but got a AReg_64 register
DS_WRITE_B64_gfx9 %9, %10, 0, 0, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: DS_WRITE_B64_gfx9 %9:vgpr_32, %11.sub1_sub2:areg_128_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: AReg_128_Align2.sub1_sub2 cannot be used for AV_64_Align2 operands.
DS_WRITE_B64_gfx9 %9, %11.sub1_sub2, 0, 0, implicit $exec
@@ -178,79 +142,55 @@ body: |
%14:areg_96_align2 = IMPLICIT_DEF
; odd def $vgpr3_vgpr4 (v3) is a misaligned VGPR pair
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr3_vgpr4 = V_PK_MOV_B32
$vgpr3_vgpr4 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
; src %12 is an unaligned VGPR pair
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_ADD_F32 0, %12:vreg_64, 11, %13:vreg_64_align2
$vgpr0_vgpr1 = V_PK_ADD_F32 0, %12, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %12 is an unaligned VGPR pair
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_ADD_F32 0, %13:vreg_64_align2, 11, %12:vreg_64
$vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %14 is an AGPR - a bank mismatch, not an alignment problem
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_ADD_F32 0, %13:vreg_64_align2, 11, %14.sub1_sub2:areg_96_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_ADD_F32 0, %13:vreg_64_align2, 11, %14.sub1_sub2:areg_96_align2
; CHECK: AReg_96_Align2.sub1_sub2 cannot be used for VS_64_Align2 operands.
$vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %14 is an AGPR - a bank mismatch, not an alignment problem
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_ADD_F32 0, %14.sub1_sub2:areg_96_align2, 11, %13:vreg_64_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_ADD_F32 0, %14.sub1_sub2:areg_96_align2, 11, %13:vreg_64_align2
; CHECK: AReg_96_Align2.sub1_sub2 cannot be used for VS_64_Align2 operands.
$vgpr0_vgpr1 = V_PK_ADD_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %12 is an unaligned VGPR pair
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_MUL_F32 0, %12:vreg_64, 11, %13:vreg_64_align2
$vgpr0_vgpr1 = V_PK_MUL_F32 0, %12, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %12 is an unaligned VGPR pair
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_MUL_F32 0, %13:vreg_64_align2, 11, %12:vreg_64
$vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %14 is an AGPR - a bank mismatch, not an alignment problem
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_MUL_F32 0, %13:vreg_64_align2, 11, %14.sub1_sub2:areg_96_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_MUL_F32 0, %13:vreg_64_align2, 11, %14.sub1_sub2:areg_96_align2
; CHECK: AReg_96_Align2.sub1_sub2 cannot be used for VS_64_Align2 operands.
$vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %14 is an AGPR - a bank mismatch, not an alignment problem
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_MUL_F32 0, %14.sub1_sub2:areg_96_align2, 11, %13:vreg_64_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: - instruction: $vgpr0_vgpr1 = V_PK_MUL_F32 0, %14.sub1_sub2:areg_96_align2, 11, %13:vreg_64_align2
; CHECK: AReg_96_Align2.sub1_sub2 cannot be used for VS_64_Align2 operands.
$vgpr0_vgpr1 = V_PK_MUL_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %12 is an unaligned VGPR pair (even aligned); src %14 is an AGPR (bank mismatch)
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %12:vreg_64, 8, %13:vreg_64_align2, 11, %14.sub0_sub1:areg_96_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: AReg_96_Align2.sub0_sub1 cannot be used for VS_64_Align2 operands.
$vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %12, 8, %13, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %12 is an unaligned VGPR pair (even aligned); src %14 is an AGPR (bank mismatch)
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13:vreg_64_align2, 8, %12:vreg_64, 11, %14.sub0_sub1:areg_96_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: AReg_96_Align2.sub0_sub1 cannot be used for VS_64_Align2 operands.
$vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13, 8, %12, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; src %14 is an AGPR - a bank mismatch (both %13 sources are aligned)
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13:vreg_64_align2, 8, %13:vreg_64_align2, 11, %14.sub1_sub2:areg_96_align2
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
; CHECK: - instruction: $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13:vreg_64_align2, 8, %13:vreg_64_align2, 11, %14.sub1_sub2:areg_96_align2
; CHECK: AReg_96_Align2.sub1_sub2 cannot be used for VS_64_Align2 operands.
diff --git a/llvm/test/CodeGen/AMDGPU/verify-image.mir b/llvm/test/CodeGen/AMDGPU/verify-image.mir
index 0d1cec5170cb5..2e9fc6f1a858f 100644
--- a/llvm/test/CodeGen/AMDGPU/verify-image.mir
+++ b/llvm/test/CodeGen/AMDGPU/verify-image.mir
@@ -7,8 +7,6 @@ body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9
- ; GFX11-ERR: *** Bad machine code: Operand has incorrect register class. ***
- ; GFX11-ERR: - instruction: renamable $vgpr10 = IMAGE_SAMPLE_D_V1_V9_nsa_gfx11 renamable $vgpr1, renamable $vgpr0, renamable $vgpr2, renamable $vgpr3, renamable $vgpr4_vgpr5_vgpr6_vgpr7, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX11-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX11-ERR: - instruction: renamable $vgpr10 = IMAGE_SAMPLE_D_V1_V9_nsa_gfx11 renamable $vgpr1, renamable $vgpr0, renamable $vgpr2, renamable $vgpr3, renamable $vgpr4_vgpr5_vgpr6_vgpr7, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX11-ERR: - operand 5: renamable $vgpr4_vgpr5_vgpr6_vgpr7
@@ -16,8 +14,6 @@ body: |
renamable $vgpr10 = IMAGE_SAMPLE_D_V1_V9_nsa_gfx11 renamable $vgpr1, renamable $vgpr0, renamable $vgpr2, renamable $vgpr3, renamable $vgpr4_vgpr5_vgpr6_vgpr7, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
- ; GFX11-ERR: *** Bad machine code: Operand has incorrect register class. ***
- ; GFX11-ERR: - instruction: renamable $vgpr11 = IMAGE_SAMPLE_D_V1_V9_nsa_gfx11 renamable $vgpr1, renamable $vgpr0, renamable $vgpr2, renamable $vgpr3, renamable $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX11-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX11-ERR: - instruction: renamable $vgpr11 = IMAGE_SAMPLE_D_V1_V9_nsa_gfx11 renamable $vgpr1, renamable $vgpr0, renamable $vgpr2, renamable $vgpr3, renamable $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX11-ERR: - operand 5: renamable $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
diff --git a/llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir b/llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
index 6c3860e48a850..c1c3cd60a6829 100644
--- a/llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
+++ b/llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
@@ -34,16 +34,12 @@ body: |
; GFX12-ERR: - instruction: renamable $vgpr26 = IMAGE_SAMPLE_V1_V1_gfx12 killed renamable $vgpr0, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr8_sgpr9_sgpr10_sgpr11, 15, 0, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load (s128), addrspace 7)
renamable $vgpr26 = IMAGE_SAMPLE_V1_V1_gfx12 killed renamable $vgpr0, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, killed renamable $sgpr8_sgpr9_sgpr10_sgpr11, 15, 0, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load (s128), addrspace 7)
- ; GFX12-ERR: *** Bad machine code: Operand has incorrect register class. ***
- ; GFX12-ERR: - instruction: renamable $vgpr27 = IMAGE_SAMPLE_D_V1_V9_gfx12 renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX12-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX12-ERR: - instruction: renamable $vgpr27 = IMAGE_SAMPLE_D_V1_V9_gfx12 renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX12-ERR: - operand 4: renamable $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX12-ERR: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 is not a VReg_192 register.
renamable $vgpr27 = IMAGE_SAMPLE_D_V1_V9_gfx12 renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
- ; GFX12-ERR: *** Bad machine code: Operand has incorrect register class. ***
- ; GFX12-ERR: - instruction: renamable $vgpr28 = IMAGE_SAMPLE_D_V1_V9_gfx12 renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX12-ERR: *** Bad machine code: Illegal physical register for instruction ***
; GFX12-ERR: - instruction: renamable $vgpr28 = IMAGE_SAMPLE_D_V1_V9_gfx12 renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; GFX12-ERR: - operand 4: renamable $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
diff --git a/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir b/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
index 5b1aaa6337261..6ddf0f62a6f1c 100644
--- a/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
@@ -21,10 +21,6 @@ body: |
; CHECK-NEXT: - operand 1: %1.sub16_sub17_sub18_sub19:vreg_512_align2
; CHECK-NEXT: Register class VReg_512_Align2 does not support subreg index sub16_sub17_sub18_sub19
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK-NEXT: - function: uses_invalid_subregister_for_regclass
- ; CHECK-NEXT: - basic block: %bb.0
- ; CHECK-NEXT: - instruction: GLOBAL_STORE_DWORDX4_SADDR %0:vgpr_32, %2.sub16_sub17_sub18_sub19:vreg_512, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
GLOBAL_STORE_DWORDX4_SADDR %0, %1.sub16_sub17_sub18_sub19, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
; Test with unaligned class
diff --git a/llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir b/llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir
index c982b1a35d44a..52d79ef9f1084 100644
--- a/llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir
@@ -9,12 +9,9 @@ body: |
bb.0:
liveins: $vgpr1_vgpr2
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
- ; CHECK: - instruction: $vcc = V_CMP_NE_U64_e64 0, $vgpr1_vgpr2, implicit $exec
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
$vcc = V_CMP_NE_U64_e64 0, $vgpr1_vgpr2, implicit $exec
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
; CHECK: *** Bad machine code: Illegal physical register for instruction ***
; CHECK: - instruction: V_CMP_NE_U64_e32 0, $vgpr1_vgpr2, implicit-def $vcc, implicit $exec
V_CMP_NE_U64_e32 0, $vgpr1_vgpr2, implicit-def $vcc, implicit $exec
@@ -23,12 +20,10 @@ body: |
%1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
%2:vreg_64 = IMPLICIT_DEF
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
%3:areg_128_align2 = V_MFMA_F32_4X4X1F32_e64 %0, %1, %2, 0, 0, 0, implicit $mode, implicit $exec
%4:vreg_64 = IMPLICIT_DEF
- ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
%5:vreg_128_align2 = V_MFMA_F32_4X4X1F32_vgprcd_e64 %0, %1, %4, 0, 0, 0, implicit $mode, implicit $exec
...
More information about the llvm-commits
mailing list